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keypad working

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This commit is contained in:
Nicholas Orlowsky 2024-04-15 09:32:48 -05:00
parent 55adbcf90a
commit 4855bbc42d
Signed by: nickorlow
GPG key ID: 838827D8C4611687
10 changed files with 526 additions and 213 deletions
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25
aastructs.sv
View file

@ -1,12 +1,23 @@
package structs;
typedef enum {ADD, ADDL, SUB, SE, SNE, OR, AND, XOR, SHR, SHL} alu_op;
typedef enum {
ADD,
ADDL,
SUB,
SE,
SNE,
OR,
AND,
XOR,
SHR,
SHL
} alu_op;
typedef struct packed {
logic [7:0] operand_a;
logic [7:0] operand_b;
logic [11:0] operand_b_long;
alu_op op;
} alu_input;
typedef struct packed {
logic [7:0] operand_a;
logic [7:0] operand_b;
logic [11:0] operand_b_long;
alu_op op;
} alu_input;
endpackage

157
alu.sv
View file

@ -1,6 +1,6 @@
import structs::*;
module alu(
module alu (
input wire rst_in,
input wire clk_in,
input alu_input in,
@ -8,88 +8,87 @@ module alu(
output logic [15:0] result_long,
output logic overflow,
output logic done
);
);
logic [8:0] result_int;
int cnt;
logic [8:0] result_int;
int cnt;
initial begin
overflow = 0;
result = 8'hxx;
result_int = 9'bxxxxxxxxx;
done = 0;
cnt = 0;
end
initial begin
overflow = 0;
result = 8'hxx;
result_int = 9'bxxxxxxxxx;
done = 0;
cnt = 0;
end
always_ff @(posedge clk_in) begin
if (rst_in) begin
done <= 0;
overflow <= 0;
result <= 8'hxx;
result_int <= 9'bxxxxxxxxx;
cnt <= 0;
end else begin
case(in.op)
structs::ADD: begin
result_int <= in.operand_a + in.operand_b;
result <= result_int[7:0];
overflow <= result_int[8];
if (cnt >= 2) begin
$display("%b %b + %b %b ya", result, in.operand_a, in.operand_b, result_int);
done <= 1;
end
cnt <= cnt + 1;
end
structs::ADDL: begin
result_long <= {8'h00, in.operand_a} + {4'h0, in.operand_b_long};
done <= 1;
cnt <= cnt + 1;
end
structs::SUB: begin
result_int <= in.operand_a - in.operand_b;
result <= result_int[7:0];
// FIXME: if this fails, just do vx > vy
overflow <= !result_int[8];
if (cnt >= 2) begin
done <= 1;
end
cnt <= cnt + 1;
end
structs::SE: begin
result <= {7'b0000000, in.operand_a == in.operand_b};
done <= 1;
end
structs::SNE: begin
result <= {7'b0000000, in.operand_a != in.operand_b};
done <= 1;
end
structs::OR: begin
result <= in.operand_a | in.operand_b;
overflow <= 0;
done <= 1;
end
structs::AND: begin
result <= in.operand_a & in.operand_b;
overflow <= 0;
done <= 1;
end
structs::XOR: begin
result <= in.operand_a ^ in.operand_b;
overflow <= 0;
done <= 1;
end
structs::SHR: begin
result <= in.operand_a >> in.operand_b;
overflow <= in.operand_a[0];
done <= 1;
end
structs::SHL: begin
result <= in.operand_a << in.operand_b;
overflow <= in.operand_a[7];
done <= 1;
end
endcase
always_ff @(posedge clk_in) begin
if (rst_in) begin
done <= 0;
overflow <= 0;
result <= 8'hxx;
result_int <= 9'bxxxxxxxxx;
cnt <= 0;
end else begin
case (in.op)
structs::ADD: begin
result_int <= in.operand_a + in.operand_b;
result <= result_int[7:0];
overflow <= result_int[8];
if (cnt >= 2) begin
done <= 1;
end
cnt <= cnt + 1;
end
structs::ADDL: begin
result_long <= {8'h00, in.operand_a} + {4'h0, in.operand_b_long};
done <= 1;
cnt <= cnt + 1;
end
structs::SUB: begin
result_int <= in.operand_a - in.operand_b;
result <= result_int[7:0];
// FIXME: if this fails, just do vx > vy
overflow <= !result_int[8];
if (cnt >= 2) begin
done <= 1;
end
cnt <= cnt + 1;
end
structs::SE: begin
result <= {7'b0000000, in.operand_a == in.operand_b};
done <= 1;
end
structs::SNE: begin
result <= {7'b0000000, in.operand_a != in.operand_b};
done <= 1;
end
structs::OR: begin
result <= in.operand_a | in.operand_b;
overflow <= 0;
done <= 1;
end
structs::AND: begin
result <= in.operand_a & in.operand_b;
overflow <= 0;
done <= 1;
end
structs::XOR: begin
result <= in.operand_a ^ in.operand_b;
overflow <= 0;
done <= 1;
end
structs::SHR: begin
result <= in.operand_a >> in.operand_b;
overflow <= in.operand_a[0];
done <= 1;
end
structs::SHL: begin
result <= in.operand_a << in.operand_b;
overflow <= in.operand_a[7];
done <= 1;
end
endcase
end
end
endmodule

61
chip8.sv
View file

@ -7,17 +7,29 @@ module chip8 (
input wire [3:0] row,
output logic [3:0] col
);
logic slow_clk;
logic debug_overlay;
logic slow_clk;
`ifdef FAST_CLK
assign slow_clk = fpga_clk;
assign slow_clk = fpga_clk;
`endif
`ifndef FAST_CLK
downclocker #(10) dc(fpga_clk, slow_clk);
downclocker #(12) dc (
fpga_clk,
slow_clk
);
`endif
logic key_clk;
downclocker #(24) dck(fpga_clk, key_clk);
`ifdef FAST_CLK
downclocker #(1) dck (
`endif
`ifndef FAST_CLK
downclocker #(12) dck (
`endif
fpga_clk,
key_clk
);
logic [7:0] rd_memory_data;
logic [11:0] rd_memory_address;
@ -25,20 +37,29 @@ logic slow_clk;
logic [7:0] wr_memory_data;
logic wr_go;
memory #(4096) mem (
slow_clk,
wr_go,
wr_memory_address,
wr_memory_data,
rd_memory_address,
rd_memory_data
);
slow_clk,
wr_go,
wr_memory_address,
wr_memory_data,
rd_memory_address,
rd_memory_data
);
keypad keypad(
key_clk,
row,
col,
led
);
logic [15:0] keymap;
keypad keypad (
`ifndef DUMMY_KEYPAD
key_clk,
`endif
`ifdef DUMMY_KEYPAD
slow_clk,
`endif
row,
col,
keymap
);
assign led = { key_clk, 1'b0, slow_clk, 1'b0, fpga_clk, 1'b0};
int cycle_counter;
logic [5:0] nc;
@ -46,6 +67,7 @@ logic slow_clk;
slow_clk,
fpga_clk,
rd_memory_data,
keymap,
cycle_counter,
rd_memory_address,
wr_memory_address,
@ -53,7 +75,10 @@ logic slow_clk;
wr_go,
lcd_clk,
lcd_data,
nc
nc,
row,
col,
debug_overlay
);
endmodule

159
cpu.sv
View file

@ -4,6 +4,7 @@ module cpu (
input wire clk_in,
input wire fpga_clk,
input wire [7:0] rd_memory_data,
input wire [15:0] keymap,
output int cycle_counter,
output logic [11:0] rd_memory_address,
output logic [11:0] wr_memory_address,
@ -11,7 +12,10 @@ module cpu (
output logic wr_go,
output logic lcd_clk,
output logic lcd_data,
output logic [5:0] led
output logic [5:0] led,
input wire [3:0] row,
input wire [3:0] col,
input wire debug_overlay
);
logic [5:0] lcd_led;
@ -60,19 +64,19 @@ logic [5:0] lcd_led;
if (vram[`BLP/8][7-(`BLP%8)] == 1) begin
registers[15] <= 1;
end
vram[`BLP/8][7-(`BLP%8)] <= 1;
vram[`BLP/8][7-(`BLP%8)] = vram[`BLP/8][7-(`BLP%8)] ^ 1;
// bottom right
`define BRP ((y*128*2) + x*2 +129)
vram[`BRP/8][7-(`BRP%8)] <= 1;
vram[`BRP/8][7-(`BRP%8)] = vram[`BRP/8][7-(`BRP%8)] ^ 1;
// top left
`define TLP ((y*128*2) + x*2)
vram[`TLP/8][7-(`TLP%8)] <= 1;
vram[`TLP/8][7-(`TLP%8)] = vram[`TLP/8][7-(`TLP%8)] ^ 1;
// top right
`define TRP ((y*128*2) + x*2+1)
vram[`TRP/8][7-(`TRP%8)] <= 1;
vram[`TRP/8][7-(`TRP%8)] = vram[`TRP/8][7-(`TRP%8)] ^ 1;
end
endtask
@ -90,6 +94,7 @@ logic [5:0] lcd_led;
logic [7:0] delay_timer;
logic [7:0] ldl_cnt;
int clr_cnt;
@ -98,8 +103,8 @@ logic [5:0] lcd_led;
typedef enum {INIT, DRAW} draw_stage;
typedef enum {CLS, LD, DRW, JP, ALU, CALU, CALL, RET, ALUJ, LDL, BCD} cpu_opcode;
typedef enum {REG, IDX_REG, BYTE, MEM, SPRITE_MEM} data_type;
typedef enum {CLS, LD, DRW, JP, ALU, CALU, CALL, RET, ALUJ, LDL, BCD, IOJ, IOW, NIOJ} cpu_opcode;
typedef enum {REG, IDX_REG, BYTE, MEM, SPRITE_MEM, KEY, DELAY_TIMER, SOUND_TIMER} data_type;
struct {
draw_stage stage;
@ -121,6 +126,7 @@ logic [5:0] lcd_led;
alu_input alu_i;
logic [11:0] src_byte;
logic [3:0] src_key;
logic [(8*16)-1:0] src_sprite;
logic [11:0] src_sprite_addr;
@ -148,6 +154,16 @@ logic [5:0] lcd_led;
end
always_ff @(posedge clk_in) begin
`ifdef FAST_CLOCK
if (cycle_counter % 100 == 0) begin
`endif
if (delay_timer > 0)
delay_timer <= delay_timer - 1;
if (sound_timer > 0)
sound_timer <= sound_timer - 1;
`ifdef FAST_CLOCK
end
`endif
case (state)
ST_FETCH_HI: begin
rd_memory_address <= program_counter[11:0];
@ -172,7 +188,8 @@ logic [5:0] lcd_led;
16'h0???: begin
if (opcode == 16'h00e0) begin
instr.op <= CLS;
state <= ST_CLEANUP;
state <= ST_EXEC;
clr_cnt <= 0;
program_counter <= program_counter + 2;
end else if (opcode == 16'h00EE) begin
instr.op <= RET;
@ -413,6 +430,61 @@ logic [5:0] lcd_led;
state <= ST_FETCH_MEM;
end
16'hE?9E: begin
instr.op <= IOJ;
instr.src <= KEY;
instr.src_key <= registers[opcode[11:8]][3:0];
state <= ST_EXEC;
end
16'hE?A1: begin
instr.op <= NIOJ;
instr.src <= KEY;
instr.src_key <= registers[opcode[11:8]][3:0];
state <= ST_EXEC;
end
16'hF?07: begin
instr.op <= LD;
instr.src <= DELAY_TIMER;
instr.dst <= REG;
instr.dst_reg <= opcode[11:8];
state <= ST_EXEC;
end
16'hF?0A: begin
$display("IO waiting");
instr.op <= IOW;
instr.src <= KEY;
instr.dst <= REG;
instr.dst_reg <= opcode[11:8];
state <= ST_EXEC;
end
16'hF?15: begin
instr.op <= LD;
instr.src <= REG;
instr.src_reg <= opcode[11:8];
instr.dst <= DELAY_TIMER;
state <= ST_EXEC;
end
16'hF?18: begin
instr.op <= LD;
instr.src <= REG;
instr.src_reg <= opcode[11:8];
instr.dst <= SOUND_TIMER;
state <= ST_EXEC;
end
16'hF?1E: begin
instr.op <= ALU;
@ -427,6 +499,16 @@ logic [5:0] lcd_led;
state <= ST_EXEC;
end
16'hF?29: begin
instr.op <= LD;
instr.src <= BYTE;
instr.src_byte <= registers[opcode[11:8]] * 5;
instr.dst <= IDX_REG;
state <= ST_EXEC;
end
16'hF?33: begin
instr.op <= BCD;
@ -494,7 +576,6 @@ logic [5:0] lcd_led;
instr.src_sprite_idx <= instr.src_sprite_idx + 1;
for (int l = 0; l < 8; l++)
instr.src_sprite[(instr.src_sprite_idx)*8+l] <= rd_memory_data[7-l];
$display("%b", rd_memory_data);
end else begin
instr.src_sprite_x <= registers[instr.src_sprite_vx] % 8'd64;
instr.src_sprite_y <= registers[instr.src_sprite_vy] % 8'd32;
@ -542,12 +623,14 @@ logic [5:0] lcd_led;
end
ST_EXEC: begin
$display("CPU : IN EXEC");
case (instr.op)
LD: begin
if (instr.src == REG) begin
instr.src_byte <= { 4'h0, registers[instr.src_reg] };
instr.src <= BYTE;
end else if (instr.src == DELAY_TIMER) begin
instr.src_byte <= { 4'h0, delay_timer };
instr.src <= BYTE;
end
end
LDL: begin
@ -567,7 +650,6 @@ logic [5:0] lcd_led;
if (instr.dst == MEM) begin
instr.src <= BYTE;
$display("%0d set to %h (r%0d)", instr.dst_addr,registers[instr.src_reg], instr.src_reg );
instr.src_byte <= {4'h0, registers[instr.src_reg]};
instr.src_reg <= instr.src_reg - 1;
instr.dst_addr <= instr.dst_addr - 1;
@ -655,13 +737,49 @@ logic [5:0] lcd_led;
program_counter <= stack[stack_pointer-1] + 2;
state <= ST_CLEANUP;
end
IOJ: begin
if (keymap[instr.src_key] == 1) begin
program_counter <= program_counter + 4;
end else begin
program_counter <= program_counter + 2;
end
state <= ST_CLEANUP;
end
NIOJ: begin
if (keymap[instr.src_key] != 1) begin
program_counter <= program_counter + 4;
end else begin
program_counter <= program_counter + 2;
end
state <= ST_CLEANUP;
end
IOW: begin
if (|keymap != 0) begin
$display("IO not waiting");
for(int m = 0; m < 16; m++) begin
if (keymap[m])
instr.src_byte <= m[11:0];
end
program_counter <= program_counter + 2;
state <= ST_WB;
instr.src <= BYTE;
end
end
CLS: begin
if (clr_cnt == 1024) begin
state <= ST_CLEANUP;
program_counter <= program_counter + 2;
end else begin
clr_cnt <= clr_cnt + 1;
vram[clr_cnt] <= 0;
end
end
endcase
case (instr.op)
LD,
DRW,
CLS: begin
DRW: begin
program_counter <= program_counter + 2;
state <= ST_WB;
@ -670,7 +788,6 @@ logic [5:0] lcd_led;
end
ST_WB: begin
$display("CPU : IN WB");
if (instr.src != BYTE)
$fatal();
@ -679,10 +796,11 @@ logic [5:0] lcd_led;
wr_memory_address <= instr.dst_addr;
wr_memory_data <= instr.src_byte[7:0];
wr_go <= 1'b1;
$display("writing back byte %b to %h", instr.src_byte, instr.dst_addr);
end
REG: registers[instr.dst_reg] <= instr.src_byte[7:0];
IDX_REG: index_reg <= {4'h0, instr.src_byte};
DELAY_TIMER: delay_timer <= instr.src_byte[7:0];
SOUND_TIMER: sound_timer <= instr.src_byte[7:0];
endcase
if (instr.op != LDL && instr.op != BCD)
@ -700,6 +818,17 @@ logic [5:0] lcd_led;
end
endcase
if (debug_overlay) begin
for(int w = 0; w < 16; w++) begin
vram[16+w] <= keymap[w] ? 8'hff : 0;
end
for (int z = 0; z < 4; z++) begin
vram[32 + z] = col[z] ? 8'hff : 0;
vram[64 + z] = row[z] ? 8'hff : 0;
end
end
cycle_counter <= cycle_counter + 1;
end
endmodule

30
downclocker.sv
View file

@ -1,21 +1,23 @@
module downclocker #(parameter DC_BITS = 21) (
input wire clk_in,
module downclocker #(
parameter DC_BITS = 21
) (
input wire clk_in,
output logic clk_out
);
logic [DC_BITS-1:0] counter;
logic [DC_BITS-1:0] counter;
initial begin
counter = 0;
clk_out = 0;
end
initial begin
counter = 0;
clk_out = 0;
end
always_ff @(posedge clk_in) begin
if (counter[DC_BITS-1] == 1) begin
clk_out <= !clk_out;
counter <= 0;
end else begin
counter <= counter + 1;
end
always_ff @(posedge clk_in) begin
if (counter[DC_BITS-1] == 1) begin
clk_out <= !clk_out;
counter <= 0;
end else begin
counter <= counter + 1;
end
end
endmodule

4
gpu.sv
View file

@ -1,7 +1,7 @@
module gpu (
input wire sys_clk,
input wire sys_rst_n_ms,
input wire [7:0] vram [0:1023],
input wire [7:0] vram[0:1023],
output logic lcd_clk, // This goes to the E pin
output logic lcd_data, // This goes to the R/W pin
output logic [5:0] led
@ -17,6 +17,6 @@ module gpu (
always_comb begin
draw_screen(vram);
draw_screen(vram);
end
endmodule

55
keypad.sv
View file

@ -2,13 +2,55 @@ module keypad(
input clk_in,
input wire [3:0] row,
output logic [3:0] col,
output [5:0] cur_press
output logic [15:0] keymap_out
);
logic [1:0] col_idx;
logic [15:0] keymap;
logic [15:0] keymap_db;
logic [15:0] keymap_db2;
/* old
assign keymap_out[0] = keymap[13];
assign keymap_out[1] = keymap[0];
assign keymap_out[2] = keymap[1];
assign keymap_out[3] = keymap[2];
assign keymap_out[4] = keymap[4];
assign keymap_out[5] = keymap[5];
assign keymap_out[6] = keymap[6];
assign keymap_out[7] = keymap[8];
assign keymap_out[8] = keymap[9];
assign keymap_out[9] = keymap[10];
assign cur_press = {clk_in, 1'b0, keymap[3:0]};
assign keymap_out[10] = keymap[3];
assign keymap_out[11] = keymap[7];
assign keymap_out[12] = keymap[11];
assign keymap_out[13] = keymap[15];
assign keymap_out[14] = keymap[12];
assign keymap_out[15] = keymap[14];
*/
//assign keymap_out = keymap;
assign keymap_out[1] = !keymap[1];
assign keymap_out[2] = !keymap[0];
assign keymap_out[3] = !keymap[2];
assign keymap_out[12] =!keymap[3];
assign keymap_out[4] = !keymap[5];
assign keymap_out[5] = !keymap[4];
assign keymap_out[6] = !keymap[6];
assign keymap_out[13] =!keymap[7]; //E
assign keymap_out[7] = !keymap[9];
assign keymap_out[8] = !keymap[8];
assign keymap_out[9] = !keymap[10];
assign keymap_out[14] =!keymap[11]; //F
assign keymap_out[10] =!keymap[13];
assign keymap_out[0] = !keymap[12]; //0
assign keymap_out[11] =!keymap[14];
assign keymap_out[15] =!keymap[15];// D
initial begin
col_idx = 0;
@ -18,12 +60,13 @@ module keypad(
always_ff @(posedge clk_in) begin
for(logic [2:0] i = 0; i < 4; i++) begin
keymap[(i*4)+col_idx] <= row[i[1:0]];
keymap_db[(i*4)+col_idx] <= row[i[1:0]];
end
keymap_db2 <= keymap_db;
keymap <= keymap_db2;
col[col_idx] <= 1;
col[col_idx+1] <= 0;
col_idx <= col_idx + 1;
col[col_idx == 3 ? 0 : col_idx +1] <= 0;
col_idx <= col_idx == 3 ? 0 : col_idx + 1;
end
endmodule

7
makefile
View file

@ -2,7 +2,7 @@
SDL_CFLAGS = `sdl2-config --cflags`
SDL_LDFLAGS = `sdl2-config --libs`
SV_FILES=aastructs.sv cpu.sv chip8.sv gpu.sv alu.sv
SV_FILES=aastructs.sv cpu.sv chip8.sv gpu.sv alu.sv keypad.sv
lint:
verilator --lint-only -DDUMMY_GPU --timing ${SV_FILES}
@ -11,7 +11,7 @@ build-rom:
python3 ./gen_rom.py ${ROM_FILE} rom.bin
build: build-rom
verilator --cc --exe --build --timing -j 0 --top-module chip8 *.sv yayacemu.cpp -DDUMMY_GPU -DFAST_CLK -CFLAGS "${SDL_CFLAGS}" -LDFLAGS "${SDL_LDFLAGS}" && clear
verilator --cc --exe --build --timing -j 0 --top-module chip8 *.sv yayacemu.cpp -DDUMMY_KEYPAD -DDUMMY_GPU -DFAST_CLK -CFLAGS "${SDL_CFLAGS}" -LDFLAGS "${SDL_LDFLAGS}" && clear
run: build
obj_dir/Vchip8
@ -23,7 +23,8 @@ format:
verible-verilog-format *.sv --inplace && clang-format *.cpp -i
build-fpga: *.sv *.qsf *.qpf rom.bin build-rom
quartus_sh --flow compile chip8 && ./make_cdf.sh
quartus_sh --flow compile chip8 && ./make_cdf.sh && \
notify-send "Quartus Build Complete"
run-fpga:
quartus_pgm -m jtag -o "p;./output_files/chip8.sof" ./output_files/chip8.cdf

30
memory.sv
View file

@ -1,27 +1,29 @@
module memory #(parameter RAM_SIZE_BYTES = 4096) (
module memory #(
parameter RAM_SIZE_BYTES = 4096
) (
input wire clk_in,
input wire do_write,
input wire [$clog2(RAM_SIZE_BYTES)-1:0] write_address,
input wire [7:0] data_in,
input wire [$clog2(RAM_SIZE_BYTES)-1:0] read_address,
output logic [7:0] data_out/*,
output logic [7:0] data_out /*,
input wire [$clog2(RAM_SIZE_BYTES)-1:0] read_address_gfx,
output logic [7:0] data_out_gfxA*/
);
logic [7:0] mem [0:RAM_SIZE_BYTES-1];
logic [7:0] mem[0:RAM_SIZE_BYTES-1];
initial begin
$readmemh("fontset.bin", mem, 0);
$readmemb("rom.bin", mem, 'h200);
end
initial begin
$readmemh("fontset.bin", mem, 0);
$readmemb("rom.bin", mem, 'h200);
end
always_ff @(negedge clk_in) begin
if (do_write) begin
mem[write_address] <= data_in;
end
//$display("MEM : Reading address %h (%h)", read_address, mem[read_address]);
data_out <= mem[read_address];
//data_out_gfx <= mem[read_address_gfx];
always_ff @(negedge clk_in) begin
if (do_write) begin
mem[write_address] <= data_in;
end
//$display("MEM : Reading address %h (%h)", read_address, mem[read_address]);
data_out <= mem[read_address];
//data_out_gfx <= mem[read_address_gfx];
end
endmodule

197
yayacemu.cpp
View file

@ -12,7 +12,7 @@
#define SCREEN_WIDTH 128
#define SCREEN_HEIGHT 64
#define EMULATION_HZ 10000
#define EMULATION_HZ 50000
SDL_Window *window;
SDL_Renderer *renderer;
@ -42,71 +42,171 @@ void set_beep(const svBit beep) {
void draw_screen(const svLogicVecVal *vram) {
uint32_t *screen = (uint32_t *)malloc(SCREEN_WIDTH * SCREEN_HEIGHT * 32);
for (int i = 0; i < 1024; i++) {
uint8_t line_byte = (uint8_t) vram[i].aval;
for (int j = 0; j < 8; j++) {
uint8_t pixel_val = (line_byte >> (7-j)) & 1;
screen[(i*8) + j] = pixel_val == 1 ? 0xFFFFFFFF : 0x00000000;
}
uint8_t line_byte = (uint8_t)vram[i].aval;
for (int j = 0; j < 8; j++) {
uint8_t pixel_val = (line_byte >> (7 - j)) & 1;
screen[(i * 8) + j] = pixel_val == 1 ? 0xFFFFFFFF : 0x00000000;
}
}
SDL_UpdateTexture(texture, NULL, screen, sizeof(screen[0]) * SCREEN_WIDTH);
SDL_RenderClear(renderer);
SDL_RenderCopy(renderer, texture, NULL, NULL);
SDL_RenderPresent(renderer);
free(screen);
//std::cout << "INF_EMU: Drawing Frame" << '\n';
// std::cout << "INF_EMU: Drawing Frame" << '\n';
}
svBitVecVal get_key() {
// 1 2 3 A
// 4 5 6 B
// 7 8 9 C
// * 0 # D
//
int keys[16];
uint8_t get_key(uint8_t col) {
SDL_Event event;
uint8_t down = 0;
uint8_t res = 0xFF;
// col 1000 - r1
while (SDL_PollEvent(&event)) {
uint8_t down = 0;
switch (event.type) {
case SDL_KEYDOWN:
down = 128;
down = 1;
case SDL_KEYUP:
switch (event.key.keysym.sym) {
case SDLK_0:
return down | (uint8_t)0;
case SDLK_1:
return down | (uint8_t)1;
case SDLK_2:
return down | (uint8_t)2;
case SDLK_3:
return down | (uint8_t)3;
case SDLK_4:
return down | (uint8_t)4;
case SDLK_5:
return down | (uint8_t)5;
case SDLK_6:
return down | (uint8_t)6;
case SDLK_7:
return down | (uint8_t)7;
case SDLK_8:
return down | (uint8_t)8;
case SDLK_9:
return down | (uint8_t)9;
case SDLK_a:
return down | (uint8_t)10;
case SDLK_b:
return down | (uint8_t)11;
case SDLK_c:
return down | (uint8_t)12;
case SDLK_d:
return down | (uint8_t)13;
case SDLK_e:
return down | (uint8_t)14;
case SDLK_f:
return down | (uint8_t)15;
default:
return 255;
}
default:
return 255;
case SDLK_1:
keys[1] = down;
break;
case SDLK_2:
keys[2] = down;
break;
case SDLK_3:
keys[3] = down;
break;
case SDLK_a:
keys[10] = down;
break;
case SDLK_4:
keys[4] = down;
break;
case SDLK_5:
keys[5] = down;
break;
case SDLK_6:
keys[6] = down;
break;
case SDLK_7:
keys[7] = down;
break;
case SDLK_b:
keys[11] = down;
break;
case SDLK_8:
keys[8] = down;
break;
case SDLK_9:
keys[9] = down;
break;
case SDLK_c:
keys[12] = down;
break;
case SDLK_0:
keys[0] = down;
break;
case SDLK_e:
keys[14] = down;
break;
case SDLK_f:
keys[15] = down;
break;
case SDLK_d:
keys[13] = down;
break;
}
}
}
return 255;
if (keys[0] == 1) {
if (col == 0b1110)
res = res & 0b0111;
}
if (keys[1] == 1) {
if (col == 0b1101)
res = res & 0b1110;
}
if (keys[2] == 1) {
if (col == 0b1110)
res = res & 0b1110;
}
if (keys[3] == 1) {
if (col == 0b1011)
res = res & 0b1110;
}
if (keys[4] == 1) {
if (col == 0b1101)
res = res & 0b1101;
}
if (keys[5] == 1) {
if (col == 0b1110)
res = res & 0b1101;
}
if (keys[6] == 1) {
if (col == 0b1011)
res = res & 0b1101;
}
if (keys[7] == 1) {
if (col == 0b1101)
res = res & 0b1011;
}
if (keys[8] == 1) {
if (col == 0b1110)
res = res & 0b1011;
}
if (keys[9] == 1) {
if (col == 0b1011)
res = res & 0b1011;
}
if (keys[10] == 1) {
if (col == 0b1101)
res = res & 0b0111;
}
if (keys[11] == 1) {
if (col == 0b1011)
res = res & 0b0111;
}
if (keys[12] == 1) {
if (col == 0b0111)
res = res & 0b1110;
}
if (keys[13] == 1) {
if (col == 0b0111)
res = res & 0b1101;
}
if (keys[14] == 1) {
if (col == 0b0111)
res = res & 0b1011;
}
if (keys[15] == 1) {
if (col == 0b0111)
res = res & 0b0111;
}
//if (res != 0)
// printf("%04b %04b\n", res, col);
return res;
}
int main(int argc, char **argv) {
@ -118,6 +218,7 @@ int main(int argc, char **argv) {
dut->rst_in = 0;
dut->fpga_clk = 1;
while (true) {
dut->row = get_key(dut->col);
dut->fpga_clk ^= 1;
dut->eval();