73 lines
2 KiB
Systemverilog
73 lines
2 KiB
Systemverilog
module keypad(
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input clk_in,
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input wire [3:0] row,
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output logic [3:0] col,
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output logic [15:0] keymap_out
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);
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logic [1:0] col_idx;
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logic [15:0] keymap;
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logic [15:0] keymap_db;
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logic [15:0] keymap_db2;
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/* old
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assign keymap_out[0] = keymap[13];
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assign keymap_out[1] = keymap[0];
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assign keymap_out[2] = keymap[1];
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assign keymap_out[3] = keymap[2];
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assign keymap_out[4] = keymap[4];
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assign keymap_out[5] = keymap[5];
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assign keymap_out[6] = keymap[6];
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assign keymap_out[7] = keymap[8];
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assign keymap_out[8] = keymap[9];
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assign keymap_out[9] = keymap[10];
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assign keymap_out[10] = keymap[3];
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assign keymap_out[11] = keymap[7];
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assign keymap_out[12] = keymap[11];
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assign keymap_out[13] = keymap[15];
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assign keymap_out[14] = keymap[12];
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assign keymap_out[15] = keymap[14];
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*/
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//assign keymap_out = keymap;
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assign keymap_out[1] = !keymap[1];
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assign keymap_out[2] = !keymap[0];
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assign keymap_out[3] = !keymap[2];
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assign keymap_out[12] =!keymap[3];
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assign keymap_out[4] = !keymap[5];
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assign keymap_out[5] = !keymap[4];
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assign keymap_out[6] = !keymap[6];
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assign keymap_out[13] =!keymap[7]; //E
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assign keymap_out[7] = !keymap[9];
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assign keymap_out[8] = !keymap[8];
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assign keymap_out[9] = !keymap[10];
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assign keymap_out[14] =!keymap[11]; //F
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assign keymap_out[10] =!keymap[13];
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assign keymap_out[0] = !keymap[12]; //0
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assign keymap_out[11] =!keymap[14];
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assign keymap_out[15] =!keymap[15];// D
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initial begin
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col_idx = 0;
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col = 0;
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keymap = 0;
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end
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always_ff @(posedge clk_in) begin
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for(logic [2:0] i = 0; i < 4; i++) begin
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keymap_db[(i*4)+col_idx] <= row[i[1:0]];
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end
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keymap_db2 <= keymap_db;
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keymap <= keymap_db2;
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col[col_idx] <= 1;
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col[col_idx == 3 ? 0 : col_idx +1] <= 0;
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col_idx <= col_idx == 3 ? 0 : col_idx + 1;
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end
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endmodule
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