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This commit is contained in:
Nicholas Orlowsky 2024-04-07 23:55:54 -05:00
parent f2c0935b60
commit a93cc69e2c
Signed by: nickorlow
GPG key ID: 838827D8C4611687
51 changed files with 25967 additions and 36047 deletions
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3
chip8.qsf
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@ -35,7 +35,7 @@ set_global_assignment -name SDC_FILE chip8.sdc
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_location_assignment PIN_V11 -to clk_in
set_location_assignment PIN_V11 -to fpga_clk
set_location_assignment PIN_D8 -to lcd_clk
@ -60,4 +60,5 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to lcd_cs
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to lcd_data
set_location_assignment PIN_W20 -to rst_in
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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chip8.qws
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cpu.sv
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@ -112,7 +112,7 @@ module cpu (
cycle_counter = 0;
program_counter = 'h200;
wr_go = 0;
for (int i = 0; i < 2048; i++) begin
for (int i = 0; i < 1024; i++) begin
vram[i] = 0;
end
end

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db/chip8.db_info
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@ -1,3 +1,3 @@
Quartus_Version = Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition
Version_Index = 570679040
Creation_Time = Sun Apr 7 15:25:35 2024
Creation_Time = Sun Apr 7 23:44:47 2024

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db/chip8.fit.qmsg
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@ -1,10 +1,47 @@
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1712529585582 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "12 12 " "Parallel compilation is enabled and will use 12 of the 12 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1712529585582 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "chip8 5CSEBA6U23I7 " "Selected device 5CSEBA6U23I7 for design \"chip8\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1712529587114 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature -40 degrees C " "Low junction temperature is -40 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1712529587136 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 100 degrees C " "High junction temperature is 100 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1712529587136 ""}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1712529592466 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1712529592564 ""}
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1712529600469 ""}
{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1712529632442 ""}
{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "2 s (2 global) " "Automatically promoted 2 clocks (2 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "dc:dc\|clk_out~CLKENA0 35217 global CLKCTRL_G2 " "dc:dc\|clk_out~CLKENA0 with 35217 fanout uses global clock CLKCTRL_G2" { { "Info" "ICCLK_UNLOCKED_FOR_VPR" "" "This signal is driven by core routing -- it may be moved during placement to reduce routing delays" { } { } 0 12525 "This signal is driven by core routing -- it may be moved during placement to reduce routing delays" 0 0 "Design Software" 0 -1 1712529642530 ""} } { } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1712529642530 ""} { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "clk_in~inputCLKENA0 31 global CLKCTRL_G5 " "clk_in~inputCLKENA0 with 31 fanout uses global clock CLKCTRL_G5" { } { } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1712529642530 ""} } { } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1712529642530 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1712551555206 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "12 12 " "Parallel compilation is enabled and will use 12 of the 12 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1712551555206 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "chip8 5CSEBA6U23I7 " "Selected device 5CSEBA6U23I7 for design \"chip8\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1712551555269 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature -40 degrees C " "Low junction temperature is -40 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1712551555292 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 100 degrees C " "High junction temperature is 100 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1712551555292 ""}
{ "Warning" "WMPP_MPP_RAM_IS_ACTUALLY_ROM_TOP" "" "Found RAM instances implemented as ROM because the write logic is disabled. One instance is listed below as an example." { { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "memory:mem\|altsyncram:mem_rtl_0\|altsyncram_dsq1:auto_generated\|ram_block1a4 " "Atom \"memory:mem\|altsyncram:mem_rtl_0\|altsyncram_dsq1:auto_generated\|ram_block1a4\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Design Software" 0 -1 1712551555358 "|chip8|memory:mem|altsyncram:mem_rtl_0|altsyncram_dsq1:auto_generated|ram_block1a4"} } { } 0 18550 "Found RAM instances implemented as ROM because the write logic is disabled. One instance is listed below as an example." 0 0 "Fitter" 0 -1 1712551555358 ""}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1712551555754 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1712551555775 ""}
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1712551556100 ""}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1712551556280 ""}
{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1712551564414 ""}
{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1 (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "fpga_clk~inputCLKENA0 8563 global CLKCTRL_G5 " "fpga_clk~inputCLKENA0 with 8563 fanout uses global clock CLKCTRL_G5" { } { } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1712551564875 ""} } { } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1712551564875 ""}
{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1712551564876 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1712551564962 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1712551564999 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1712551565068 ""}
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1712551565142 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1712551565142 ""}
{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1712551565178 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "chip8.sdc " "Synopsys Design Constraints File file not found: 'chip8.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1712551566238 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1712551566238 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1712551566558 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1712551566558 ""}
{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1712551566563 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1712551568020 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1712551568056 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1712551568056 ""}
{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "lcd_cs " "Node \"lcd_cs\" is assigned to location or region, but does not exist in design" { } { { "/opt/intelFPGA/23.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/opt/intelFPGA/23.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "lcd_cs" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1712551568422 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1712551568422 ""}
{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:13 " "Fitter preparation operations ending: elapsed time is 00:00:13" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1712551568422 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1712551572577 ""}
{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1712551575144 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:52 " "Fitter placement preparation operations ending: elapsed time is 00:00:52" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1712551625159 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1712551662013 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1712551685328 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:24 " "Fitter placement operations ending: elapsed time is 00:00:24" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1712551685328 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1712551687722 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "12 " "Router estimated average interconnect usage is 12% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "57 X22_Y23 X32_Y34 " "Router estimated peak interconnect usage is 57% of the available device resources in the region that extends from location X22_Y23 to location X32_Y34" { } { { "loc" "" { Generic "/home/nickorlow/programming/school/warminster/yayacemu/" { { 1 { 0 "Router estimated peak interconnect usage is 57% of the available device resources in the region that extends from location X22_Y23 to location X32_Y34"} { { 12 { 0 ""} 22 23 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1712551718020 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1712551718020 ""}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1712551878467 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1712551878467 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:03:08 " "Fitter routing operations ending: elapsed time is 00:03:08" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1712551878471 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 49.90 " "Total time spent on timing analysis during the Fitter is 49.90 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1712551894479 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1712551894660 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1712551899814 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1712551899828 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1712551905639 ""}
{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:29 " "Fitter post-fit operations ending: elapsed time is 00:00:29" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1712551923094 ""}
{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1712551923931 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/nickorlow/programming/school/warminster/yayacemu/output_files/chip8.fit.smsg " "Generated suppressed messages file /home/nickorlow/programming/school/warminster/yayacemu/output_files/chip8.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1712551925355 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 8 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2797 " "Peak virtual memory: 2797 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1712551929265 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 7 23:52:09 2024 " "Processing ended: Sun Apr 7 23:52:09 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1712551929265 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:06:15 " "Elapsed time: 00:06:15" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1712551929265 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:14:19 " "Total CPU time (on all processors): 00:14:19" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1712551929265 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1712551929265 ""}

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db/chip8.hier_info
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db/chip8.lpc.html
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@ -16,23 +16,7 @@
<TH>Output only Bidir</TH>
</TR>
<TR >
<TD >randy</TD>
<TD >65</TD>
<TD >32</TD>
<TD >0</TD>
<TD >32</TD>
<TD >8</TD>
<TD >32</TD>
<TD >32</TD>
<TD >32</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >gpu|dff</TD>
<TD >cpu|gpu|dff</TD>
<TD >2</TD>
<TD >0</TD>
<TD >0</TD>
@ -48,7 +32,7 @@
<TD >0</TD>
</TR>
<TR >
<TD >gpu|com</TD>
<TD >cpu|gpu|com</TD>
<TD >12</TD>
<TD >0</TD>
<TD >0</TD>
@ -64,12 +48,12 @@
<TD >0</TD>
</TR>
<TR >
<TD >gpu</TD>
<TD >10</TD>
<TD >cpu|gpu</TD>
<TD >8194</TD>
<TD >1</TD>
<TD >0</TD>
<TD >1</TD>
<TD >18</TD>
<TD >8</TD>
<TD >1</TD>
<TD >1</TD>
<TD >1</TD>
@ -81,14 +65,14 @@
</TR>
<TR >
<TD >cpu</TD>
<TD >37</TD>
<TD >25</TD>
<TD >9</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >73</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >25</TD>
<TD >48</TD>
<TD >25</TD>
<TD >25</TD>
<TD >25</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
@ -96,12 +80,12 @@
<TD >0</TD>
</TR>
<TR >
<TD >dc</TD>
<TD >1</TD>
<TD >mem</TD>
<TD >34</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >1</TD>
<TD >8</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>

BIN
db/chip8.lpc.rdb
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23
db/chip8.lpc.txt
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@ -1,12 +1,11 @@
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Legal Partition Candidates ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; randy ; 65 ; 32 ; 0 ; 32 ; 8 ; 32 ; 32 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; gpu|dff ; 2 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; gpu|com ; 12 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; gpu ; 10 ; 1 ; 0 ; 1 ; 18 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; cpu ; 37 ; 25 ; 0 ; 25 ; 48 ; 25 ; 25 ; 25 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; dc ; 1 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Legal Partition Candidates ;
+-------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
+-------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; cpu|gpu|dff ; 2 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; cpu|gpu|com ; 12 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; cpu|gpu ; 8194 ; 1 ; 0 ; 1 ; 8 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; cpu ; 9 ; 0 ; 0 ; 0 ; 73 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; mem ; 34 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+-------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

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db/chip8.map.kpt
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67
db/chip8.map.qmsg
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@ -1,21 +1,46 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1712551112815 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition " "Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1712551112815 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 7 23:38:32 2024 " "Processing started: Sun Apr 7 23:38:32 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1712551112815 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712551112815 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off chip8 -c chip8 " "Command: quartus_map --read_settings_files=on --write_settings_files=off chip8 -c chip8" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712551112816 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1712551112956 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "12 12 " "Parallel compilation is enabled and will use 12 of the 12 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1712551112956 ""}
{ "Critical Warning" "WVRFX_VERI_UNDEFINED_MACRO" "DELAY_BITS st7920_serial_driver.sv(12) " "Verilog HDL Compiler Directive warning at st7920_serial_driver.sv(12): text macro \"DELAY_BITS\" is undefined" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 12 0 0 } } } 1 10191 "Verilog HDL Compiler Directive warning at %2!s!: text macro \"%1!s!\" is undefined" 0 0 "Analysis & Synthesis" 0 -1 1712551118395 ""}
{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\":\"; expecting an operand st7920_serial_driver.sv(12) " "Verilog HDL syntax error at st7920_serial_driver.sv(12) near text: \":\"; expecting an operand. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 12 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1712551118395 ""}
{ "Critical Warning" "WVRFX_VERI_UNDEFINED_MACRO" "BOOTSTRAP_INSTRS st7920_serial_driver.sv(64) " "Verilog HDL Compiler Directive warning at st7920_serial_driver.sv(64): text macro \"BOOTSTRAP_INSTRS\" is undefined" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 64 0 0 } } } 1 10191 "Verilog HDL Compiler Directive warning at %2!s!: text macro \"%1!s!\" is undefined" 0 0 "Analysis & Synthesis" 0 -1 1712551118395 ""}
{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\")\"; expecting an operand st7920_serial_driver.sv(64) " "Verilog HDL syntax error at st7920_serial_driver.sv(64) near text: \")\"; expecting an operand. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 64 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1712551118395 ""}
{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"else\"; expecting \"end\" st7920_serial_driver.sv(70) " "Verilog HDL syntax error at st7920_serial_driver.sv(70) near text: \"else\"; expecting \"end\". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 70 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1712551118395 ""}
{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\")\"; expecting an operand st7920_serial_driver.sv(94) " "Verilog HDL syntax error at st7920_serial_driver.sv(94) near text: \")\"; expecting an operand. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 94 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1712551118395 ""}
{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\")\"; expecting an operand st7920_serial_driver.sv(97) " "Verilog HDL syntax error at st7920_serial_driver.sv(97) near text: \")\"; expecting an operand. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 97 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1712551118395 ""}
{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"\]\"; expecting an operand st7920_serial_driver.sv(124) " "Verilog HDL syntax error at st7920_serial_driver.sv(124) near text: \"\]\"; expecting an operand. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 124 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1712551118395 ""}
{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"else\"; expecting \"end\" st7920_serial_driver.sv(127) " "Verilog HDL syntax error at st7920_serial_driver.sv(127) near text: \"else\"; expecting \"end\". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 127 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1712551118395 ""}
{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "st7920_serial_driver st7920_serial_driver.sv(1) " "Ignored design unit \"st7920_serial_driver\" at st7920_serial_driver.sv(1) due to previous errors" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 1 0 0 } } } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Analysis & Synthesis" 0 -1 1712551118395 ""}
{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "d_flip_flop st7920_serial_driver.sv(134) " "Ignored design unit \"d_flip_flop\" at st7920_serial_driver.sv(134) due to previous errors" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 134 0 0 } } } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Analysis & Synthesis" 0 -1 1712551118395 ""}
{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "commander st7920_serial_driver.sv(144) " "Ignored design unit \"commander\" at st7920_serial_driver.sv(144) due to previous errors" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 144 0 0 } } } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Analysis & Synthesis" 0 -1 1712551118396 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "the-bomb/st7920_serial_driver.sv 0 0 " "Found 0 design units, including 0 entities, in source file the-bomb/st7920_serial_driver.sv" { } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712551118396 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "chip8.sv 1 1 " "Found 1 design units, including 1 entities, in source file chip8.sv" { { "Info" "ISGN_ENTITY_NAME" "1 chip8 " "Found entity 1: chip8" { } { { "chip8.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/chip8.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712551118397 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712551118397 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu.sv 1 1 " "Found 1 design units, including 1 entities, in source file cpu.sv" { { "Info" "ISGN_ENTITY_NAME" "1 cpu " "Found entity 1: cpu" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712551118398 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712551118398 ""}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 10 s 3 s Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 10 errors, 3 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "383 " "Peak virtual memory: 383 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1712551118425 ""} { "Error" "EQEXE_END_BANNER_TIME" "Sun Apr 7 23:38:38 2024 " "Processing ended: Sun Apr 7 23:38:38 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1712551118425 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1712551118425 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:14 " "Total CPU time (on all processors): 00:00:14" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1712551118425 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1712551118425 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1712551491860 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition " "Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1712551491860 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 7 23:44:51 2024 " "Processing started: Sun Apr 7 23:44:51 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1712551491860 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712551491860 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off chip8 -c chip8 " "Command: quartus_map --read_settings_files=on --write_settings_files=off chip8 -c chip8" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712551491860 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1712551492019 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "12 12 " "Parallel compilation is enabled and will use 12 of the 12 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1712551492019 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "the-bomb/st7920_serial_driver.sv 3 3 " "Found 3 design units, including 3 entities, in source file the-bomb/st7920_serial_driver.sv" { { "Info" "ISGN_ENTITY_NAME" "1 st7920_serial_driver " "Found entity 1: st7920_serial_driver" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712551496896 ""} { "Info" "ISGN_ENTITY_NAME" "2 d_flip_flop " "Found entity 2: d_flip_flop" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 137 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712551496896 ""} { "Info" "ISGN_ENTITY_NAME" "3 commander " "Found entity 3: commander" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 147 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712551496896 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712551496896 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "chip8.sv 1 1 " "Found 1 design units, including 1 entities, in source file chip8.sv" { { "Info" "ISGN_ENTITY_NAME" "1 chip8 " "Found entity 1: chip8" { } { { "chip8.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/chip8.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712551496897 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712551496897 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu.sv 1 1 " "Found 1 design units, including 1 entities, in source file cpu.sv" { { "Info" "ISGN_ENTITY_NAME" "1 cpu " "Found entity 1: cpu" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712551496898 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712551496898 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "chip8 " "Elaborating entity \"chip8\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1712551496936 ""}
{ "Warning" "WSGN_SEARCH_FILE" "memory.sv 1 1 " "Using design file memory.sv, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 memory " "Found entity 1: memory" { } { { "memory.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/memory.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712551496940 ""} } { } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1712551496940 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "memory memory:mem " "Elaborating entity \"memory\" for hierarchy \"memory:mem\"" { } { { "chip8.sv" "mem" { Text "/home/nickorlow/programming/school/warminster/yayacemu/chip8.sv" 21 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712551496940 ""}
{ "Warning" "WVRFX_VERI_2111_UNCONVERTED" "80 0 4095 memory.sv(14) " "Verilog HDL warning at memory.sv(14): number of words (80) in memory file does not match the number of elements in the address range \[0:4095\]" { } { { "memory.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/memory.sv" 14 0 0 } } } 0 10850 "Verilog HDL warning at %4!s!: number of words (%1!d!) in memory file does not match the number of elements in the address range \[%2!d!:%3!d!\]" 0 0 "Analysis & Synthesis" 0 -1 1712551496941 "|chip8|memory:mem"}
{ "Warning" "WVRFX_VERI_2111_UNCONVERTED" "260 512 4095 memory.sv(15) " "Verilog HDL warning at memory.sv(15): number of words (260) in memory file does not match the number of elements in the address range \[512:4095\]" { } { { "memory.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/memory.sv" 15 0 0 } } } 0 10850 "Verilog HDL warning at %4!s!: number of words (%1!d!) in memory file does not match the number of elements in the address range \[%2!d!:%3!d!\]" 0 0 "Analysis & Synthesis" 0 -1 1712551496941 "|chip8|memory:mem"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu cpu:cpu " "Elaborating entity \"cpu\" for hierarchy \"cpu:cpu\"" { } { { "chip8.sv" "cpu" { Text "/home/nickorlow/programming/school/warminster/yayacemu/chip8.sv" 35 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712551496941 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(124) " "Verilog HDL assignment warning at cpu.sv(124): truncated value with size 32 to match size of target (16)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 124 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712551497024 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(130) " "Verilog HDL assignment warning at cpu.sv(130): truncated value with size 32 to match size of target (16)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 130 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712551497024 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(147) " "Verilog HDL assignment warning at cpu.sv(147): truncated value with size 32 to match size of target (16)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 147 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712551497024 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 cpu.sv(210) " "Verilog HDL assignment warning at cpu.sv(210): truncated value with size 32 to match size of target (5)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 210 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712551497024 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 cpu.sv(213) " "Verilog HDL assignment warning at cpu.sv(213): truncated value with size 32 to match size of target (5)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 213 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712551497024 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(242) " "Verilog HDL assignment warning at cpu.sv(242): truncated value with size 32 to match size of target (16)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 242 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712551497024 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 cpu.sv(246) " "Verilog HDL assignment warning at cpu.sv(246): truncated value with size 32 to match size of target (5)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 246 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712551497024 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 cpu.sv(257) " "Verilog HDL assignment warning at cpu.sv(257): truncated value with size 32 to match size of target (5)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 257 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712551497024 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(284) " "Verilog HDL assignment warning at cpu.sv(284): truncated value with size 32 to match size of target (16)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 284 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712551497024 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "instr.src_reg 0 cpu.sv(108) " "Net \"instr.src_reg\" at cpu.sv(108) has no driver or initial value, using a default initial value '0'" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 108 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1712551497024 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "instr.src_addr 0 cpu.sv(108) " "Net \"instr.src_addr\" at cpu.sv(108) has no driver or initial value, using a default initial value '0'" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 108 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1712551497024 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "instr.dst_addr 0 cpu.sv(108) " "Net \"instr.dst_addr\" at cpu.sv(108) has no driver or initial value, using a default initial value '0'" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 108 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1712551497024 "|chip8|cpu:cpu"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "st7920_serial_driver cpu:cpu\|st7920_serial_driver:gpu " "Elaborating entity \"st7920_serial_driver\" for hierarchy \"cpu:cpu\|st7920_serial_driver:gpu\"" { } { { "cpu.sv" "gpu" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 28 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712551497028 ""}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "line_idx st7920_serial_driver.sv(23) " "Verilog HDL or VHDL warning at st7920_serial_driver.sv(23): object \"line_idx\" assigned a value but never read" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 23 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1712551497040 "|chip8|cpu:cpu|st7920_serial_driver:gpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 st7920_serial_driver.sv(71) " "Verilog HDL assignment warning at st7920_serial_driver.sv(71): truncated value with size 32 to match size of target (7)" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 71 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712551497040 "|chip8|cpu:cpu|st7920_serial_driver:gpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 st7920_serial_driver.sv(84) " "Verilog HDL assignment warning at st7920_serial_driver.sv(84): truncated value with size 32 to match size of target (7)" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 84 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712551497040 "|chip8|cpu:cpu|st7920_serial_driver:gpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 st7920_serial_driver.sv(103) " "Verilog HDL assignment warning at st7920_serial_driver.sv(103): truncated value with size 32 to match size of target (6)" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 103 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712551497040 "|chip8|cpu:cpu|st7920_serial_driver:gpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 9 st7920_serial_driver.sv(131) " "Verilog HDL assignment warning at st7920_serial_driver.sv(131): truncated value with size 32 to match size of target (9)" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 131 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712551497040 "|chip8|cpu:cpu|st7920_serial_driver:gpu"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "commands\[6..10\] 0 st7920_serial_driver.sv(26) " "Net \"commands\[6..10\]\" at st7920_serial_driver.sv(26) has no driver or initial value, using a default initial value '0'" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 26 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1712551497040 "|chip8|cpu:cpu|st7920_serial_driver:gpu"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "commander cpu:cpu\|st7920_serial_driver:gpu\|commander:com " "Elaborating entity \"commander\" for hierarchy \"cpu:cpu\|st7920_serial_driver:gpu\|commander:com\"" { } { { "the-bomb/st7920_serial_driver.sv" "com" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 42 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712551497041 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "d_flip_flop cpu:cpu\|st7920_serial_driver:gpu\|d_flip_flop:dff " "Elaborating entity \"d_flip_flop\" for hierarchy \"cpu:cpu\|st7920_serial_driver:gpu\|d_flip_flop:dff\"" { } { { "the-bomb/st7920_serial_driver.sv" "dff" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 50 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712551497041 ""}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "IINFER_ALTSYNCRAM_INFERRED" "memory:mem\|mem_rtl_0 " "Inferred altsyncram megafunction from the following design logic: \"memory:mem\|mem_rtl_0\" " { { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OPERATION_MODE DUAL_PORT " "Parameter OPERATION_MODE set to DUAL_PORT" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712551516726 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_A 8 " "Parameter WIDTH_A set to 8" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712551516726 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_A 12 " "Parameter WIDTHAD_A set to 12" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712551516726 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_A 4096 " "Parameter NUMWORDS_A set to 4096" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712551516726 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_B 8 " "Parameter WIDTH_B set to 8" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712551516726 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_B 12 " "Parameter WIDTHAD_B set to 12" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712551516726 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_B 4096 " "Parameter NUMWORDS_B set to 4096" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712551516726 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_A NONE " "Parameter ADDRESS_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712551516726 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_REG_B UNREGISTERED " "Parameter OUTDATA_REG_B set to UNREGISTERED" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712551516726 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_B NONE " "Parameter ADDRESS_ACLR_B set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712551516726 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_ACLR_B NONE " "Parameter OUTDATA_ACLR_B set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712551516726 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_REG_B CLOCK0 " "Parameter ADDRESS_REG_B set to CLOCK0" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712551516726 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "INDATA_ACLR_A NONE " "Parameter INDATA_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712551516726 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WRCONTROL_ACLR_A NONE " "Parameter WRCONTROL_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712551516726 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "INIT_FILE db/chip8.ram0_memory_e9e85012.hdl.mif " "Parameter INIT_FILE set to db/chip8.ram0_memory_e9e85012.hdl.mif" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712551516726 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "READ_DURING_WRITE_MODE_MIXED_PORTS OLD_DATA " "Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712551516726 ""} } { } 0 276029 "Inferred altsyncram megafunction from the following design logic: \"%1!s!\" " 0 0 "Design Software" 0 -1 1712551516726 ""} } { } 0 19000 "Inferred %1!d! megafunctions from design logic" 0 0 "Analysis & Synthesis" 0 -1 1712551516726 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "memory:mem\|altsyncram:mem_rtl_0 " "Elaborated megafunction instantiation \"memory:mem\|altsyncram:mem_rtl_0\"" { } { } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712551516773 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "memory:mem\|altsyncram:mem_rtl_0 " "Instantiated megafunction \"memory:mem\|altsyncram:mem_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "OPERATION_MODE DUAL_PORT " "Parameter \"OPERATION_MODE\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712551516773 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_A 8 " "Parameter \"WIDTH_A\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712551516773 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_A 12 " "Parameter \"WIDTHAD_A\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712551516773 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_A 4096 " "Parameter \"NUMWORDS_A\" = \"4096\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712551516773 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_B 8 " "Parameter \"WIDTH_B\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712551516773 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_B 12 " "Parameter \"WIDTHAD_B\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712551516773 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_B 4096 " "Parameter \"NUMWORDS_B\" = \"4096\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712551516773 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_A NONE " "Parameter \"ADDRESS_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712551516773 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_REG_B UNREGISTERED " "Parameter \"OUTDATA_REG_B\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712551516773 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_B NONE " "Parameter \"ADDRESS_ACLR_B\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712551516773 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_ACLR_B NONE " "Parameter \"OUTDATA_ACLR_B\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712551516773 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_REG_B CLOCK0 " "Parameter \"ADDRESS_REG_B\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712551516773 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INDATA_ACLR_A NONE " "Parameter \"INDATA_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712551516773 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WRCONTROL_ACLR_A NONE " "Parameter \"WRCONTROL_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712551516773 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INIT_FILE db/chip8.ram0_memory_e9e85012.hdl.mif " "Parameter \"INIT_FILE\" = \"db/chip8.ram0_memory_e9e85012.hdl.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712551516773 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "READ_DURING_WRITE_MODE_MIXED_PORTS OLD_DATA " "Parameter \"READ_DURING_WRITE_MODE_MIXED_PORTS\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712551516773 ""} } { } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1712551516773 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_dsq1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_dsq1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_dsq1 " "Found entity 1: altsyncram_dsq1" { } { { "db/altsyncram_dsq1.tdf" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/db/altsyncram_dsq1.tdf" 28 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712551516796 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712551516796 ""}
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "led\[5\] VCC " "Pin \"led\[5\]\" is stuck at VCC" { } { { "chip8.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/chip8.sv" 7 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1712551532666 "|chip8|led[5]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1712551532666 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1712551533595 ""}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "4 " "4 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1712551551646 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1712551552875 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712551552875 ""}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "1 " "Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "rst_in " "No output dependent on input pin \"rst_in\"" { } { { "chip8.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/chip8.sv" 3 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1712551553790 "|chip8|rst_in"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1712551553790 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "17374 " "Implemented 17374 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Implemented 2 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1712551553847 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1712551553847 ""} { "Info" "ICUT_CUT_TM_LCELLS" "17356 " "Implemented 17356 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1712551553847 ""} { "Info" "ICUT_CUT_TM_RAMS" "8 " "Implemented 8 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Design Software" 0 -1 1712551553847 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1712551553847 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 26 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 26 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "698 " "Peak virtual memory: 698 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1712551553879 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 7 23:45:53 2024 " "Processing ended: Sun Apr 7 23:45:53 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1712551553879 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:01:02 " "Elapsed time: 00:01:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1712551553879 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:01:46 " "Total CPU time (on all processors): 00:01:46" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1712551553879 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1712551553879 ""}

BIN
db/chip8.map.rdb
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db/chip8.map_bb.hdb
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db/chip8.pre_map.hdb
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db/chip8.root_partition.map.reg_db.cdb
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db/chip8.rtlv.hdb
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db/chip8.rtlv_sg.cdb
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db/chip8.rtlv_sg_swap.cdb
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2
db/chip8.smart_action.txt
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@ -1 +1 @@
SOURCE
DONE

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db/chip8.tis_db_list.ddb
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8
db/chip8.tmw_info
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@ -1,2 +1,6 @@
start_analysis_synthesis:s:01:10:32
start_analysis_elaboration:s
start_full_compilation:s:00:07:53
start_analysis_synthesis:s:00:01:03-start_full_compilation
start_analysis_elaboration:s-start_full_compilation
start_fitter:s:00:06:16-start_full_compilation
start_assembler:s:00:00:08-start_full_compilation
start_timing_analyzer:s:00:00:26-start_full_compilation

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db/chip8.vpr.ammdb
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2
db/chip8_partition_pins.json
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@ -32,7 +32,7 @@
"strict" : false
},
{
"name" : "clk_in",
"name" : "fpga_clk",
"strict" : false
}
]

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incremental_db/compiled_partitions/chip8.root_partition.map.cdb
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incremental_db/compiled_partitions/chip8.root_partition.map.dpi
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incremental_db/compiled_partitions/chip8.root_partition.map.hbdb.cdb
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incremental_db/compiled_partitions/chip8.root_partition.map.hbdb.hdb
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incremental_db/compiled_partitions/chip8.root_partition.map.hdb
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incremental_db/compiled_partitions/chip8.root_partition.map.kpt
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2
makefile
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@ -25,5 +25,5 @@ format:
build-fpga: *.sv *.qsf *.qpf rom.bin build-rom
quartus_sh --flow compile chip8 && ./make_cdf.sh
run-fpga: build-fpga
run-fpga:
quartus_pgm -m jtag -o "p;./output_files/chip8.sof" ./output_files/chip8.cdf

2
output_files/chip8.done
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@ -1 +1 @@
Sun Apr 7 17:30:03 2024
Sun Apr 7 23:52:44 2024

60
output_files/chip8.flow.rpt
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@ -1,5 +1,5 @@
Flow report for chip8
Sun Apr 7 23:38:38 2024
Sun Apr 7 23:52:43 2024
Quartus Prime Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition
@ -38,24 +38,29 @@ https://fpgasoftware.intel.com/eula.
+------------------------------------------------------------------------------+
; Flow Summary ;
+-----------------------------+------------------------------------------------+
; Flow Status ; Flow Failed - Sun Apr 7 23:38:38 2024 ;
; Quartus Prime Version ; 23.1std.0 Build 991 11/28/2023 SC Lite Edition ;
; Revision Name ; chip8 ;
; Top-level Entity Name ; chip8 ;
; Family ; Cyclone V ;
; Device ; 5CSEBA6U23I7 ;
; Timing Models ; Final ;
; Logic utilization (in ALMs) ; N/A until Partition Merge ;
; Total registers ; N/A until Partition Merge ;
; Total pins ; N/A until Partition Merge ;
; Total virtual pins ; N/A until Partition Merge ;
; Total block memory bits ; N/A until Partition Merge ;
; Total PLLs ; N/A until Partition Merge ;
; Total DLLs ; N/A until Partition Merge ;
+-----------------------------+------------------------------------------------+
+----------------------------------------------------------------------------------+
; Flow Summary ;
+---------------------------------+------------------------------------------------+
; Flow Status ; Successful - Sun Apr 7 23:52:17 2024 ;
; Quartus Prime Version ; 23.1std.0 Build 991 11/28/2023 SC Lite Edition ;
; Revision Name ; chip8 ;
; Top-level Entity Name ; chip8 ;
; Family ; Cyclone V ;
; Device ; 5CSEBA6U23I7 ;
; Timing Models ; Final ;
; Logic utilization (in ALMs) ; 10,549 / 41,910 ( 25 % ) ;
; Total registers ; 10004 ;
; Total pins ; 10 / 314 ( 3 % ) ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 32,768 / 5,662,720 ( < 1 % ) ;
; Total DSP Blocks ; 0 / 112 ( 0 % ) ;
; Total HSSI RX PCSs ; 0 ;
; Total HSSI PMA RX Deserializers ; 0 ;
; Total HSSI TX PCSs ; 0 ;
; Total HSSI PMA TX Serializers ; 0 ;
; Total PLLs ; 0 / 6 ( 0 % ) ;
; Total DLLs ; 0 / 4 ( 0 % ) ;
+---------------------------------+------------------------------------------------+
+-----------------------------------------+
@ -63,7 +68,7 @@ https://fpgasoftware.intel.com/eula.
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 04/07/2024 23:38:32 ;
; Start date & time ; 04/07/2024 23:44:51 ;
; Main task ; Compilation ;
; Revision Name ; chip8 ;
+-------------------+---------------------+
@ -74,7 +79,7 @@ https://fpgasoftware.intel.com/eula.
+-------------------------------------+----------------------------------------+---------------+-------------+----------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+----------------------------------------+---------------+-------------+----------------+
; COMPILER_SIGNATURE_ID ; 346662554261.171255111264037 ; -- ; -- ; -- ;
; COMPILER_SIGNATURE_ID ; 346662554261.171255149111146 ; -- ; -- ; -- ;
; EDA_OUTPUT_DATA_FORMAT ; None ; -- ; -- ; eda_simulation ;
; MAX_CORE_JUNCTION_TEMP ; 100 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; -40 ; -- ; -- ; -- ;
@ -92,8 +97,11 @@ https://fpgasoftware.intel.com/eula.
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:06 ; 1.0 ; 383 MB ; 00:00:14 ;
; Total ; 00:00:06 ; -- ; -- ; 00:00:14 ;
; Analysis & Synthesis ; 00:01:01 ; 3.7 ; 698 MB ; 00:01:45 ;
; Fitter ; 00:06:11 ; 1.6 ; 2797 MB ; 00:14:15 ;
; Assembler ; 00:00:07 ; 1.0 ; 631 MB ; 00:00:07 ;
; Timing Analyzer ; 00:00:25 ; 5.7 ; 1353 MB ; 00:01:44 ;
; Total ; 00:07:44 ; -- ; -- ; 00:17:51 ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
@ -103,6 +111,9 @@ https://fpgasoftware.intel.com/eula.
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+----------------------+------------------+-------------------+-------------------+----------------+
; Analysis & Synthesis ; broad-street ; EndeavourOS Linux ; EndeavourOS Linux ; x86_64 ;
; Fitter ; broad-street ; EndeavourOS Linux ; EndeavourOS Linux ; x86_64 ;
; Assembler ; broad-street ; EndeavourOS Linux ; EndeavourOS Linux ; x86_64 ;
; Timing Analyzer ; broad-street ; EndeavourOS Linux ; EndeavourOS Linux ; x86_64 ;
+----------------------+------------------+-------------------+-------------------+----------------+
@ -110,6 +121,9 @@ https://fpgasoftware.intel.com/eula.
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off chip8 -c chip8
quartus_fit --read_settings_files=off --write_settings_files=off chip8 -c chip8
quartus_asm --read_settings_files=off --write_settings_files=off chip8 -c chip8
quartus_sta chip8 -c chip8

537
output_files/chip8.map.rpt
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@ -1,5 +1,5 @@
Analysis & Synthesis report for chip8
Sun Apr 7 23:38:38 2024
Sun Apr 7 23:45:53 2024
Quartus Prime Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition
@ -10,7 +10,25 @@ Quartus Prime Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Parallel Compilation
5. Analysis & Synthesis Messages
5. Analysis & Synthesis Source Files Read
6. Analysis & Synthesis Resource Usage Summary
7. Analysis & Synthesis Resource Utilization by Entity
8. Analysis & Synthesis RAM Summary
9. Registers Removed During Synthesis
10. Removed Registers Triggering Further Register Optimizations
11. General Register Statistics
12. Inverted Register Statistics
13. Registers Packed Into Inferred Megafunctions
14. Multiplexer Restructuring Statistics (Restructuring Performed)
15. Source assignments for memory:mem|altsyncram:mem_rtl_0|altsyncram_dsq1:auto_generated
16. Parameter Settings for User Entity Instance: memory:mem
17. Parameter Settings for Inferred Entity Instance: memory:mem|altsyncram:mem_rtl_0
18. altsyncram Parameter Settings by Entity Instance
19. Port Connectivity Checks: "cpu:cpu|st7920_serial_driver:gpu"
20. Port Connectivity Checks: "cpu:cpu"
21. Post-Synthesis Netlist Statistics for Top Partition
22. Elapsed Time Per Partition
23. Analysis & Synthesis Messages
@ -34,22 +52,27 @@ https://fpgasoftware.intel.com/eula.
+------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+------------------------------------------------+
; Analysis & Synthesis Status ; Failed - Sun Apr 7 23:38:38 2024 ;
; Quartus Prime Version ; 23.1std.0 Build 991 11/28/2023 SC Lite Edition ;
; Revision Name ; chip8 ;
; Top-level Entity Name ; chip8 ;
; Family ; Cyclone V ;
; Logic utilization (in ALMs) ; N/A until Partition Merge ;
; Total registers ; N/A until Partition Merge ;
; Total pins ; N/A until Partition Merge ;
; Total virtual pins ; N/A until Partition Merge ;
; Total block memory bits ; N/A until Partition Merge ;
; Total PLLs ; N/A until Partition Merge ;
; Total DLLs ; N/A until Partition Merge ;
+-----------------------------+------------------------------------------------+
+----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+---------------------------------+------------------------------------------------+
; Analysis & Synthesis Status ; Successful - Sun Apr 7 23:45:53 2024 ;
; Quartus Prime Version ; 23.1std.0 Build 991 11/28/2023 SC Lite Edition ;
; Revision Name ; chip8 ;
; Top-level Entity Name ; chip8 ;
; Family ; Cyclone V ;
; Logic utilization (in ALMs) ; N/A ;
; Total registers ; 8728 ;
; Total pins ; 10 ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 32,768 ;
; Total DSP Blocks ; 0 ;
; Total HSSI RX PCSs ; 0 ;
; Total HSSI PMA RX Deserializers ; 0 ;
; Total HSSI TX PCSs ; 0 ;
; Total HSSI PMA TX Serializers ; 0 ;
; Total PLLs ; 0 ;
; Total DLLs ; 0 ;
+---------------------------------+------------------------------------------------+
+---------------------------------------------------------------------------------------------------------------------------+
@ -147,45 +170,481 @@ https://fpgasoftware.intel.com/eula.
; Number detected on machine ; 12 ;
; Maximum allowed ; 12 ;
; ; ;
; Average used ; 1.00 ;
; Maximum used ; 1 ;
; Average used ; 3.71 ;
; Maximum used ; 12 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
; Processor 2 ; 48.5% ;
; Processor 3 ; 48.3% ;
; Processor 4 ; 24.0% ;
; Processor 5 ; 24.0% ;
; Processor 6 ; 24.0% ;
; Processor 7 ; 19.2% ;
; Processor 8 ; 19.2% ;
; Processor 9 ; 19.2% ;
; Processor 10 ; 18.8% ;
; Processor 11 ; 18.8% ;
; Processor 12 ; 7.5% ;
+----------------------------+-------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+---------------------------------------+-----------------+-------------------------------------------------------+----------------------------------------------------------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
+---------------------------------------+-----------------+-------------------------------------------------------+----------------------------------------------------------------------------------------------+---------+
; the-bomb/st7920_serial_driver.sv ; yes ; User SystemVerilog HDL File ; /home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv ; ;
; chip8.sv ; yes ; User SystemVerilog HDL File ; /home/nickorlow/programming/school/warminster/yayacemu/chip8.sv ; ;
; cpu.sv ; yes ; User SystemVerilog HDL File ; /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv ; ;
; memory.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/nickorlow/programming/school/warminster/yayacemu/memory.sv ; ;
; rom.bin ; yes ; Auto-Found Unspecified File ; /home/nickorlow/programming/school/warminster/yayacemu/rom.bin ; ;
; fontset.bin ; yes ; Auto-Found Unspecified File ; /home/nickorlow/programming/school/warminster/yayacemu/fontset.bin ; ;
; altsyncram.tdf ; yes ; Megafunction ; /opt/intelFPGA/23.1/quartus/libraries/megafunctions/altsyncram.tdf ; ;
; stratix_ram_block.inc ; yes ; Megafunction ; /opt/intelFPGA/23.1/quartus/libraries/megafunctions/stratix_ram_block.inc ; ;
; lpm_mux.inc ; yes ; Megafunction ; /opt/intelFPGA/23.1/quartus/libraries/megafunctions/lpm_mux.inc ; ;
; lpm_decode.inc ; yes ; Megafunction ; /opt/intelFPGA/23.1/quartus/libraries/megafunctions/lpm_decode.inc ; ;
; aglobal231.inc ; yes ; Megafunction ; /opt/intelFPGA/23.1/quartus/libraries/megafunctions/aglobal231.inc ; ;
; a_rdenreg.inc ; yes ; Megafunction ; /opt/intelFPGA/23.1/quartus/libraries/megafunctions/a_rdenreg.inc ; ;
; altrom.inc ; yes ; Megafunction ; /opt/intelFPGA/23.1/quartus/libraries/megafunctions/altrom.inc ; ;
; altram.inc ; yes ; Megafunction ; /opt/intelFPGA/23.1/quartus/libraries/megafunctions/altram.inc ; ;
; altdpram.inc ; yes ; Megafunction ; /opt/intelFPGA/23.1/quartus/libraries/megafunctions/altdpram.inc ; ;
; db/altsyncram_dsq1.tdf ; yes ; Auto-Generated Megafunction ; /home/nickorlow/programming/school/warminster/yayacemu/db/altsyncram_dsq1.tdf ; ;
; db/chip8.ram0_memory_e9e85012.hdl.mif ; yes ; Auto-Generated Auto-Found Memory Initialization File ; /home/nickorlow/programming/school/warminster/yayacemu/db/chip8.ram0_memory_e9e85012.hdl.mif ; ;
+---------------------------------------+-----------------+-------------------------------------------------------+----------------------------------------------------------------------------------------------+---------+
+--------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+----------------+
; Resource ; Usage ;
+---------------------------------------------+----------------+
; Estimate of Logic utilization (ALMs needed) ; 10412 ;
; ; ;
; Combinational ALUT usage for logic ; 17065 ;
; -- 7 input functions ; 58 ;
; -- 6 input functions ; 3654 ;
; -- 5 input functions ; 5900 ;
; -- 4 input functions ; 2000 ;
; -- <=3 input functions ; 5453 ;
; ; ;
; Dedicated logic registers ; 8728 ;
; ; ;
; I/O pins ; 10 ;
; Total MLAB memory bits ; 0 ;
; Total block memory bits ; 32768 ;
; ; ;
; Total DSP Blocks ; 0 ;
; ; ;
; Maximum fan-out node ; fpga_clk~input ;
; Maximum fan-out ; 8564 ;
; Total fan-out ; 102143 ;
; Average fan-out ; 3.96 ;
+---------------------------------------------+----------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+-------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+-----------------------------------------------------------------------+----------------------+--------------+
; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
+-------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+-----------------------------------------------------------------------+----------------------+--------------+
; |chip8 ; 17065 (1) ; 8728 (0) ; 32768 ; 0 ; 10 ; 0 ; |chip8 ; chip8 ; work ;
; |cpu:cpu| ; 17064 (11448) ; 8728 (8546) ; 0 ; 0 ; 0 ; 0 ; |chip8|cpu:cpu ; cpu ; work ;
; |st7920_serial_driver:gpu| ; 5616 (5570) ; 182 (129) ; 0 ; 0 ; 0 ; 0 ; |chip8|cpu:cpu|st7920_serial_driver:gpu ; st7920_serial_driver ; work ;
; |commander:com| ; 46 (46) ; 53 (53) ; 0 ; 0 ; 0 ; 0 ; |chip8|cpu:cpu|st7920_serial_driver:gpu|commander:com ; commander ; work ;
; |memory:mem| ; 0 (0) ; 0 (0) ; 32768 ; 0 ; 0 ; 0 ; |chip8|memory:mem ; memory ; work ;
; |altsyncram:mem_rtl_0| ; 0 (0) ; 0 (0) ; 32768 ; 0 ; 0 ; 0 ; |chip8|memory:mem|altsyncram:mem_rtl_0 ; altsyncram ; work ;
; |altsyncram_dsq1:auto_generated| ; 0 (0) ; 0 (0) ; 32768 ; 0 ; 0 ; 0 ; |chip8|memory:mem|altsyncram:mem_rtl_0|altsyncram_dsq1:auto_generated ; altsyncram_dsq1 ; work ;
+-------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+-----------------------------------------------------------------------+----------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ;
+---------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+---------------------------------------+
; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
+---------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+---------------------------------------+
; memory:mem|altsyncram:mem_rtl_0|altsyncram_dsq1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 4096 ; 8 ; 4096 ; 8 ; 32768 ; db/chip8.ram0_memory_e9e85012.hdl.mif ;
+---------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+---------------------------------------+
+----------------------------------------------------------------------------------------------------------------------+
; Registers Removed During Synthesis ;
+------------------------------------------------------------------------+---------------------------------------------+
; Register name ; Reason for Removal ;
+------------------------------------------------------------------------+---------------------------------------------+
; cpu:cpu|st7920_serial_driver:gpu|d_flip_flop:dff|data_out ; Stuck at VCC due to stuck port data_in ;
; cpu:cpu|wr_memory_address[0..11] ; Stuck at GND due to stuck port data_in ;
; cpu:cpu|instr.src_sprite_sz[4] ; Stuck at GND due to stuck port data_in ;
; cpu:cpu|instr.src_sprite_y[5..7] ; Stuck at GND due to stuck port data_in ;
; cpu:cpu|instr.src_sprite_x[6,7] ; Stuck at GND due to stuck port data_in ;
; cpu:cpu|instr.dst[1..31] ; Stuck at GND due to stuck port data_in ;
; cpu:cpu|instr.op[2..31] ; Stuck at GND due to stuck port data_in ;
; cpu:cpu|wr_memory_data[0..7] ; Stuck at GND due to stuck port clock_enable ;
; cpu:cpu|draw_state.stage[1..9,11..31] ; Merged with cpu:cpu|draw_state.stage[10] ;
; cpu:cpu|state[4..9,11..31] ; Merged with cpu:cpu|state[10] ;
; cpu:cpu|instr.src[3..31] ; Merged with cpu:cpu|instr.src[0] ;
; cpu:cpu|st7920_serial_driver:gpu|command[8] ; Stuck at GND due to stuck port data_in ;
; cpu:cpu|st7920_serial_driver:gpu|commander:com|full_command_bits[0..3] ; Stuck at GND due to stuck port data_in ;
; cpu:cpu|wr_go ; Stuck at GND due to stuck port data_in ;
; cpu:cpu|draw_state.stage[10] ; Stuck at GND due to stuck port data_in ;
; cpu:cpu|instr.src[0] ; Stuck at GND due to stuck port data_in ;
; cpu:cpu|state[10] ; Stuck at GND due to stuck port data_in ;
; cpu:cpu|program_counter[12..15] ; Lost fanout ;
; Total Number of Removed Registers = 187 ; ;
+------------------------------------------------------------------------+---------------------------------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Removed Registers Triggering Further Register Optimizations ;
+---------------------------------------------------------------------+---------------------------+----------------------------------------------------------------------------------+
; Register name ; Reason for Removal ; Registers Removed due to This Register ;
+---------------------------------------------------------------------+---------------------------+----------------------------------------------------------------------------------+
; cpu:cpu|instr.dst[1] ; Stuck at GND ; cpu:cpu|wr_memory_data[7], cpu:cpu|wr_memory_data[6], cpu:cpu|wr_memory_data[5], ;
; ; due to stuck port data_in ; cpu:cpu|wr_memory_data[4], cpu:cpu|wr_memory_data[3], cpu:cpu|wr_memory_data[2], ;
; ; ; cpu:cpu|wr_memory_data[1], cpu:cpu|wr_memory_data[0], cpu:cpu|wr_go ;
; cpu:cpu|instr.src_sprite_sz[4] ; Stuck at GND ; cpu:cpu|instr.src_sprite_y[5], cpu:cpu|instr.src_sprite_y[6], ;
; ; due to stuck port data_in ; cpu:cpu|instr.src_sprite_y[7], cpu:cpu|instr.src_sprite_x[6], ;
; ; ; cpu:cpu|instr.src_sprite_x[7], cpu:cpu|draw_state.stage[10], cpu:cpu|state[10] ;
; cpu:cpu|st7920_serial_driver:gpu|commander:com|full_command_bits[0] ; Stuck at GND ; cpu:cpu|st7920_serial_driver:gpu|commander:com|full_command_bits[1], ;
; ; due to stuck port data_in ; cpu:cpu|st7920_serial_driver:gpu|commander:com|full_command_bits[2], ;
; ; ; cpu:cpu|st7920_serial_driver:gpu|commander:com|full_command_bits[3] ;
; cpu:cpu|st7920_serial_driver:gpu|d_flip_flop:dff|data_out ; Stuck at VCC ; cpu:cpu|st7920_serial_driver:gpu|command[8] ;
; ; due to stuck port data_in ; ;
+---------------------------------------------------------------------+---------------------------+----------------------------------------------------------------------------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 8728 ;
; Number of registers using Synchronous Clear ; 118 ;
; Number of registers using Synchronous Load ; 29 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 8631 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+--------------------------------------------------+
; Inverted Register Statistics ;
+----------------------------------------+---------+
; Inverted Register ; Fan out ;
+----------------------------------------+---------+
; cpu:cpu|program_counter[9] ; 5 ;
; Total number of inverted registers = 1 ; ;
+----------------------------------------+---------+
+---------------------------------------------------------+
; Registers Packed Into Inferred Megafunctions ;
+---------------------------+----------------------+------+
; Register Name ; Megafunction ; Type ;
+---------------------------+----------------------+------+
; memory:mem|data_out[0..7] ; memory:mem|mem_rtl_0 ; RAM ;
+---------------------------+----------------------+------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------------------+
; 3:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|commander:com|full_command_bits[22] ;
; 3:1 ; 8 bits ; 16 LEs ; 0 LEs ; 16 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|commander:com|full_command_bits[17] ;
; 3:1 ; 38 bits ; 76 LEs ; 0 LEs ; 76 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|commander:com|i[9] ;
; 4:1 ; 32 bits ; 64 LEs ; 0 LEs ; 64 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|line_cnt[23] ;
; 4:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|x[5] ;
; 4:1 ; 7 bits ; 14 LEs ; 7 LEs ; 7 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|y[6] ;
; 5:1 ; 32 bits ; 96 LEs ; 32 LEs ; 64 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|i[1] ;
; 1029:1 ; 2 bits ; 1372 LEs ; 1368 LEs ; 4 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|command[6] ;
; 1059:1 ; 5 bits ; 3530 LEs ; 3445 LEs ; 85 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|command[5] ;
; 3:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; Yes ; |chip8|cpu:cpu|draw_state.r[4] ;
; 4:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; Yes ; |chip8|cpu:cpu|draw_state.c[1] ;
; 16:1 ; 5 bits ; 50 LEs ; 50 LEs ; 0 LEs ; Yes ; |chip8|cpu:cpu|instr.src_sprite_y[4] ;
; 16:1 ; 6 bits ; 60 LEs ; 60 LEs ; 0 LEs ; Yes ; |chip8|cpu:cpu|instr.src_sprite_x[2] ;
; 4:1 ; 12 bits ; 24 LEs ; 0 LEs ; 24 LEs ; Yes ; |chip8|cpu:cpu|rd_memory_address[3] ;
; 5:1 ; 5 bits ; 15 LEs ; 5 LEs ; 10 LEs ; Yes ; |chip8|cpu:cpu|instr.src_sprite_idx[1] ;
; 5:1 ; 6 bits ; 18 LEs ; 6 LEs ; 12 LEs ; Yes ; |chip8|cpu:cpu|instr.src_byte[9] ;
; 5:1 ; 2 bits ; 6 LEs ; 2 LEs ; 4 LEs ; Yes ; |chip8|cpu:cpu|draw_state.stage[10] ;
; 6:1 ; 8 bits ; 32 LEs ; 0 LEs ; 32 LEs ; Yes ; |chip8|cpu:cpu|instr.src_byte[2] ;
; 6:1 ; 6 bits ; 24 LEs ; 12 LEs ; 12 LEs ; Yes ; |chip8|cpu:cpu|registers[15][5] ;
; 10:1 ; 4 bits ; 24 LEs ; 8 LEs ; 16 LEs ; Yes ; |chip8|cpu:cpu|program_counter[15] ;
; 10:1 ; 10 bits ; 60 LEs ; 20 LEs ; 40 LEs ; Yes ; |chip8|cpu:cpu|program_counter[1] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------------------+
+---------------------------------------------------------------------------------------+
; Source assignments for memory:mem|altsyncram:mem_rtl_0|altsyncram_dsq1:auto_generated ;
+---------------------------------+--------------------+------+-------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+-------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+-------------------------+
+---------------------------------------------------------+
; Parameter Settings for User Entity Instance: memory:mem ;
+----------------+-------+--------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+--------------------------------+
; RAM_SIZE_BYTES ; 4096 ; Signed Integer ;
+----------------+-------+--------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+---------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: memory:mem|altsyncram:mem_rtl_0 ;
+------------------------------------+---------------------------------------+----------------+
; Parameter Name ; Value ; Type ;
+------------------------------------+---------------------------------------+----------------+
; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; WIDTH_BYTEENA ; 1 ; Untyped ;
; OPERATION_MODE ; DUAL_PORT ; Untyped ;
; WIDTH_A ; 8 ; Untyped ;
; WIDTHAD_A ; 12 ; Untyped ;
; NUMWORDS_A ; 4096 ; Untyped ;
; OUTDATA_REG_A ; UNREGISTERED ; Untyped ;
; ADDRESS_ACLR_A ; NONE ; Untyped ;
; OUTDATA_ACLR_A ; NONE ; Untyped ;
; WRCONTROL_ACLR_A ; NONE ; Untyped ;
; INDATA_ACLR_A ; NONE ; Untyped ;
; BYTEENA_ACLR_A ; NONE ; Untyped ;
; WIDTH_B ; 8 ; Untyped ;
; WIDTHAD_B ; 12 ; Untyped ;
; NUMWORDS_B ; 4096 ; Untyped ;
; INDATA_REG_B ; CLOCK1 ; Untyped ;
; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
; ADDRESS_REG_B ; CLOCK0 ; Untyped ;
; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
; INDATA_ACLR_B ; NONE ; Untyped ;
; WRCONTROL_ACLR_B ; NONE ; Untyped ;
; ADDRESS_ACLR_B ; NONE ; Untyped ;
; OUTDATA_ACLR_B ; NONE ; Untyped ;
; RDCONTROL_ACLR_B ; NONE ; Untyped ;
; BYTEENA_ACLR_B ; NONE ; Untyped ;
; WIDTH_BYTEENA_A ; 1 ; Untyped ;
; WIDTH_BYTEENA_B ; 1 ; Untyped ;
; RAM_BLOCK_TYPE ; AUTO ; Untyped ;
; BYTE_SIZE ; 8 ; Untyped ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA ; Untyped ;
; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ;
; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ;
; INIT_FILE ; db/chip8.ram0_memory_e9e85012.hdl.mif ; Untyped ;
; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
; MAXIMUM_DEPTH ; 0 ; Untyped ;
; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ;
; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ;
; ENABLE_ECC ; FALSE ; Untyped ;
; ECC_PIPELINE_STAGE_ENABLED ; FALSE ; Untyped ;
; WIDTH_ECCSTATUS ; 3 ; Untyped ;
; DEVICE_FAMILY ; Cyclone V ; Untyped ;
; CBXI_PARAMETER ; altsyncram_dsq1 ; Untyped ;
+------------------------------------+---------------------------------------+----------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-----------------------------------------------------------------------------+
; altsyncram Parameter Settings by Entity Instance ;
+-------------------------------------------+---------------------------------+
; Name ; Value ;
+-------------------------------------------+---------------------------------+
; Number of entity instances ; 1 ;
; Entity Instance ; memory:mem|altsyncram:mem_rtl_0 ;
; -- OPERATION_MODE ; DUAL_PORT ;
; -- WIDTH_A ; 8 ;
; -- NUMWORDS_A ; 4096 ;
; -- OUTDATA_REG_A ; UNREGISTERED ;
; -- WIDTH_B ; 8 ;
; -- NUMWORDS_B ; 4096 ;
; -- ADDRESS_REG_B ; CLOCK0 ;
; -- OUTDATA_REG_B ; UNREGISTERED ;
; -- RAM_BLOCK_TYPE ; AUTO ;
; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA ;
+-------------------------------------------+---------------------------------+
+--------------------------------------------------------------+
; Port Connectivity Checks: "cpu:cpu|st7920_serial_driver:gpu" ;
+--------------+-------+----------+----------------------------+
; Port ; Type ; Severity ; Details ;
+--------------+-------+----------+----------------------------+
; sys_rst_n_ms ; Input ; Info ; Stuck at VCC ;
+--------------+-------+----------+----------------------------+
+-------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "cpu:cpu" ;
+---------------+--------+----------+-------------------------------------------------------------------------------------+
; Port ; Type ; Severity ; Details ;
+---------------+--------+----------+-------------------------------------------------------------------------------------+
; cycle_counter ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+---------------+--------+----------+-------------------------------------------------------------------------------------+
+-----------------------------------------------------+
; Post-Synthesis Netlist Statistics for Top Partition ;
+-----------------------+-----------------------------+
; Type ; Count ;
+-----------------------+-----------------------------+
; arriav_ff ; 8728 ;
; ENA ; 8526 ;
; ENA SCLR ; 77 ;
; ENA SLD ; 28 ;
; SCLR ; 41 ;
; SLD ; 1 ;
; plain ; 55 ;
; arriav_lcell_comb ; 17066 ;
; arith ; 257 ;
; 0 data inputs ; 7 ;
; 1 data inputs ; 229 ;
; 2 data inputs ; 17 ;
; 3 data inputs ; 1 ;
; 4 data inputs ; 1 ;
; 5 data inputs ; 2 ;
; extend ; 58 ;
; 7 data inputs ; 58 ;
; normal ; 16745 ;
; 0 data inputs ; 2 ;
; 1 data inputs ; 1 ;
; 2 data inputs ; 176 ;
; 3 data inputs ; 5015 ;
; 4 data inputs ; 1999 ;
; 5 data inputs ; 5898 ;
; 6 data inputs ; 3654 ;
; shared ; 6 ;
; 2 data inputs ; 6 ;
; boundary_port ; 10 ;
; stratixv_ram_block ; 8 ;
; ; ;
; Max LUT depth ; 55.00 ;
; Average LUT depth ; 17.90 ;
+-----------------------+-----------------------------+
+-------------------------------+
; Elapsed Time Per Partition ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top ; 00:00:53 ;
+----------------+--------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
Info: Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition
Info: Processing started: Sun Apr 7 23:38:32 2024
Info: Processing started: Sun Apr 7 23:44:51 2024
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off chip8 -c chip8
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 12 of the 12 processors detected
Critical Warning (10191): Verilog HDL Compiler Directive warning at st7920_serial_driver.sv(12): text macro "DELAY_BITS" is undefined File: /home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv Line: 12
Error (10170): Verilog HDL syntax error at st7920_serial_driver.sv(12) near text: ":"; expecting an operand. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. File: /home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv Line: 12
Critical Warning (10191): Verilog HDL Compiler Directive warning at st7920_serial_driver.sv(64): text macro "BOOTSTRAP_INSTRS" is undefined File: /home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv Line: 64
Error (10170): Verilog HDL syntax error at st7920_serial_driver.sv(64) near text: ")"; expecting an operand. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. File: /home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv Line: 64
Error (10170): Verilog HDL syntax error at st7920_serial_driver.sv(70) near text: "else"; expecting "end". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. File: /home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv Line: 70
Error (10170): Verilog HDL syntax error at st7920_serial_driver.sv(94) near text: ")"; expecting an operand. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. File: /home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv Line: 94
Error (10170): Verilog HDL syntax error at st7920_serial_driver.sv(97) near text: ")"; expecting an operand. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. File: /home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv Line: 97
Error (10170): Verilog HDL syntax error at st7920_serial_driver.sv(124) near text: "]"; expecting an operand. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. File: /home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv Line: 124
Error (10170): Verilog HDL syntax error at st7920_serial_driver.sv(127) near text: "else"; expecting "end". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. File: /home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv Line: 127
Error (10112): Ignored design unit "st7920_serial_driver" at st7920_serial_driver.sv(1) due to previous errors File: /home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv Line: 1
Error (10112): Ignored design unit "d_flip_flop" at st7920_serial_driver.sv(134) due to previous errors File: /home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv Line: 134
Error (10112): Ignored design unit "commander" at st7920_serial_driver.sv(144) due to previous errors File: /home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv Line: 144
Info (12021): Found 0 design units, including 0 entities, in source file the-bomb/st7920_serial_driver.sv
Info (12021): Found 3 design units, including 3 entities, in source file the-bomb/st7920_serial_driver.sv
Info (12023): Found entity 1: st7920_serial_driver File: /home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv Line: 4
Info (12023): Found entity 2: d_flip_flop File: /home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv Line: 137
Info (12023): Found entity 3: commander File: /home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv Line: 147
Info (12021): Found 1 design units, including 1 entities, in source file chip8.sv
Info (12023): Found entity 1: chip8 File: /home/nickorlow/programming/school/warminster/yayacemu/chip8.sv Line: 1
Info (12021): Found 1 design units, including 1 entities, in source file cpu.sv
Info (12023): Found entity 1: cpu File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 1
Error: Quartus Prime Analysis & Synthesis was unsuccessful. 10 errors, 3 warnings
Error: Peak virtual memory: 383 megabytes
Error: Processing ended: Sun Apr 7 23:38:38 2024
Error: Elapsed time: 00:00:06
Error: Total CPU time (on all processors): 00:00:14
Info (12127): Elaborating entity "chip8" for the top level hierarchy
Warning (12125): Using design file memory.sv, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info (12023): Found entity 1: memory File: /home/nickorlow/programming/school/warminster/yayacemu/memory.sv Line: 1
Info (12128): Elaborating entity "memory" for hierarchy "memory:mem" File: /home/nickorlow/programming/school/warminster/yayacemu/chip8.sv Line: 21
Warning (10850): Verilog HDL warning at memory.sv(14): number of words (80) in memory file does not match the number of elements in the address range [0:4095] File: /home/nickorlow/programming/school/warminster/yayacemu/memory.sv Line: 14
Warning (10850): Verilog HDL warning at memory.sv(15): number of words (260) in memory file does not match the number of elements in the address range [512:4095] File: /home/nickorlow/programming/school/warminster/yayacemu/memory.sv Line: 15
Info (12128): Elaborating entity "cpu" for hierarchy "cpu:cpu" File: /home/nickorlow/programming/school/warminster/yayacemu/chip8.sv Line: 35
Warning (10230): Verilog HDL assignment warning at cpu.sv(124): truncated value with size 32 to match size of target (16) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 124
Warning (10230): Verilog HDL assignment warning at cpu.sv(130): truncated value with size 32 to match size of target (16) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 130
Warning (10230): Verilog HDL assignment warning at cpu.sv(147): truncated value with size 32 to match size of target (16) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 147
Warning (10230): Verilog HDL assignment warning at cpu.sv(210): truncated value with size 32 to match size of target (5) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 210
Warning (10230): Verilog HDL assignment warning at cpu.sv(213): truncated value with size 32 to match size of target (5) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 213
Warning (10230): Verilog HDL assignment warning at cpu.sv(242): truncated value with size 32 to match size of target (16) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 242
Warning (10230): Verilog HDL assignment warning at cpu.sv(246): truncated value with size 32 to match size of target (5) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 246
Warning (10230): Verilog HDL assignment warning at cpu.sv(257): truncated value with size 32 to match size of target (5) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 257
Warning (10230): Verilog HDL assignment warning at cpu.sv(284): truncated value with size 32 to match size of target (16) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 284
Warning (10030): Net "instr.src_reg" at cpu.sv(108) has no driver or initial value, using a default initial value '0' File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 108
Warning (10030): Net "instr.src_addr" at cpu.sv(108) has no driver or initial value, using a default initial value '0' File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 108
Warning (10030): Net "instr.dst_addr" at cpu.sv(108) has no driver or initial value, using a default initial value '0' File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 108
Info (12128): Elaborating entity "st7920_serial_driver" for hierarchy "cpu:cpu|st7920_serial_driver:gpu" File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 28
Warning (10036): Verilog HDL or VHDL warning at st7920_serial_driver.sv(23): object "line_idx" assigned a value but never read File: /home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv Line: 23
Warning (10230): Verilog HDL assignment warning at st7920_serial_driver.sv(71): truncated value with size 32 to match size of target (7) File: /home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv Line: 71
Warning (10230): Verilog HDL assignment warning at st7920_serial_driver.sv(84): truncated value with size 32 to match size of target (7) File: /home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv Line: 84
Warning (10230): Verilog HDL assignment warning at st7920_serial_driver.sv(103): truncated value with size 32 to match size of target (6) File: /home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv Line: 103
Warning (10230): Verilog HDL assignment warning at st7920_serial_driver.sv(131): truncated value with size 32 to match size of target (9) File: /home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv Line: 131
Warning (10030): Net "commands[6..10]" at st7920_serial_driver.sv(26) has no driver or initial value, using a default initial value '0' File: /home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv Line: 26
Info (12128): Elaborating entity "commander" for hierarchy "cpu:cpu|st7920_serial_driver:gpu|commander:com" File: /home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv Line: 42
Info (12128): Elaborating entity "d_flip_flop" for hierarchy "cpu:cpu|st7920_serial_driver:gpu|d_flip_flop:dff" File: /home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv Line: 50
Info (19000): Inferred 1 megafunctions from design logic
Info (276029): Inferred altsyncram megafunction from the following design logic: "memory:mem|mem_rtl_0"
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
Info (286033): Parameter WIDTH_A set to 8
Info (286033): Parameter WIDTHAD_A set to 12
Info (286033): Parameter NUMWORDS_A set to 4096
Info (286033): Parameter WIDTH_B set to 8
Info (286033): Parameter WIDTHAD_B set to 12
Info (286033): Parameter NUMWORDS_B set to 4096
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
Info (286033): Parameter INDATA_ACLR_A set to NONE
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
Info (286033): Parameter INIT_FILE set to db/chip8.ram0_memory_e9e85012.hdl.mif
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
Info (12130): Elaborated megafunction instantiation "memory:mem|altsyncram:mem_rtl_0"
Info (12133): Instantiated megafunction "memory:mem|altsyncram:mem_rtl_0" with the following parameter:
Info (12134): Parameter "OPERATION_MODE" = "DUAL_PORT"
Info (12134): Parameter "WIDTH_A" = "8"
Info (12134): Parameter "WIDTHAD_A" = "12"
Info (12134): Parameter "NUMWORDS_A" = "4096"
Info (12134): Parameter "WIDTH_B" = "8"
Info (12134): Parameter "WIDTHAD_B" = "12"
Info (12134): Parameter "NUMWORDS_B" = "4096"
Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE"
Info (12134): Parameter "OUTDATA_REG_B" = "UNREGISTERED"
Info (12134): Parameter "ADDRESS_ACLR_B" = "NONE"
Info (12134): Parameter "OUTDATA_ACLR_B" = "NONE"
Info (12134): Parameter "ADDRESS_REG_B" = "CLOCK0"
Info (12134): Parameter "INDATA_ACLR_A" = "NONE"
Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE"
Info (12134): Parameter "INIT_FILE" = "db/chip8.ram0_memory_e9e85012.hdl.mif"
Info (12134): Parameter "READ_DURING_WRITE_MODE_MIXED_PORTS" = "OLD_DATA"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_dsq1.tdf
Info (12023): Found entity 1: altsyncram_dsq1 File: /home/nickorlow/programming/school/warminster/yayacemu/db/altsyncram_dsq1.tdf Line: 28
Warning (13024): Output pins are stuck at VCC or GND
Warning (13410): Pin "led[5]" is stuck at VCC File: /home/nickorlow/programming/school/warminster/yayacemu/chip8.sv Line: 7
Info (286030): Timing-Driven Synthesis is running
Info (17049): 4 registers lost all their fanouts during netlist optimizations.
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
Warning (21074): Design contains 1 input pin(s) that do not drive logic
Warning (15610): No output dependent on input pin "rst_in" File: /home/nickorlow/programming/school/warminster/yayacemu/chip8.sv Line: 3
Info (21057): Implemented 17374 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 2 input pins
Info (21059): Implemented 8 output pins
Info (21061): Implemented 17356 logic cells
Info (21064): Implemented 8 RAM segments
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 26 warnings
Info: Peak virtual memory: 698 megabytes
Info: Processing ended: Sun Apr 7 23:45:53 2024
Info: Elapsed time: 00:01:02
Info: Total CPU time (on all processors): 00:01:46

21
output_files/chip8.map.summary
View file

@ -1,12 +1,17 @@
Analysis & Synthesis Status : Failed - Sun Apr 7 23:38:38 2024
Analysis & Synthesis Status : Successful - Sun Apr 7 23:45:53 2024
Quartus Prime Version : 23.1std.0 Build 991 11/28/2023 SC Lite Edition
Revision Name : chip8
Top-level Entity Name : chip8
Family : Cyclone V
Logic utilization (in ALMs) : N/A until Partition Merge
Total registers : N/A until Partition Merge
Total pins : N/A until Partition Merge
Total virtual pins : N/A until Partition Merge
Total block memory bits : N/A until Partition Merge
Total PLLs : N/A until Partition Merge
Total DLLs : N/A until Partition Merge
Logic utilization (in ALMs) : N/A
Total registers : 8728
Total pins : 10
Total virtual pins : 0
Total block memory bits : 32,768
Total DSP Blocks : 0
Total HSSI RX PCSs : 0
Total HSSI PMA RX Deserializers : 0
Total HSSI TX PCSs : 0
Total HSSI PMA TX Serializers : 0
Total PLLs : 0
Total DLLs : 0

2
the-bomb

@ -1 +1 @@
Subproject commit 69d8de45d344738425b88d9f8506a6c5c715a7ca
Subproject commit 6d88fb2756c80be38c1b35134dca0e66d74dbb94