30 lines
736 B
Makefile
30 lines
736 B
Makefile
.PHONY: run clean format
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SDL_CFLAGS = `sdl2-config --cflags`
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SDL_LDFLAGS = `sdl2-config --libs`
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SV_FILES=cpu.sv chip8.sv gpu.sv
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lint:
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verilator --lint-only -DDUMMY_GPU --timing ${SV_FILES}
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build-rom:
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python3 ./gen_rom.py ${ROM_FILE} rom.bin
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build: lint build-rom
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verilator --cc --exe --build --timing -j 0 --top-module chip8 *.sv yayacemu.cpp -DDUMMY_GPU -CFLAGS "${SDL_CFLAGS}" -LDFLAGS "${SDL_LDFLAGS}" && clear
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run: build
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obj_dir/Vchip8
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clean:
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rm -rf obj_dir
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format:
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verible-verilog-format *.sv --inplace && clang-format *.cpp -i
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build-fpga: *.sv *.qsf *.qpf rom.bin build-rom
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quartus_sh --flow compile chip8 && ./make_cdf.sh
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run-fpga:
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quartus_pgm -m jtag -o "p;./output_files/chip8.sof" ./output_files/chip8.cdf
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