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This commit is contained in:
Nicholas Orlowsky 2024-04-07 23:39:15 -05:00
parent fdd6553f11
commit f2c0935b60
Signed by: nickorlow
GPG key ID: 838827D8C4611687
128 changed files with 39530 additions and 530 deletions
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1
.nvim/svlangserver/index.json Normal file
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+incdir+/work
+incdir+/work/the-bomb
+incdir+/work
+incdir+/work/the-bomb

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beeper.sv
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module beeper (
input wire [7:0] sound_timer
);
import "DPI-C" function void set_beep(bit beep);
always_comb begin
set_beep(sound_timer > 0);
end
endmodule

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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2023 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition
# Date created = 19:42:33 April 05, 2024
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "23.1"
DATE = "19:42:33 April 05, 2024"
# Revisions
PROJECT_REVISION = "chip8"

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#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# st7920_driver_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Intel recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CSEBA6U23I7
set_global_assignment -name TOP_LEVEL_ENTITY chip8
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 23.1STD.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:27:46 FEBRUARY 02, 2024"
set_global_assignment -name LAST_QUARTUS_VERSION "23.1std.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name SYSTEMVERILOG_FILE "./the-bomb/st7920_serial_driver.sv"
set_global_assignment -name SYSTEMVERILOG_FILE chip8.sv
set_global_assignment -name SYSTEMVERILOG_FILE cpu.sv
set_global_assignment -name SDC_FILE chip8.sdc
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_location_assignment PIN_V11 -to clk_in
set_location_assignment PIN_D8 -to lcd_clk
set_location_assignment PIN_V12 -to lcd_cs
set_location_assignment PIN_W12 -to lcd_data
set_location_assignment PIN_AE26 -to led[5]
set_location_assignment PIN_AF26 -to led[4]
set_location_assignment PIN_V15 -to led[3]
set_location_assignment PIN_V16 -to led[2]
set_location_assignment PIN_AA24 -to led[1]
set_location_assignment PIN_W15 -to led[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_simulation
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to lcd_clock
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to lcd_cs
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to lcd_data
set_location_assignment PIN_W20 -to rst_in
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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chip8.sv
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module chip8 (
input wire clk_in,
input wire rst_in
input wire fpga_clk,
input wire rst_in,
output logic lcd_clk,
output logic lcd_data,
output logic [5:0] led
);
bit [7:0] vram[0:1023];
bit [7:0] memory[0:4095];
bit keyboard[15:0];
bit [7:0] sound_timer;
bit [15:0] program_counter;
logic [7:0] rd_memory_data;
logic [11:0] rd_memory_address;
logic [11:0] wr_memory_address;
logic [7:0] wr_memory_data;
logic wr_go;
memory #(4096) mem (
fpga_clk,
wr_go,
wr_memory_address,
wr_memory_data,
rd_memory_address,
rd_memory_data
);
int cycle_counter;
bit rom_ready;
bit font_ready;
bit system_ready;
bit halt;
bit [7:0] random_number;
and(system_ready, rom_ready, font_ready);
beeper beeper (sound_timer);
cpu cpu (
system_ready,
memory,
clk_in,
keyboard,
random_number,
fpga_clk,
rd_memory_data,
cycle_counter,
program_counter,
vram,
sound_timer
rd_memory_address,
wr_memory_address,
wr_memory_data,
wr_go,
lcd_clk,
lcd_data,
led
);
gpu gpu (vram);
keyboard kb (
clk_in,
keyboard
);
rng randy (
clk_in,
program_counter,
keyboard,
cycle_counter,
random_number
);
rom_loader loader (clk_in, rst_in, memory, rom_ready);
always_ff @(negedge clk_in) begin
if (~font_ready) begin
bit [7:0] fontset[79:0] = {
8'hF0,
8'h90,
8'h90,
8'h90,
8'hF0, // 0
8'h20,
8'h60,
8'h20,
8'h20,
8'h70, // 1
8'hF0,
8'h10,
8'hF0,
8'h80,
8'hF0, // 2
8'hF0,
8'h10,
8'hF0,
8'h10,
8'hF0, // 3
8'h90,
8'h90,
8'hF0,
8'h10,
8'h10, // 4
8'hF0,
8'h80,
8'hF0,
8'h10,
8'hF0, // 5
8'hF0,
8'h80,
8'hF0,
8'h90,
8'hF0, // 6
8'hF0,
8'h10,
8'h20,
8'h40,
8'h40, // 7
8'hF0,
8'h90,
8'hF0,
8'h90,
8'hF0, // 8
8'hF0,
8'h90,
8'hF0,
8'h10,
8'hF0, // 9
8'hF0,
8'h90,
8'hF0,
8'h90,
8'h90, // A
8'hE0,
8'h90,
8'hE0,
8'h90,
8'hE0, // B
8'hF0,
8'h80,
8'h80,
8'h80,
8'hF0, // C
8'hE0,
8'h90,
8'h90,
8'h90,
8'hE0, // D
8'hF0,
8'h80,
8'hF0,
8'h80,
8'hF0, // E
8'hF0,
8'h80,
8'hF0,
8'h80,
8'h80 // F
};
// Load fontset into memory
for (int i = 0; i < 80; i++) begin
memory[i] = fontset[79-i];
end
font_ready = 1;
end
end
endmodule

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module chip8 (
input wire clk_in,
input wire rst_in,
output logic lcd_clk,
output logic lcd_data,
output logic [5:0] led
);
bit [7:0] vram[0:1023];
bit [7:0] memory[0:4095];
bit keyboard[15:0];
bit [7:0] sound_timer;
bit [15:0] program_counter;
int cycle_counter;
bit rom_ready;
bit font_ready;
bit system_ready;
bit halt;
bit [7:0] random_number;
and(system_ready, rom_ready, font_ready);
cpu cpu (
system_ready,
memory,
clk_in,
keyboard,
random_number,
cycle_counter,
program_counter,
vram,
sound_timer
);
st7920_serial_driver gpu (clk_in, 1'b1, vram, lcd_clk, lcd_data, led);
rng randy (
clk_in,
program_counter,
keyboard,
cycle_counter,
random_number
);
initial begin
if (~font_ready) begin
$readmemh("fontset.bin", memory, 0);
$readmemb("rom.bin", memory, 'h200);
font_ready = 1;
rom_ready = 1;
end
end
endmodule

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module cpu (
input wire system_ready,
output bit [7:0] memory[0:4095],
input wire clk_in,
input wire keyboard[15:0],
input wire [7:0] random_number,
input wire [7:0] rd_memory_data,
output int cycle_counter,
output wire [15:0] program_counter,
output wire [7:0] vram[0:1023],
output wire [7:0] sound_timer
output logic [11:0] rd_memory_address,
output logic [11:0] wr_memory_address,
output logic [7:0] wr_memory_data,
output logic wr_go,
output logic lcd_clk,
output logic lcd_data,
output logic [5:0] led
);
bit halt;
int watch_key;
logic [7:0] vram [0:1023];
logic [15:0] stack[0:15];
logic [15:0] index_reg;
logic [3:0] stack_pointer;
logic [7:0] registers[0:15];
logic [15:0] opcode;
logic [7:0] delay_timer;
`ifdef DUMMY_GPU
gpu gpu(
`endif
`ifndef DUMMY_GPU
st7920_serial_driver gpu(
`endif
clk_in,
1'b1,
vram,
lcd_clk,
lcd_data,
led
);
logic [15:0] scratch;
logic [15:0] scratch2;
logic [7:0] scratch_8;
logic [7:0] scratch_82;
logic [31:0] x_cord;
logic [31:0] y_cord;
logic [7:0] size;
logic screen_pixel;
logic [7:0] sprite_pixel;
task write_pixels;
input [31:0] x;
input [31:0] y;
int i;
begin
// bottom left
i = (y*128*2) + x*2 +127;
begin
// bottom left
`define BLP ((y*128*2) + x*2 +127)
if (vram[`BLP/8][7-(`BLP%8)] == 1) begin
registers[15] <= 1;
end
vram[`BLP/8][7-(`BLP%8)] <= 1;
if (vram[i/8][7-(i%8)] == 1) begin
registers[15] = 1;
end
// bottom right
`define BRP ((y*128*2) + x*2 +128)
vram[`BRP/8][7-(`BRP%8)] <= 1;
vram[i/8][7-(i%8)] ^= 1;
// top left
`define TLP ((y*128*2) + x*2-1)
vram[`TLP/8][7-(`TLP%8)] <= 1;
// bottom right
i = (y*128*2) + x*2 +128;
vram[i/8][7-(i%8)] ^= 1;
// top left
i = (y*128*2) + x*2-1;
vram[i/8][7-(i%8)] ^= 1;
// top right
i = (y*128*2) + x*2;
vram[i/8][7-(i%8)] ^= 1;
end
// top right
`define TRP ((y*128*2) + x*2)
vram[`TRP/8][7-(`TRP%8)] <= 1;
end
endtask
always_ff @(negedge clk_in) begin
if (system_ready) begin
opcode = {memory[program_counter+0], memory[program_counter+1]};
$display("HW : opcode is 0x%h (%b)", opcode, opcode);
$display("HW : PC %0d 0x%h", program_counter, program_counter);
logic [15:0] program_counter;
if (cycle_counter % 20 == 0) begin
if (delay_timer > 0) delay_timer--;
if (sound_timer > 0) sound_timer--;
logic [7:0] registers[0:15];
logic [15:0] index_reg;
logic [15:0] stack[0:15];
logic [3:0] stack_pointer;
logic [15:0] opcode;
logic [7:0] sound_timer;
logic [7:0] delay_timer;
typedef enum {ST_FETCH_HI, ST_FETCH_LO, ST_FETCH_LO2, ST_DECODE, ST_EXEC, ST_DRAW, ST_FETCH_MEM, ST_WB, ST_CLEANUP, ST_HALT} cpu_state;
cpu_state state;
typedef enum {INIT, DRAW} draw_stage;
typedef enum {CLS, LD, DRW, JP} cpu_opcode;
typedef enum {REG, IDX_REG, BYTE, MEM, SPRITE_MEM} data_type;
struct {
draw_stage stage;
logic [4:0] r;
logic [4:0] c;
logic [7:0] x;
logic [7:0] y;
} draw_state;
struct {
cpu_opcode op;
data_type src;
data_type dst;
logic [3:0] dst_reg;
logic [3:0] src_reg;
logic [11:0] src_byte;
logic [(8*16)-1:0] src_sprite;
logic [11:0] src_sprite_addr;
logic [3:0] src_sprite_vx;
logic [3:0] src_sprite_vy;
logic [7:0] src_sprite_x;
logic [7:0] src_sprite_y;
logic [4:0] src_sprite_sz;
logic [4:0] src_sprite_idx;
logic [11:0] src_addr;
logic [11:0] dst_addr;
} instr;
initial begin
state = ST_FETCH_HI;
cycle_counter = 0;
program_counter = 'h200;
wr_go = 0;
for (int i = 0; i < 2048; i++) begin
vram[i] = 0;
end
end
casez (opcode)
'h00E0: begin
$display("HW : INSTR CLS");
for (int i = 0; i < 2048; i++) begin
vram[i] = 0;
always_ff @(posedge clk_in) begin
case (state)
ST_FETCH_HI: begin
rd_memory_address <= program_counter[11:0];
program_counter <= program_counter + 1;
state <= ST_FETCH_LO;
end
end
'h00EE: begin
$display("HW : INSTR RET");
stack_pointer--;
program_counter = stack[stack_pointer];
end
'h0???: $display("HW : INSTR SYS addr (Treating as NOP)");
'h1???: begin
$display("HW : INSTR JP addr");
program_counter = (opcode & 'h0FFF) - 2;
end
'h2???: begin
$display("HW : INSTR CALL addr");
stack[stack_pointer] = program_counter;
stack_pointer++;
program_counter = (opcode & 'h0FFF) - 2;
end
'h3???: begin
$display("HW : INSTR SE Vx, byte");
scratch = (opcode & 'h00FF);
if (scratch[7:0] == registers[(opcode&'h0F00)>>8]) begin
program_counter += 2;
ST_FETCH_LO: begin
rd_memory_address <= program_counter[11:0];
program_counter <= program_counter - 1;
opcode <= { rd_memory_data, 8'h00 };
$display("CPU : Opcode HI is %h", rd_memory_data);
state <= ST_FETCH_LO2;
end
end
'h4???: begin
$display("HW : INSTR SNE Vx, byte");
scratch = (opcode & 'h00FF);
if (scratch[7:0] != registers[(opcode&'h0F00)>>8]) begin
program_counter += 2;
ST_FETCH_LO2: begin
opcode <= { opcode[15:8], rd_memory_data};
$display("CPU : Opcode LO is %h", rd_memory_data);
state <= ST_DECODE;
end
end
'h5??0: begin
$display("HW : INSTR SE Vx, Vy");
if (registers[(opcode&'h00F0)>>4] == registers[(opcode&'h0F00)>>8]) begin
program_counter += 2;
ST_DECODE: begin
casez (opcode)
16'h00E0: begin
instr.op <= CLS;
state <= ST_CLEANUP;
program_counter <= program_counter + 2;
end
16'h1???: begin
instr.op <= JP;
instr.src_byte <= opcode[11:0];
state <= ST_EXEC;
end
16'h6???: begin
$display("Instruction is LD Vx, Byte");
instr.op <= LD;
instr.src <= BYTE;
instr.src_byte <= {4'h00, opcode[7:0]};
instr.dst <= REG;
instr.dst_reg <= opcode[11:8];
state <= ST_EXEC;
end
16'hA???: begin
$display("Instruction is LD I, Byte");
instr.op <= LD;
instr.src <= BYTE;
instr.src_byte <= opcode[11:0];
instr.dst <= IDX_REG;
state <= ST_EXEC;
end
16'hD???: begin
instr.op <= DRW;
instr.src <= SPRITE_MEM;
instr.src_sprite_sz <= {1'b0, opcode[3:0]};
instr.src_sprite_addr <= index_reg[11:0];
instr.src_sprite_vx <= opcode[11:8];
instr.src_sprite_vy <= opcode[7:4];
instr.src_sprite_idx <= 0;
state <= ST_FETCH_MEM;
end
default: begin
$display("ILLEGAL INSTRUCTION %h at PC 0x%h (%0d)", opcode, program_counter, program_counter);
$fatal();
end
endcase
end
end
'h6???: begin
$display("HW : INSTR LD Vx, byte");
scratch = (opcode & 'h00FF);
registers[(opcode&'h0F00)>>8] = scratch[7:0];
end
'h7???: begin
$display("HW : INSTR ADD Vx, byte");
scratch = (opcode & 'h00FF);
registers[(opcode&'h0F00)>>8] += scratch[7:0];
end
'h8??0: begin
$display("HW : INSTR LD Vx, Vy");
registers[(opcode&'h0F00)>>8] = registers[(opcode&'h00F0)>>4];
end
'h8??1: begin
$display("HW : INSTR OR Vx, Vy");
registers[(opcode&'h0F00)>>8] |= registers[(opcode&'h00F0)>>4];
registers[15] = 0;
end
'h8??2: begin
$display("HW : INSTR AND Vx, Vy");
registers[(opcode&'h0F00)>>8] &= registers[(opcode&'h00F0)>>4];
registers[15] = 0;
end
'h8??3: begin
$display("HW : INSTR XOR Vx, Vy");
registers[(opcode&'h0F00)>>8] ^= registers[(opcode&'h00F0)>>4];
registers[15] = 0;
end
'h8??4: begin
$display("HW : INSTR ADD Vx, Vy");
scratch_8 = registers[(opcode&'h0F00)>>8];
registers[(opcode&'h0F00)>>8] += registers[(opcode&'h00F0)>>4];
registers[15] = {7'b0000000, scratch_8 > registers[(opcode&'h0F00)>>8]};
end
'h8??5: begin
$display("HW : INSTR SUB Vx, Vy");
scratch_8 = registers[(opcode&'h0F00)>>8];
registers[(opcode&'h0F00)>>8] -= registers[(opcode&'h00F0)>>4];
registers[15] = {7'b0000000, scratch_8 >= registers[(opcode&'h0F00)>>8]};
end
'h8??6: begin
$display("HW : INSTR SHR Vx {, Vy}");
scratch_8 = registers[(opcode&'h0F00)>>8];
registers[(opcode&'h0F00)>>8] = registers[(opcode&'h00F0)>>4] >> 1;
registers[15] = {7'b0000000, ((scratch_8 & 8'h01) == 8'h01)};
end
'h8??7: begin
$display("HW : INSTR SUBN Vx, Vy");
scratch_8 = registers[(opcode&'h00F0)>>4];
scratch_82 = registers[(opcode&'h0F00)>>8];
registers[(opcode & 'h0F00) >> 8] = registers[(opcode & 'h00F0) >> 4] - registers[(opcode & 'h0F00) >> 8];
registers[15] = {7'b0000000, (scratch_8 >= scratch_82)};
end
'h8??E: begin
$display("HW : INSTR SHL Vx {, Vy}");
scratch_8 = registers[(opcode&'h0F00)>>8];
registers[(opcode&'h0F00)>>8] = registers[(opcode&'h00F0)>>4] << 1;
registers[15] = {7'b0000000, (scratch_8[7])};
end
'h9??0: begin
$display("HW : INSTR SNE Vx, Vy");
if (registers[(opcode&'h00F0)>>4] != registers[(opcode&'h0F00)>>8]) begin
program_counter += 2;
end
end
'hA???: begin
$display("HW : INSTR LD I, addr");
index_reg = (opcode & 'h0FFF);
end
'hb???: begin
$display("HW : INSTR JP V0, addr");
program_counter = {8'h00, registers[0]} + (opcode & 'h0FFF) - 2;
end
'hc???: begin
$display("HW : RND Vx, addr");
// TODO: use a real RNG module, this is not synthesizeable
scratch = {8'h00, random_number} % 16'h0100;
scratch2 = (opcode & 'h00FF);
registers[(opcode&'h0F00)>>8] = scratch[7:0] & scratch2[7:0];
end
'hD???: begin
$display("HW : INSTR DRW Vx, Vy, nibble");
if (cycle_counter % 20 != 0) begin
halt = 1;
end else begin
halt = 0;
x_cord = {24'h000000, registers[(opcode&'h0F00)>>8]};
y_cord = {24'h000000, registers[(opcode&'h00F0)>>4]};
x_cord %= 64;
y_cord %= 32;
scratch = (opcode & 'h000F);
size = scratch[7:0];
registers[15] = 0;
for (int r = 0; r < size; r++) begin
for (int c = 0; c < 8; c++) begin
if (r + y_cord >= 32 || x_cord + c >= 64) continue;
sprite_pixel = memory[{16'h0000, index_reg}+r] & ('h80 >> c);
if (|sprite_pixel) begin
write_pixels(x_cord + c, r+y_cord);
end
ST_FETCH_MEM: begin
if (instr.src == MEM) begin
if (rd_memory_address == instr.src_addr) begin
instr.src_byte <= { 4'h0, rd_memory_data};
instr.src <= BYTE;
state <= ST_EXEC;
end else begin
rd_memory_address <= instr.src_addr;
end
end
end
end
end
'hE?9E: begin
$display("HW : INSTR SKP Vx");
scratch_8 = registers[(opcode&'h0F00)>>8];
if (keyboard[scratch_8[3:0]] == 1) begin
program_counter += 2;
end
end
'hE?A1: begin
$display("HW : INSTR SNE Vx");
scratch_8 = registers[(opcode&'h0F00)>>8];
if (keyboard[scratch_8[3:0]] != 1) begin
program_counter += 2;
end
end
'hF?07: begin
$display("HW : INSTR LD Vx, DT");
registers[(opcode&'h0F00)>>8] = delay_timer;
end
'hF?0A: begin
$display("HW : INSTR LD Vx, K");
halt = 1;
for (int i = 0; i < 16; i++) begin
if (watch_key == 255) begin
if (keyboard[i]) begin
watch_key = i;
if (instr.src == SPRITE_MEM) begin
if (instr.src_sprite_idx == 0) begin
rd_memory_address <= instr.src_sprite_addr + {7'b0000000, instr.src_sprite_idx};
instr.src_sprite_idx <= instr.src_sprite_idx + 1;
end else if (instr.src_sprite_idx <= instr.src_sprite_sz) begin
rd_memory_address <= instr.src_sprite_addr + {7'b0000000, instr.src_sprite_idx};
instr.src_sprite_idx <= instr.src_sprite_idx + 1;
for (int l = 0; l < 8; l++)
instr.src_sprite[(instr.src_sprite_idx)*8+l] <= rd_memory_data[7-l];
$display("%b", rd_memory_data);
end else begin
instr.src_sprite_x <= registers[instr.src_sprite_vx] % 8'd64;
instr.src_sprite_y <= registers[instr.src_sprite_vy] % 8'd32;
state <= ST_DRAW;
draw_state.stage <= INIT;
end
end
end else begin
if (!keyboard[watch_key]) begin
halt = 0;
watch_key = 255;
end
ST_HALT: begin end
ST_DRAW: begin
if (draw_state.stage == INIT) begin
draw_state.x <= instr.src_sprite_x;
draw_state.y <= instr.src_sprite_y;
draw_state.r <= 0;
draw_state.c <= 0;
draw_state.stage <= DRAW;
registers[15] <= 0;
end else begin
if (draw_state.r == instr.src_sprite_sz + 1) begin
$display("sprite is %0d big at coord %d %d sprite=%b idx=%0d", instr.src_sprite_sz, instr.src_sprite_x, instr.src_sprite_y, instr.src_sprite, instr.src_sprite_addr);
state <= ST_CLEANUP;
program_counter <= program_counter + 2;
end else begin
if (draw_state.c == 5'd8) begin
draw_state.c <= 0;
draw_state.r <= draw_state.r + 1;
end else begin
/* verilator lint_off WIDTHEXPAND */
if (draw_state.r + instr.src_sprite_y < 32 && draw_state.c + instr.src_sprite_x < 64) begin
`define DRAW_PX ((draw_state.r + instr.src_sprite_y)*64 + (draw_state.c + instr.src_sprite_x))
/* verilator lint_off WIDTHEXPAND */
if (instr.src_sprite[(draw_state.r*8) + draw_state.c]) begin
write_pixels(draw_state.c + instr.src_sprite_x, draw_state.r + instr.src_sprite_y);
end
end
draw_state.c <= draw_state.c + 1;
end
end
end
end
end
end
'hF?15: begin
$display("HW : INSTR LD DT, Vx");
delay_timer = registers[(opcode&'h0F00)>>8];
end
'hF?18: begin
$display("HW : INSTR LD ST, Vx");
sound_timer = registers[(opcode&'h0F00)>>8];
end
'hF?1E: begin
$display("HW : INSTR ADD I, Vx");
index_reg = index_reg + {8'h00, registers[(opcode&'h0F00)>>8]};
end
'hF?29: begin
$display("HW : INSTR LDL F, Vx");
index_reg = registers[(opcode&'h0F00)>>8] * 5;
end
'hF?33: begin
$display("HW : INSTR LD B, Vx");
scratch = {8'h00, registers[(opcode&'h0F00)>>8]};
scratch2 = scratch % 10;
memory[index_reg+2] = scratch2[7:0];
scratch /= 10;
scratch2 = scratch % 10;
memory[index_reg+1] = scratch2[7:0];
scratch /= 10;
scratch2 = scratch % 10;
memory[index_reg+0] = scratch2[7:0];
end
'hF?55: begin
$display("HW : INSTR LD [I], Vx");
scratch = (opcode & 'h0F00) >> 8;
for (bit [7:0] i8 = 0; i8 <= scratch[7:0]; i8++) begin
scratch2 = index_reg + {8'h00, i8};
memory[scratch2[11:0]] = registers[i8[3:0]];
ST_EXEC: begin
$display("CPU : IN EXEC");
case (instr.op)
LD: begin
if (instr.src == REG) begin
instr.src_byte <= { 4'h0, registers[instr.src_reg] };
instr.src <= BYTE;
end
end
JP: begin
program_counter <= {4'h00, instr.src_byte};
state <= ST_CLEANUP;
end
endcase
case (instr.op)
LD,
DRW,
CLS: begin
program_counter <= program_counter + 2;
state <= ST_WB;
end
endcase
end
index_reg++;
end
'hF?65: begin
$display("HW : INSTR LD Vx, [I]");
scratch = (opcode & 'h0F00) >> 8;
for (bit [7:0] i8 = 0; i8 <= scratch[7:0]; i8++) begin
scratch2 = index_reg + {8'h00, i8};
registers[i8[3:0]] = memory[scratch2[11:0]];
ST_WB: begin
$display("CPU : IN WB");
if (instr.src != BYTE)
$fatal();
case (instr.dst)
MEM: begin
wr_memory_address <= instr.dst_addr;
wr_memory_data <= instr.src_byte[7:0];
wr_go <= 1'b1;
$display("writing back byte %b to %h", instr.src_byte, instr.dst_addr);
end
REG: registers[instr.dst_reg] <= instr.src_byte[7:0];
IDX_REG: index_reg <= {4'h0, instr.src_byte};
endcase
state <= ST_CLEANUP;
end
ST_CLEANUP: begin
wr_go <= 0;
state <= ST_FETCH_HI;
end
index_reg++;
end
default: $display("HW : ILLEGAL INSTRUCTION");
endcase
if (!halt) program_counter += 2;
cycle_counter++;
end
cycle_counter <= cycle_counter + 1;
end
endmodule

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module cpu (
input wire system_ready,
input wire clk_in,
input wire keyboard[15:0],
input wire [7:0] random_number,
output int cycle_counter,
output wire vram [0:1023],
output wire [7:0] sound_timer
);
logic [15:0] program_counter;
logic [7:0] memory[0:4095];
logic halt;
int watch_key;
logic [15:0] stack[0:15];
logic [15:0] index_reg;
logic [3:0] stack_pointer;
logic [7:0] registers[0:15];
logic [15:0] opcode;
logic [7:0] delay_timer;
logic [15:0] scratch;
logic [15:0] scratch2;
logic [7:0] scratch_8;
logic [7:0] scratch_82;
logic [31:0] x_cord;
logic [31:0] y_cord;
logic [7:0] size;
logic [7:0] sprite_pixel;
logic [7:0] i8;
initial begin
$readmemh("fontset.bin", memory, 0);
$readmemb("rom.bin", memory, 'h200);
end
task write_pixels;
input [31:0] x;
input [31:0] y;
int i;
begin
// bottom left
i = (y*64) + x;
vram[i] ^= 1;
end
endtask
always_ff @(negedge clk_in) begin
opcode = {memory[program_counter+0], memory[program_counter+1]};
if (cycle_counter % 20 == 0) begin
if (delay_timer > 0) delay_timer--;
if (sound_timer > 0) sound_timer--;
end
casez (opcode)
'h00E0: begin
for (int i = 0; i < 2048; i++) begin
vram[i] = 0;
end
end
'h00EE: begin
stack_pointer--;
program_counter = stack[stack_pointer];
end
'h1???: begin
program_counter = (opcode & 'h0FFF) - 2;
end
'h2???: begin
stack[stack_pointer] = program_counter;
stack_pointer++;
program_counter = (opcode & 'h0FFF) - 2;
end
'h3???: begin
scratch = (opcode & 'h00FF);
if (scratch[7:0] == registers[(opcode&'h0F00)>>8]) begin
program_counter += 2;
end
end
'h4???: begin
scratch = (opcode & 'h00FF);
if (scratch[7:0] != registers[(opcode&'h0F00)>>8]) begin
program_counter += 2;
end
end
'h5??0: begin
if (registers[(opcode&'h00F0)>>4] == registers[(opcode&'h0F00)>>8]) begin
program_counter += 2;
end
end
'h6???: begin
scratch = (opcode & 'h00FF);
registers[(opcode&'h0F00)>>8] = scratch[7:0];
end
'h7???: begin
scratch = (opcode & 'h00FF);
registers[(opcode&'h0F00)>>8] += scratch[7:0];
end
'h8??0: begin
registers[(opcode&'h0F00)>>8] = registers[(opcode&'h00F0)>>4];
end
'h8??1: begin
registers[(opcode&'h0F00)>>8] |= registers[(opcode&'h00F0)>>4];
registers[15] = 0;
end
'h8??2: begin
registers[(opcode&'h0F00)>>8] &= registers[(opcode&'h00F0)>>4];
registers[15] = 0;
end
'h8??3: begin
registers[(opcode&'h0F00)>>8] ^= registers[(opcode&'h00F0)>>4];
registers[15] = 0;
end
'h8??4: begin
scratch_8 = registers[(opcode&'h0F00)>>8];
registers[(opcode&'h0F00)>>8] += registers[(opcode&'h00F0)>>4];
registers[15] = {7'b0000000, scratch_8 > registers[(opcode&'h0F00)>>8]};
end
'h8??5: begin
scratch_8 = registers[(opcode&'h0F00)>>8];
registers[(opcode&'h0F00)>>8] -= registers[(opcode&'h00F0)>>4];
registers[15] = {7'b0000000, scratch_8 >= registers[(opcode&'h0F00)>>8]};
end
'h8??6: begin
scratch_8 = registers[(opcode&'h0F00)>>8];
registers[(opcode&'h0F00)>>8] = registers[(opcode&'h00F0)>>4] >> 1;
registers[15] = {7'b0000000, ((scratch_8 & 8'h01) == 8'h01)};
end
'h8??7: begin
scratch_8 = registers[(opcode&'h00F0)>>4];
scratch_82 = registers[(opcode&'h0F00)>>8];
registers[(opcode & 'h0F00) >> 8] = registers[(opcode & 'h00F0) >> 4] - registers[(opcode & 'h0F00) >> 8];
registers[15] = {7'b0000000, (scratch_8 >= scratch_82)};
end
'h8??E: begin
scratch_8 = registers[(opcode&'h0F00)>>8];
registers[(opcode&'h0F00)>>8] = registers[(opcode&'h00F0)>>4] << 1;
registers[15] = {7'b0000000, (scratch_8[7])};
end
'h9??0: begin
if (registers[(opcode&'h00F0)>>4] != registers[(opcode&'h0F00)>>8]) begin
program_counter += 2;
end
end
'hA???: begin
index_reg = (opcode & 'h0FFF);
end
'hb???: begin
program_counter = {8'h00, registers[0]} + (opcode & 'h0FFF) - 2;
end
'hc???: begin
// TODO: use a real RNG module, this is not synthesizeable
scratch = {8'h00, random_number} % 16'h0100;
scratch2 = (opcode & 'h00FF);
registers[(opcode&'h0F00)>>8] = scratch[7:0] & scratch2[7:0];
end
'hD???: begin
if (cycle_counter % 20 != 0) begin
halt = 1;
end else begin
halt = 0;
x_cord = {24'h000000, registers[(opcode&'h0F00)>>8]} % 64;
y_cord = {24'h000000, registers[(opcode&'h00F0)>>4]} % 32;
scratch = (opcode & 'h000F);
size = scratch[7:0];
registers[15] = 0;
for (int r = 0; r < size; r++) begin
for (int c = 0; c < 8; c++) begin
if (!(r + y_cord >= 32 || x_cord + c >= 64)) begin
sprite_pixel = memory[{16'h0000, index_reg}+r] & ('h80 >> c);
if (|sprite_pixel) begin
write_pixels(x_cord + c, r+y_cord);
end
end
end
end
end
end
'hE?9E: begin
scratch_8 = registers[(opcode&'h0F00)>>8];
if (keyboard[scratch_8[3:0]] == 1) begin
program_counter += 2;
end
end
'hE?A1: begin
scratch_8 = registers[(opcode&'h0F00)>>8];
if (keyboard[scratch_8[3:0]] != 1) begin
program_counter += 2;
end
end
'hF?07: begin
registers[(opcode&'h0F00)>>8] = delay_timer;
end
'hF?0A: begin
halt = 1;
for (int i = 0; i < 16; i++) begin
if (watch_key == 255) begin
if (keyboard[i]) begin
watch_key = i;
end
end else begin
if (!keyboard[watch_key]) begin
halt = 0;
watch_key = 255;
end
end
end
end
'hF?15: begin
delay_timer = registers[(opcode&'h0F00)>>8];
end
'hF?18: begin
sound_timer = registers[(opcode&'h0F00)>>8];
end
'hF?1E: begin
index_reg = index_reg + {8'h00, registers[(opcode&'h0F00)>>8]};
end
'hF?29: begin
index_reg = registers[(opcode&'h0F00)>>8] * 5;
end
'hF?33: begin
scratch = {8'h00, registers[(opcode&'h0F00)>>8]};
scratch2 = scratch % 10;
memory[index_reg+2] = scratch2[7:0];
scratch /= 10;
scratch2 = scratch % 10;
memory[index_reg+1] = scratch2[7:0];
scratch /= 10;
scratch2 = scratch % 10;
memory[index_reg+0] = scratch2[7:0];
end
'hF?55: begin
scratch = (opcode & 'h0F00) >> 8;
for (i8 = 0; i8 <= scratch[7:0]; i8++) begin
scratch2 = index_reg + {8'h00, i8};
memory[scratch2[11:0]] = registers[i8[3:0]];
end
index_reg++;
end
'hF?65: begin
scratch = (opcode & 'h0F00) >> 8;
for (i8 = 0; i8 <= scratch[7:0]; i8++) begin
scratch2 = index_reg + {8'h00, i8};
registers[i8[3:0]] = memory[scratch2[11:0]];
end
index_reg++;
end
endcase
if (!halt) program_counter += 2;
cycle_counter++;
end
endmodule

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--abs_divider DEN_REPRESENTATION="SIGNED" LPM_PIPELINE=0 MAXIMIZE_SPEED=5 NUM_REPRESENTATION="SIGNED" SKIP_BITS=0 WIDTH_D=4 WIDTH_N=32 denominator numerator quotient remainder
--VERSION_BEGIN 23.1 cbx_cycloneii 2023:11:29:19:33:06:SC cbx_lpm_abs 2023:11:29:19:33:06:SC cbx_lpm_add_sub 2023:11:29:19:33:06:SC cbx_lpm_divide 2023:11:29:19:33:06:SC cbx_mgl 2023:11:29:19:43:53:SC cbx_nadder 2023:11:29:19:33:06:SC cbx_stratix 2023:11:29:19:33:06:SC cbx_stratixii 2023:11:29:19:33:05:SC cbx_util_mgl 2023:11:29:19:33:06:SC VERSION_END
-- Copyright (C) 2023 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details, at
-- https://fpgasoftware.intel.com/eula.
FUNCTION alt_u_div_mve (denominator[3..0], numerator[31..0])
RETURNS ( quotient[31..0], remainder[3..0]);
FUNCTION lpm_abs_jn9 (data[3..0])
RETURNS ( overflow, result[3..0]);
FUNCTION lpm_abs_4p9 (data[31..0])
RETURNS ( result[31..0]);
--synthesis_resources = lut 221
SUBDESIGN abs_divider_jbg
(
denominator[3..0] : input;
numerator[31..0] : input;
quotient[31..0] : output;
remainder[3..0] : output;
)
VARIABLE
divider : alt_u_div_mve;
my_abs_den : lpm_abs_jn9;
my_abs_num : lpm_abs_4p9;
compl_add_quot_result_int[32..0] : WIRE;
compl_add_quot_cin : WIRE;
compl_add_quot_dataa[31..0] : WIRE;
compl_add_quot_datab[31..0] : WIRE;
compl_add_quot_result[31..0] : WIRE;
compl_add_rem_result_int[4..0] : WIRE;
compl_add_rem_cin : WIRE;
compl_add_rem_dataa[3..0] : WIRE;
compl_add_rem_datab[3..0] : WIRE;
compl_add_rem_result[3..0] : WIRE;
diff_signs : WIRE;
gnd_wire : WIRE;
neg_quot[31..0] : WIRE;
neg_rem[3..0] : WIRE;
norm_den[3..0] : WIRE;
norm_num[31..0] : WIRE;
num_sign : WIRE;
protect_quotient[31..0] : WIRE;
protect_remainder[3..0] : WIRE;
vcc_wire : WIRE;
BEGIN
divider.denominator[] = norm_den[];
divider.numerator[] = norm_num[];
my_abs_den.data[] = denominator[];
my_abs_num.data[] = numerator[];
compl_add_quot_result_int[] = (compl_add_quot_dataa[], compl_add_quot_cin) + (compl_add_quot_datab[], compl_add_quot_cin);
compl_add_quot_result[] = compl_add_quot_result_int[32..1];
compl_add_quot_cin = vcc_wire;
compl_add_quot_dataa[] = (! protect_quotient[]);
compl_add_quot_datab[] = ( gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire);
compl_add_rem_result_int[] = (compl_add_rem_dataa[], compl_add_rem_cin) + (compl_add_rem_datab[], compl_add_rem_cin);
compl_add_rem_result[] = compl_add_rem_result_int[4..1];
compl_add_rem_cin = vcc_wire;
compl_add_rem_dataa[] = (! protect_remainder[]);
compl_add_rem_datab[] = ( gnd_wire, gnd_wire, gnd_wire, gnd_wire);
diff_signs = (numerator[31..31] $ denominator[3..3]);
gnd_wire = B"0";
neg_quot[] = compl_add_quot_result[];
neg_rem[] = compl_add_rem_result[];
norm_den[] = my_abs_den.result[];
norm_num[] = my_abs_num.result[];
num_sign = numerator[31..31];
protect_quotient[] = divider.quotient[];
protect_remainder[] = divider.remainder[];
quotient[] = ((protect_quotient[] & (! diff_signs)) # (neg_quot[] & diff_signs));
remainder[] = ((protect_remainder[] & (! num_sign)) # (neg_rem[] & num_sign));
vcc_wire = B"1";
END;
--VALID FILE

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--abs_divider DEN_REPRESENTATION="SIGNED" LPM_PIPELINE=0 MAXIMIZE_SPEED=5 NUM_REPRESENTATION="SIGNED" SKIP_BITS=0 WIDTH_D=6 WIDTH_N=32 denominator numerator quotient remainder
--VERSION_BEGIN 23.1 cbx_cycloneii 2023:11:29:19:33:06:SC cbx_lpm_abs 2023:11:29:19:33:06:SC cbx_lpm_add_sub 2023:11:29:19:33:06:SC cbx_lpm_divide 2023:11:29:19:33:06:SC cbx_mgl 2023:11:29:19:43:53:SC cbx_nadder 2023:11:29:19:33:06:SC cbx_stratix 2023:11:29:19:33:06:SC cbx_stratixii 2023:11:29:19:33:05:SC cbx_util_mgl 2023:11:29:19:33:06:SC VERSION_END
-- Copyright (C) 2023 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details, at
-- https://fpgasoftware.intel.com/eula.
FUNCTION alt_u_div_qve (denominator[5..0], numerator[31..0])
RETURNS ( quotient[31..0], remainder[5..0]);
FUNCTION lpm_abs_ln9 (data[5..0])
RETURNS ( overflow, result[5..0]);
FUNCTION lpm_abs_4p9 (data[31..0])
RETURNS ( overflow, result[31..0]);
--synthesis_resources = lut 311
SUBDESIGN abs_divider_lbg
(
denominator[5..0] : input;
numerator[31..0] : input;
quotient[31..0] : output;
remainder[5..0] : output;
)
VARIABLE
divider : alt_u_div_qve;
my_abs_den : lpm_abs_ln9;
my_abs_num : lpm_abs_4p9;
compl_add_quot_result_int[32..0] : WIRE;
compl_add_quot_cin : WIRE;
compl_add_quot_dataa[31..0] : WIRE;
compl_add_quot_datab[31..0] : WIRE;
compl_add_quot_result[31..0] : WIRE;
compl_add_rem_result_int[6..0] : WIRE;
compl_add_rem_cin : WIRE;
compl_add_rem_dataa[5..0] : WIRE;
compl_add_rem_datab[5..0] : WIRE;
compl_add_rem_result[5..0] : WIRE;
diff_signs : WIRE;
gnd_wire : WIRE;
neg_quot[31..0] : WIRE;
neg_rem[5..0] : WIRE;
norm_den[5..0] : WIRE;
norm_num[31..0] : WIRE;
num_sign : WIRE;
protect_quotient[31..0] : WIRE;
protect_remainder[5..0] : WIRE;
vcc_wire : WIRE;
BEGIN
divider.denominator[] = norm_den[];
divider.numerator[] = norm_num[];
my_abs_den.data[] = denominator[];
my_abs_num.data[] = numerator[];
compl_add_quot_result_int[] = (compl_add_quot_dataa[], compl_add_quot_cin) + (compl_add_quot_datab[], compl_add_quot_cin);
compl_add_quot_result[] = compl_add_quot_result_int[32..1];
compl_add_quot_cin = vcc_wire;
compl_add_quot_dataa[] = (! protect_quotient[]);
compl_add_quot_datab[] = ( gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire);
compl_add_rem_result_int[] = (compl_add_rem_dataa[], compl_add_rem_cin) + (compl_add_rem_datab[], compl_add_rem_cin);
compl_add_rem_result[] = compl_add_rem_result_int[6..1];
compl_add_rem_cin = vcc_wire;
compl_add_rem_dataa[] = (! protect_remainder[]);
compl_add_rem_datab[] = ( gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire);
diff_signs = (numerator[31..31] $ denominator[5..5]);
gnd_wire = B"0";
neg_quot[] = compl_add_quot_result[];
neg_rem[] = compl_add_rem_result[];
norm_den[] = my_abs_den.result[];
norm_num[] = my_abs_num.result[];
num_sign = numerator[31..31];
protect_quotient[] = divider.quotient[];
protect_remainder[] = divider.remainder[];
quotient[] = ((protect_quotient[] & (! diff_signs)) # (neg_quot[] & diff_signs));
remainder[] = ((protect_remainder[] & (! num_sign)) # (neg_rem[] & num_sign));
vcc_wire = B"1";
END;
--VALID FILE

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--alt_u_div DEVICE_FAMILY="Cyclone V" LPM_PIPELINE=0 MAXIMIZE_SPEED=5 SKIP_BITS=0 WIDTH_D=4 WIDTH_N=8 WIDTH_Q=8 WIDTH_R=4 denominator numerator quotient remainder
--VERSION_BEGIN 23.1 cbx_cycloneii 2023:11:29:19:33:06:SC cbx_lpm_abs 2023:11:29:19:33:06:SC cbx_lpm_add_sub 2023:11:29:19:33:06:SC cbx_lpm_divide 2023:11:29:19:33:06:SC cbx_mgl 2023:11:29:19:43:53:SC cbx_nadder 2023:11:29:19:33:06:SC cbx_stratix 2023:11:29:19:33:06:SC cbx_stratixii 2023:11:29:19:33:05:SC cbx_util_mgl 2023:11:29:19:33:06:SC VERSION_END
-- Copyright (C) 2023 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details, at
-- https://fpgasoftware.intel.com/eula.
--synthesis_resources = lut 38
SUBDESIGN alt_u_div_sse
(
denominator[3..0] : input;
numerator[7..0] : input;
quotient[7..0] : output;
remainder[3..0] : output;
)
VARIABLE
add_sub_0_result_int[1..0] : WIRE;
add_sub_0_cout : WIRE;
add_sub_0_dataa[0..0] : WIRE;
add_sub_0_datab[0..0] : WIRE;
add_sub_0_result[0..0] : WIRE;
add_sub_1_result_int[2..0] : WIRE;
add_sub_1_cout : WIRE;
add_sub_1_dataa[1..0] : WIRE;
add_sub_1_datab[1..0] : WIRE;
add_sub_1_result[1..0] : WIRE;
add_sub_2_result_int[3..0] : WIRE;
add_sub_2_cout : WIRE;
add_sub_2_dataa[2..0] : WIRE;
add_sub_2_datab[2..0] : WIRE;
add_sub_2_result[2..0] : WIRE;
add_sub_3_result_int[4..0] : WIRE;
add_sub_3_cout : WIRE;
add_sub_3_dataa[3..0] : WIRE;
add_sub_3_datab[3..0] : WIRE;
add_sub_3_result[3..0] : WIRE;
add_sub_4_result_int[5..0] : WIRE;
add_sub_4_cout : WIRE;
add_sub_4_dataa[4..0] : WIRE;
add_sub_4_datab[4..0] : WIRE;
add_sub_4_result[4..0] : WIRE;
add_sub_5_result_int[5..0] : WIRE;
add_sub_5_cout : WIRE;
add_sub_5_dataa[4..0] : WIRE;
add_sub_5_datab[4..0] : WIRE;
add_sub_5_result[4..0] : WIRE;
add_sub_6_result_int[5..0] : WIRE;
add_sub_6_cout : WIRE;
add_sub_6_dataa[4..0] : WIRE;
add_sub_6_datab[4..0] : WIRE;
add_sub_6_result[4..0] : WIRE;
add_sub_7_result_int[5..0] : WIRE;
add_sub_7_cout : WIRE;
add_sub_7_dataa[4..0] : WIRE;
add_sub_7_datab[4..0] : WIRE;
add_sub_7_result[4..0] : WIRE;
DenominatorIn[44..0] : WIRE;
DenominatorIn_tmp[44..0] : WIRE;
gnd_wire : WIRE;
nose[71..0] : WIRE;
NumeratorIn[71..0] : WIRE;
NumeratorIn_tmp[71..0] : WIRE;
prestg[39..0] : WIRE;
quotient_tmp[7..0] : WIRE;
sel[35..0] : WIRE;
selnose[71..0] : WIRE;
StageIn[44..0] : WIRE;
StageIn_tmp[44..0] : WIRE;
StageOut[39..0] : WIRE;
BEGIN
add_sub_0_result_int[] = (0, add_sub_0_dataa[]) - (0, add_sub_0_datab[]);
add_sub_0_result[] = add_sub_0_result_int[0..0];
add_sub_0_cout = !add_sub_0_result_int[1];
add_sub_0_dataa[] = NumeratorIn[7..7];
add_sub_0_datab[] = DenominatorIn[0..0];
add_sub_1_result_int[] = (0, add_sub_1_dataa[]) - (0, add_sub_1_datab[]);
add_sub_1_result[] = add_sub_1_result_int[1..0];
add_sub_1_cout = !add_sub_1_result_int[2];
add_sub_1_dataa[] = ( StageIn[5..5], NumeratorIn[14..14]);
add_sub_1_datab[] = DenominatorIn[6..5];
add_sub_2_result_int[] = (0, add_sub_2_dataa[]) - (0, add_sub_2_datab[]);
add_sub_2_result[] = add_sub_2_result_int[2..0];
add_sub_2_cout = !add_sub_2_result_int[3];
add_sub_2_dataa[] = ( StageIn[11..10], NumeratorIn[21..21]);
add_sub_2_datab[] = DenominatorIn[12..10];
add_sub_3_result_int[] = (0, add_sub_3_dataa[]) - (0, add_sub_3_datab[]);
add_sub_3_result[] = add_sub_3_result_int[3..0];
add_sub_3_cout = !add_sub_3_result_int[4];
add_sub_3_dataa[] = ( StageIn[17..15], NumeratorIn[28..28]);
add_sub_3_datab[] = DenominatorIn[18..15];
add_sub_4_result_int[] = (0, add_sub_4_dataa[]) - (0, add_sub_4_datab[]);
add_sub_4_result[] = add_sub_4_result_int[4..0];
add_sub_4_cout = !add_sub_4_result_int[5];
add_sub_4_dataa[] = ( StageIn[23..20], NumeratorIn[35..35]);
add_sub_4_datab[] = DenominatorIn[24..20];
add_sub_5_result_int[] = (0, add_sub_5_dataa[]) - (0, add_sub_5_datab[]);
add_sub_5_result[] = add_sub_5_result_int[4..0];
add_sub_5_cout = !add_sub_5_result_int[5];
add_sub_5_dataa[] = ( StageIn[28..25], NumeratorIn[42..42]);
add_sub_5_datab[] = DenominatorIn[29..25];
add_sub_6_result_int[] = (0, add_sub_6_dataa[]) - (0, add_sub_6_datab[]);
add_sub_6_result[] = add_sub_6_result_int[4..0];
add_sub_6_cout = !add_sub_6_result_int[5];
add_sub_6_dataa[] = ( StageIn[33..30], NumeratorIn[49..49]);
add_sub_6_datab[] = DenominatorIn[34..30];
add_sub_7_result_int[] = (0, add_sub_7_dataa[]) - (0, add_sub_7_datab[]);
add_sub_7_result[] = add_sub_7_result_int[4..0];
add_sub_7_cout = !add_sub_7_result_int[5];
add_sub_7_dataa[] = ( StageIn[38..35], NumeratorIn[56..56]);
add_sub_7_datab[] = DenominatorIn[39..35];
DenominatorIn[] = DenominatorIn_tmp[];
DenominatorIn_tmp[] = ( DenominatorIn[39..0], ( gnd_wire, denominator[]));
gnd_wire = B"0";
nose[] = ( B"00000000", add_sub_7_cout, B"00000000", add_sub_6_cout, B"00000000", add_sub_5_cout, B"00000000", add_sub_4_cout, B"00000000", add_sub_3_cout, B"00000000", add_sub_2_cout, B"00000000", add_sub_1_cout, B"00000000", add_sub_0_cout);
NumeratorIn[] = NumeratorIn_tmp[];
NumeratorIn_tmp[] = ( NumeratorIn[63..0], numerator[]);
prestg[] = ( add_sub_7_result[], add_sub_6_result[], add_sub_5_result[], add_sub_4_result[], GND, add_sub_3_result[], B"00", add_sub_2_result[], B"000", add_sub_1_result[], B"0000", add_sub_0_result[]);
quotient[] = quotient_tmp[];
quotient_tmp[] = ( (! selnose[0..0]), (! selnose[9..9]), (! selnose[18..18]), (! selnose[27..27]), (! selnose[36..36]), (! selnose[45..45]), (! selnose[54..54]), (! selnose[63..63]));
remainder[3..0] = StageIn[43..40];
sel[] = ( gnd_wire, (sel[35..35] # DenominatorIn[43..43]), (sel[34..34] # DenominatorIn[42..42]), (sel[33..33] # DenominatorIn[41..41]), gnd_wire, (sel[31..31] # DenominatorIn[38..38]), (sel[30..30] # DenominatorIn[37..37]), (sel[29..29] # DenominatorIn[36..36]), gnd_wire, (sel[27..27] # DenominatorIn[33..33]), (sel[26..26] # DenominatorIn[32..32]), (sel[25..25] # DenominatorIn[31..31]), gnd_wire, (sel[23..23] # DenominatorIn[28..28]), (sel[22..22] # DenominatorIn[27..27]), (sel[21..21] # DenominatorIn[26..26]), gnd_wire, (sel[19..19] # DenominatorIn[23..23]), (sel[18..18] # DenominatorIn[22..22]), (sel[17..17] # DenominatorIn[21..21]), gnd_wire, (sel[15..15] # DenominatorIn[18..18]), (sel[14..14] # DenominatorIn[17..17]), (sel[13..13] # DenominatorIn[16..16]), gnd_wire, (sel[11..11] # DenominatorIn[13..13]), (sel[10..10] # DenominatorIn[12..12]), (sel[9..9] # DenominatorIn[11..11]), gnd_wire, (sel[7..7] # DenominatorIn[8..8]), (sel[6..6] # DenominatorIn[7..7]), (sel[5..5] # DenominatorIn[6..6]), gnd_wire, (sel[3..3] # DenominatorIn[3..3]), (sel[2..2] # DenominatorIn[2..2]), (sel[1..1] # DenominatorIn[1..1]));
selnose[] = ( (! nose[71..71]), (! nose[70..70]), (! nose[69..69]), (! nose[68..68]), ((! nose[67..67]) # sel[35..35]), ((! nose[66..66]) # sel[34..34]), ((! nose[65..65]) # sel[33..33]), ((! nose[64..64]) # sel[32..32]), (! nose[63..63]), (! nose[62..62]), (! nose[61..61]), (! nose[60..60]), ((! nose[59..59]) # sel[31..31]), ((! nose[58..58]) # sel[30..30]), ((! nose[57..57]) # sel[29..29]), ((! nose[56..56]) # sel[28..28]), (! nose[55..55]), (! nose[54..54]), (! nose[53..53]), (! nose[52..52]), ((! nose[51..51]) # sel[27..27]), ((! nose[50..50]) # sel[26..26]), ((! nose[49..49]) # sel[25..25]), ((! nose[48..48]) # sel[24..24]), (! nose[47..47]), (! nose[46..46]), (! nose[45..45]), (! nose[44..44]), ((! nose[43..43]) # sel[23..23]), ((! nose[42..42]) # sel[22..22]), ((! nose[41..41]) # sel[21..21]), ((! nose[40..40]) # sel[20..20]), (! nose[39..39]), (! nose[38..38]), (! nose[37..37]), (! nose[36..36]), ((! nose[35..35]) # sel[19..19]), ((! nose[34..34]) # sel[18..18]), ((! nose[33..33]) # sel[17..17]), ((! nose[32..32]) # sel[16..16]), (! nose[31..31]), (! nose[30..30]), (! nose[29..29]), (! nose[28..28]), ((! nose[27..27]) # sel[15..15]), ((! nose[26..26]) # sel[14..14]), ((! nose[25..25]) # sel[13..13]), ((! nose[24..24]) # sel[12..12]), (! nose[23..23]), (! nose[22..22]), (! nose[21..21]), (! nose[20..20]), ((! nose[19..19]) # sel[11..11]), ((! nose[18..18]) # sel[10..10]), ((! nose[17..17]) # sel[9..9]), ((! nose[16..16]) # sel[8..8]), (! nose[15..15]), (! nose[14..14]), (! nose[13..13]), (! nose[12..12]), ((! nose[11..11]) # sel[7..7]), ((! nose[10..10]) # sel[6..6]), ((! nose[9..9]) # sel[5..5]), ((! nose[8..8]) # sel[4..4]), (! nose[7..7]), (! nose[6..6]), (! nose[5..5]), (! nose[4..4]), ((! nose[3..3]) # sel[3..3]), ((! nose[2..2]) # sel[2..2]), ((! nose[1..1]) # sel[1..1]), ((! nose[0..0]) # sel[0..0]));
StageIn[] = StageIn_tmp[];
StageIn_tmp[] = ( StageOut[39..0], B"00000");
StageOut[] = ( ((( StageIn[38..35], NumeratorIn[56..56]) & selnose[63..63]) # (prestg[39..35] & (! selnose[63..63]))), ((( StageIn[33..30], NumeratorIn[49..49]) & selnose[54..54]) # (prestg[34..30] & (! selnose[54..54]))), ((( StageIn[28..25], NumeratorIn[42..42]) & selnose[45..45]) # (prestg[29..25] & (! selnose[45..45]))), ((( StageIn[23..20], NumeratorIn[35..35]) & selnose[36..36]) # (prestg[24..20] & (! selnose[36..36]))), ((( StageIn[18..15], NumeratorIn[28..28]) & selnose[27..27]) # (prestg[19..15] & (! selnose[27..27]))), ((( StageIn[13..10], NumeratorIn[21..21]) & selnose[18..18]) # (prestg[14..10] & (! selnose[18..18]))), ((( StageIn[8..5], NumeratorIn[14..14]) & selnose[9..9]) # (prestg[9..5] & (! selnose[9..9]))), ((( StageIn[3..0], NumeratorIn[7..7]) & selnose[0..0]) # (prestg[4..0] & (! selnose[0..0]))));
END;
--VALID FILE

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<?xml version="1.0" ?>
<LOG_ROOT>
<PROJECT NAME="chip8">
</PROJECT>
</LOG_ROOT>

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Quartus_Version = Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition
Version_Index = 570679040
Creation_Time = Sun Apr 7 15:25:35 2024

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{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1712529585582 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "12 12 " "Parallel compilation is enabled and will use 12 of the 12 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1712529585582 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "chip8 5CSEBA6U23I7 " "Selected device 5CSEBA6U23I7 for design \"chip8\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1712529587114 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature -40 degrees C " "Low junction temperature is -40 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1712529587136 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 100 degrees C " "High junction temperature is 100 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1712529587136 ""}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1712529592466 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1712529592564 ""}
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1712529600469 ""}
{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1712529632442 ""}
{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "2 s (2 global) " "Automatically promoted 2 clocks (2 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "dc:dc\|clk_out~CLKENA0 35217 global CLKCTRL_G2 " "dc:dc\|clk_out~CLKENA0 with 35217 fanout uses global clock CLKCTRL_G2" { { "Info" "ICCLK_UNLOCKED_FOR_VPR" "" "This signal is driven by core routing -- it may be moved during placement to reduce routing delays" { } { } 0 12525 "This signal is driven by core routing -- it may be moved during placement to reduce routing delays" 0 0 "Design Software" 0 -1 1712529642530 ""} } { } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1712529642530 ""} { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "clk_in~inputCLKENA0 31 global CLKCTRL_G5 " "clk_in~inputCLKENA0 with 31 fanout uses global clock CLKCTRL_G5" { } { } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1712529642530 ""} } { } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1712529642530 ""}

36265
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<TABLE>
<TR bgcolor="#C0C0C0">
<TH>Hierarchy</TH>
<TH>Input</TH>
<TH>Constant Input</TH>
<TH>Unused Input</TH>
<TH>Floating Input</TH>
<TH>Output</TH>
<TH>Constant Output</TH>
<TH>Unused Output</TH>
<TH>Floating Output</TH>
<TH>Bidir</TH>
<TH>Constant Bidir</TH>
<TH>Unused Bidir</TH>
<TH>Input only Bidir</TH>
<TH>Output only Bidir</TH>
</TR>
<TR >
<TD >randy</TD>
<TD >65</TD>
<TD >32</TD>
<TD >0</TD>
<TD >32</TD>
<TD >8</TD>
<TD >32</TD>
<TD >32</TD>
<TD >32</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >gpu|dff</TD>
<TD >2</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >gpu|com</TD>
<TD >12</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >gpu</TD>
<TD >10</TD>
<TD >1</TD>
<TD >0</TD>
<TD >1</TD>
<TD >18</TD>
<TD >1</TD>
<TD >1</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >cpu</TD>
<TD >37</TD>
<TD >25</TD>
<TD >0</TD>
<TD >25</TD>
<TD >48</TD>
<TD >25</TD>
<TD >25</TD>
<TD >25</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >dc</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
</TABLE>

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+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Legal Partition Candidates ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; randy ; 65 ; 32 ; 0 ; 32 ; 8 ; 32 ; 32 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; gpu|dff ; 2 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; gpu|com ; 12 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; gpu ; 10 ; 1 ; 0 ; 1 ; 18 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; cpu ; 37 ; 25 ; 0 ; 25 ; 48 ; 25 ; 25 ; 25 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; dc ; 1 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1712551112815 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition " "Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1712551112815 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 7 23:38:32 2024 " "Processing started: Sun Apr 7 23:38:32 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1712551112815 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712551112815 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off chip8 -c chip8 " "Command: quartus_map --read_settings_files=on --write_settings_files=off chip8 -c chip8" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712551112816 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1712551112956 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "12 12 " "Parallel compilation is enabled and will use 12 of the 12 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1712551112956 ""}
{ "Critical Warning" "WVRFX_VERI_UNDEFINED_MACRO" "DELAY_BITS st7920_serial_driver.sv(12) " "Verilog HDL Compiler Directive warning at st7920_serial_driver.sv(12): text macro \"DELAY_BITS\" is undefined" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 12 0 0 } } } 1 10191 "Verilog HDL Compiler Directive warning at %2!s!: text macro \"%1!s!\" is undefined" 0 0 "Analysis & Synthesis" 0 -1 1712551118395 ""}
{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\":\"; expecting an operand st7920_serial_driver.sv(12) " "Verilog HDL syntax error at st7920_serial_driver.sv(12) near text: \":\"; expecting an operand. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 12 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1712551118395 ""}
{ "Critical Warning" "WVRFX_VERI_UNDEFINED_MACRO" "BOOTSTRAP_INSTRS st7920_serial_driver.sv(64) " "Verilog HDL Compiler Directive warning at st7920_serial_driver.sv(64): text macro \"BOOTSTRAP_INSTRS\" is undefined" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 64 0 0 } } } 1 10191 "Verilog HDL Compiler Directive warning at %2!s!: text macro \"%1!s!\" is undefined" 0 0 "Analysis & Synthesis" 0 -1 1712551118395 ""}
{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\")\"; expecting an operand st7920_serial_driver.sv(64) " "Verilog HDL syntax error at st7920_serial_driver.sv(64) near text: \")\"; expecting an operand. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 64 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1712551118395 ""}
{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"else\"; expecting \"end\" st7920_serial_driver.sv(70) " "Verilog HDL syntax error at st7920_serial_driver.sv(70) near text: \"else\"; expecting \"end\". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 70 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1712551118395 ""}
{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\")\"; expecting an operand st7920_serial_driver.sv(94) " "Verilog HDL syntax error at st7920_serial_driver.sv(94) near text: \")\"; expecting an operand. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 94 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1712551118395 ""}
{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\")\"; expecting an operand st7920_serial_driver.sv(97) " "Verilog HDL syntax error at st7920_serial_driver.sv(97) near text: \")\"; expecting an operand. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 97 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1712551118395 ""}
{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"\]\"; expecting an operand st7920_serial_driver.sv(124) " "Verilog HDL syntax error at st7920_serial_driver.sv(124) near text: \"\]\"; expecting an operand. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 124 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1712551118395 ""}
{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"else\"; expecting \"end\" st7920_serial_driver.sv(127) " "Verilog HDL syntax error at st7920_serial_driver.sv(127) near text: \"else\"; expecting \"end\". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 127 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1712551118395 ""}
{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "st7920_serial_driver st7920_serial_driver.sv(1) " "Ignored design unit \"st7920_serial_driver\" at st7920_serial_driver.sv(1) due to previous errors" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 1 0 0 } } } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Analysis & Synthesis" 0 -1 1712551118395 ""}
{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "d_flip_flop st7920_serial_driver.sv(134) " "Ignored design unit \"d_flip_flop\" at st7920_serial_driver.sv(134) due to previous errors" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 134 0 0 } } } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Analysis & Synthesis" 0 -1 1712551118395 ""}
{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "commander st7920_serial_driver.sv(144) " "Ignored design unit \"commander\" at st7920_serial_driver.sv(144) due to previous errors" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 144 0 0 } } } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Analysis & Synthesis" 0 -1 1712551118396 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "the-bomb/st7920_serial_driver.sv 0 0 " "Found 0 design units, including 0 entities, in source file the-bomb/st7920_serial_driver.sv" { } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712551118396 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "chip8.sv 1 1 " "Found 1 design units, including 1 entities, in source file chip8.sv" { { "Info" "ISGN_ENTITY_NAME" "1 chip8 " "Found entity 1: chip8" { } { { "chip8.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/chip8.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712551118397 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712551118397 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu.sv 1 1 " "Found 1 design units, including 1 entities, in source file cpu.sv" { { "Info" "ISGN_ENTITY_NAME" "1 cpu " "Found entity 1: cpu" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712551118398 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712551118398 ""}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 10 s 3 s Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 10 errors, 3 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "383 " "Peak virtual memory: 383 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1712551118425 ""} { "Error" "EQEXE_END_BANNER_TIME" "Sun Apr 7 23:38:38 2024 " "Processing ended: Sun Apr 7 23:38:38 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1712551118425 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1712551118425 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:14 " "Total CPU time (on all processors): 00:00:14" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1712551118425 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1712551118425 ""}

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SOURCE

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start_analysis_synthesis:s:01:10:32
start_analysis_elaboration:s

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{
"partitions" : [
{
"name" : "Top",
"pins" : [
{
"name" : "lcd_clk",
"strict" : false
},
{
"name" : "lcd_data",
"strict" : false
},
{
"name" : "led[0]",
"strict" : false
},
{
"name" : "led[1]",
"strict" : false
},
{
"name" : "led[2]",
"strict" : false
},
{
"name" : "led[3]",
"strict" : false
},
{
"name" : "led[4]",
"strict" : false
},
{
"name" : "clk_in",
"strict" : false
}
]
}
]
}

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--lpm_abs CARRY_CHAIN="MANUAL" DEVICE_FAMILY="Cyclone V" IGNORE_CARRY_BUFFERS="OFF" LPM_WIDTH=32 data result
--VERSION_BEGIN 23.1 cbx_cycloneii 2023:11:29:19:33:06:SC cbx_lpm_abs 2023:11:29:19:33:06:SC cbx_lpm_add_sub 2023:11:29:19:33:06:SC cbx_mgl 2023:11:29:19:43:53:SC cbx_nadder 2023:11:29:19:33:06:SC cbx_stratix 2023:11:29:19:33:06:SC cbx_stratixii 2023:11:29:19:33:05:SC cbx_util_mgl 2023:11:29:19:33:06:SC VERSION_END
-- Copyright (C) 2023 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details, at
-- https://fpgasoftware.intel.com/eula.
--synthesis_resources = lut 32
SUBDESIGN lpm_abs_4p9
(
data[31..0] : input;
overflow : output;
result[31..0] : output;
)
VARIABLE
adder_result_int[32..0] : WIRE;
adder_cin : WIRE;
adder_dataa[31..0] : WIRE;
adder_datab[31..0] : WIRE;
adder_result[31..0] : WIRE;
gnd_wire : WIRE;
result_tmp[31..0] : WIRE;
BEGIN
adder_result_int[] = (adder_dataa[], adder_cin) + (adder_datab[], adder_cin);
adder_result[] = adder_result_int[32..1];
adder_cin = data[31..31];
adder_dataa[] = (data[] $ data[31..31]);
adder_datab[] = ( gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire);
gnd_wire = B"0";
overflow = (result_tmp[31..31] & data[31..31]);
result[] = result_tmp[];
result_tmp[] = adder_result[];
END;
--VALID FILE

37
db/lpm_abs_jn9.tdf Normal file
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--lpm_abs CARRY_CHAIN="MANUAL" DEVICE_FAMILY="Cyclone V" IGNORE_CARRY_BUFFERS="OFF" LPM_WIDTH=4 data result
--VERSION_BEGIN 23.1 cbx_cycloneii 2023:11:29:19:33:06:SC cbx_lpm_abs 2023:11:29:19:33:06:SC cbx_lpm_add_sub 2023:11:29:19:33:06:SC cbx_mgl 2023:11:29:19:43:53:SC cbx_nadder 2023:11:29:19:33:06:SC cbx_stratix 2023:11:29:19:33:06:SC cbx_stratixii 2023:11:29:19:33:05:SC cbx_util_mgl 2023:11:29:19:33:06:SC VERSION_END
-- Copyright (C) 2023 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details, at
-- https://fpgasoftware.intel.com/eula.
--synthesis_resources = lut 3
SUBDESIGN lpm_abs_jn9
(
data[3..0] : input;
overflow : output;
result[3..0] : output;
)
VARIABLE
result_tmp[3..0] : WIRE;
BEGIN
overflow = (result_tmp[3..3] & data[3..3]);
result[] = result_tmp[];
result_tmp[] = ( (data[3..3] & (! ((data[2..2] # data[1..1]) # data[0..0]))), (((data[2..2] $ (data[1..1] # data[0..0])) & data[3..3]) # (data[2..2] & (! data[3..3]))), (((data[1..1] $ data[0..0]) & data[3..3]) # (data[1..1] & (! data[3..3]))), data[0..0]);
END;
--VALID FILE

49
db/lpm_abs_ln9.tdf Normal file
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--lpm_abs CARRY_CHAIN="MANUAL" DEVICE_FAMILY="Cyclone V" IGNORE_CARRY_BUFFERS="OFF" LPM_WIDTH=6 data result
--VERSION_BEGIN 23.1 cbx_cycloneii 2023:11:29:19:33:06:SC cbx_lpm_abs 2023:11:29:19:33:06:SC cbx_lpm_add_sub 2023:11:29:19:33:06:SC cbx_mgl 2023:11:29:19:43:53:SC cbx_nadder 2023:11:29:19:33:06:SC cbx_stratix 2023:11:29:19:33:06:SC cbx_stratixii 2023:11:29:19:33:05:SC cbx_util_mgl 2023:11:29:19:33:06:SC VERSION_END
-- Copyright (C) 2023 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details, at
-- https://fpgasoftware.intel.com/eula.
--synthesis_resources = lut 6
SUBDESIGN lpm_abs_ln9
(
data[5..0] : input;
overflow : output;
result[5..0] : output;
)
VARIABLE
adder_result_int[6..0] : WIRE;
adder_cin : WIRE;
adder_dataa[5..0] : WIRE;
adder_datab[5..0] : WIRE;
adder_result[5..0] : WIRE;
gnd_wire : WIRE;
result_tmp[5..0] : WIRE;
BEGIN
adder_result_int[] = (adder_dataa[], adder_cin) + (adder_datab[], adder_cin);
adder_result[] = adder_result_int[6..1];
adder_cin = data[5..5];
adder_dataa[] = (data[] $ data[5..5]);
adder_datab[] = ( gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire);
gnd_wire = B"0";
overflow = (result_tmp[5..5] & data[5..5]);
result[] = result_tmp[];
result_tmp[] = adder_result[];
END;
--VALID FILE

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--lpm_divide DEVICE_FAMILY="Cyclone V" LPM_DREPRESENTATION="UNSIGNED" LPM_NREPRESENTATION="UNSIGNED" LPM_WIDTHD=4 LPM_WIDTHN=8 OPTIMIZE_FOR_SPEED=5 denom numer quotient CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 IGNORE_CARRY_BUFFERS="OFF"
--VERSION_BEGIN 23.1 cbx_cycloneii 2023:11:29:19:33:06:SC cbx_lpm_abs 2023:11:29:19:33:06:SC cbx_lpm_add_sub 2023:11:29:19:33:06:SC cbx_lpm_divide 2023:11:29:19:33:06:SC cbx_mgl 2023:11:29:19:43:53:SC cbx_nadder 2023:11:29:19:33:06:SC cbx_stratix 2023:11:29:19:33:06:SC cbx_stratixii 2023:11:29:19:33:05:SC cbx_util_mgl 2023:11:29:19:33:06:SC VERSION_END
-- Copyright (C) 2023 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details, at
-- https://fpgasoftware.intel.com/eula.
FUNCTION sign_div_unsign_bkh (denominator[3..0], numerator[7..0])
RETURNS ( quotient[7..0], remainder[3..0]);
--synthesis_resources =
SUBDESIGN lpm_divide_5am
(
denom[3..0] : input;
numer[7..0] : input;
quotient[7..0] : output;
remain[3..0] : output;
)
VARIABLE
divider : sign_div_unsign_bkh;
numer_tmp[7..0] : WIRE;
BEGIN
divider.denominator[] = denom[];
divider.numerator[] = numer_tmp[];
numer_tmp[] = numer[];
quotient[] = divider.quotient[];
remain[] = divider.remainder[];
END;
--VALID FILE

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--lpm_divide DEVICE_FAMILY="Cyclone V" LPM_DREPRESENTATION="UNSIGNED" LPM_NREPRESENTATION="UNSIGNED" LPM_WIDTHD=4 LPM_WIDTHN=8 OPTIMIZE_FOR_SPEED=5 denom numer remain CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 IGNORE_CARRY_BUFFERS="OFF"
--VERSION_BEGIN 23.1 cbx_cycloneii 2023:11:29:19:33:06:SC cbx_lpm_abs 2023:11:29:19:33:06:SC cbx_lpm_add_sub 2023:11:29:19:33:06:SC cbx_lpm_divide 2023:11:29:19:33:06:SC cbx_mgl 2023:11:29:19:43:53:SC cbx_nadder 2023:11:29:19:33:06:SC cbx_stratix 2023:11:29:19:33:06:SC cbx_stratixii 2023:11:29:19:33:05:SC cbx_util_mgl 2023:11:29:19:33:06:SC VERSION_END
-- Copyright (C) 2023 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details, at
-- https://fpgasoftware.intel.com/eula.
FUNCTION sign_div_unsign_bkh (denominator[3..0], numerator[7..0])
RETURNS ( quotient[7..0], remainder[3..0]);
--synthesis_resources = lut 38
SUBDESIGN lpm_divide_82m
(
denom[3..0] : input;
numer[7..0] : input;
quotient[7..0] : output;
remain[3..0] : output;
)
VARIABLE
divider : sign_div_unsign_bkh;
numer_tmp[7..0] : WIRE;
BEGIN
divider.denominator[] = denom[];
divider.numerator[] = numer_tmp[];
numer_tmp[] = numer[];
quotient[] = divider.quotient[];
remain[] = divider.remainder[];
END;
--VALID FILE

43
db/lpm_divide_dho.tdf Normal file
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--lpm_divide DEVICE_FAMILY="Cyclone V" LPM_DREPRESENTATION="SIGNED" LPM_NREPRESENTATION="SIGNED" LPM_REMAINDERPOSITIVE="FALSE" LPM_WIDTHD=4 LPM_WIDTHN=32 OPTIMIZE_FOR_SPEED=5 denom numer remain CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 IGNORE_CARRY_BUFFERS="OFF"
--VERSION_BEGIN 23.1 cbx_cycloneii 2023:11:29:19:33:06:SC cbx_lpm_abs 2023:11:29:19:33:06:SC cbx_lpm_add_sub 2023:11:29:19:33:06:SC cbx_lpm_divide 2023:11:29:19:33:06:SC cbx_mgl 2023:11:29:19:43:53:SC cbx_nadder 2023:11:29:19:33:06:SC cbx_stratix 2023:11:29:19:33:06:SC cbx_stratixii 2023:11:29:19:33:05:SC cbx_util_mgl 2023:11:29:19:33:06:SC VERSION_END
-- Copyright (C) 2023 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details, at
-- https://fpgasoftware.intel.com/eula.
FUNCTION abs_divider_jbg (denominator[3..0], numerator[31..0])
RETURNS ( quotient[31..0], remainder[3..0]);
--synthesis_resources = lut 221
SUBDESIGN lpm_divide_dho
(
denom[3..0] : input;
numer[31..0] : input;
quotient[31..0] : output;
remain[3..0] : output;
)
VARIABLE
divider : abs_divider_jbg;
numer_tmp[31..0] : WIRE;
BEGIN
divider.denominator[] = denom[];
divider.numerator[] = numer_tmp[];
numer_tmp[] = numer[];
quotient[] = divider.quotient[];
remain[] = divider.remainder[];
END;
--VALID FILE

43
db/lpm_divide_fho.tdf Normal file
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@ -0,0 +1,43 @@
--lpm_divide DEVICE_FAMILY="Cyclone V" LPM_DREPRESENTATION="SIGNED" LPM_NREPRESENTATION="SIGNED" LPM_REMAINDERPOSITIVE="FALSE" LPM_WIDTHD=6 LPM_WIDTHN=32 OPTIMIZE_FOR_SPEED=5 denom numer remain CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 IGNORE_CARRY_BUFFERS="OFF"
--VERSION_BEGIN 23.1 cbx_cycloneii 2023:11:29:19:33:06:SC cbx_lpm_abs 2023:11:29:19:33:06:SC cbx_lpm_add_sub 2023:11:29:19:33:06:SC cbx_lpm_divide 2023:11:29:19:33:06:SC cbx_mgl 2023:11:29:19:43:53:SC cbx_nadder 2023:11:29:19:33:06:SC cbx_stratix 2023:11:29:19:33:06:SC cbx_stratixii 2023:11:29:19:33:05:SC cbx_util_mgl 2023:11:29:19:33:06:SC VERSION_END
-- Copyright (C) 2023 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details, at
-- https://fpgasoftware.intel.com/eula.
FUNCTION abs_divider_lbg (denominator[5..0], numerator[31..0])
RETURNS ( quotient[31..0], remainder[5..0]);
--synthesis_resources = lut 311
SUBDESIGN lpm_divide_fho
(
denom[5..0] : input;
numer[31..0] : input;
quotient[31..0] : output;
remain[5..0] : output;
)
VARIABLE
divider : abs_divider_lbg;
numer_tmp[31..0] : WIRE;
BEGIN
divider.denominator[] = denom[];
divider.numerator[] = numer_tmp[];
numer_tmp[] = numer[];
quotient[] = divider.quotient[];
remain[] = divider.remainder[];
END;
--VALID FILE

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