gitignore more files
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5
.gitignore
vendored
5
.gitignore
vendored
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@ -1 +1,6 @@
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obj_dir/
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db/
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incremental_db/
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output_files/
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c5_pin_model_dump.txt
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rom.bin
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@ -1,118 +0,0 @@
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io_4iomodule_c5_index: 55gpio_index: 2
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io_4iomodule_c5_index: 54gpio_index: 465
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io_4iomodule_c5_index: 33gpio_index: 6
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io_4iomodule_c5_index: 51gpio_index: 461
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io_4iomodule_c5_index: 27gpio_index: 10
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io_4iomodule_c5_index: 57gpio_index: 457
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io_4iomodule_c5_index: 34gpio_index: 14
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io_4iomodule_c5_index: 28gpio_index: 453
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io_4iomodule_c5_index: 26gpio_index: 19
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io_4iomodule_c5_index: 47gpio_index: 449
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io_4iomodule_c5_index: 29gpio_index: 22
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io_4iomodule_c5_index: 3gpio_index: 445
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io_4iomodule_c5_index: 16gpio_index: 27
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io_4iomodule_c5_index: 6gpio_index: 441
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io_4iomodule_c5_index: 50gpio_index: 30
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io_4iomodule_c5_index: 35gpio_index: 437
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io_4iomodule_c5_index: 7gpio_index: 35
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io_4iomodule_c5_index: 53gpio_index: 433
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io_4iomodule_c5_index: 12gpio_index: 38
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io_4iomodule_c5_index: 1gpio_index: 429
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io_4iomodule_c5_index: 22gpio_index: 43
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io_4iomodule_c5_index: 8gpio_index: 425
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io_4iomodule_c5_index: 20gpio_index: 46
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io_4iomodule_c5_index: 30gpio_index: 421
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io_4iomodule_c5_index: 2gpio_index: 51
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io_4iomodule_c5_index: 31gpio_index: 417
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io_4iomodule_c5_index: 39gpio_index: 54
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io_4iomodule_c5_index: 18gpio_index: 413
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io_4iomodule_c5_index: 10gpio_index: 59
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io_4iomodule_c5_index: 42gpio_index: 409
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io_4iomodule_c5_index: 5gpio_index: 62
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io_4iomodule_c5_index: 24gpio_index: 405
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io_4iomodule_c5_index: 37gpio_index: 67
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io_4iomodule_c5_index: 13gpio_index: 401
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io_4iomodule_c5_index: 0gpio_index: 70
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io_4iomodule_c5_index: 44gpio_index: 397
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io_4iomodule_c5_index: 38gpio_index: 75
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io_4iomodule_c5_index: 52gpio_index: 393
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io_4iomodule_c5_index: 32gpio_index: 78
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io_4iomodule_c5_index: 56gpio_index: 389
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io_4iomodule_a_index: 13gpio_index: 385
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io_4iomodule_c5_index: 4gpio_index: 83
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io_4iomodule_c5_index: 23gpio_index: 86
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io_4iomodule_a_index: 15gpio_index: 381
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io_4iomodule_a_index: 8gpio_index: 377
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io_4iomodule_c5_index: 46gpio_index: 91
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io_4iomodule_a_index: 5gpio_index: 373
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io_4iomodule_a_index: 11gpio_index: 369
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io_4iomodule_c5_index: 41gpio_index: 94
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io_4iomodule_a_index: 3gpio_index: 365
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io_4iomodule_c5_index: 25gpio_index: 99
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io_4iomodule_a_index: 7gpio_index: 361
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io_4iomodule_c5_index: 9gpio_index: 102
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io_4iomodule_a_index: 0gpio_index: 357
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io_4iomodule_c5_index: 14gpio_index: 107
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io_4iomodule_a_index: 12gpio_index: 353
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io_4iomodule_c5_index: 45gpio_index: 110
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io_4iomodule_c5_index: 17gpio_index: 115
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io_4iomodule_a_index: 4gpio_index: 349
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io_4iomodule_c5_index: 36gpio_index: 118
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io_4iomodule_a_index: 10gpio_index: 345
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io_4iomodule_a_index: 16gpio_index: 341
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io_4iomodule_c5_index: 15gpio_index: 123
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io_4iomodule_a_index: 14gpio_index: 337
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io_4iomodule_c5_index: 43gpio_index: 126
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io_4iomodule_c5_index: 19gpio_index: 131
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io_4iomodule_a_index: 1gpio_index: 333
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io_4iomodule_c5_index: 59gpio_index: 134
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io_4iomodule_a_index: 2gpio_index: 329
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io_4iomodule_a_index: 9gpio_index: 325
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io_4iomodule_c5_index: 48gpio_index: 139
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io_4iomodule_a_index: 6gpio_index: 321
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io_4iomodule_a_index: 17gpio_index: 317
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io_4iomodule_c5_index: 40gpio_index: 142
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io_4iomodule_c5_index: 11gpio_index: 147
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io_4iomodule_c5_index: 58gpio_index: 150
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io_4iomodule_c5_index: 21gpio_index: 155
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io_4iomodule_c5_index: 49gpio_index: 158
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io_4iomodule_h_c5_index: 0gpio_index: 161
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io_4iomodule_h_c5_index: 6gpio_index: 165
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io_4iomodule_h_c5_index: 10gpio_index: 169
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io_4iomodule_h_c5_index: 3gpio_index: 173
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io_4iomodule_h_c5_index: 8gpio_index: 176
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io_4iomodule_h_c5_index: 11gpio_index: 180
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io_4iomodule_h_c5_index: 7gpio_index: 184
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io_4iomodule_h_c5_index: 5gpio_index: 188
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io_4iomodule_h_c5_index: 1gpio_index: 192
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io_4iomodule_h_c5_index: 2gpio_index: 196
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io_4iomodule_h_c5_index: 9gpio_index: 200
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io_4iomodule_h_c5_index: 4gpio_index: 204
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io_4iomodule_h_index: 15gpio_index: 208
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io_4iomodule_h_index: 1gpio_index: 212
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io_4iomodule_h_index: 3gpio_index: 216
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io_4iomodule_h_index: 2gpio_index: 220
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io_4iomodule_h_index: 11gpio_index: 224
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io_4iomodule_vref_h_index: 1gpio_index: 228
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io_4iomodule_h_index: 20gpio_index: 231
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io_4iomodule_h_index: 8gpio_index: 235
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io_4iomodule_h_index: 6gpio_index: 239
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io_4iomodule_h_index: 10gpio_index: 243
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io_4iomodule_h_index: 23gpio_index: 247
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io_4iomodule_h_index: 7gpio_index: 251
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io_4iomodule_h_index: 22gpio_index: 255
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io_4iomodule_h_index: 5gpio_index: 259
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io_4iomodule_h_index: 24gpio_index: 263
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io_4iomodule_h_index: 0gpio_index: 267
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io_4iomodule_h_index: 13gpio_index: 271
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io_4iomodule_h_index: 21gpio_index: 275
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io_4iomodule_h_index: 16gpio_index: 279
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io_4iomodule_vref_h_index: 0gpio_index: 283
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io_4iomodule_h_index: 12gpio_index: 286
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io_4iomodule_h_index: 4gpio_index: 290
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io_4iomodule_h_index: 19gpio_index: 294
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io_4iomodule_h_index: 18gpio_index: 298
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io_4iomodule_h_index: 17gpio_index: 302
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io_4iomodule_h_index: 25gpio_index: 306
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io_4iomodule_h_index: 14gpio_index: 310
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io_4iomodule_h_index: 9gpio_index: 314
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BIN
db/.cmp.kpt
BIN
db/.cmp.kpt
Binary file not shown.
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@ -1,89 +0,0 @@
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--abs_divider DEN_REPRESENTATION="SIGNED" LPM_PIPELINE=0 MAXIMIZE_SPEED=5 NUM_REPRESENTATION="SIGNED" SKIP_BITS=0 WIDTH_D=4 WIDTH_N=32 denominator numerator quotient remainder
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--VERSION_BEGIN 23.1 cbx_cycloneii 2023:11:29:19:33:06:SC cbx_lpm_abs 2023:11:29:19:33:06:SC cbx_lpm_add_sub 2023:11:29:19:33:06:SC cbx_lpm_divide 2023:11:29:19:33:06:SC cbx_mgl 2023:11:29:19:43:53:SC cbx_nadder 2023:11:29:19:33:06:SC cbx_stratix 2023:11:29:19:33:06:SC cbx_stratixii 2023:11:29:19:33:05:SC cbx_util_mgl 2023:11:29:19:33:06:SC VERSION_END
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-- Copyright (C) 2023 Intel Corporation. All rights reserved.
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-- Your use of Intel Corporation's design tools, logic functions
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-- and other software and tools, and any partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Intel Program License
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-- Subscription Agreement, the Intel Quartus Prime License Agreement,
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-- the Intel FPGA IP License Agreement, or other applicable license
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-- agreement, including, without limitation, that your use is for
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-- the sole purpose of programming logic devices manufactured by
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-- Intel and sold by Intel or its authorized distributors. Please
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-- refer to the applicable agreement for further details, at
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-- https://fpgasoftware.intel.com/eula.
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FUNCTION alt_u_div_mve (denominator[3..0], numerator[31..0])
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RETURNS ( quotient[31..0], remainder[3..0]);
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FUNCTION lpm_abs_jn9 (data[3..0])
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RETURNS ( overflow, result[3..0]);
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FUNCTION lpm_abs_4p9 (data[31..0])
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RETURNS ( result[31..0]);
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--synthesis_resources = lut 221
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SUBDESIGN abs_divider_jbg
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(
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denominator[3..0] : input;
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numerator[31..0] : input;
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quotient[31..0] : output;
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remainder[3..0] : output;
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)
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VARIABLE
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divider : alt_u_div_mve;
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my_abs_den : lpm_abs_jn9;
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my_abs_num : lpm_abs_4p9;
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compl_add_quot_result_int[32..0] : WIRE;
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compl_add_quot_cin : WIRE;
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compl_add_quot_dataa[31..0] : WIRE;
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compl_add_quot_datab[31..0] : WIRE;
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compl_add_quot_result[31..0] : WIRE;
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compl_add_rem_result_int[4..0] : WIRE;
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compl_add_rem_cin : WIRE;
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compl_add_rem_dataa[3..0] : WIRE;
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compl_add_rem_datab[3..0] : WIRE;
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compl_add_rem_result[3..0] : WIRE;
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diff_signs : WIRE;
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gnd_wire : WIRE;
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neg_quot[31..0] : WIRE;
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neg_rem[3..0] : WIRE;
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norm_den[3..0] : WIRE;
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norm_num[31..0] : WIRE;
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num_sign : WIRE;
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protect_quotient[31..0] : WIRE;
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protect_remainder[3..0] : WIRE;
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vcc_wire : WIRE;
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BEGIN
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divider.denominator[] = norm_den[];
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divider.numerator[] = norm_num[];
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my_abs_den.data[] = denominator[];
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my_abs_num.data[] = numerator[];
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compl_add_quot_result_int[] = (compl_add_quot_dataa[], compl_add_quot_cin) + (compl_add_quot_datab[], compl_add_quot_cin);
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compl_add_quot_result[] = compl_add_quot_result_int[32..1];
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compl_add_quot_cin = vcc_wire;
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compl_add_quot_dataa[] = (! protect_quotient[]);
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compl_add_quot_datab[] = ( gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire);
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compl_add_rem_result_int[] = (compl_add_rem_dataa[], compl_add_rem_cin) + (compl_add_rem_datab[], compl_add_rem_cin);
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compl_add_rem_result[] = compl_add_rem_result_int[4..1];
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compl_add_rem_cin = vcc_wire;
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compl_add_rem_dataa[] = (! protect_remainder[]);
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compl_add_rem_datab[] = ( gnd_wire, gnd_wire, gnd_wire, gnd_wire);
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diff_signs = (numerator[31..31] $ denominator[3..3]);
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gnd_wire = B"0";
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neg_quot[] = compl_add_quot_result[];
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neg_rem[] = compl_add_rem_result[];
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norm_den[] = my_abs_den.result[];
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norm_num[] = my_abs_num.result[];
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num_sign = numerator[31..31];
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protect_quotient[] = divider.quotient[];
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protect_remainder[] = divider.remainder[];
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quotient[] = ((protect_quotient[] & (! diff_signs)) # (neg_quot[] & diff_signs));
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remainder[] = ((protect_remainder[] & (! num_sign)) # (neg_rem[] & num_sign));
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vcc_wire = B"1";
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END;
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--VALID FILE
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@ -1,89 +0,0 @@
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--abs_divider DEN_REPRESENTATION="SIGNED" LPM_PIPELINE=0 MAXIMIZE_SPEED=5 NUM_REPRESENTATION="SIGNED" SKIP_BITS=0 WIDTH_D=6 WIDTH_N=32 denominator numerator quotient remainder
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--VERSION_BEGIN 23.1 cbx_cycloneii 2023:11:29:19:33:06:SC cbx_lpm_abs 2023:11:29:19:33:06:SC cbx_lpm_add_sub 2023:11:29:19:33:06:SC cbx_lpm_divide 2023:11:29:19:33:06:SC cbx_mgl 2023:11:29:19:43:53:SC cbx_nadder 2023:11:29:19:33:06:SC cbx_stratix 2023:11:29:19:33:06:SC cbx_stratixii 2023:11:29:19:33:05:SC cbx_util_mgl 2023:11:29:19:33:06:SC VERSION_END
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-- Copyright (C) 2023 Intel Corporation. All rights reserved.
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-- Your use of Intel Corporation's design tools, logic functions
|
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-- and other software and tools, and any partner logic
|
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-- functions, and any output files from any of the foregoing
|
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-- (including device programming or simulation files), and any
|
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-- associated documentation or information are expressly subject
|
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-- to the terms and conditions of the Intel Program License
|
||||
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
-- the Intel FPGA IP License Agreement, or other applicable license
|
||||
-- agreement, including, without limitation, that your use is for
|
||||
-- the sole purpose of programming logic devices manufactured by
|
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-- Intel and sold by Intel or its authorized distributors. Please
|
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-- refer to the applicable agreement for further details, at
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-- https://fpgasoftware.intel.com/eula.
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FUNCTION alt_u_div_qve (denominator[5..0], numerator[31..0])
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RETURNS ( quotient[31..0], remainder[5..0]);
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FUNCTION lpm_abs_ln9 (data[5..0])
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RETURNS ( overflow, result[5..0]);
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FUNCTION lpm_abs_4p9 (data[31..0])
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RETURNS ( overflow, result[31..0]);
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--synthesis_resources = lut 311
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SUBDESIGN abs_divider_lbg
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(
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denominator[5..0] : input;
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numerator[31..0] : input;
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quotient[31..0] : output;
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remainder[5..0] : output;
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)
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VARIABLE
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divider : alt_u_div_qve;
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my_abs_den : lpm_abs_ln9;
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my_abs_num : lpm_abs_4p9;
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compl_add_quot_result_int[32..0] : WIRE;
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compl_add_quot_cin : WIRE;
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compl_add_quot_dataa[31..0] : WIRE;
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compl_add_quot_datab[31..0] : WIRE;
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compl_add_quot_result[31..0] : WIRE;
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compl_add_rem_result_int[6..0] : WIRE;
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compl_add_rem_cin : WIRE;
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compl_add_rem_dataa[5..0] : WIRE;
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compl_add_rem_datab[5..0] : WIRE;
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compl_add_rem_result[5..0] : WIRE;
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diff_signs : WIRE;
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gnd_wire : WIRE;
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neg_quot[31..0] : WIRE;
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neg_rem[5..0] : WIRE;
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norm_den[5..0] : WIRE;
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norm_num[31..0] : WIRE;
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num_sign : WIRE;
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protect_quotient[31..0] : WIRE;
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protect_remainder[5..0] : WIRE;
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vcc_wire : WIRE;
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BEGIN
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divider.denominator[] = norm_den[];
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divider.numerator[] = norm_num[];
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my_abs_den.data[] = denominator[];
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my_abs_num.data[] = numerator[];
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compl_add_quot_result_int[] = (compl_add_quot_dataa[], compl_add_quot_cin) + (compl_add_quot_datab[], compl_add_quot_cin);
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compl_add_quot_result[] = compl_add_quot_result_int[32..1];
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compl_add_quot_cin = vcc_wire;
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compl_add_quot_dataa[] = (! protect_quotient[]);
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compl_add_quot_datab[] = ( gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire);
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compl_add_rem_result_int[] = (compl_add_rem_dataa[], compl_add_rem_cin) + (compl_add_rem_datab[], compl_add_rem_cin);
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compl_add_rem_result[] = compl_add_rem_result_int[6..1];
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compl_add_rem_cin = vcc_wire;
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compl_add_rem_dataa[] = (! protect_remainder[]);
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compl_add_rem_datab[] = ( gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire);
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diff_signs = (numerator[31..31] $ denominator[5..5]);
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gnd_wire = B"0";
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neg_quot[] = compl_add_quot_result[];
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neg_rem[] = compl_add_rem_result[];
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norm_den[] = my_abs_den.result[];
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norm_num[] = my_abs_num.result[];
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num_sign = numerator[31..31];
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protect_quotient[] = divider.quotient[];
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protect_remainder[] = divider.remainder[];
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quotient[] = ((protect_quotient[] & (! diff_signs)) # (neg_quot[] & diff_signs));
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remainder[] = ((protect_remainder[] & (! num_sign)) # (neg_rem[] & num_sign));
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vcc_wire = B"1";
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END;
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--VALID FILE
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File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
|
|
@ -1,142 +0,0 @@
|
|||
--alt_u_div DEVICE_FAMILY="Cyclone V" LPM_PIPELINE=0 MAXIMIZE_SPEED=5 SKIP_BITS=0 WIDTH_D=4 WIDTH_N=8 WIDTH_Q=8 WIDTH_R=4 denominator numerator quotient remainder
|
||||
--VERSION_BEGIN 23.1 cbx_cycloneii 2023:11:29:19:33:06:SC cbx_lpm_abs 2023:11:29:19:33:06:SC cbx_lpm_add_sub 2023:11:29:19:33:06:SC cbx_lpm_divide 2023:11:29:19:33:06:SC cbx_mgl 2023:11:29:19:43:53:SC cbx_nadder 2023:11:29:19:33:06:SC cbx_stratix 2023:11:29:19:33:06:SC cbx_stratixii 2023:11:29:19:33:05:SC cbx_util_mgl 2023:11:29:19:33:06:SC VERSION_END
|
||||
|
||||
|
||||
-- Copyright (C) 2023 Intel Corporation. All rights reserved.
|
||||
-- Your use of Intel Corporation's design tools, logic functions
|
||||
-- and other software and tools, and any partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Intel Program License
|
||||
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
-- the Intel FPGA IP License Agreement, or other applicable license
|
||||
-- agreement, including, without limitation, that your use is for
|
||||
-- the sole purpose of programming logic devices manufactured by
|
||||
-- Intel and sold by Intel or its authorized distributors. Please
|
||||
-- refer to the applicable agreement for further details, at
|
||||
-- https://fpgasoftware.intel.com/eula.
|
||||
|
||||
|
||||
|
||||
--synthesis_resources = lut 38
|
||||
SUBDESIGN alt_u_div_sse
|
||||
(
|
||||
denominator[3..0] : input;
|
||||
numerator[7..0] : input;
|
||||
quotient[7..0] : output;
|
||||
remainder[3..0] : output;
|
||||
)
|
||||
VARIABLE
|
||||
add_sub_0_result_int[1..0] : WIRE;
|
||||
add_sub_0_cout : WIRE;
|
||||
add_sub_0_dataa[0..0] : WIRE;
|
||||
add_sub_0_datab[0..0] : WIRE;
|
||||
add_sub_0_result[0..0] : WIRE;
|
||||
add_sub_1_result_int[2..0] : WIRE;
|
||||
add_sub_1_cout : WIRE;
|
||||
add_sub_1_dataa[1..0] : WIRE;
|
||||
add_sub_1_datab[1..0] : WIRE;
|
||||
add_sub_1_result[1..0] : WIRE;
|
||||
add_sub_2_result_int[3..0] : WIRE;
|
||||
add_sub_2_cout : WIRE;
|
||||
add_sub_2_dataa[2..0] : WIRE;
|
||||
add_sub_2_datab[2..0] : WIRE;
|
||||
add_sub_2_result[2..0] : WIRE;
|
||||
add_sub_3_result_int[4..0] : WIRE;
|
||||
add_sub_3_cout : WIRE;
|
||||
add_sub_3_dataa[3..0] : WIRE;
|
||||
add_sub_3_datab[3..0] : WIRE;
|
||||
add_sub_3_result[3..0] : WIRE;
|
||||
add_sub_4_result_int[5..0] : WIRE;
|
||||
add_sub_4_cout : WIRE;
|
||||
add_sub_4_dataa[4..0] : WIRE;
|
||||
add_sub_4_datab[4..0] : WIRE;
|
||||
add_sub_4_result[4..0] : WIRE;
|
||||
add_sub_5_result_int[5..0] : WIRE;
|
||||
add_sub_5_cout : WIRE;
|
||||
add_sub_5_dataa[4..0] : WIRE;
|
||||
add_sub_5_datab[4..0] : WIRE;
|
||||
add_sub_5_result[4..0] : WIRE;
|
||||
add_sub_6_result_int[5..0] : WIRE;
|
||||
add_sub_6_cout : WIRE;
|
||||
add_sub_6_dataa[4..0] : WIRE;
|
||||
add_sub_6_datab[4..0] : WIRE;
|
||||
add_sub_6_result[4..0] : WIRE;
|
||||
add_sub_7_result_int[5..0] : WIRE;
|
||||
add_sub_7_cout : WIRE;
|
||||
add_sub_7_dataa[4..0] : WIRE;
|
||||
add_sub_7_datab[4..0] : WIRE;
|
||||
add_sub_7_result[4..0] : WIRE;
|
||||
DenominatorIn[44..0] : WIRE;
|
||||
DenominatorIn_tmp[44..0] : WIRE;
|
||||
gnd_wire : WIRE;
|
||||
nose[71..0] : WIRE;
|
||||
NumeratorIn[71..0] : WIRE;
|
||||
NumeratorIn_tmp[71..0] : WIRE;
|
||||
prestg[39..0] : WIRE;
|
||||
quotient_tmp[7..0] : WIRE;
|
||||
sel[35..0] : WIRE;
|
||||
selnose[71..0] : WIRE;
|
||||
StageIn[44..0] : WIRE;
|
||||
StageIn_tmp[44..0] : WIRE;
|
||||
StageOut[39..0] : WIRE;
|
||||
|
||||
BEGIN
|
||||
add_sub_0_result_int[] = (0, add_sub_0_dataa[]) - (0, add_sub_0_datab[]);
|
||||
add_sub_0_result[] = add_sub_0_result_int[0..0];
|
||||
add_sub_0_cout = !add_sub_0_result_int[1];
|
||||
add_sub_0_dataa[] = NumeratorIn[7..7];
|
||||
add_sub_0_datab[] = DenominatorIn[0..0];
|
||||
add_sub_1_result_int[] = (0, add_sub_1_dataa[]) - (0, add_sub_1_datab[]);
|
||||
add_sub_1_result[] = add_sub_1_result_int[1..0];
|
||||
add_sub_1_cout = !add_sub_1_result_int[2];
|
||||
add_sub_1_dataa[] = ( StageIn[5..5], NumeratorIn[14..14]);
|
||||
add_sub_1_datab[] = DenominatorIn[6..5];
|
||||
add_sub_2_result_int[] = (0, add_sub_2_dataa[]) - (0, add_sub_2_datab[]);
|
||||
add_sub_2_result[] = add_sub_2_result_int[2..0];
|
||||
add_sub_2_cout = !add_sub_2_result_int[3];
|
||||
add_sub_2_dataa[] = ( StageIn[11..10], NumeratorIn[21..21]);
|
||||
add_sub_2_datab[] = DenominatorIn[12..10];
|
||||
add_sub_3_result_int[] = (0, add_sub_3_dataa[]) - (0, add_sub_3_datab[]);
|
||||
add_sub_3_result[] = add_sub_3_result_int[3..0];
|
||||
add_sub_3_cout = !add_sub_3_result_int[4];
|
||||
add_sub_3_dataa[] = ( StageIn[17..15], NumeratorIn[28..28]);
|
||||
add_sub_3_datab[] = DenominatorIn[18..15];
|
||||
add_sub_4_result_int[] = (0, add_sub_4_dataa[]) - (0, add_sub_4_datab[]);
|
||||
add_sub_4_result[] = add_sub_4_result_int[4..0];
|
||||
add_sub_4_cout = !add_sub_4_result_int[5];
|
||||
add_sub_4_dataa[] = ( StageIn[23..20], NumeratorIn[35..35]);
|
||||
add_sub_4_datab[] = DenominatorIn[24..20];
|
||||
add_sub_5_result_int[] = (0, add_sub_5_dataa[]) - (0, add_sub_5_datab[]);
|
||||
add_sub_5_result[] = add_sub_5_result_int[4..0];
|
||||
add_sub_5_cout = !add_sub_5_result_int[5];
|
||||
add_sub_5_dataa[] = ( StageIn[28..25], NumeratorIn[42..42]);
|
||||
add_sub_5_datab[] = DenominatorIn[29..25];
|
||||
add_sub_6_result_int[] = (0, add_sub_6_dataa[]) - (0, add_sub_6_datab[]);
|
||||
add_sub_6_result[] = add_sub_6_result_int[4..0];
|
||||
add_sub_6_cout = !add_sub_6_result_int[5];
|
||||
add_sub_6_dataa[] = ( StageIn[33..30], NumeratorIn[49..49]);
|
||||
add_sub_6_datab[] = DenominatorIn[34..30];
|
||||
add_sub_7_result_int[] = (0, add_sub_7_dataa[]) - (0, add_sub_7_datab[]);
|
||||
add_sub_7_result[] = add_sub_7_result_int[4..0];
|
||||
add_sub_7_cout = !add_sub_7_result_int[5];
|
||||
add_sub_7_dataa[] = ( StageIn[38..35], NumeratorIn[56..56]);
|
||||
add_sub_7_datab[] = DenominatorIn[39..35];
|
||||
DenominatorIn[] = DenominatorIn_tmp[];
|
||||
DenominatorIn_tmp[] = ( DenominatorIn[39..0], ( gnd_wire, denominator[]));
|
||||
gnd_wire = B"0";
|
||||
nose[] = ( B"00000000", add_sub_7_cout, B"00000000", add_sub_6_cout, B"00000000", add_sub_5_cout, B"00000000", add_sub_4_cout, B"00000000", add_sub_3_cout, B"00000000", add_sub_2_cout, B"00000000", add_sub_1_cout, B"00000000", add_sub_0_cout);
|
||||
NumeratorIn[] = NumeratorIn_tmp[];
|
||||
NumeratorIn_tmp[] = ( NumeratorIn[63..0], numerator[]);
|
||||
prestg[] = ( add_sub_7_result[], add_sub_6_result[], add_sub_5_result[], add_sub_4_result[], GND, add_sub_3_result[], B"00", add_sub_2_result[], B"000", add_sub_1_result[], B"0000", add_sub_0_result[]);
|
||||
quotient[] = quotient_tmp[];
|
||||
quotient_tmp[] = ( (! selnose[0..0]), (! selnose[9..9]), (! selnose[18..18]), (! selnose[27..27]), (! selnose[36..36]), (! selnose[45..45]), (! selnose[54..54]), (! selnose[63..63]));
|
||||
remainder[3..0] = StageIn[43..40];
|
||||
sel[] = ( gnd_wire, (sel[35..35] # DenominatorIn[43..43]), (sel[34..34] # DenominatorIn[42..42]), (sel[33..33] # DenominatorIn[41..41]), gnd_wire, (sel[31..31] # DenominatorIn[38..38]), (sel[30..30] # DenominatorIn[37..37]), (sel[29..29] # DenominatorIn[36..36]), gnd_wire, (sel[27..27] # DenominatorIn[33..33]), (sel[26..26] # DenominatorIn[32..32]), (sel[25..25] # DenominatorIn[31..31]), gnd_wire, (sel[23..23] # DenominatorIn[28..28]), (sel[22..22] # DenominatorIn[27..27]), (sel[21..21] # DenominatorIn[26..26]), gnd_wire, (sel[19..19] # DenominatorIn[23..23]), (sel[18..18] # DenominatorIn[22..22]), (sel[17..17] # DenominatorIn[21..21]), gnd_wire, (sel[15..15] # DenominatorIn[18..18]), (sel[14..14] # DenominatorIn[17..17]), (sel[13..13] # DenominatorIn[16..16]), gnd_wire, (sel[11..11] # DenominatorIn[13..13]), (sel[10..10] # DenominatorIn[12..12]), (sel[9..9] # DenominatorIn[11..11]), gnd_wire, (sel[7..7] # DenominatorIn[8..8]), (sel[6..6] # DenominatorIn[7..7]), (sel[5..5] # DenominatorIn[6..6]), gnd_wire, (sel[3..3] # DenominatorIn[3..3]), (sel[2..2] # DenominatorIn[2..2]), (sel[1..1] # DenominatorIn[1..1]));
|
||||
selnose[] = ( (! nose[71..71]), (! nose[70..70]), (! nose[69..69]), (! nose[68..68]), ((! nose[67..67]) # sel[35..35]), ((! nose[66..66]) # sel[34..34]), ((! nose[65..65]) # sel[33..33]), ((! nose[64..64]) # sel[32..32]), (! nose[63..63]), (! nose[62..62]), (! nose[61..61]), (! nose[60..60]), ((! nose[59..59]) # sel[31..31]), ((! nose[58..58]) # sel[30..30]), ((! nose[57..57]) # sel[29..29]), ((! nose[56..56]) # sel[28..28]), (! nose[55..55]), (! nose[54..54]), (! nose[53..53]), (! nose[52..52]), ((! nose[51..51]) # sel[27..27]), ((! nose[50..50]) # sel[26..26]), ((! nose[49..49]) # sel[25..25]), ((! nose[48..48]) # sel[24..24]), (! nose[47..47]), (! nose[46..46]), (! nose[45..45]), (! nose[44..44]), ((! nose[43..43]) # sel[23..23]), ((! nose[42..42]) # sel[22..22]), ((! nose[41..41]) # sel[21..21]), ((! nose[40..40]) # sel[20..20]), (! nose[39..39]), (! nose[38..38]), (! nose[37..37]), (! nose[36..36]), ((! nose[35..35]) # sel[19..19]), ((! nose[34..34]) # sel[18..18]), ((! nose[33..33]) # sel[17..17]), ((! nose[32..32]) # sel[16..16]), (! nose[31..31]), (! nose[30..30]), (! nose[29..29]), (! nose[28..28]), ((! nose[27..27]) # sel[15..15]), ((! nose[26..26]) # sel[14..14]), ((! nose[25..25]) # sel[13..13]), ((! nose[24..24]) # sel[12..12]), (! nose[23..23]), (! nose[22..22]), (! nose[21..21]), (! nose[20..20]), ((! nose[19..19]) # sel[11..11]), ((! nose[18..18]) # sel[10..10]), ((! nose[17..17]) # sel[9..9]), ((! nose[16..16]) # sel[8..8]), (! nose[15..15]), (! nose[14..14]), (! nose[13..13]), (! nose[12..12]), ((! nose[11..11]) # sel[7..7]), ((! nose[10..10]) # sel[6..6]), ((! nose[9..9]) # sel[5..5]), ((! nose[8..8]) # sel[4..4]), (! nose[7..7]), (! nose[6..6]), (! nose[5..5]), (! nose[4..4]), ((! nose[3..3]) # sel[3..3]), ((! nose[2..2]) # sel[2..2]), ((! nose[1..1]) # sel[1..1]), ((! nose[0..0]) # sel[0..0]));
|
||||
StageIn[] = StageIn_tmp[];
|
||||
StageIn_tmp[] = ( StageOut[39..0], B"00000");
|
||||
StageOut[] = ( ((( StageIn[38..35], NumeratorIn[56..56]) & selnose[63..63]) # (prestg[39..35] & (! selnose[63..63]))), ((( StageIn[33..30], NumeratorIn[49..49]) & selnose[54..54]) # (prestg[34..30] & (! selnose[54..54]))), ((( StageIn[28..25], NumeratorIn[42..42]) & selnose[45..45]) # (prestg[29..25] & (! selnose[45..45]))), ((( StageIn[23..20], NumeratorIn[35..35]) & selnose[36..36]) # (prestg[24..20] & (! selnose[36..36]))), ((( StageIn[18..15], NumeratorIn[28..28]) & selnose[27..27]) # (prestg[19..15] & (! selnose[27..27]))), ((( StageIn[13..10], NumeratorIn[21..21]) & selnose[18..18]) # (prestg[14..10] & (! selnose[18..18]))), ((( StageIn[8..5], NumeratorIn[14..14]) & selnose[9..9]) # (prestg[9..5] & (! selnose[9..9]))), ((( StageIn[3..0], NumeratorIn[7..7]) & selnose[0..0]) # (prestg[4..0] & (! selnose[0..0]))));
|
||||
END;
|
||||
--VALID FILE
|
||||
|
|
@ -1,300 +0,0 @@
|
|||
--altsyncram ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone V" INDATA_ACLR_A="NONE" INIT_FILE="db/chip8.ram0_memory_e9e85012.hdl.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=4096 NUMWORDS_B=4096 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED" READ_DURING_WRITE_MODE_MIXED_PORTS="OLD_DATA" WIDTH_A=8 WIDTH_B=8 WIDTHAD_A=12 WIDTHAD_B=12 WRCONTROL_ACLR_A="NONE" address_a address_b clock0 data_a q_b CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
|
||||
--VERSION_BEGIN 23.1 cbx_altera_syncram_nd_impl 2023:11:29:19:33:06:SC cbx_altsyncram 2023:11:29:19:33:06:SC cbx_cycloneii 2023:11:29:19:33:06:SC cbx_lpm_add_sub 2023:11:29:19:33:06:SC cbx_lpm_compare 2023:11:29:19:33:06:SC cbx_lpm_decode 2023:11:29:19:33:06:SC cbx_lpm_mux 2023:11:29:19:33:05:SC cbx_mgl 2023:11:29:19:43:53:SC cbx_nadder 2023:11:29:19:33:06:SC cbx_stratix 2023:11:29:19:33:06:SC cbx_stratixii 2023:11:29:19:33:05:SC cbx_stratixiii 2023:11:29:19:33:06:SC cbx_stratixv 2023:11:29:19:33:05:SC cbx_util_mgl 2023:11:29:19:33:06:SC VERSION_END
|
||||
|
||||
|
||||
-- Copyright (C) 2023 Intel Corporation. All rights reserved.
|
||||
-- Your use of Intel Corporation's design tools, logic functions
|
||||
-- and other software and tools, and any partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Intel Program License
|
||||
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
-- the Intel FPGA IP License Agreement, or other applicable license
|
||||
-- agreement, including, without limitation, that your use is for
|
||||
-- the sole purpose of programming logic devices manufactured by
|
||||
-- Intel and sold by Intel or its authorized distributors. Please
|
||||
-- refer to the applicable agreement for further details, at
|
||||
-- https://fpgasoftware.intel.com/eula.
|
||||
|
||||
|
||||
FUNCTION cyclonev_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
|
||||
WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, ENABLE_ECC, INIT_FILE, INIT_FILE_LAYOUT, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init10, mem_init11, mem_init12, mem_init13, mem_init14, mem_init15, mem_init16, mem_init17, mem_init18, mem_init19, mem_init2, mem_init20, mem_init21, mem_init22, mem_init23, mem_init24, mem_init25, mem_init26, mem_init27, mem_init28, mem_init29, mem_init3, mem_init30, mem_init31, mem_init32, mem_init33, mem_init34, mem_init35, mem_init36, mem_init37, mem_init38, mem_init39, mem_init4, mem_init40, mem_init41, mem_init42, mem_init43, mem_init44, mem_init45, mem_init46, mem_init47, mem_init48, mem_init49, mem_init5, mem_init50, mem_init51, mem_init52, mem_init53, mem_init54, mem_init55, mem_init56, mem_init57, mem_init58, mem_init59, mem_init6, mem_init60, mem_init61, mem_init62, mem_init63, mem_init64, mem_init65, mem_init66, mem_init67, mem_init68, mem_init69, mem_init7, mem_init70, mem_init71, mem_init8, mem_init9, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, WIDTH_ECCSTATUS = 3)
|
||||
RETURNS ( dftout[8..0], eccstatus[WIDTH_ECCSTATUS-1..0], portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
|
||||
|
||||
--synthesis_resources = M10K 4
|
||||
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
|
||||
|
||||
SUBDESIGN altsyncram_dsq1
|
||||
(
|
||||
address_a[11..0] : input;
|
||||
address_b[11..0] : input;
|
||||
clock0 : input;
|
||||
data_a[7..0] : input;
|
||||
q_b[7..0] : output;
|
||||
)
|
||||
VARIABLE
|
||||
ram_block1a0 : cyclonev_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "db/chip8.ram0_memory_e9e85012.hdl.mif",
|
||||
INIT_FILE_LAYOUT = "port_b",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
||||
OPERATION_MODE = "dual_port",
|
||||
PORT_A_ADDRESS_WIDTH = 12,
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 0,
|
||||
PORT_A_LAST_ADDRESS = 4095,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 4096,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
||||
PORT_B_ADDRESS_CLEAR = "none",
|
||||
PORT_B_ADDRESS_CLOCK = "clock0",
|
||||
PORT_B_ADDRESS_WIDTH = 12,
|
||||
PORT_B_DATA_OUT_CLEAR = "none",
|
||||
PORT_B_DATA_WIDTH = 1,
|
||||
PORT_B_FIRST_ADDRESS = 0,
|
||||
PORT_B_FIRST_BIT_NUMBER = 0,
|
||||
PORT_B_LAST_ADDRESS = 4095,
|
||||
PORT_B_LOGICAL_RAM_DEPTH = 4096,
|
||||
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
||||
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a1 : cyclonev_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "db/chip8.ram0_memory_e9e85012.hdl.mif",
|
||||
INIT_FILE_LAYOUT = "port_b",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
||||
OPERATION_MODE = "dual_port",
|
||||
PORT_A_ADDRESS_WIDTH = 12,
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 1,
|
||||
PORT_A_LAST_ADDRESS = 4095,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 4096,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
||||
PORT_B_ADDRESS_CLEAR = "none",
|
||||
PORT_B_ADDRESS_CLOCK = "clock0",
|
||||
PORT_B_ADDRESS_WIDTH = 12,
|
||||
PORT_B_DATA_OUT_CLEAR = "none",
|
||||
PORT_B_DATA_WIDTH = 1,
|
||||
PORT_B_FIRST_ADDRESS = 0,
|
||||
PORT_B_FIRST_BIT_NUMBER = 1,
|
||||
PORT_B_LAST_ADDRESS = 4095,
|
||||
PORT_B_LOGICAL_RAM_DEPTH = 4096,
|
||||
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
||||
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a2 : cyclonev_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "db/chip8.ram0_memory_e9e85012.hdl.mif",
|
||||
INIT_FILE_LAYOUT = "port_b",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
||||
OPERATION_MODE = "dual_port",
|
||||
PORT_A_ADDRESS_WIDTH = 12,
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 2,
|
||||
PORT_A_LAST_ADDRESS = 4095,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 4096,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
||||
PORT_B_ADDRESS_CLEAR = "none",
|
||||
PORT_B_ADDRESS_CLOCK = "clock0",
|
||||
PORT_B_ADDRESS_WIDTH = 12,
|
||||
PORT_B_DATA_OUT_CLEAR = "none",
|
||||
PORT_B_DATA_WIDTH = 1,
|
||||
PORT_B_FIRST_ADDRESS = 0,
|
||||
PORT_B_FIRST_BIT_NUMBER = 2,
|
||||
PORT_B_LAST_ADDRESS = 4095,
|
||||
PORT_B_LOGICAL_RAM_DEPTH = 4096,
|
||||
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
||||
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a3 : cyclonev_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "db/chip8.ram0_memory_e9e85012.hdl.mif",
|
||||
INIT_FILE_LAYOUT = "port_b",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
||||
OPERATION_MODE = "dual_port",
|
||||
PORT_A_ADDRESS_WIDTH = 12,
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 3,
|
||||
PORT_A_LAST_ADDRESS = 4095,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 4096,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
||||
PORT_B_ADDRESS_CLEAR = "none",
|
||||
PORT_B_ADDRESS_CLOCK = "clock0",
|
||||
PORT_B_ADDRESS_WIDTH = 12,
|
||||
PORT_B_DATA_OUT_CLEAR = "none",
|
||||
PORT_B_DATA_WIDTH = 1,
|
||||
PORT_B_FIRST_ADDRESS = 0,
|
||||
PORT_B_FIRST_BIT_NUMBER = 3,
|
||||
PORT_B_LAST_ADDRESS = 4095,
|
||||
PORT_B_LOGICAL_RAM_DEPTH = 4096,
|
||||
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
||||
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a4 : cyclonev_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "db/chip8.ram0_memory_e9e85012.hdl.mif",
|
||||
INIT_FILE_LAYOUT = "port_b",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
||||
OPERATION_MODE = "dual_port",
|
||||
PORT_A_ADDRESS_WIDTH = 12,
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 4,
|
||||
PORT_A_LAST_ADDRESS = 4095,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 4096,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
||||
PORT_B_ADDRESS_CLEAR = "none",
|
||||
PORT_B_ADDRESS_CLOCK = "clock0",
|
||||
PORT_B_ADDRESS_WIDTH = 12,
|
||||
PORT_B_DATA_OUT_CLEAR = "none",
|
||||
PORT_B_DATA_WIDTH = 1,
|
||||
PORT_B_FIRST_ADDRESS = 0,
|
||||
PORT_B_FIRST_BIT_NUMBER = 4,
|
||||
PORT_B_LAST_ADDRESS = 4095,
|
||||
PORT_B_LOGICAL_RAM_DEPTH = 4096,
|
||||
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
||||
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a5 : cyclonev_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "db/chip8.ram0_memory_e9e85012.hdl.mif",
|
||||
INIT_FILE_LAYOUT = "port_b",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
||||
OPERATION_MODE = "dual_port",
|
||||
PORT_A_ADDRESS_WIDTH = 12,
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 5,
|
||||
PORT_A_LAST_ADDRESS = 4095,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 4096,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
||||
PORT_B_ADDRESS_CLEAR = "none",
|
||||
PORT_B_ADDRESS_CLOCK = "clock0",
|
||||
PORT_B_ADDRESS_WIDTH = 12,
|
||||
PORT_B_DATA_OUT_CLEAR = "none",
|
||||
PORT_B_DATA_WIDTH = 1,
|
||||
PORT_B_FIRST_ADDRESS = 0,
|
||||
PORT_B_FIRST_BIT_NUMBER = 5,
|
||||
PORT_B_LAST_ADDRESS = 4095,
|
||||
PORT_B_LOGICAL_RAM_DEPTH = 4096,
|
||||
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
||||
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a6 : cyclonev_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "db/chip8.ram0_memory_e9e85012.hdl.mif",
|
||||
INIT_FILE_LAYOUT = "port_b",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
||||
OPERATION_MODE = "dual_port",
|
||||
PORT_A_ADDRESS_WIDTH = 12,
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 6,
|
||||
PORT_A_LAST_ADDRESS = 4095,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 4096,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
||||
PORT_B_ADDRESS_CLEAR = "none",
|
||||
PORT_B_ADDRESS_CLOCK = "clock0",
|
||||
PORT_B_ADDRESS_WIDTH = 12,
|
||||
PORT_B_DATA_OUT_CLEAR = "none",
|
||||
PORT_B_DATA_WIDTH = 1,
|
||||
PORT_B_FIRST_ADDRESS = 0,
|
||||
PORT_B_FIRST_BIT_NUMBER = 6,
|
||||
PORT_B_LAST_ADDRESS = 4095,
|
||||
PORT_B_LOGICAL_RAM_DEPTH = 4096,
|
||||
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
||||
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a7 : cyclonev_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "db/chip8.ram0_memory_e9e85012.hdl.mif",
|
||||
INIT_FILE_LAYOUT = "port_b",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
||||
OPERATION_MODE = "dual_port",
|
||||
PORT_A_ADDRESS_WIDTH = 12,
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 7,
|
||||
PORT_A_LAST_ADDRESS = 4095,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 4096,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
||||
PORT_B_ADDRESS_CLEAR = "none",
|
||||
PORT_B_ADDRESS_CLOCK = "clock0",
|
||||
PORT_B_ADDRESS_WIDTH = 12,
|
||||
PORT_B_DATA_OUT_CLEAR = "none",
|
||||
PORT_B_DATA_WIDTH = 1,
|
||||
PORT_B_FIRST_ADDRESS = 0,
|
||||
PORT_B_FIRST_BIT_NUMBER = 7,
|
||||
PORT_B_LAST_ADDRESS = 4095,
|
||||
PORT_B_LOGICAL_RAM_DEPTH = 4096,
|
||||
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
||||
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
address_a_wire[11..0] : WIRE;
|
||||
address_b_wire[11..0] : WIRE;
|
||||
wren_a : NODE;
|
||||
|
||||
BEGIN
|
||||
ram_block1a[7..0].clk0 = clock0;
|
||||
ram_block1a[7..0].portaaddr[] = ( address_a_wire[11..0]);
|
||||
ram_block1a[0].portadatain[] = ( data_a[0..0]);
|
||||
ram_block1a[1].portadatain[] = ( data_a[1..1]);
|
||||
ram_block1a[2].portadatain[] = ( data_a[2..2]);
|
||||
ram_block1a[3].portadatain[] = ( data_a[3..3]);
|
||||
ram_block1a[4].portadatain[] = ( data_a[4..4]);
|
||||
ram_block1a[5].portadatain[] = ( data_a[5..5]);
|
||||
ram_block1a[6].portadatain[] = ( data_a[6..6]);
|
||||
ram_block1a[7].portadatain[] = ( data_a[7..7]);
|
||||
ram_block1a[7..0].portawe = wren_a;
|
||||
ram_block1a[7..0].portbaddr[] = ( address_b_wire[11..0]);
|
||||
ram_block1a[7..0].portbre = B"11111111";
|
||||
address_a_wire[] = address_a[];
|
||||
address_b_wire[] = address_b[];
|
||||
q_b[] = ( ram_block1a[7..0].portbdataout[0..0]);
|
||||
wren_a = GND;
|
||||
END;
|
||||
--VALID FILE
|
||||
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|
|
@ -1,6 +0,0 @@
|
|||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1712584339260 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition " "Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1712584339260 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Apr 8 08:52:19 2024 " "Processing started: Mon Apr 8 08:52:19 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1712584339260 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1712584339260 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off chip8 -c chip8 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off chip8 -c chip8" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1712584339260 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1712584340042 ""}
|
||||
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1712584345507 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "628 " "Peak virtual memory: 628 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1712584345784 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 8 08:52:25 2024 " "Processing ended: Mon Apr 8 08:52:25 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1712584345784 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1712584345784 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1712584345784 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1712584345784 ""}
|
||||
BIN
db/chip8.asm.rdb
BIN
db/chip8.asm.rdb
Binary file not shown.
|
|
@ -1,5 +0,0 @@
|
|||
<?xml version="1.0" ?>
|
||||
<LOG_ROOT>
|
||||
<PROJECT NAME="chip8">
|
||||
</PROJECT>
|
||||
</LOG_ROOT>
|
||||
BIN
db/chip8.cmp.bpm
BIN
db/chip8.cmp.bpm
Binary file not shown.
BIN
db/chip8.cmp.cdb
BIN
db/chip8.cmp.cdb
Binary file not shown.
BIN
db/chip8.cmp.hdb
BIN
db/chip8.cmp.hdb
Binary file not shown.
BIN
db/chip8.cmp.idb
BIN
db/chip8.cmp.idb
Binary file not shown.
|
|
@ -1,50 +0,0 @@
|
|||
v1
|
||||
IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
|
||||
IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
|
||||
IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
|
||||
IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
|
||||
IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
|
||||
IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
|
||||
IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
|
||||
IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
|
||||
IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
|
||||
IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
|
||||
IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
|
||||
IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
|
||||
IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,
|
||||
IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,
|
||||
IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
|
||||
IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
|
||||
IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
|
||||
IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,
|
||||
IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
|
||||
IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
|
||||
IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,
|
||||
IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
|
||||
IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
|
||||
IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
|
||||
IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
|
||||
IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
|
||||
IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
|
||||
IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 0 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
|
||||
IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
|
||||
IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000001;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000047;IO_000046;IO_000045;IO_000027;IO_000026;IO_000024;IO_000023;IO_000022;IO_000021;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000034,
|
||||
IO_RULES_MATRIX,Total Pass,0;10;10;0;0;10;10;0;0;0;0;0;0;1;0;0;0;0;1;0;0;0;0;1;0;10;10;0,
|
||||
IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
|
||||
IO_RULES_MATRIX,Total Inapplicable,10;0;0;10;10;0;0;10;10;10;10;10;10;9;10;10;10;10;9;10;10;10;10;9;10;0;0;10,
|
||||
IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
|
||||
IO_RULES_MATRIX,lcd_clk,Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
|
||||
IO_RULES_MATRIX,lcd_data,Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
|
||||
IO_RULES_MATRIX,led[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
|
||||
IO_RULES_MATRIX,led[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
|
||||
IO_RULES_MATRIX,led[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
|
||||
IO_RULES_MATRIX,led[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
|
||||
IO_RULES_MATRIX,led[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
|
||||
IO_RULES_MATRIX,led[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
|
||||
IO_RULES_MATRIX,rst_in,Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
|
||||
IO_RULES_MATRIX,fpga_clk,Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
|
||||
IO_RULES_SUMMARY,Total I/O Rules,28,
|
||||
IO_RULES_SUMMARY,Number of I/O Rules Passed,9,
|
||||
IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
|
||||
IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
|
||||
IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,19,
|
||||
BIN
db/chip8.cmp.rdb
BIN
db/chip8.cmp.rdb
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -1,3 +0,0 @@
|
|||
Quartus_Version = Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition
|
||||
Version_Index = 570679040
|
||||
Creation_Time = Sun Apr 7 23:44:47 2024
|
||||
BIN
db/chip8.eco.cdb
BIN
db/chip8.eco.cdb
Binary file not shown.
|
|
@ -1,47 +0,0 @@
|
|||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1712584068646 ""}
|
||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "12 12 " "Parallel compilation is enabled and will use 12 of the 12 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1712584068647 ""}
|
||||
{ "Info" "IMPP_MPP_USER_DEVICE" "chip8 5CSEBA6U23I7 " "Selected device 5CSEBA6U23I7 for design \"chip8\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1712584068695 ""}
|
||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature -40 degrees C " "Low junction temperature is -40 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1712584068718 ""}
|
||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 100 degrees C " "High junction temperature is 100 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1712584068719 ""}
|
||||
{ "Warning" "WMPP_MPP_RAM_IS_ACTUALLY_ROM_TOP" "" "Found RAM instances implemented as ROM because the write logic is disabled. One instance is listed below as an example." { { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "memory:mem\|altsyncram:mem_rtl_0\|altsyncram_dsq1:auto_generated\|ram_block1a4 " "Atom \"memory:mem\|altsyncram:mem_rtl_0\|altsyncram_dsq1:auto_generated\|ram_block1a4\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Design Software" 0 -1 1712584068781 "|chip8|memory:mem|altsyncram:mem_rtl_0|altsyncram_dsq1:auto_generated|ram_block1a4"} } { } 0 18550 "Found RAM instances implemented as ROM because the write logic is disabled. One instance is listed below as an example." 0 0 "Fitter" 0 -1 1712584068781 ""}
|
||||
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1712584069129 ""}
|
||||
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1712584069151 ""}
|
||||
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1712584069410 ""}
|
||||
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1712584069535 ""}
|
||||
{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1712584076794 ""}
|
||||
{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "2 s (2 global) " "Automatically promoted 2 clocks (2 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "downclocker:dc\|clk_out~CLKENA0 8651 global CLKCTRL_G2 " "downclocker:dc\|clk_out~CLKENA0 with 8651 fanout uses global clock CLKCTRL_G2" { { "Info" "ICCLK_UNLOCKED_FOR_VPR" "" "This signal is driven by core routing -- it may be moved during placement to reduce routing delays" { } { } 0 12525 "This signal is driven by core routing -- it may be moved during placement to reduce routing delays" 0 0 "Design Software" 0 -1 1712584077135 ""} } { } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1712584077135 ""} { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "fpga_clk~inputCLKENA0 19 global CLKCTRL_G5 " "fpga_clk~inputCLKENA0 with 19 fanout uses global clock CLKCTRL_G5" { } { } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1712584077135 ""} } { } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1712584077135 ""}
|
||||
{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1712584077136 ""}
|
||||
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1712584077211 ""}
|
||||
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1712584077246 ""}
|
||||
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1712584077302 ""}
|
||||
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1712584077356 ""}
|
||||
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1712584077356 ""}
|
||||
{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1712584077382 ""}
|
||||
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "chip8.sdc " "Synopsys Design Constraints File file not found: 'chip8.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1712584078336 ""}
|
||||
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1712584078336 ""}
|
||||
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1712584078556 ""}
|
||||
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1712584078557 ""}
|
||||
{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1712584078562 ""}
|
||||
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1712584079519 ""}
|
||||
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1712584079542 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1712584079542 ""}
|
||||
{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "lcd_cs " "Node \"lcd_cs\" is assigned to location or region, but does not exist in design" { } { { "/opt/intelFPGA/23.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/opt/intelFPGA/23.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "lcd_cs" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1712584079755 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1712584079755 ""}
|
||||
{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:10 " "Fitter preparation operations ending: elapsed time is 00:00:10" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1712584079756 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1712584082588 ""}
|
||||
{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1712584084069 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:39 " "Fitter placement preparation operations ending: elapsed time is 00:00:39" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1712584121786 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1712584149944 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1712584168529 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:19 " "Fitter placement operations ending: elapsed time is 00:00:19" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1712584168529 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1712584170647 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "12 " "Router estimated average interconnect usage is 12% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "58 X22_Y11 X32_Y22 " "Router estimated peak interconnect usage is 58% of the available device resources in the region that extends from location X22_Y11 to location X32_Y22" { } { { "loc" "" { Generic "/home/nickorlow/programming/school/warminster/yayacemu/" { { 1 { 0 "Router estimated peak interconnect usage is 58% of the available device resources in the region that extends from location X22_Y11 to location X32_Y22"} { { 12 { 0 ""} 22 11 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1712584194284 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1712584194284 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1712584298166 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1712584298166 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:02:05 " "Fitter routing operations ending: elapsed time is 00:02:05" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1712584298172 ""}
|
||||
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 36.34 " "Total time spent on timing analysis during the Fitter is 36.34 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1712584310458 ""}
|
||||
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1712584310576 ""}
|
||||
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1712584314203 ""}
|
||||
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1712584314216 ""}
|
||||
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1712584318324 ""}
|
||||
{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:23 " "Fitter post-fit operations ending: elapsed time is 00:00:23" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1712584333182 ""}
|
||||
{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1712584333786 ""}
|
||||
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/nickorlow/programming/school/warminster/yayacemu/output_files/chip8.fit.smsg " "Generated suppressed messages file /home/nickorlow/programming/school/warminster/yayacemu/output_files/chip8.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1712584334741 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 8 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2824 " "Peak virtual memory: 2824 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1712584338184 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 8 08:52:18 2024 " "Processing ended: Mon Apr 8 08:52:18 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1712584338184 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:04:30 " "Elapsed time: 00:04:30" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1712584338184 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:11:39 " "Total CPU time (on all processors): 00:11:39" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1712584338184 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1712584338184 ""}
|
||||
25868
db/chip8.hier_info
25868
db/chip8.hier_info
File diff suppressed because it is too large
Load diff
BIN
db/chip8.hif
BIN
db/chip8.hif
Binary file not shown.
|
|
@ -1,130 +0,0 @@
|
|||
<TABLE>
|
||||
<TR bgcolor="#C0C0C0">
|
||||
<TH>Hierarchy</TH>
|
||||
<TH>Input</TH>
|
||||
<TH>Constant Input</TH>
|
||||
<TH>Unused Input</TH>
|
||||
<TH>Floating Input</TH>
|
||||
<TH>Output</TH>
|
||||
<TH>Constant Output</TH>
|
||||
<TH>Unused Output</TH>
|
||||
<TH>Floating Output</TH>
|
||||
<TH>Bidir</TH>
|
||||
<TH>Constant Bidir</TH>
|
||||
<TH>Unused Bidir</TH>
|
||||
<TH>Input only Bidir</TH>
|
||||
<TH>Output only Bidir</TH>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >cpu|gpu|dff</TD>
|
||||
<TD >2</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >1</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >cpu|gpu|com</TD>
|
||||
<TD >12</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >1</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >cpu|gpu</TD>
|
||||
<TD >8194</TD>
|
||||
<TD >7</TD>
|
||||
<TD >0</TD>
|
||||
<TD >7</TD>
|
||||
<TD >8</TD>
|
||||
<TD >7</TD>
|
||||
<TD >7</TD>
|
||||
<TD >7</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >cpu|alu</TD>
|
||||
<TD >50</TD>
|
||||
<TD >0</TD>
|
||||
<TD >32</TD>
|
||||
<TD >0</TD>
|
||||
<TD >10</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >cpu</TD>
|
||||
<TD >10</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >73</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >mem</TD>
|
||||
<TD >34</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >8</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >dc</TD>
|
||||
<TD >1</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >1</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
</TABLE>
|
||||
BIN
db/chip8.lpc.rdb
BIN
db/chip8.lpc.rdb
Binary file not shown.
|
|
@ -1,13 +0,0 @@
|
|||
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Legal Partition Candidates ;
|
||||
+-------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
|
||||
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
|
||||
+-------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
|
||||
; cpu|gpu|dff ; 2 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; cpu|gpu|com ; 12 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; cpu|gpu ; 8194 ; 7 ; 0 ; 7 ; 8 ; 7 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; cpu|alu ; 50 ; 0 ; 32 ; 0 ; 10 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; cpu ; 10 ; 0 ; 0 ; 0 ; 73 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; mem ; 34 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; dc ; 1 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
+-------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
|
||||
Binary file not shown.
BIN
db/chip8.map.bpm
BIN
db/chip8.map.bpm
Binary file not shown.
BIN
db/chip8.map.cdb
BIN
db/chip8.map.cdb
Binary file not shown.
BIN
db/chip8.map.hdb
BIN
db/chip8.map.hdb
Binary file not shown.
BIN
db/chip8.map.kpt
BIN
db/chip8.map.kpt
Binary file not shown.
|
|
@ -1,55 +0,0 @@
|
|||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1712584011618 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition " "Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1712584011618 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Apr 8 08:46:51 2024 " "Processing started: Mon Apr 8 08:46:51 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1712584011618 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712584011618 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off chip8 -c chip8 " "Command: quartus_map --read_settings_files=on --write_settings_files=off chip8 -c chip8" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712584011618 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1712584011793 ""}
|
||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "12 12 " "Parallel compilation is enabled and will use 12 of the 12 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1712584011793 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "the-bomb/st7920_serial_driver.sv 3 3 " "Found 3 design units, including 3 entities, in source file the-bomb/st7920_serial_driver.sv" { { "Info" "ISGN_ENTITY_NAME" "1 st7920_serial_driver " "Found entity 1: st7920_serial_driver" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712584016098 ""} { "Info" "ISGN_ENTITY_NAME" "2 d_flip_flop " "Found entity 2: d_flip_flop" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 137 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712584016098 ""} { "Info" "ISGN_ENTITY_NAME" "3 commander " "Found entity 3: commander" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 147 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712584016098 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712584016098 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "chip8.sv 1 1 " "Found 1 design units, including 1 entities, in source file chip8.sv" { { "Info" "ISGN_ENTITY_NAME" "1 chip8 " "Found entity 1: chip8" { } { { "chip8.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/chip8.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712584016099 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712584016099 ""}
|
||||
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "alu ALU cpu.sv(33) " "Verilog HDL Declaration information at cpu.sv(33): object \"alu\" differs only in case from object \"ALU\" in the same scope" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 33 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1712584016100 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu.sv 1 1 " "Found 1 design units, including 1 entities, in source file cpu.sv" { { "Info" "ISGN_ENTITY_NAME" "1 cpu " "Found entity 1: cpu" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712584016100 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712584016100 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "alu.sv 1 1 " "Found 1 design units, including 1 entities, in source file alu.sv" { { "Info" "ISGN_ENTITY_NAME" "1 alu " "Found entity 1: alu" { } { { "alu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/alu.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712584016100 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712584016100 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "aastructs.sv 1 0 " "Found 1 design units, including 0 entities, in source file aastructs.sv" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 structs (SystemVerilog) " "Found design unit 1: structs (SystemVerilog)" { } { { "aastructs.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/aastructs.sv" 1 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712584016101 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712584016101 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "downclocker.sv 1 1 " "Found 1 design units, including 1 entities, in source file downclocker.sv" { { "Info" "ISGN_ENTITY_NAME" "1 downclocker " "Found entity 1: downclocker" { } { { "downclocker.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/downclocker.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712584016101 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712584016101 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_TOP" "chip8 " "Elaborating entity \"chip8\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1712584016136 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "downclocker downclocker:dc " "Elaborating entity \"downclocker\" for hierarchy \"downclocker:dc\"" { } { { "chip8.sv" "dc" { Text "/home/nickorlow/programming/school/warminster/yayacemu/chip8.sv" 14 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712584016138 ""}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 downclocker.sv(18) " "Verilog HDL assignment warning at downclocker.sv(18): truncated value with size 32 to match size of target (10)" { } { { "downclocker.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/downclocker.sv" 18 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712584016138 "|chip8|downclocker:dc"}
|
||||
{ "Warning" "WSGN_SEARCH_FILE" "memory.sv 1 1 " "Using design file memory.sv, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 memory " "Found entity 1: memory" { } { { "memory.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/memory.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712584016142 ""} } { } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1712584016142 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "memory memory:mem " "Elaborating entity \"memory\" for hierarchy \"memory:mem\"" { } { { "chip8.sv" "mem" { Text "/home/nickorlow/programming/school/warminster/yayacemu/chip8.sv" 29 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712584016143 ""}
|
||||
{ "Warning" "WVRFX_VERI_2111_UNCONVERTED" "80 0 4095 memory.sv(14) " "Verilog HDL warning at memory.sv(14): number of words (80) in memory file does not match the number of elements in the address range \[0:4095\]" { } { { "memory.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/memory.sv" 14 0 0 } } } 0 10850 "Verilog HDL warning at %4!s!: number of words (%1!d!) in memory file does not match the number of elements in the address range \[%2!d!:%3!d!\]" 0 0 "Analysis & Synthesis" 0 -1 1712584016143 "|chip8|memory:mem"}
|
||||
{ "Warning" "WVRFX_VERI_2111_UNCONVERTED" "132 512 4095 memory.sv(15) " "Verilog HDL warning at memory.sv(15): number of words (132) in memory file does not match the number of elements in the address range \[512:4095\]" { } { { "memory.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/memory.sv" 15 0 0 } } } 0 10850 "Verilog HDL warning at %4!s!: number of words (%1!d!) in memory file does not match the number of elements in the address range \[%2!d!:%3!d!\]" 0 0 "Analysis & Synthesis" 0 -1 1712584016143 "|chip8|memory:mem"}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu cpu:cpu " "Elaborating entity \"cpu\" for hierarchy \"cpu:cpu\"" { } { { "chip8.sv" "cpu" { Text "/home/nickorlow/programming/school/warminster/yayacemu/chip8.sv" 44 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712584016144 ""}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(148) " "Verilog HDL assignment warning at cpu.sv(148): truncated value with size 32 to match size of target (16)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 148 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712584016275 "|chip8|cpu:cpu"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(154) " "Verilog HDL assignment warning at cpu.sv(154): truncated value with size 32 to match size of target (16)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 154 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712584016275 "|chip8|cpu:cpu"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(171) " "Verilog HDL assignment warning at cpu.sv(171): truncated value with size 32 to match size of target (16)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 171 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712584016275 "|chip8|cpu:cpu"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 cpu.sv(249) " "Verilog HDL assignment warning at cpu.sv(249): truncated value with size 32 to match size of target (5)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 249 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712584016277 "|chip8|cpu:cpu"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 cpu.sv(252) " "Verilog HDL assignment warning at cpu.sv(252): truncated value with size 32 to match size of target (5)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 252 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712584016277 "|chip8|cpu:cpu"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(281) " "Verilog HDL assignment warning at cpu.sv(281): truncated value with size 32 to match size of target (16)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 281 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712584016282 "|chip8|cpu:cpu"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 cpu.sv(285) " "Verilog HDL assignment warning at cpu.sv(285): truncated value with size 32 to match size of target (5)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 285 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712584016282 "|chip8|cpu:cpu"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 cpu.sv(296) " "Verilog HDL assignment warning at cpu.sv(296): truncated value with size 32 to match size of target (5)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 296 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712584016642 "|chip8|cpu:cpu"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(323) " "Verilog HDL assignment warning at cpu.sv(323): truncated value with size 32 to match size of target (16)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 323 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712584016663 "|chip8|cpu:cpu"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(333) " "Verilog HDL assignment warning at cpu.sv(333): truncated value with size 32 to match size of target (16)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 333 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712584016664 "|chip8|cpu:cpu"}
|
||||
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "instr.src_reg 0 cpu.sv(131) " "Net \"instr.src_reg\" at cpu.sv(131) has no driver or initial value, using a default initial value '0'" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 131 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1712584017054 "|chip8|cpu:cpu"}
|
||||
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "instr.src_addr 0 cpu.sv(131) " "Net \"instr.src_addr\" at cpu.sv(131) has no driver or initial value, using a default initial value '0'" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 131 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1712584017054 "|chip8|cpu:cpu"}
|
||||
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "instr.dst_addr 0 cpu.sv(131) " "Net \"instr.dst_addr\" at cpu.sv(131) has no driver or initial value, using a default initial value '0'" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 131 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1712584017054 "|chip8|cpu:cpu"}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu cpu:cpu\|alu:alu " "Elaborating entity \"alu\" for hierarchy \"cpu:cpu\|alu:alu\"" { } { { "cpu.sv" "alu" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 33 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712584019602 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "st7920_serial_driver cpu:cpu\|st7920_serial_driver:gpu " "Elaborating entity \"st7920_serial_driver\" for hierarchy \"cpu:cpu\|st7920_serial_driver:gpu\"" { } { { "cpu.sv" "gpu" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 49 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712584019606 ""}
|
||||
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "line_idx st7920_serial_driver.sv(23) " "Verilog HDL or VHDL warning at st7920_serial_driver.sv(23): object \"line_idx\" assigned a value but never read" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 23 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1712584019620 "|chip8|cpu:cpu|st7920_serial_driver:gpu"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 st7920_serial_driver.sv(71) " "Verilog HDL assignment warning at st7920_serial_driver.sv(71): truncated value with size 32 to match size of target (7)" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 71 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712584019620 "|chip8|cpu:cpu|st7920_serial_driver:gpu"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 st7920_serial_driver.sv(84) " "Verilog HDL assignment warning at st7920_serial_driver.sv(84): truncated value with size 32 to match size of target (7)" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 84 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712584019620 "|chip8|cpu:cpu|st7920_serial_driver:gpu"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 st7920_serial_driver.sv(103) " "Verilog HDL assignment warning at st7920_serial_driver.sv(103): truncated value with size 32 to match size of target (6)" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 103 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712584019620 "|chip8|cpu:cpu|st7920_serial_driver:gpu"}
|
||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 9 st7920_serial_driver.sv(131) " "Verilog HDL assignment warning at st7920_serial_driver.sv(131): truncated value with size 32 to match size of target (9)" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 131 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712584019620 "|chip8|cpu:cpu|st7920_serial_driver:gpu"}
|
||||
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "commands\[6..10\] 0 st7920_serial_driver.sv(26) " "Net \"commands\[6..10\]\" at st7920_serial_driver.sv(26) has no driver or initial value, using a default initial value '0'" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 26 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1712584019620 "|chip8|cpu:cpu|st7920_serial_driver:gpu"}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "commander cpu:cpu\|st7920_serial_driver:gpu\|commander:com " "Elaborating entity \"commander\" for hierarchy \"cpu:cpu\|st7920_serial_driver:gpu\|commander:com\"" { } { { "the-bomb/st7920_serial_driver.sv" "com" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 42 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712584019621 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "d_flip_flop cpu:cpu\|st7920_serial_driver:gpu\|d_flip_flop:dff " "Elaborating entity \"d_flip_flop\" for hierarchy \"cpu:cpu\|st7920_serial_driver:gpu\|d_flip_flop:dff\"" { } { { "the-bomb/st7920_serial_driver.sv" "dff" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 50 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712584019622 ""}
|
||||
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "IINFER_ALTSYNCRAM_INFERRED" "memory:mem\|mem_rtl_0 " "Inferred altsyncram megafunction from the following design logic: \"memory:mem\|mem_rtl_0\" " { { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OPERATION_MODE DUAL_PORT " "Parameter OPERATION_MODE set to DUAL_PORT" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712584036621 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_A 8 " "Parameter WIDTH_A set to 8" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712584036621 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_A 12 " "Parameter WIDTHAD_A set to 12" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712584036621 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_A 4096 " "Parameter NUMWORDS_A set to 4096" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712584036621 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_B 8 " "Parameter WIDTH_B set to 8" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712584036621 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_B 12 " "Parameter WIDTHAD_B set to 12" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712584036621 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_B 4096 " "Parameter NUMWORDS_B set to 4096" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712584036621 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_A NONE " "Parameter ADDRESS_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712584036621 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_REG_B UNREGISTERED " "Parameter OUTDATA_REG_B set to UNREGISTERED" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712584036621 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_B NONE " "Parameter ADDRESS_ACLR_B set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712584036621 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_ACLR_B NONE " "Parameter OUTDATA_ACLR_B set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712584036621 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_REG_B CLOCK0 " "Parameter ADDRESS_REG_B set to CLOCK0" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712584036621 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "INDATA_ACLR_A NONE " "Parameter INDATA_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712584036621 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WRCONTROL_ACLR_A NONE " "Parameter WRCONTROL_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712584036621 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "INIT_FILE db/chip8.ram0_memory_e9e85012.hdl.mif " "Parameter INIT_FILE set to db/chip8.ram0_memory_e9e85012.hdl.mif" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712584036621 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "READ_DURING_WRITE_MODE_MIXED_PORTS OLD_DATA " "Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712584036621 ""} } { } 0 276029 "Inferred altsyncram megafunction from the following design logic: \"%1!s!\" " 0 0 "Design Software" 0 -1 1712584036621 ""} } { } 0 19000 "Inferred %1!d! megafunctions from design logic" 0 0 "Analysis & Synthesis" 0 -1 1712584036621 ""}
|
||||
{ "Info" "ISGN_ELABORATION_HEADER" "memory:mem\|altsyncram:mem_rtl_0 " "Elaborated megafunction instantiation \"memory:mem\|altsyncram:mem_rtl_0\"" { } { } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712584036659 ""}
|
||||
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "memory:mem\|altsyncram:mem_rtl_0 " "Instantiated megafunction \"memory:mem\|altsyncram:mem_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "OPERATION_MODE DUAL_PORT " "Parameter \"OPERATION_MODE\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712584036659 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_A 8 " "Parameter \"WIDTH_A\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712584036659 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_A 12 " "Parameter \"WIDTHAD_A\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712584036659 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_A 4096 " "Parameter \"NUMWORDS_A\" = \"4096\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712584036659 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_B 8 " "Parameter \"WIDTH_B\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712584036659 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_B 12 " "Parameter \"WIDTHAD_B\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712584036659 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_B 4096 " "Parameter \"NUMWORDS_B\" = \"4096\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712584036659 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_A NONE " "Parameter \"ADDRESS_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712584036659 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_REG_B UNREGISTERED " "Parameter \"OUTDATA_REG_B\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712584036659 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_B NONE " "Parameter \"ADDRESS_ACLR_B\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712584036659 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_ACLR_B NONE " "Parameter \"OUTDATA_ACLR_B\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712584036659 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_REG_B CLOCK0 " "Parameter \"ADDRESS_REG_B\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712584036659 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INDATA_ACLR_A NONE " "Parameter \"INDATA_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712584036659 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WRCONTROL_ACLR_A NONE " "Parameter \"WRCONTROL_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712584036659 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INIT_FILE db/chip8.ram0_memory_e9e85012.hdl.mif " "Parameter \"INIT_FILE\" = \"db/chip8.ram0_memory_e9e85012.hdl.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712584036659 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "READ_DURING_WRITE_MODE_MIXED_PORTS OLD_DATA " "Parameter \"READ_DURING_WRITE_MODE_MIXED_PORTS\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712584036659 ""} } { } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1712584036659 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_dsq1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_dsq1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_dsq1 " "Found entity 1: altsyncram_dsq1" { } { { "db/altsyncram_dsq1.tdf" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/db/altsyncram_dsq1.tdf" 28 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712584036680 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712584036680 ""}
|
||||
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "led\[4\] GND " "Pin \"led\[4\]\" is stuck at GND" { } { { "chip8.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/chip8.sv" 7 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1712584046983 "|chip8|led[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "led\[5\] GND " "Pin \"led\[5\]\" is stuck at GND" { } { { "chip8.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/chip8.sv" 7 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1712584046983 "|chip8|led[5]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1712584046983 ""}
|
||||
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1712584047706 ""}
|
||||
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "6 " "6 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1712584065406 ""}
|
||||
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/nickorlow/programming/school/warminster/yayacemu/output_files/chip8.map.smsg " "Generated suppressed messages file /home/nickorlow/programming/school/warminster/yayacemu/output_files/chip8.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712584065742 ""}
|
||||
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1712584066477 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712584066477 ""}
|
||||
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "1 " "Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "rst_in " "No output dependent on input pin \"rst_in\"" { } { { "chip8.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/chip8.sv" 3 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1712584067334 "|chip8|rst_in"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1712584067334 ""}
|
||||
{ "Info" "ICUT_CUT_TM_SUMMARY" "17552 " "Implemented 17552 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Implemented 2 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1712584067389 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1712584067389 ""} { "Info" "ICUT_CUT_TM_LCELLS" "17534 " "Implemented 17534 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1712584067389 ""} { "Info" "ICUT_CUT_TM_RAMS" "8 " "Implemented 8 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Design Software" 0 -1 1712584067389 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1712584067389 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 29 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 29 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "775 " "Peak virtual memory: 775 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1712584067421 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 8 08:47:47 2024 " "Processing ended: Mon Apr 8 08:47:47 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1712584067421 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:56 " "Elapsed time: 00:00:56" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1712584067421 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:01:34 " "Total CPU time (on all processors): 00:01:34" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1712584067421 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1712584067421 ""}
|
||||
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db/chip8.map.rdb
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db/chip8.map.rdb
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