nickorlow/yayacemu
1
0
Fork 0
Code Issues Pull requests Actions Packages Projects Releases Wiki Activity

alu works on fpga

Browse source
This commit is contained in:
Nicholas Orlowsky 2024-04-08 08:54:48 -05:00
parent 7fdf4e7739
commit 0ba56bc41e
Signed by: nickorlow
GPG key ID: 838827D8C4611687
75 changed files with 2771 additions and 2316 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
aastructs.sv
View file

@ -2,7 +2,7 @@ package structs;
typedef enum {ADD} alu_op;
typedef struct {
typedef struct packed {
logic [7:0] operand_a;
logic [7:0] operand_b;
alu_op op;

2
alu.sv
View file

@ -33,7 +33,7 @@ module alu(
result_int <= in.operand_a + in.operand_b;
result <= result_int[7:0];
overflow <= result_int[8];
if (cnt == 2) begin
if (cnt >= 2) begin
$display("%b %b + %b %b ya", result, in.operand_a, in.operand_b, result_int);
done <= 1;
end

3
chip8.qsf
View file

@ -31,6 +31,9 @@ set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name SYSTEMVERILOG_FILE "./the-bomb/st7920_serial_driver.sv"
set_global_assignment -name SYSTEMVERILOG_FILE chip8.sv
set_global_assignment -name SYSTEMVERILOG_FILE cpu.sv
set_global_assignment -name SYSTEMVERILOG_FILE alu.sv
set_global_assignment -name SYSTEMVERILOG_FILE aastructs.sv
set_global_assignment -name SYSTEMVERILOG_FILE downclocker.sv
set_global_assignment -name SDC_FILE chip8.sdc
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"

11
chip8.sv
View file

@ -5,6 +5,14 @@ module chip8 (
output logic lcd_data,
output logic [5:0] led
);
logic slow_clk;
`ifdef FAST_CLK
assign slow_clk = fpga_clk;
`endif
`ifndef FAST_CLK
downclocker #(10) dc(fpga_clk, slow_clk);
`endif
logic [7:0] rd_memory_data;
logic [11:0] rd_memory_address;
@ -12,7 +20,7 @@ module chip8 (
logic [7:0] wr_memory_data;
logic wr_go;
memory #(4096) mem (
fpga_clk,
slow_clk,
wr_go,
wr_memory_address,
wr_memory_data,
@ -22,6 +30,7 @@ module chip8 (
int cycle_counter;
cpu cpu (
slow_clk,
fpga_clk,
rd_memory_data,
cycle_counter,

10
cpu.sv
View file

@ -2,6 +2,7 @@ import structs::*;
module cpu (
input wire clk_in,
input wire fpga_clk,
input wire [7:0] rd_memory_data,
output int cycle_counter,
output logic [11:0] rd_memory_address,
@ -13,12 +14,15 @@ module cpu (
output logic [5:0] led
);
logic [5:0] lcd_led;
logic alu_rst;
logic [7:0] alu_result;
logic alu_overflow;
logic alu_done;
logic compute_of;
assign led = state[5:0];
alu alu (
alu_rst,
clk_in,
@ -36,12 +40,12 @@ module cpu (
`ifndef DUMMY_GPU
st7920_serial_driver gpu(
`endif
clk_in,
fpga_clk,
1'b1,
vram,
lcd_clk,
lcd_data,
led
lcd_led
);
task write_pixels;
@ -101,7 +105,7 @@ module cpu (
} draw_state;
struct {
struct packed {
cpu_opcode op;
data_type src;
data_type dst;

BIN
db/.cmp.kpt
View file

Binary file not shown.

BIN
db/chip8.(0).cnf.cdb
View file

Binary file not shown.

BIN
db/chip8.(0).cnf.hdb
View file

Binary file not shown.

BIN
db/chip8.(1).cnf.cdb
View file

Binary file not shown.

BIN
db/chip8.(1).cnf.hdb
View file

Binary file not shown.

BIN
db/chip8.(2).cnf.cdb
View file

Binary file not shown.

BIN
db/chip8.(2).cnf.hdb
View file

Binary file not shown.

12
db/chip8.asm.qmsg
View file

@ -1,6 +1,6 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1712551930527 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition " "Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1712551930527 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 7 23:52:10 2024 " "Processing started: Sun Apr 7 23:52:10 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1712551930527 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1712551930527 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off chip8 -c chip8 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off chip8 -c chip8" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1712551930527 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1712551931223 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1712551937283 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "631 " "Peak virtual memory: 631 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1712551937598 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 7 23:52:17 2024 " "Processing ended: Sun Apr 7 23:52:17 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1712551937598 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1712551937598 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1712551937598 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1712551937598 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1712584339260 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition " "Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1712584339260 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Apr 8 08:52:19 2024 " "Processing started: Mon Apr 8 08:52:19 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1712584339260 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1712584339260 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off chip8 -c chip8 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off chip8 -c chip8" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1712584339260 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1712584340042 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1712584345507 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "628 " "Peak virtual memory: 628 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1712584345784 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 8 08:52:25 2024 " "Processing ended: Mon Apr 8 08:52:25 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1712584345784 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1712584345784 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1712584345784 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1712584345784 ""}

BIN
db/chip8.asm.rdb
View file

Binary file not shown.

BIN
db/chip8.cmp.bpm
View file

Binary file not shown.

BIN
db/chip8.cmp.cdb
View file

Binary file not shown.

BIN
db/chip8.cmp.hdb
View file

Binary file not shown.

BIN
db/chip8.cmp.idb
View file

Binary file not shown.

BIN
db/chip8.cmp.rdb
View file

Binary file not shown.

94
db/chip8.fit.qmsg
View file

@ -1,47 +1,47 @@
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1712551555206 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "12 12 " "Parallel compilation is enabled and will use 12 of the 12 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1712551555206 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "chip8 5CSEBA6U23I7 " "Selected device 5CSEBA6U23I7 for design \"chip8\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1712551555269 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature -40 degrees C " "Low junction temperature is -40 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1712551555292 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 100 degrees C " "High junction temperature is 100 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1712551555292 ""}
{ "Warning" "WMPP_MPP_RAM_IS_ACTUALLY_ROM_TOP" "" "Found RAM instances implemented as ROM because the write logic is disabled. One instance is listed below as an example." { { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "memory:mem\|altsyncram:mem_rtl_0\|altsyncram_dsq1:auto_generated\|ram_block1a4 " "Atom \"memory:mem\|altsyncram:mem_rtl_0\|altsyncram_dsq1:auto_generated\|ram_block1a4\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Design Software" 0 -1 1712551555358 "|chip8|memory:mem|altsyncram:mem_rtl_0|altsyncram_dsq1:auto_generated|ram_block1a4"} } { } 0 18550 "Found RAM instances implemented as ROM because the write logic is disabled. One instance is listed below as an example." 0 0 "Fitter" 0 -1 1712551555358 ""}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1712551555754 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1712551555775 ""}
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1712551556100 ""}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1712551556280 ""}
{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1712551564414 ""}
{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1 (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "fpga_clk~inputCLKENA0 8563 global CLKCTRL_G5 " "fpga_clk~inputCLKENA0 with 8563 fanout uses global clock CLKCTRL_G5" { } { } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1712551564875 ""} } { } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1712551564875 ""}
{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1712551564876 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1712551564962 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1712551564999 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1712551565068 ""}
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1712551565142 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1712551565142 ""}
{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1712551565178 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "chip8.sdc " "Synopsys Design Constraints File file not found: 'chip8.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1712551566238 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1712551566238 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1712551566558 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1712551566558 ""}
{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1712551566563 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1712551568020 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1712551568056 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1712551568056 ""}
{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "lcd_cs " "Node \"lcd_cs\" is assigned to location or region, but does not exist in design" { } { { "/opt/intelFPGA/23.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/opt/intelFPGA/23.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "lcd_cs" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1712551568422 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1712551568422 ""}
{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:13 " "Fitter preparation operations ending: elapsed time is 00:00:13" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1712551568422 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1712551572577 ""}
{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1712551575144 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:52 " "Fitter placement preparation operations ending: elapsed time is 00:00:52" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1712551625159 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1712551662013 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1712551685328 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:24 " "Fitter placement operations ending: elapsed time is 00:00:24" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1712551685328 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1712551687722 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "12 " "Router estimated average interconnect usage is 12% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "57 X22_Y23 X32_Y34 " "Router estimated peak interconnect usage is 57% of the available device resources in the region that extends from location X22_Y23 to location X32_Y34" { } { { "loc" "" { Generic "/home/nickorlow/programming/school/warminster/yayacemu/" { { 1 { 0 "Router estimated peak interconnect usage is 57% of the available device resources in the region that extends from location X22_Y23 to location X32_Y34"} { { 12 { 0 ""} 22 23 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1712551718020 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1712551718020 ""}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1712551878467 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1712551878467 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:03:08 " "Fitter routing operations ending: elapsed time is 00:03:08" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1712551878471 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 49.90 " "Total time spent on timing analysis during the Fitter is 49.90 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1712551894479 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1712551894660 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1712551899814 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1712551899828 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1712551905639 ""}
{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:29 " "Fitter post-fit operations ending: elapsed time is 00:00:29" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1712551923094 ""}
{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1712551923931 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/nickorlow/programming/school/warminster/yayacemu/output_files/chip8.fit.smsg " "Generated suppressed messages file /home/nickorlow/programming/school/warminster/yayacemu/output_files/chip8.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1712551925355 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 8 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2797 " "Peak virtual memory: 2797 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1712551929265 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 7 23:52:09 2024 " "Processing ended: Sun Apr 7 23:52:09 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1712551929265 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:06:15 " "Elapsed time: 00:06:15" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1712551929265 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:14:19 " "Total CPU time (on all processors): 00:14:19" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1712551929265 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1712551929265 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1712584068646 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "12 12 " "Parallel compilation is enabled and will use 12 of the 12 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1712584068647 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "chip8 5CSEBA6U23I7 " "Selected device 5CSEBA6U23I7 for design \"chip8\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1712584068695 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature -40 degrees C " "Low junction temperature is -40 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1712584068718 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 100 degrees C " "High junction temperature is 100 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1712584068719 ""}
{ "Warning" "WMPP_MPP_RAM_IS_ACTUALLY_ROM_TOP" "" "Found RAM instances implemented as ROM because the write logic is disabled. One instance is listed below as an example." { { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "memory:mem\|altsyncram:mem_rtl_0\|altsyncram_dsq1:auto_generated\|ram_block1a4 " "Atom \"memory:mem\|altsyncram:mem_rtl_0\|altsyncram_dsq1:auto_generated\|ram_block1a4\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Design Software" 0 -1 1712584068781 "|chip8|memory:mem|altsyncram:mem_rtl_0|altsyncram_dsq1:auto_generated|ram_block1a4"} } { } 0 18550 "Found RAM instances implemented as ROM because the write logic is disabled. One instance is listed below as an example." 0 0 "Fitter" 0 -1 1712584068781 ""}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1712584069129 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1712584069151 ""}
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1712584069410 ""}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1712584069535 ""}
{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1712584076794 ""}
{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "2 s (2 global) " "Automatically promoted 2 clocks (2 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "downclocker:dc\|clk_out~CLKENA0 8651 global CLKCTRL_G2 " "downclocker:dc\|clk_out~CLKENA0 with 8651 fanout uses global clock CLKCTRL_G2" { { "Info" "ICCLK_UNLOCKED_FOR_VPR" "" "This signal is driven by core routing -- it may be moved during placement to reduce routing delays" { } { } 0 12525 "This signal is driven by core routing -- it may be moved during placement to reduce routing delays" 0 0 "Design Software" 0 -1 1712584077135 ""} } { } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1712584077135 ""} { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "fpga_clk~inputCLKENA0 19 global CLKCTRL_G5 " "fpga_clk~inputCLKENA0 with 19 fanout uses global clock CLKCTRL_G5" { } { } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1712584077135 ""} } { } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1712584077135 ""}
{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1712584077136 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1712584077211 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1712584077246 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1712584077302 ""}
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1712584077356 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1712584077356 ""}
{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1712584077382 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "chip8.sdc " "Synopsys Design Constraints File file not found: 'chip8.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1712584078336 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1712584078336 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1712584078556 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1712584078557 ""}
{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1712584078562 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1712584079519 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1712584079542 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1712584079542 ""}
{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "lcd_cs " "Node \"lcd_cs\" is assigned to location or region, but does not exist in design" { } { { "/opt/intelFPGA/23.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/opt/intelFPGA/23.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "lcd_cs" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1712584079755 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1712584079755 ""}
{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:10 " "Fitter preparation operations ending: elapsed time is 00:00:10" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1712584079756 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1712584082588 ""}
{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1712584084069 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:39 " "Fitter placement preparation operations ending: elapsed time is 00:00:39" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1712584121786 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1712584149944 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1712584168529 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:19 " "Fitter placement operations ending: elapsed time is 00:00:19" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1712584168529 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1712584170647 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "12 " "Router estimated average interconnect usage is 12% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "58 X22_Y11 X32_Y22 " "Router estimated peak interconnect usage is 58% of the available device resources in the region that extends from location X22_Y11 to location X32_Y22" { } { { "loc" "" { Generic "/home/nickorlow/programming/school/warminster/yayacemu/" { { 1 { 0 "Router estimated peak interconnect usage is 58% of the available device resources in the region that extends from location X22_Y11 to location X32_Y22"} { { 12 { 0 ""} 22 11 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1712584194284 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1712584194284 ""}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1712584298166 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1712584298166 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:02:05 " "Fitter routing operations ending: elapsed time is 00:02:05" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1712584298172 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 36.34 " "Total time spent on timing analysis during the Fitter is 36.34 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1712584310458 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1712584310576 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1712584314203 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1712584314216 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1712584318324 ""}
{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:23 " "Fitter post-fit operations ending: elapsed time is 00:00:23" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1712584333182 ""}
{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1712584333786 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/nickorlow/programming/school/warminster/yayacemu/output_files/chip8.fit.smsg " "Generated suppressed messages file /home/nickorlow/programming/school/warminster/yayacemu/output_files/chip8.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1712584334741 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 8 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2824 " "Peak virtual memory: 2824 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1712584338184 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 8 08:52:18 2024 " "Processing ended: Mon Apr 8 08:52:18 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1712584338184 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:04:30 " "Elapsed time: 00:04:30" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1712584338184 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:11:39 " "Total CPU time (on all processors): 00:11:39" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1712584338184 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1712584338184 ""}

257
db/chip8.hier_info
View file

@ -1,14 +1,29 @@
|chip8
fpga_clk => fpga_clk.IN2
rst_in => ~NO_FANOUT~
lcd_clk << cpu:cpu.port7
lcd_data << cpu:cpu.port8
led[0] << cpu:cpu.port9
led[1] << cpu:cpu.port9
led[2] << cpu:cpu.port9
led[3] << cpu:cpu.port9
led[4] << cpu:cpu.port9
led[5] << cpu:cpu.port9
lcd_clk << cpu:cpu.port8
lcd_data << cpu:cpu.port9
led[0] << cpu:cpu.port10
led[1] << cpu:cpu.port10
led[2] << cpu:cpu.port10
led[3] << cpu:cpu.port10
led[4] << cpu:cpu.port10
led[5] << cpu:cpu.port10
|chip8|downclocker:dc
clk_in => counter[0].CLK
clk_in => counter[1].CLK
clk_in => counter[2].CLK
clk_in => counter[3].CLK
clk_in => counter[4].CLK
clk_in => counter[5].CLK
clk_in => counter[6].CLK
clk_in => counter[7].CLK
clk_in => counter[8].CLK
clk_in => counter[9].CLK
clk_in => clk_out~reg0.CLK
clk_out <= clk_out~reg0.DB_MAX_OUTPUT_PORT_TYPE
|chip8|memory:mem
@ -107,7 +122,7 @@ data_out[7] <= data_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|chip8|cpu:cpu
clk_in => st7920_serial_driver:gpu.sys_clk
clk_in => alu:alu.clk_in
clk_in => cycle_counter[0]~reg0.CLK
clk_in => cycle_counter[1]~reg0.CLK
clk_in => cycle_counter[2]~reg0.CLK
@ -173,6 +188,7 @@ clk_in => wr_memory_address[8]~reg0.CLK
clk_in => wr_memory_address[9]~reg0.CLK
clk_in => wr_memory_address[10]~reg0.CLK
clk_in => wr_memory_address[11]~reg0.CLK
clk_in => alu_rst.CLK
clk_in => vram[1023][0].CLK
clk_in => vram[1023][1].CLK
clk_in => vram[1023][2].CLK
@ -8535,6 +8551,7 @@ clk_in => draw_state.stage[28].CLK
clk_in => draw_state.stage[29].CLK
clk_in => draw_state.stage[30].CLK
clk_in => draw_state.stage[31].CLK
clk_in => compute_of.CLK
clk_in => instr.src_sprite_idx[0].CLK
clk_in => instr.src_sprite_idx[1].CLK
clk_in => instr.src_sprite_idx[2].CLK
@ -8721,6 +8738,54 @@ clk_in => instr.src_byte[8].CLK
clk_in => instr.src_byte[9].CLK
clk_in => instr.src_byte[10].CLK
clk_in => instr.src_byte[11].CLK
clk_in => instr.alu_i.op[0].CLK
clk_in => instr.alu_i.op[1].CLK
clk_in => instr.alu_i.op[2].CLK
clk_in => instr.alu_i.op[3].CLK
clk_in => instr.alu_i.op[4].CLK
clk_in => instr.alu_i.op[5].CLK
clk_in => instr.alu_i.op[6].CLK
clk_in => instr.alu_i.op[7].CLK
clk_in => instr.alu_i.op[8].CLK
clk_in => instr.alu_i.op[9].CLK
clk_in => instr.alu_i.op[10].CLK
clk_in => instr.alu_i.op[11].CLK
clk_in => instr.alu_i.op[12].CLK
clk_in => instr.alu_i.op[13].CLK
clk_in => instr.alu_i.op[14].CLK
clk_in => instr.alu_i.op[15].CLK
clk_in => instr.alu_i.op[16].CLK
clk_in => instr.alu_i.op[17].CLK
clk_in => instr.alu_i.op[18].CLK
clk_in => instr.alu_i.op[19].CLK
clk_in => instr.alu_i.op[20].CLK
clk_in => instr.alu_i.op[21].CLK
clk_in => instr.alu_i.op[22].CLK
clk_in => instr.alu_i.op[23].CLK
clk_in => instr.alu_i.op[24].CLK
clk_in => instr.alu_i.op[25].CLK
clk_in => instr.alu_i.op[26].CLK
clk_in => instr.alu_i.op[27].CLK
clk_in => instr.alu_i.op[28].CLK
clk_in => instr.alu_i.op[29].CLK
clk_in => instr.alu_i.op[30].CLK
clk_in => instr.alu_i.op[31].CLK
clk_in => instr.alu_i.operand_b[0].CLK
clk_in => instr.alu_i.operand_b[1].CLK
clk_in => instr.alu_i.operand_b[2].CLK
clk_in => instr.alu_i.operand_b[3].CLK
clk_in => instr.alu_i.operand_b[4].CLK
clk_in => instr.alu_i.operand_b[5].CLK
clk_in => instr.alu_i.operand_b[6].CLK
clk_in => instr.alu_i.operand_b[7].CLK
clk_in => instr.alu_i.operand_a[0].CLK
clk_in => instr.alu_i.operand_a[1].CLK
clk_in => instr.alu_i.operand_a[2].CLK
clk_in => instr.alu_i.operand_a[3].CLK
clk_in => instr.alu_i.operand_a[4].CLK
clk_in => instr.alu_i.operand_a[5].CLK
clk_in => instr.alu_i.operand_a[6].CLK
clk_in => instr.alu_i.operand_a[7].CLK
clk_in => instr.dst_reg[0].CLK
clk_in => instr.dst_reg[1].CLK
clk_in => instr.dst_reg[2].CLK
@ -8897,6 +8962,7 @@ clk_in => rd_memory_address[8]~reg0.CLK
clk_in => rd_memory_address[9]~reg0.CLK
clk_in => rd_memory_address[10]~reg0.CLK
clk_in => rd_memory_address[11]~reg0.CLK
fpga_clk => st7920_serial_driver:gpu.sys_clk
rd_memory_data[0] => instr.DATAB
rd_memory_data[0] => src_sprite.DATAB
rd_memory_data[0] => src_sprite.DATAB
@ -8914,7 +8980,7 @@ rd_memory_data[0] => src_sprite.DATAB
rd_memory_data[0] => src_sprite.DATAB
rd_memory_data[0] => src_sprite.DATAB
rd_memory_data[0] => src_sprite.DATAB
rd_memory_data[0] => Selector79.IN4
rd_memory_data[0] => Selector171.IN4
rd_memory_data[0] => opcode[8].DATAIN
rd_memory_data[1] => instr.DATAB
rd_memory_data[1] => src_sprite.DATAB
@ -8933,7 +8999,7 @@ rd_memory_data[1] => src_sprite.DATAB
rd_memory_data[1] => src_sprite.DATAB
rd_memory_data[1] => src_sprite.DATAB
rd_memory_data[1] => src_sprite.DATAB
rd_memory_data[1] => Selector78.IN4
rd_memory_data[1] => Selector170.IN4
rd_memory_data[1] => opcode[9].DATAIN
rd_memory_data[2] => instr.DATAB
rd_memory_data[2] => src_sprite.DATAB
@ -8952,7 +9018,7 @@ rd_memory_data[2] => src_sprite.DATAB
rd_memory_data[2] => src_sprite.DATAB
rd_memory_data[2] => src_sprite.DATAB
rd_memory_data[2] => src_sprite.DATAB
rd_memory_data[2] => Selector77.IN4
rd_memory_data[2] => Selector169.IN4
rd_memory_data[2] => opcode[10].DATAIN
rd_memory_data[3] => instr.DATAB
rd_memory_data[3] => src_sprite.DATAB
@ -8971,7 +9037,7 @@ rd_memory_data[3] => src_sprite.DATAB
rd_memory_data[3] => src_sprite.DATAB
rd_memory_data[3] => src_sprite.DATAB
rd_memory_data[3] => src_sprite.DATAB
rd_memory_data[3] => Selector76.IN4
rd_memory_data[3] => Selector168.IN4
rd_memory_data[3] => opcode[11].DATAIN
rd_memory_data[4] => instr.DATAB
rd_memory_data[4] => src_sprite.DATAB
@ -8990,7 +9056,7 @@ rd_memory_data[4] => src_sprite.DATAB
rd_memory_data[4] => src_sprite.DATAB
rd_memory_data[4] => src_sprite.DATAB
rd_memory_data[4] => src_sprite.DATAB
rd_memory_data[4] => Selector75.IN4
rd_memory_data[4] => Selector167.IN4
rd_memory_data[4] => opcode[12].DATAIN
rd_memory_data[5] => instr.DATAB
rd_memory_data[5] => src_sprite.DATAB
@ -9009,7 +9075,7 @@ rd_memory_data[5] => src_sprite.DATAB
rd_memory_data[5] => src_sprite.DATAB
rd_memory_data[5] => src_sprite.DATAB
rd_memory_data[5] => src_sprite.DATAB
rd_memory_data[5] => Selector74.IN4
rd_memory_data[5] => Selector166.IN4
rd_memory_data[5] => opcode[13].DATAIN
rd_memory_data[6] => instr.DATAB
rd_memory_data[6] => src_sprite.DATAB
@ -9028,7 +9094,7 @@ rd_memory_data[6] => src_sprite.DATAB
rd_memory_data[6] => src_sprite.DATAB
rd_memory_data[6] => src_sprite.DATAB
rd_memory_data[6] => src_sprite.DATAB
rd_memory_data[6] => Selector73.IN4
rd_memory_data[6] => Selector165.IN4
rd_memory_data[6] => opcode[14].DATAIN
rd_memory_data[7] => instr.DATAB
rd_memory_data[7] => src_sprite.DATAB
@ -9047,7 +9113,7 @@ rd_memory_data[7] => src_sprite.DATAB
rd_memory_data[7] => src_sprite.DATAB
rd_memory_data[7] => src_sprite.DATAB
rd_memory_data[7] => src_sprite.DATAB
rd_memory_data[7] => Selector72.IN4
rd_memory_data[7] => Selector164.IN4
rd_memory_data[7] => opcode[15].DATAIN
cycle_counter[0] <= cycle_counter[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cycle_counter[1] <= cycle_counter[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
@ -9116,12 +9182,157 @@ wr_memory_data[7] <= wr_memory_data[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wr_go <= wr_go~reg0.DB_MAX_OUTPUT_PORT_TYPE
lcd_clk <= st7920_serial_driver:gpu.lcd_clk
lcd_data <= st7920_serial_driver:gpu.lcd_data
led[0] <= st7920_serial_driver:gpu.led[0]
led[1] <= st7920_serial_driver:gpu.led[1]
led[2] <= st7920_serial_driver:gpu.led[2]
led[3] <= st7920_serial_driver:gpu.led[3]
led[4] <= st7920_serial_driver:gpu.led[4]
led[5] <= st7920_serial_driver:gpu.led[5]
led[0] <= state[0].DB_MAX_OUTPUT_PORT_TYPE
led[1] <= state[1].DB_MAX_OUTPUT_PORT_TYPE
led[2] <= state[2].DB_MAX_OUTPUT_PORT_TYPE
led[3] <= state[3].DB_MAX_OUTPUT_PORT_TYPE
led[4] <= state[4].DB_MAX_OUTPUT_PORT_TYPE
led[5] <= state[5].DB_MAX_OUTPUT_PORT_TYPE
|chip8|cpu:cpu|alu:alu
rst_in => done.OUTPUTSELECT
rst_in => cnt.OUTPUTSELECT
rst_in => cnt.OUTPUTSELECT
rst_in => cnt.OUTPUTSELECT
rst_in => cnt.OUTPUTSELECT
rst_in => cnt.OUTPUTSELECT
rst_in => cnt.OUTPUTSELECT
rst_in => cnt.OUTPUTSELECT
rst_in => cnt.OUTPUTSELECT
rst_in => cnt.OUTPUTSELECT
rst_in => cnt.OUTPUTSELECT
rst_in => cnt.OUTPUTSELECT
rst_in => cnt.OUTPUTSELECT
rst_in => cnt.OUTPUTSELECT
rst_in => cnt.OUTPUTSELECT
rst_in => cnt.OUTPUTSELECT
rst_in => cnt.OUTPUTSELECT
rst_in => cnt.OUTPUTSELECT
rst_in => cnt.OUTPUTSELECT
rst_in => cnt.OUTPUTSELECT
rst_in => cnt.OUTPUTSELECT
rst_in => cnt.OUTPUTSELECT
rst_in => cnt.OUTPUTSELECT
rst_in => cnt.OUTPUTSELECT
rst_in => cnt.OUTPUTSELECT
rst_in => cnt.OUTPUTSELECT
rst_in => cnt.OUTPUTSELECT
rst_in => cnt.OUTPUTSELECT
rst_in => cnt.OUTPUTSELECT
rst_in => cnt.OUTPUTSELECT
rst_in => cnt.OUTPUTSELECT
rst_in => cnt.OUTPUTSELECT
rst_in => cnt.OUTPUTSELECT
clk_in => cnt[0].CLK
clk_in => cnt[1].CLK
clk_in => cnt[2].CLK
clk_in => cnt[3].CLK
clk_in => cnt[4].CLK
clk_in => cnt[5].CLK
clk_in => cnt[6].CLK
clk_in => cnt[7].CLK
clk_in => cnt[8].CLK
clk_in => cnt[9].CLK
clk_in => cnt[10].CLK
clk_in => cnt[11].CLK
clk_in => cnt[12].CLK
clk_in => cnt[13].CLK
clk_in => cnt[14].CLK
clk_in => cnt[15].CLK
clk_in => cnt[16].CLK
clk_in => cnt[17].CLK
clk_in => cnt[18].CLK
clk_in => cnt[19].CLK
clk_in => cnt[20].CLK
clk_in => cnt[21].CLK
clk_in => cnt[22].CLK
clk_in => cnt[23].CLK
clk_in => cnt[24].CLK
clk_in => cnt[25].CLK
clk_in => cnt[26].CLK
clk_in => cnt[27].CLK
clk_in => cnt[28].CLK
clk_in => cnt[29].CLK
clk_in => cnt[30].CLK
clk_in => cnt[31].CLK
clk_in => result_int[0].CLK
clk_in => result_int[1].CLK
clk_in => result_int[2].CLK
clk_in => result_int[3].CLK
clk_in => result_int[4].CLK
clk_in => result_int[5].CLK
clk_in => result_int[6].CLK
clk_in => result_int[7].CLK
clk_in => result_int[8].CLK
clk_in => result[0]~reg0.CLK
clk_in => result[1]~reg0.CLK
clk_in => result[2]~reg0.CLK
clk_in => result[3]~reg0.CLK
clk_in => result[4]~reg0.CLK
clk_in => result[5]~reg0.CLK
clk_in => result[6]~reg0.CLK
clk_in => result[7]~reg0.CLK
clk_in => overflow~reg0.CLK
clk_in => done~reg0.CLK
in.op[0] => ~NO_FANOUT~
in.op[1] => ~NO_FANOUT~
in.op[2] => ~NO_FANOUT~
in.op[3] => ~NO_FANOUT~
in.op[4] => ~NO_FANOUT~
in.op[5] => ~NO_FANOUT~
in.op[6] => ~NO_FANOUT~
in.op[7] => ~NO_FANOUT~
in.op[8] => ~NO_FANOUT~
in.op[9] => ~NO_FANOUT~
in.op[10] => ~NO_FANOUT~
in.op[11] => ~NO_FANOUT~
in.op[12] => ~NO_FANOUT~
in.op[13] => ~NO_FANOUT~
in.op[14] => ~NO_FANOUT~
in.op[15] => ~NO_FANOUT~
in.op[16] => ~NO_FANOUT~
in.op[17] => ~NO_FANOUT~
in.op[18] => ~NO_FANOUT~
in.op[19] => ~NO_FANOUT~
in.op[20] => ~NO_FANOUT~
in.op[21] => ~NO_FANOUT~
in.op[22] => ~NO_FANOUT~
in.op[23] => ~NO_FANOUT~
in.op[24] => ~NO_FANOUT~
in.op[25] => ~NO_FANOUT~
in.op[26] => ~NO_FANOUT~
in.op[27] => ~NO_FANOUT~
in.op[28] => ~NO_FANOUT~
in.op[29] => ~NO_FANOUT~
in.op[30] => ~NO_FANOUT~
in.op[31] => ~NO_FANOUT~
in.operand_b[0] => Add0.IN16
in.operand_b[1] => Add0.IN15
in.operand_b[2] => Add0.IN14
in.operand_b[3] => Add0.IN13
in.operand_b[4] => Add0.IN12
in.operand_b[5] => Add0.IN11
in.operand_b[6] => Add0.IN10
in.operand_b[7] => Add0.IN9
in.operand_a[0] => Add0.IN8
in.operand_a[1] => Add0.IN7
in.operand_a[2] => Add0.IN6
in.operand_a[3] => Add0.IN5
in.operand_a[4] => Add0.IN4
in.operand_a[5] => Add0.IN3
in.operand_a[6] => Add0.IN2
in.operand_a[7] => Add0.IN1
result[0] <= result[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
result[1] <= result[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
result[2] <= result[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
result[3] <= result[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
result[4] <= result[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
result[5] <= result[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
result[6] <= result[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
result[7] <= result[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
overflow <= overflow~reg0.DB_MAX_OUTPUT_PORT_TYPE
done <= done~reg0.DB_MAX_OUTPUT_PORT_TYPE
|chip8|cpu:cpu|st7920_serial_driver:gpu

BIN
db/chip8.hif
View file

Binary file not shown.

44
db/chip8.lpc.html
View file

@ -50,13 +50,29 @@
<TR >
<TD >cpu|gpu</TD>
<TD >8194</TD>
<TD >1</TD>
<TD >7</TD>
<TD >0</TD>
<TD >1</TD>
<TD >7</TD>
<TD >8</TD>
<TD >1</TD>
<TD >1</TD>
<TD >1</TD>
<TD >7</TD>
<TD >7</TD>
<TD >7</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >cpu|alu</TD>
<TD >50</TD>
<TD >0</TD>
<TD >32</TD>
<TD >0</TD>
<TD >10</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
@ -65,7 +81,7 @@
</TR>
<TR >
<TD >cpu</TD>
<TD >9</TD>
<TD >10</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
@ -95,4 +111,20 @@
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >dc</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
</TABLE>

BIN
db/chip8.lpc.rdb
View file

Binary file not shown.

6
db/chip8.lpc.txt
View file

@ -5,7 +5,9 @@
+-------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; cpu|gpu|dff ; 2 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; cpu|gpu|com ; 12 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; cpu|gpu ; 8194 ; 1 ; 0 ; 1 ; 8 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; cpu ; 9 ; 0 ; 0 ; 0 ; 73 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; cpu|gpu ; 8194 ; 7 ; 0 ; 7 ; 8 ; 7 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; cpu|alu ; 50 ; 0 ; 32 ; 0 ; 10 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; cpu ; 10 ; 0 ; 0 ; 0 ; 73 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; mem ; 34 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; dc ; 1 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+-------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

BIN
db/chip8.map.bpm
View file

Binary file not shown.

BIN
db/chip8.map.cdb
View file

Binary file not shown.

BIN
db/chip8.map.hdb
View file

Binary file not shown.

BIN
db/chip8.map.kpt
View file

Binary file not shown.

101
db/chip8.map.qmsg
View file

@ -1,46 +1,55 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1712551491860 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition " "Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1712551491860 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 7 23:44:51 2024 " "Processing started: Sun Apr 7 23:44:51 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1712551491860 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712551491860 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off chip8 -c chip8 " "Command: quartus_map --read_settings_files=on --write_settings_files=off chip8 -c chip8" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712551491860 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1712551492019 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "12 12 " "Parallel compilation is enabled and will use 12 of the 12 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1712551492019 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "the-bomb/st7920_serial_driver.sv 3 3 " "Found 3 design units, including 3 entities, in source file the-bomb/st7920_serial_driver.sv" { { "Info" "ISGN_ENTITY_NAME" "1 st7920_serial_driver " "Found entity 1: st7920_serial_driver" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712551496896 ""} { "Info" "ISGN_ENTITY_NAME" "2 d_flip_flop " "Found entity 2: d_flip_flop" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 137 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712551496896 ""} { "Info" "ISGN_ENTITY_NAME" "3 commander " "Found entity 3: commander" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 147 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712551496896 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712551496896 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "chip8.sv 1 1 " "Found 1 design units, including 1 entities, in source file chip8.sv" { { "Info" "ISGN_ENTITY_NAME" "1 chip8 " "Found entity 1: chip8" { } { { "chip8.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/chip8.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712551496897 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712551496897 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu.sv 1 1 " "Found 1 design units, including 1 entities, in source file cpu.sv" { { "Info" "ISGN_ENTITY_NAME" "1 cpu " "Found entity 1: cpu" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712551496898 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712551496898 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "chip8 " "Elaborating entity \"chip8\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1712551496936 ""}
{ "Warning" "WSGN_SEARCH_FILE" "memory.sv 1 1 " "Using design file memory.sv, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 memory " "Found entity 1: memory" { } { { "memory.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/memory.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712551496940 ""} } { } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1712551496940 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "memory memory:mem " "Elaborating entity \"memory\" for hierarchy \"memory:mem\"" { } { { "chip8.sv" "mem" { Text "/home/nickorlow/programming/school/warminster/yayacemu/chip8.sv" 21 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712551496940 ""}
{ "Warning" "WVRFX_VERI_2111_UNCONVERTED" "80 0 4095 memory.sv(14) " "Verilog HDL warning at memory.sv(14): number of words (80) in memory file does not match the number of elements in the address range \[0:4095\]" { } { { "memory.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/memory.sv" 14 0 0 } } } 0 10850 "Verilog HDL warning at %4!s!: number of words (%1!d!) in memory file does not match the number of elements in the address range \[%2!d!:%3!d!\]" 0 0 "Analysis & Synthesis" 0 -1 1712551496941 "|chip8|memory:mem"}
{ "Warning" "WVRFX_VERI_2111_UNCONVERTED" "260 512 4095 memory.sv(15) " "Verilog HDL warning at memory.sv(15): number of words (260) in memory file does not match the number of elements in the address range \[512:4095\]" { } { { "memory.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/memory.sv" 15 0 0 } } } 0 10850 "Verilog HDL warning at %4!s!: number of words (%1!d!) in memory file does not match the number of elements in the address range \[%2!d!:%3!d!\]" 0 0 "Analysis & Synthesis" 0 -1 1712551496941 "|chip8|memory:mem"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu cpu:cpu " "Elaborating entity \"cpu\" for hierarchy \"cpu:cpu\"" { } { { "chip8.sv" "cpu" { Text "/home/nickorlow/programming/school/warminster/yayacemu/chip8.sv" 35 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712551496941 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(124) " "Verilog HDL assignment warning at cpu.sv(124): truncated value with size 32 to match size of target (16)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 124 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712551497024 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(130) " "Verilog HDL assignment warning at cpu.sv(130): truncated value with size 32 to match size of target (16)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 130 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712551497024 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(147) " "Verilog HDL assignment warning at cpu.sv(147): truncated value with size 32 to match size of target (16)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 147 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712551497024 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 cpu.sv(210) " "Verilog HDL assignment warning at cpu.sv(210): truncated value with size 32 to match size of target (5)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 210 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712551497024 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 cpu.sv(213) " "Verilog HDL assignment warning at cpu.sv(213): truncated value with size 32 to match size of target (5)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 213 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712551497024 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(242) " "Verilog HDL assignment warning at cpu.sv(242): truncated value with size 32 to match size of target (16)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 242 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712551497024 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 cpu.sv(246) " "Verilog HDL assignment warning at cpu.sv(246): truncated value with size 32 to match size of target (5)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 246 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712551497024 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 cpu.sv(257) " "Verilog HDL assignment warning at cpu.sv(257): truncated value with size 32 to match size of target (5)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 257 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712551497024 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(284) " "Verilog HDL assignment warning at cpu.sv(284): truncated value with size 32 to match size of target (16)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 284 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712551497024 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "instr.src_reg 0 cpu.sv(108) " "Net \"instr.src_reg\" at cpu.sv(108) has no driver or initial value, using a default initial value '0'" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 108 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1712551497024 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "instr.src_addr 0 cpu.sv(108) " "Net \"instr.src_addr\" at cpu.sv(108) has no driver or initial value, using a default initial value '0'" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 108 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1712551497024 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "instr.dst_addr 0 cpu.sv(108) " "Net \"instr.dst_addr\" at cpu.sv(108) has no driver or initial value, using a default initial value '0'" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 108 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1712551497024 "|chip8|cpu:cpu"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "st7920_serial_driver cpu:cpu\|st7920_serial_driver:gpu " "Elaborating entity \"st7920_serial_driver\" for hierarchy \"cpu:cpu\|st7920_serial_driver:gpu\"" { } { { "cpu.sv" "gpu" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 28 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712551497028 ""}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "line_idx st7920_serial_driver.sv(23) " "Verilog HDL or VHDL warning at st7920_serial_driver.sv(23): object \"line_idx\" assigned a value but never read" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 23 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1712551497040 "|chip8|cpu:cpu|st7920_serial_driver:gpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 st7920_serial_driver.sv(71) " "Verilog HDL assignment warning at st7920_serial_driver.sv(71): truncated value with size 32 to match size of target (7)" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 71 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712551497040 "|chip8|cpu:cpu|st7920_serial_driver:gpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 st7920_serial_driver.sv(84) " "Verilog HDL assignment warning at st7920_serial_driver.sv(84): truncated value with size 32 to match size of target (7)" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 84 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712551497040 "|chip8|cpu:cpu|st7920_serial_driver:gpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 st7920_serial_driver.sv(103) " "Verilog HDL assignment warning at st7920_serial_driver.sv(103): truncated value with size 32 to match size of target (6)" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 103 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712551497040 "|chip8|cpu:cpu|st7920_serial_driver:gpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 9 st7920_serial_driver.sv(131) " "Verilog HDL assignment warning at st7920_serial_driver.sv(131): truncated value with size 32 to match size of target (9)" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 131 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712551497040 "|chip8|cpu:cpu|st7920_serial_driver:gpu"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "commands\[6..10\] 0 st7920_serial_driver.sv(26) " "Net \"commands\[6..10\]\" at st7920_serial_driver.sv(26) has no driver or initial value, using a default initial value '0'" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 26 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1712551497040 "|chip8|cpu:cpu|st7920_serial_driver:gpu"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "commander cpu:cpu\|st7920_serial_driver:gpu\|commander:com " "Elaborating entity \"commander\" for hierarchy \"cpu:cpu\|st7920_serial_driver:gpu\|commander:com\"" { } { { "the-bomb/st7920_serial_driver.sv" "com" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 42 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712551497041 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "d_flip_flop cpu:cpu\|st7920_serial_driver:gpu\|d_flip_flop:dff " "Elaborating entity \"d_flip_flop\" for hierarchy \"cpu:cpu\|st7920_serial_driver:gpu\|d_flip_flop:dff\"" { } { { "the-bomb/st7920_serial_driver.sv" "dff" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 50 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712551497041 ""}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "IINFER_ALTSYNCRAM_INFERRED" "memory:mem\|mem_rtl_0 " "Inferred altsyncram megafunction from the following design logic: \"memory:mem\|mem_rtl_0\" " { { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OPERATION_MODE DUAL_PORT " "Parameter OPERATION_MODE set to DUAL_PORT" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712551516726 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_A 8 " "Parameter WIDTH_A set to 8" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712551516726 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_A 12 " "Parameter WIDTHAD_A set to 12" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712551516726 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_A 4096 " "Parameter NUMWORDS_A set to 4096" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712551516726 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_B 8 " "Parameter WIDTH_B set to 8" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712551516726 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_B 12 " "Parameter WIDTHAD_B set to 12" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712551516726 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_B 4096 " "Parameter NUMWORDS_B set to 4096" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712551516726 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_A NONE " "Parameter ADDRESS_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712551516726 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_REG_B UNREGISTERED " "Parameter OUTDATA_REG_B set to UNREGISTERED" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712551516726 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_B NONE " "Parameter ADDRESS_ACLR_B set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712551516726 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_ACLR_B NONE " "Parameter OUTDATA_ACLR_B set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712551516726 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_REG_B CLOCK0 " "Parameter ADDRESS_REG_B set to CLOCK0" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712551516726 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "INDATA_ACLR_A NONE " "Parameter INDATA_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712551516726 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WRCONTROL_ACLR_A NONE " "Parameter WRCONTROL_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712551516726 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "INIT_FILE db/chip8.ram0_memory_e9e85012.hdl.mif " "Parameter INIT_FILE set to db/chip8.ram0_memory_e9e85012.hdl.mif" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712551516726 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "READ_DURING_WRITE_MODE_MIXED_PORTS OLD_DATA " "Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712551516726 ""} } { } 0 276029 "Inferred altsyncram megafunction from the following design logic: \"%1!s!\" " 0 0 "Design Software" 0 -1 1712551516726 ""} } { } 0 19000 "Inferred %1!d! megafunctions from design logic" 0 0 "Analysis & Synthesis" 0 -1 1712551516726 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "memory:mem\|altsyncram:mem_rtl_0 " "Elaborated megafunction instantiation \"memory:mem\|altsyncram:mem_rtl_0\"" { } { } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712551516773 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "memory:mem\|altsyncram:mem_rtl_0 " "Instantiated megafunction \"memory:mem\|altsyncram:mem_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "OPERATION_MODE DUAL_PORT " "Parameter \"OPERATION_MODE\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712551516773 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_A 8 " "Parameter \"WIDTH_A\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712551516773 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_A 12 " "Parameter \"WIDTHAD_A\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712551516773 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_A 4096 " "Parameter \"NUMWORDS_A\" = \"4096\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712551516773 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_B 8 " "Parameter \"WIDTH_B\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712551516773 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_B 12 " "Parameter \"WIDTHAD_B\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712551516773 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_B 4096 " "Parameter \"NUMWORDS_B\" = \"4096\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712551516773 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_A NONE " "Parameter \"ADDRESS_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712551516773 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_REG_B UNREGISTERED " "Parameter \"OUTDATA_REG_B\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712551516773 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_B NONE " "Parameter \"ADDRESS_ACLR_B\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712551516773 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_ACLR_B NONE " "Parameter \"OUTDATA_ACLR_B\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712551516773 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_REG_B CLOCK0 " "Parameter \"ADDRESS_REG_B\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712551516773 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INDATA_ACLR_A NONE " "Parameter \"INDATA_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712551516773 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WRCONTROL_ACLR_A NONE " "Parameter \"WRCONTROL_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712551516773 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INIT_FILE db/chip8.ram0_memory_e9e85012.hdl.mif " "Parameter \"INIT_FILE\" = \"db/chip8.ram0_memory_e9e85012.hdl.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712551516773 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "READ_DURING_WRITE_MODE_MIXED_PORTS OLD_DATA " "Parameter \"READ_DURING_WRITE_MODE_MIXED_PORTS\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712551516773 ""} } { } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1712551516773 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_dsq1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_dsq1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_dsq1 " "Found entity 1: altsyncram_dsq1" { } { { "db/altsyncram_dsq1.tdf" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/db/altsyncram_dsq1.tdf" 28 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712551516796 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712551516796 ""}
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "led\[5\] VCC " "Pin \"led\[5\]\" is stuck at VCC" { } { { "chip8.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/chip8.sv" 7 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1712551532666 "|chip8|led[5]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1712551532666 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1712551533595 ""}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "4 " "4 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1712551551646 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1712551552875 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712551552875 ""}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "1 " "Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "rst_in " "No output dependent on input pin \"rst_in\"" { } { { "chip8.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/chip8.sv" 3 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1712551553790 "|chip8|rst_in"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1712551553790 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "17374 " "Implemented 17374 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Implemented 2 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1712551553847 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1712551553847 ""} { "Info" "ICUT_CUT_TM_LCELLS" "17356 " "Implemented 17356 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1712551553847 ""} { "Info" "ICUT_CUT_TM_RAMS" "8 " "Implemented 8 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Design Software" 0 -1 1712551553847 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1712551553847 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 26 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 26 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "698 " "Peak virtual memory: 698 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1712551553879 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 7 23:45:53 2024 " "Processing ended: Sun Apr 7 23:45:53 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1712551553879 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:01:02 " "Elapsed time: 00:01:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1712551553879 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:01:46 " "Total CPU time (on all processors): 00:01:46" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1712551553879 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1712551553879 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1712584011618 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition " "Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1712584011618 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Apr 8 08:46:51 2024 " "Processing started: Mon Apr 8 08:46:51 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1712584011618 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712584011618 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off chip8 -c chip8 " "Command: quartus_map --read_settings_files=on --write_settings_files=off chip8 -c chip8" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712584011618 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1712584011793 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "12 12 " "Parallel compilation is enabled and will use 12 of the 12 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1712584011793 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "the-bomb/st7920_serial_driver.sv 3 3 " "Found 3 design units, including 3 entities, in source file the-bomb/st7920_serial_driver.sv" { { "Info" "ISGN_ENTITY_NAME" "1 st7920_serial_driver " "Found entity 1: st7920_serial_driver" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712584016098 ""} { "Info" "ISGN_ENTITY_NAME" "2 d_flip_flop " "Found entity 2: d_flip_flop" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 137 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712584016098 ""} { "Info" "ISGN_ENTITY_NAME" "3 commander " "Found entity 3: commander" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 147 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712584016098 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712584016098 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "chip8.sv 1 1 " "Found 1 design units, including 1 entities, in source file chip8.sv" { { "Info" "ISGN_ENTITY_NAME" "1 chip8 " "Found entity 1: chip8" { } { { "chip8.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/chip8.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712584016099 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712584016099 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "alu ALU cpu.sv(33) " "Verilog HDL Declaration information at cpu.sv(33): object \"alu\" differs only in case from object \"ALU\" in the same scope" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 33 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1712584016100 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu.sv 1 1 " "Found 1 design units, including 1 entities, in source file cpu.sv" { { "Info" "ISGN_ENTITY_NAME" "1 cpu " "Found entity 1: cpu" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712584016100 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712584016100 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "alu.sv 1 1 " "Found 1 design units, including 1 entities, in source file alu.sv" { { "Info" "ISGN_ENTITY_NAME" "1 alu " "Found entity 1: alu" { } { { "alu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/alu.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712584016100 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712584016100 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "aastructs.sv 1 0 " "Found 1 design units, including 0 entities, in source file aastructs.sv" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 structs (SystemVerilog) " "Found design unit 1: structs (SystemVerilog)" { } { { "aastructs.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/aastructs.sv" 1 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712584016101 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712584016101 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "downclocker.sv 1 1 " "Found 1 design units, including 1 entities, in source file downclocker.sv" { { "Info" "ISGN_ENTITY_NAME" "1 downclocker " "Found entity 1: downclocker" { } { { "downclocker.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/downclocker.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712584016101 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712584016101 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "chip8 " "Elaborating entity \"chip8\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1712584016136 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "downclocker downclocker:dc " "Elaborating entity \"downclocker\" for hierarchy \"downclocker:dc\"" { } { { "chip8.sv" "dc" { Text "/home/nickorlow/programming/school/warminster/yayacemu/chip8.sv" 14 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712584016138 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 downclocker.sv(18) " "Verilog HDL assignment warning at downclocker.sv(18): truncated value with size 32 to match size of target (10)" { } { { "downclocker.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/downclocker.sv" 18 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712584016138 "|chip8|downclocker:dc"}
{ "Warning" "WSGN_SEARCH_FILE" "memory.sv 1 1 " "Using design file memory.sv, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 memory " "Found entity 1: memory" { } { { "memory.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/memory.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712584016142 ""} } { } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1712584016142 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "memory memory:mem " "Elaborating entity \"memory\" for hierarchy \"memory:mem\"" { } { { "chip8.sv" "mem" { Text "/home/nickorlow/programming/school/warminster/yayacemu/chip8.sv" 29 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712584016143 ""}
{ "Warning" "WVRFX_VERI_2111_UNCONVERTED" "80 0 4095 memory.sv(14) " "Verilog HDL warning at memory.sv(14): number of words (80) in memory file does not match the number of elements in the address range \[0:4095\]" { } { { "memory.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/memory.sv" 14 0 0 } } } 0 10850 "Verilog HDL warning at %4!s!: number of words (%1!d!) in memory file does not match the number of elements in the address range \[%2!d!:%3!d!\]" 0 0 "Analysis & Synthesis" 0 -1 1712584016143 "|chip8|memory:mem"}
{ "Warning" "WVRFX_VERI_2111_UNCONVERTED" "132 512 4095 memory.sv(15) " "Verilog HDL warning at memory.sv(15): number of words (132) in memory file does not match the number of elements in the address range \[512:4095\]" { } { { "memory.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/memory.sv" 15 0 0 } } } 0 10850 "Verilog HDL warning at %4!s!: number of words (%1!d!) in memory file does not match the number of elements in the address range \[%2!d!:%3!d!\]" 0 0 "Analysis & Synthesis" 0 -1 1712584016143 "|chip8|memory:mem"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu cpu:cpu " "Elaborating entity \"cpu\" for hierarchy \"cpu:cpu\"" { } { { "chip8.sv" "cpu" { Text "/home/nickorlow/programming/school/warminster/yayacemu/chip8.sv" 44 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712584016144 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(148) " "Verilog HDL assignment warning at cpu.sv(148): truncated value with size 32 to match size of target (16)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 148 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712584016275 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(154) " "Verilog HDL assignment warning at cpu.sv(154): truncated value with size 32 to match size of target (16)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 154 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712584016275 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(171) " "Verilog HDL assignment warning at cpu.sv(171): truncated value with size 32 to match size of target (16)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 171 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712584016275 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 cpu.sv(249) " "Verilog HDL assignment warning at cpu.sv(249): truncated value with size 32 to match size of target (5)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 249 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712584016277 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 cpu.sv(252) " "Verilog HDL assignment warning at cpu.sv(252): truncated value with size 32 to match size of target (5)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 252 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712584016277 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(281) " "Verilog HDL assignment warning at cpu.sv(281): truncated value with size 32 to match size of target (16)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 281 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712584016282 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 cpu.sv(285) " "Verilog HDL assignment warning at cpu.sv(285): truncated value with size 32 to match size of target (5)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 285 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712584016282 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 cpu.sv(296) " "Verilog HDL assignment warning at cpu.sv(296): truncated value with size 32 to match size of target (5)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 296 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712584016642 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(323) " "Verilog HDL assignment warning at cpu.sv(323): truncated value with size 32 to match size of target (16)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 323 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712584016663 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(333) " "Verilog HDL assignment warning at cpu.sv(333): truncated value with size 32 to match size of target (16)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 333 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712584016664 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "instr.src_reg 0 cpu.sv(131) " "Net \"instr.src_reg\" at cpu.sv(131) has no driver or initial value, using a default initial value '0'" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 131 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1712584017054 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "instr.src_addr 0 cpu.sv(131) " "Net \"instr.src_addr\" at cpu.sv(131) has no driver or initial value, using a default initial value '0'" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 131 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1712584017054 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "instr.dst_addr 0 cpu.sv(131) " "Net \"instr.dst_addr\" at cpu.sv(131) has no driver or initial value, using a default initial value '0'" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 131 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1712584017054 "|chip8|cpu:cpu"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu cpu:cpu\|alu:alu " "Elaborating entity \"alu\" for hierarchy \"cpu:cpu\|alu:alu\"" { } { { "cpu.sv" "alu" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 33 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712584019602 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "st7920_serial_driver cpu:cpu\|st7920_serial_driver:gpu " "Elaborating entity \"st7920_serial_driver\" for hierarchy \"cpu:cpu\|st7920_serial_driver:gpu\"" { } { { "cpu.sv" "gpu" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 49 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712584019606 ""}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "line_idx st7920_serial_driver.sv(23) " "Verilog HDL or VHDL warning at st7920_serial_driver.sv(23): object \"line_idx\" assigned a value but never read" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 23 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1712584019620 "|chip8|cpu:cpu|st7920_serial_driver:gpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 st7920_serial_driver.sv(71) " "Verilog HDL assignment warning at st7920_serial_driver.sv(71): truncated value with size 32 to match size of target (7)" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 71 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712584019620 "|chip8|cpu:cpu|st7920_serial_driver:gpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 st7920_serial_driver.sv(84) " "Verilog HDL assignment warning at st7920_serial_driver.sv(84): truncated value with size 32 to match size of target (7)" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 84 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712584019620 "|chip8|cpu:cpu|st7920_serial_driver:gpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 st7920_serial_driver.sv(103) " "Verilog HDL assignment warning at st7920_serial_driver.sv(103): truncated value with size 32 to match size of target (6)" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 103 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712584019620 "|chip8|cpu:cpu|st7920_serial_driver:gpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 9 st7920_serial_driver.sv(131) " "Verilog HDL assignment warning at st7920_serial_driver.sv(131): truncated value with size 32 to match size of target (9)" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 131 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712584019620 "|chip8|cpu:cpu|st7920_serial_driver:gpu"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "commands\[6..10\] 0 st7920_serial_driver.sv(26) " "Net \"commands\[6..10\]\" at st7920_serial_driver.sv(26) has no driver or initial value, using a default initial value '0'" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 26 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1712584019620 "|chip8|cpu:cpu|st7920_serial_driver:gpu"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "commander cpu:cpu\|st7920_serial_driver:gpu\|commander:com " "Elaborating entity \"commander\" for hierarchy \"cpu:cpu\|st7920_serial_driver:gpu\|commander:com\"" { } { { "the-bomb/st7920_serial_driver.sv" "com" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 42 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712584019621 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "d_flip_flop cpu:cpu\|st7920_serial_driver:gpu\|d_flip_flop:dff " "Elaborating entity \"d_flip_flop\" for hierarchy \"cpu:cpu\|st7920_serial_driver:gpu\|d_flip_flop:dff\"" { } { { "the-bomb/st7920_serial_driver.sv" "dff" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 50 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712584019622 ""}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "IINFER_ALTSYNCRAM_INFERRED" "memory:mem\|mem_rtl_0 " "Inferred altsyncram megafunction from the following design logic: \"memory:mem\|mem_rtl_0\" " { { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OPERATION_MODE DUAL_PORT " "Parameter OPERATION_MODE set to DUAL_PORT" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712584036621 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_A 8 " "Parameter WIDTH_A set to 8" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712584036621 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_A 12 " "Parameter WIDTHAD_A set to 12" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712584036621 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_A 4096 " "Parameter NUMWORDS_A set to 4096" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712584036621 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_B 8 " "Parameter WIDTH_B set to 8" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712584036621 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_B 12 " "Parameter WIDTHAD_B set to 12" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712584036621 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_B 4096 " "Parameter NUMWORDS_B set to 4096" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712584036621 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_A NONE " "Parameter ADDRESS_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712584036621 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_REG_B UNREGISTERED " "Parameter OUTDATA_REG_B set to UNREGISTERED" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712584036621 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_B NONE " "Parameter ADDRESS_ACLR_B set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712584036621 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_ACLR_B NONE " "Parameter OUTDATA_ACLR_B set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712584036621 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_REG_B CLOCK0 " "Parameter ADDRESS_REG_B set to CLOCK0" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712584036621 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "INDATA_ACLR_A NONE " "Parameter INDATA_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712584036621 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WRCONTROL_ACLR_A NONE " "Parameter WRCONTROL_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712584036621 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "INIT_FILE db/chip8.ram0_memory_e9e85012.hdl.mif " "Parameter INIT_FILE set to db/chip8.ram0_memory_e9e85012.hdl.mif" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712584036621 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "READ_DURING_WRITE_MODE_MIXED_PORTS OLD_DATA " "Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712584036621 ""} } { } 0 276029 "Inferred altsyncram megafunction from the following design logic: \"%1!s!\" " 0 0 "Design Software" 0 -1 1712584036621 ""} } { } 0 19000 "Inferred %1!d! megafunctions from design logic" 0 0 "Analysis & Synthesis" 0 -1 1712584036621 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "memory:mem\|altsyncram:mem_rtl_0 " "Elaborated megafunction instantiation \"memory:mem\|altsyncram:mem_rtl_0\"" { } { } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712584036659 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "memory:mem\|altsyncram:mem_rtl_0 " "Instantiated megafunction \"memory:mem\|altsyncram:mem_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "OPERATION_MODE DUAL_PORT " "Parameter \"OPERATION_MODE\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712584036659 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_A 8 " "Parameter \"WIDTH_A\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712584036659 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_A 12 " "Parameter \"WIDTHAD_A\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712584036659 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_A 4096 " "Parameter \"NUMWORDS_A\" = \"4096\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712584036659 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_B 8 " "Parameter \"WIDTH_B\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712584036659 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_B 12 " "Parameter \"WIDTHAD_B\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712584036659 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_B 4096 " "Parameter \"NUMWORDS_B\" = \"4096\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712584036659 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_A NONE " "Parameter \"ADDRESS_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712584036659 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_REG_B UNREGISTERED " "Parameter \"OUTDATA_REG_B\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712584036659 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_B NONE " "Parameter \"ADDRESS_ACLR_B\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712584036659 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_ACLR_B NONE " "Parameter \"OUTDATA_ACLR_B\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712584036659 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_REG_B CLOCK0 " "Parameter \"ADDRESS_REG_B\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712584036659 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INDATA_ACLR_A NONE " "Parameter \"INDATA_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712584036659 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WRCONTROL_ACLR_A NONE " "Parameter \"WRCONTROL_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712584036659 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INIT_FILE db/chip8.ram0_memory_e9e85012.hdl.mif " "Parameter \"INIT_FILE\" = \"db/chip8.ram0_memory_e9e85012.hdl.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712584036659 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "READ_DURING_WRITE_MODE_MIXED_PORTS OLD_DATA " "Parameter \"READ_DURING_WRITE_MODE_MIXED_PORTS\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712584036659 ""} } { } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1712584036659 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_dsq1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_dsq1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_dsq1 " "Found entity 1: altsyncram_dsq1" { } { { "db/altsyncram_dsq1.tdf" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/db/altsyncram_dsq1.tdf" 28 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712584036680 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712584036680 ""}
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "led\[4\] GND " "Pin \"led\[4\]\" is stuck at GND" { } { { "chip8.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/chip8.sv" 7 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1712584046983 "|chip8|led[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "led\[5\] GND " "Pin \"led\[5\]\" is stuck at GND" { } { { "chip8.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/chip8.sv" 7 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1712584046983 "|chip8|led[5]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1712584046983 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1712584047706 ""}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "6 " "6 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1712584065406 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/nickorlow/programming/school/warminster/yayacemu/output_files/chip8.map.smsg " "Generated suppressed messages file /home/nickorlow/programming/school/warminster/yayacemu/output_files/chip8.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712584065742 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1712584066477 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712584066477 ""}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "1 " "Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "rst_in " "No output dependent on input pin \"rst_in\"" { } { { "chip8.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/chip8.sv" 3 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1712584067334 "|chip8|rst_in"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1712584067334 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "17552 " "Implemented 17552 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Implemented 2 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1712584067389 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1712584067389 ""} { "Info" "ICUT_CUT_TM_LCELLS" "17534 " "Implemented 17534 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1712584067389 ""} { "Info" "ICUT_CUT_TM_RAMS" "8 " "Implemented 8 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Design Software" 0 -1 1712584067389 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1712584067389 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 29 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 29 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "775 " "Peak virtual memory: 775 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1712584067421 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 8 08:47:47 2024 " "Processing ended: Mon Apr 8 08:47:47 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1712584067421 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:56 " "Elapsed time: 00:00:56" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1712584067421 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:01:34 " "Total CPU time (on all processors): 00:01:34" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1712584067421 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1712584067421 ""}

BIN
db/chip8.map.rdb
View file

Binary file not shown.

BIN
db/chip8.map_bb.cdb
View file

Binary file not shown.

BIN
db/chip8.map_bb.hdb
View file

Binary file not shown.

BIN
db/chip8.pre_map.hdb
View file

Binary file not shown.

482
db/chip8.ram0_memory_e9e85012.hdl.mif
View file

@ -3333,264 +3333,264 @@ CONTENT BEGIN
774 : XXXXXXXX;
773 : XXXXXXXX;
772 : XXXXXXXX;
771 : 01110000;
770 : 10000000;
769 : 11110000;
768 : 10010000;
767 : 01100000;
766 : 00000000;
765 : 00000000;
764 : 11111100;
763 : 11111110;
762 : 10000111;
761 : 00000011;
760 : 00000011;
759 : 00000011;
758 : 10000111;
757 : 11001110;
756 : 10100110;
755 : 10101000;
754 : 10101000;
753 : 10001110;
752 : 00101000;
751 : 00000000;
750 : 00000000;
749 : 01110001;
748 : 00100011;
747 : 01100111;
746 : 00100111;
745 : 00000111;
744 : 00000111;
743 : 00000011;
742 : 11110001;
741 : 01100011;
740 : 00010100;
739 : 00100100;
738 : 01000100;
737 : 00110000;
736 : 00000000;
735 : 00000000;
734 : 11000101;
733 : 11000100;
732 : 11011100;
731 : 11010100;
730 : 11000000;
729 : 11111000;
728 : 11111100;
727 : 11001110;
726 : 00011000;
725 : 10100000;
724 : 00100000;
723 : 00111000;
722 : 10100000;
721 : 00000000;
720 : 00000000;
719 : 11011101;
718 : 11011101;
717 : 11011101;
716 : 11011101;
715 : 11011101;
714 : 11011101;
713 : 11011101;
712 : 11011101;
711 : 00111011;
710 : 01000000;
709 : 01111001;
708 : 01001010;
707 : 00110001;
706 : 00000000;
705 : 00000000;
704 : 00111000;
703 : 10111000;
702 : 10111000;
701 : 00111000;
700 : 00111000;
699 : 00111000;
698 : 00111000;
697 : 00111001;
696 : 00000010;
695 : 00000010;
694 : 00000010;
693 : 00000010;
692 : 00000111;
691 : 00000000;
690 : 00000000;
689 : 00011111;
688 : 00111111;
687 : 01110001;
686 : 11100000;
685 : 11100000;
684 : 11100000;
683 : 11100000;
682 : 11100111;
681 : 11111100;
680 : 11000110;
679 : 10000011;
678 : 10000011;
677 : 10000011;
676 : 11000111;
675 : 11111110;
674 : 00000000;
673 : 00000000;
672 : 00000000;
671 : 10000000;
670 : 00000000;
669 : 00000000;
668 : 10010000;
667 : 00110000;
666 : 11110000;
665 : 00000001;
664 : 00000011;
663 : 00000011;
662 : 00000011;
661 : 00000001;
660 : 00000000;
659 : 00000000;
658 : 00000000;
657 : 00111011;
656 : 01001000;
655 : 01001001;
654 : 01001010;
653 : 01001001;
652 : 00000000;
651 : 11000110;
650 : 11000110;
649 : 11000110;
648 : 11000110;
647 : 11001110;
646 : 11111100;
645 : 11111000;
644 : 00000000;
643 : 00000000;
642 : 00100111;
641 : 00101001;
640 : 00101001;
639 : 00101001;
638 : 11000111;
637 : 00000001;
636 : 10011101;
635 : 00011101;
634 : 00001101;
633 : 00000001;
632 : 00011101;
631 : 00011101;
630 : 00001100;
629 : 00000000;
628 : 00000000;
627 : 10011101;
626 : 10100001;
625 : 10111101;
624 : 10100101;
623 : 00011001;
622 : 00000000;
621 : 10111111;
620 : 00111111;
619 : 00111000;
618 : 00111000;
617 : 10111000;
616 : 10111000;
615 : 00011000;
614 : 00000000;
613 : 00000000;
612 : 00101000;
611 : 00101000;
610 : 00101000;
609 : 00101010;
608 : 00001101;
607 : 10100000;
606 : 11101000;
605 : 11100000;
604 : 11100101;
603 : 11100000;
602 : 01110001;
601 : 00111111;
600 : 00011111;
599 : 00000000;
598 : 00000000;
597 : 00000010;
596 : 00000010;
595 : 00000010;
594 : 00000010;
593 : 00000010;
592 : 00001111;
591 : 01001110;
590 : 00010010;
589 : 00011111;
588 : 11010000;
587 : 11110101;
586 : 10100010;
585 : 00110000;
584 : 01100000;
583 : 00011111;
582 : 11010000;
581 : 11100110;
580 : 10100010;
579 : 00101000;
578 : 01100000;
577 : 00011111;
576 : 11010000;
575 : 11010111;
574 : 10100010;
573 : 00100000;
572 : 01100000;
571 : 00011111;
570 : 11010000;
569 : 11001000;
568 : 10100010;
567 : 00011000;
566 : 01100000;
565 : 00011111;
564 : 11010000;
563 : 10111001;
562 : 10100010;
561 : 00010000;
560 : 01100000;
559 : 00011111;
558 : 11010000;
557 : 10101010;
556 : 10100010;
555 : 00001000;
554 : 01100000;
553 : 00010000;
552 : 01100001;
771 : XXXXXXXX;
770 : XXXXXXXX;
769 : XXXXXXXX;
768 : XXXXXXXX;
767 : XXXXXXXX;
766 : XXXXXXXX;
765 : XXXXXXXX;
764 : XXXXXXXX;
763 : XXXXXXXX;
762 : XXXXXXXX;
761 : XXXXXXXX;
760 : XXXXXXXX;
759 : XXXXXXXX;
758 : XXXXXXXX;
757 : XXXXXXXX;
756 : XXXXXXXX;
755 : XXXXXXXX;
754 : XXXXXXXX;
753 : XXXXXXXX;
752 : XXXXXXXX;
751 : XXXXXXXX;
750 : XXXXXXXX;
749 : XXXXXXXX;
748 : XXXXXXXX;
747 : XXXXXXXX;
746 : XXXXXXXX;
745 : XXXXXXXX;
744 : XXXXXXXX;
743 : XXXXXXXX;
742 : XXXXXXXX;
741 : XXXXXXXX;
740 : XXXXXXXX;
739 : XXXXXXXX;
738 : XXXXXXXX;
737 : XXXXXXXX;
736 : XXXXXXXX;
735 : XXXXXXXX;
734 : XXXXXXXX;
733 : XXXXXXXX;
732 : XXXXXXXX;
731 : XXXXXXXX;
730 : XXXXXXXX;
729 : XXXXXXXX;
728 : XXXXXXXX;
727 : XXXXXXXX;
726 : XXXXXXXX;
725 : XXXXXXXX;
724 : XXXXXXXX;
723 : XXXXXXXX;
722 : XXXXXXXX;
721 : XXXXXXXX;
720 : XXXXXXXX;
719 : XXXXXXXX;
718 : XXXXXXXX;
717 : XXXXXXXX;
716 : XXXXXXXX;
715 : XXXXXXXX;
714 : XXXXXXXX;
713 : XXXXXXXX;
712 : XXXXXXXX;
711 : XXXXXXXX;
710 : XXXXXXXX;
709 : XXXXXXXX;
708 : XXXXXXXX;
707 : XXXXXXXX;
706 : XXXXXXXX;
705 : XXXXXXXX;
704 : XXXXXXXX;
703 : XXXXXXXX;
702 : XXXXXXXX;
701 : XXXXXXXX;
700 : XXXXXXXX;
699 : XXXXXXXX;
698 : XXXXXXXX;
697 : XXXXXXXX;
696 : XXXXXXXX;
695 : XXXXXXXX;
694 : XXXXXXXX;
693 : XXXXXXXX;
692 : XXXXXXXX;
691 : XXXXXXXX;
690 : XXXXXXXX;
689 : XXXXXXXX;
688 : XXXXXXXX;
687 : XXXXXXXX;
686 : XXXXXXXX;
685 : XXXXXXXX;
684 : XXXXXXXX;
683 : XXXXXXXX;
682 : XXXXXXXX;
681 : XXXXXXXX;
680 : XXXXXXXX;
679 : XXXXXXXX;
678 : XXXXXXXX;
677 : XXXXXXXX;
676 : XXXXXXXX;
675 : XXXXXXXX;
674 : XXXXXXXX;
673 : XXXXXXXX;
672 : XXXXXXXX;
671 : XXXXXXXX;
670 : XXXXXXXX;
669 : XXXXXXXX;
668 : XXXXXXXX;
667 : XXXXXXXX;
666 : XXXXXXXX;
665 : XXXXXXXX;
664 : XXXXXXXX;
663 : XXXXXXXX;
662 : XXXXXXXX;
661 : XXXXXXXX;
660 : XXXXXXXX;
659 : XXXXXXXX;
658 : XXXXXXXX;
657 : XXXXXXXX;
656 : XXXXXXXX;
655 : XXXXXXXX;
654 : XXXXXXXX;
653 : XXXXXXXX;
652 : XXXXXXXX;
651 : XXXXXXXX;
650 : XXXXXXXX;
649 : XXXXXXXX;
648 : XXXXXXXX;
647 : XXXXXXXX;
646 : XXXXXXXX;
645 : XXXXXXXX;
644 : XXXXXXXX;
643 : 11100111;
642 : 00000010;
641 : 11100110;
640 : 00000010;
639 : 10000000;
638 : 00000010;
637 : 10000000;
636 : 00000001;
635 : 10000001;
634 : 00000111;
633 : 10000101;
632 : 00000000;
631 : 11100010;
630 : 00000101;
629 : 11100101;
628 : 01000011;
627 : 00000000;
626 : 11100011;
625 : 00000000;
624 : 11110011;
623 : 00000000;
622 : 11111011;
621 : 00000000;
620 : 10111111;
619 : 00000000;
618 : 00001111;
617 : 00000000;
616 : 00000111;
615 : 00000000;
614 : 00000011;
613 : 11111000;
612 : 00000000;
611 : 11111000;
610 : 00000000;
609 : 00111001;
608 : 00000000;
607 : 00111011;
606 : 00000000;
605 : 00111111;
604 : 00000000;
603 : 00111110;
602 : 00000000;
601 : 11111100;
600 : 00000000;
599 : 11111000;
598 : 10000000;
597 : 00000000;
596 : 11100000;
595 : 00000000;
594 : 11100000;
593 : 00000000;
592 : 10000000;
591 : 00000000;
590 : 10000000;
589 : 00000000;
588 : 11100000;
587 : 00000000;
586 : 11100000;
585 : 00000000;
584 : 10000000;
583 : 11111111;
582 : 00000000;
581 : 11111111;
580 : 00000000;
579 : 00111000;
578 : 00000000;
577 : 00111111;
576 : 00000000;
575 : 00111111;
574 : 00000000;
573 : 00111000;
572 : 00000000;
571 : 11111111;
570 : 00000000;
569 : 11111111;
568 : 11111111;
567 : 00000000;
566 : 11111111;
565 : 00000000;
564 : 00111100;
563 : 00000000;
562 : 00111100;
561 : 00000000;
560 : 00111100;
559 : 00000000;
558 : 00111100;
557 : 00000000;
556 : 11111111;
555 : 00000000;
554 : 11111111;
553 : 00101000;
552 : 00010010;
551 : 00011111;
550 : 11010000;
549 : 10011011;
549 : 01110101;
548 : 10100010;
547 : 00110000;
546 : 01100000;
547 : 00001000;
546 : 01110000;
545 : 00011111;
544 : 11010000;
543 : 10001100;
543 : 01100110;
542 : 10100010;
541 : 00101000;
540 : 01100000;
541 : 00001000;
540 : 01110000;
539 : 00011111;
538 : 11010000;
537 : 01111101;
537 : 01010111;
536 : 10100010;
535 : 00100000;
534 : 01100000;
535 : 00000100;
534 : 01110000;
533 : 00011111;
532 : 11010000;
531 : 01101110;
530 : 10100010;
529 : 00011000;
528 : 01100000;
531 : 00001000;
530 : 01110000;
529 : 01001000;
528 : 10100010;
527 : 00011111;
526 : 11010000;
525 : 01011111;
525 : 00111001;
524 : 10100010;
523 : 00010000;
522 : 01100000;
523 : 00001001;
522 : 01110000;
521 : 00011111;
520 : 11010000;
519 : 01010000;
518 : 10100010;
517 : 00001000;
519 : 00001000;
518 : 01100001;
517 : 00001100;
516 : 01100000;
515 : 00000001;
514 : 01100001;
515 : 00101010;
514 : 10100010;
513 : 11100000;
512 : 00000000;
511 : XXXXXXXX;

BIN
db/chip8.root_partition.map.reg_db.cdb
View file

Binary file not shown.

BIN
db/chip8.routing.rdb
View file

Binary file not shown.

BIN
db/chip8.rtlv.hdb
View file

Binary file not shown.

BIN
db/chip8.rtlv_sg.cdb
View file

Binary file not shown.

BIN
db/chip8.rtlv_sg_swap.cdb
View file

Binary file not shown.

112
db/chip8.sta.qmsg
View file

@ -1,56 +1,56 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1712551938749 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition " "Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1712551938749 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 7 23:52:18 2024 " "Processing started: Sun Apr 7 23:52:18 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1712551938749 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1712551938749 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta chip8 -c chip8 " "Command: quartus_sta chip8 -c chip8" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1712551938749 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1712551938772 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1712551939456 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "12 12 " "Parallel compilation is enabled and will use 12 of the 12 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1712551939456 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature -40 degrees C " "Low junction temperature is -40 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712551939481 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 100 degrees C " "High junction temperature is 100 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712551939481 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "chip8.sdc " "Synopsys Design Constraints File file not found: 'chip8.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1712551940847 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1712551940847 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name fpga_clk fpga_clk " "create_clock -period 1.000 -name fpga_clk fpga_clk" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1712551940934 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " "create_clock -period 1.000 -name cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1712551940934 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1712551940934 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1712551941197 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1712551941259 ""}
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1712551941263 ""}
{ "Info" "0" "" "Analyzing Slow 1100mV 100C Model" { } { } 0 0 "Analyzing Slow 1100mV 100C Model" 0 0 "Timing Analyzer" 0 0 1712551941268 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1712551945434 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1712551945434 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -28.406 " "Worst-case setup slack is -28.406" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551945434 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551945434 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -28.406 -1742.530 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " -28.406 -1742.530 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551945434 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -11.186 -95769.392 fpga_clk " " -11.186 -95769.392 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551945434 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712551945434 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.429 " "Worst-case hold slack is 0.429" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551945664 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551945664 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.429 0.000 fpga_clk " " 0.429 0.000 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551945664 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.476 0.000 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " 0.476 0.000 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551945664 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712551945664 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1712551945666 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1712551945667 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.636 " "Worst-case minimum pulse width slack is -2.636" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551945672 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551945672 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.636 -8463.323 fpga_clk " " -2.636 -8463.323 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551945672 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.538 -185.389 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " -0.538 -185.389 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551945672 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712551945672 ""}
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 8 synchronizer chains. " "Report Metastability: Found 8 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Design MTBF is not calculated because the design doesn't meet its timing requirements. " "Design MTBF is not calculated because the design doesn't meet its timing requirements." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1712551945720 ""} } { } 0 332114 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1712551945720 ""}
{ "Info" "0" "" "Analyzing Slow 1100mV -40C Model" { } { } 0 0 "Analyzing Slow 1100mV -40C Model" 0 0 "Timing Analyzer" 0 0 1712551945722 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1712551945782 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1712551951737 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1712551952797 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1712551953465 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1712551953465 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -26.933 " "Worst-case setup slack is -26.933" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551953465 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551953465 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -26.933 -1684.576 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " -26.933 -1684.576 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551953465 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -11.228 -94100.779 fpga_clk " " -11.228 -94100.779 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551953465 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712551953465 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.484 " "Worst-case hold slack is 0.484" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551953711 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551953711 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.484 0.000 fpga_clk " " 0.484 0.000 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551953711 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.565 0.000 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " 0.565 0.000 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551953711 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712551953711 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1712551953712 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1712551953713 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.636 " "Worst-case minimum pulse width slack is -2.636" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551953723 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551953723 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.636 -8927.522 fpga_clk " " -2.636 -8927.522 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551953723 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.538 -184.012 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " -0.538 -184.012 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551953723 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712551953723 ""}
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 8 synchronizer chains. " "Report Metastability: Found 8 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Design MTBF is not calculated because the design doesn't meet its timing requirements. " "Design MTBF is not calculated because the design doesn't meet its timing requirements." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1712551953779 ""} } { } 0 332114 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1712551953779 ""}
{ "Info" "0" "" "Analyzing Fast 1100mV 100C Model" { } { } 0 0 "Analyzing Fast 1100mV 100C Model" 0 0 "Timing Analyzer" 0 0 1712551953781 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1712551954065 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1712551959681 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1712551960616 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1712551960917 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1712551960917 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -14.774 " "Worst-case setup slack is -14.774" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551960918 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551960918 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -14.774 -901.498 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " -14.774 -901.498 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551960918 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -6.214 -50560.530 fpga_clk " " -6.214 -50560.530 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551960918 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712551960918 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.162 " "Worst-case hold slack is 0.162" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551961180 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551961180 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.162 0.000 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " 0.162 0.000 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551961180 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.177 0.000 fpga_clk " " 0.177 0.000 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551961180 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712551961180 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1712551961181 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1712551961181 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.174 " "Worst-case minimum pulse width slack is -2.174" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551961192 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551961192 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.174 -1371.543 fpga_clk " " -2.174 -1371.543 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551961192 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.192 -9.702 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " -0.192 -9.702 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551961192 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712551961192 ""}
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 8 synchronizer chains. " "Report Metastability: Found 8 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Design MTBF is not calculated because the design doesn't meet its timing requirements. " "Design MTBF is not calculated because the design doesn't meet its timing requirements." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1712551961244 ""} } { } 0 332114 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1712551961244 ""}
{ "Info" "0" "" "Analyzing Fast 1100mV -40C Model" { } { } 0 0 "Analyzing Fast 1100mV -40C Model" 0 0 "Timing Analyzer" 0 0 1712551961245 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1712551961832 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1712551962139 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1712551962139 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -12.462 " "Worst-case setup slack is -12.462" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551962139 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551962139 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -12.462 -739.747 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " -12.462 -739.747 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551962139 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.930 -40871.978 fpga_clk " " -4.930 -40871.978 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551962139 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712551962139 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.140 " "Worst-case hold slack is 0.140" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551962440 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551962440 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.140 0.000 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " 0.140 0.000 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551962440 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.164 0.000 fpga_clk " " 0.164 0.000 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551962440 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712551962440 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1712551962441 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1712551962441 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.174 " "Worst-case minimum pulse width slack is -2.174" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551962451 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551962451 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.174 -1373.239 fpga_clk " " -2.174 -1373.239 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551962451 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.137 -3.355 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " -0.137 -3.355 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551962451 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712551962451 ""}
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 8 synchronizer chains. " "Report Metastability: Found 8 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Design MTBF is not calculated because the design doesn't meet its timing requirements. " "Design MTBF is not calculated because the design doesn't meet its timing requirements." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1712551962500 ""} } { } 0 332114 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1712551962500 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1712551963345 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1712551963345 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1353 " "Peak virtual memory: 1353 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1712551963512 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 7 23:52:43 2024 " "Processing ended: Sun Apr 7 23:52:43 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1712551963512 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:25 " "Elapsed time: 00:00:25" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1712551963512 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:01:44 " "Total CPU time (on all processors): 00:01:44" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1712551963512 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1712551963512 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1712584346749 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition " "Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1712584346749 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Apr 8 08:52:26 2024 " "Processing started: Mon Apr 8 08:52:26 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1712584346749 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1712584346749 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta chip8 -c chip8 " "Command: quartus_sta chip8 -c chip8" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1712584346749 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1712584346775 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1712584347519 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "12 12 " "Parallel compilation is enabled and will use 12 of the 12 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1712584347519 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature -40 degrees C " "Low junction temperature is -40 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712584347540 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 100 degrees C " "High junction temperature is 100 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712584347540 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "chip8.sdc " "Synopsys Design Constraints File file not found: 'chip8.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1712584348745 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1712584348745 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name fpga_clk fpga_clk " "create_clock -period 1.000 -name fpga_clk fpga_clk" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1712584348809 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " "create_clock -period 1.000 -name cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1712584348809 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name downclocker:dc\|clk_out downclocker:dc\|clk_out " "create_clock -period 1.000 -name downclocker:dc\|clk_out downclocker:dc\|clk_out" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1712584348809 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1712584348809 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1712584348957 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1712584349002 ""}
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1712584349007 ""}
{ "Info" "0" "" "Analyzing Slow 1100mV 100C Model" { } { } 0 0 "Analyzing Slow 1100mV 100C Model" 0 0 "Timing Analyzer" 0 0 1712584349012 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1712584352097 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1712584352097 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -31.412 " "Worst-case setup slack is -31.412" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584352098 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584352098 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -31.412 -1884.356 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " -31.412 -1884.356 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584352098 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -11.058 -87363.415 downclocker:dc\|clk_out " " -11.058 -87363.415 downclocker:dc\|clk_out " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584352098 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.953 -27.713 fpga_clk " " -4.953 -27.713 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584352098 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712584352098 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.429 " "Worst-case hold slack is 0.429" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584352292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584352292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.429 0.000 downclocker:dc\|clk_out " " 0.429 0.000 downclocker:dc\|clk_out " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584352292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.501 0.000 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " 0.501 0.000 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584352292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.814 0.000 fpga_clk " " 0.814 0.000 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584352292 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712584352292 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1712584352293 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1712584352294 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.636 " "Worst-case minimum pulse width slack is -2.636" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584352305 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584352305 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.636 -8430.055 downclocker:dc\|clk_out " " -2.636 -8430.055 downclocker:dc\|clk_out " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584352305 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.622 -17.105 fpga_clk " " -0.622 -17.105 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584352305 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.538 -172.550 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " -0.538 -172.550 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584352305 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712584352305 ""}
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 8 synchronizer chains. " "Report Metastability: Found 8 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Design MTBF is not calculated because the design doesn't meet its timing requirements. " "Design MTBF is not calculated because the design doesn't meet its timing requirements." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1712584352352 ""} } { } 0 332114 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1712584352352 ""}
{ "Info" "0" "" "Analyzing Slow 1100mV -40C Model" { } { } 0 0 "Analyzing Slow 1100mV -40C Model" 0 0 "Timing Analyzer" 0 0 1712584352354 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1712584352416 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1712584357006 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1712584357723 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1712584358182 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1712584358182 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -29.494 " "Worst-case setup slack is -29.494" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584358183 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584358183 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.494 -1798.010 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " -29.494 -1798.010 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584358183 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -11.057 -87142.095 downclocker:dc\|clk_out " " -11.057 -87142.095 downclocker:dc\|clk_out " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584358183 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.658 -29.299 fpga_clk " " -4.658 -29.299 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584358183 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712584358183 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.483 " "Worst-case hold slack is 0.483" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584358364 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584358364 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.483 0.000 downclocker:dc\|clk_out " " 0.483 0.000 downclocker:dc\|clk_out " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584358364 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.546 0.000 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " 0.546 0.000 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584358364 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.786 0.000 fpga_clk " " 0.786 0.000 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584358364 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712584358364 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1712584358365 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1712584358367 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.636 " "Worst-case minimum pulse width slack is -2.636" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584358379 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584358379 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.636 -8301.987 downclocker:dc\|clk_out " " -2.636 -8301.987 downclocker:dc\|clk_out " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584358379 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.627 -18.184 fpga_clk " " -0.627 -18.184 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584358379 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.538 -170.070 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " -0.538 -170.070 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584358379 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712584358379 ""}
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 8 synchronizer chains. " "Report Metastability: Found 8 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Design MTBF is not calculated because the design doesn't meet its timing requirements. " "Design MTBF is not calculated because the design doesn't meet its timing requirements." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1712584358423 ""} } { } 0 332114 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1712584358423 ""}
{ "Info" "0" "" "Analyzing Fast 1100mV 100C Model" { } { } 0 0 "Analyzing Fast 1100mV 100C Model" 0 0 "Timing Analyzer" 0 0 1712584358424 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1712584358636 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1712584362578 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1712584363407 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1712584363595 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1712584363595 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -16.301 " "Worst-case setup slack is -16.301" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584363596 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584363596 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.301 -1018.017 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " -16.301 -1018.017 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584363596 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -5.608 -44394.911 downclocker:dc\|clk_out " " -5.608 -44394.911 downclocker:dc\|clk_out " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584363596 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.718 -8.178 fpga_clk " " -3.718 -8.178 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584363596 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712584363596 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.160 " "Worst-case hold slack is 0.160" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584363790 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584363790 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.160 0.000 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " 0.160 0.000 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584363790 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.177 0.000 downclocker:dc\|clk_out " " 0.177 0.000 downclocker:dc\|clk_out " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584363790 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.303 0.000 fpga_clk " " 0.303 0.000 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584363790 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712584363790 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1712584363791 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1712584363791 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.174 " "Worst-case minimum pulse width slack is -2.174" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584363803 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584363803 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.174 -537.344 downclocker:dc\|clk_out " " -2.174 -537.344 downclocker:dc\|clk_out " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584363803 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.517 -2.901 fpga_clk " " -0.517 -2.901 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584363803 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.144 -6.507 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " -0.144 -6.507 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584363803 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712584363803 ""}
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 8 synchronizer chains. " "Report Metastability: Found 8 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Design MTBF is not calculated because the design doesn't meet its timing requirements. " "Design MTBF is not calculated because the design doesn't meet its timing requirements." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1712584363846 ""} } { } 0 332114 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1712584363846 ""}
{ "Info" "0" "" "Analyzing Fast 1100mV -40C Model" { } { } 0 0 "Analyzing Fast 1100mV -40C Model" 0 0 "Timing Analyzer" 0 0 1712584363847 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1712584364332 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1712584364514 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1712584364514 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -14.004 " "Worst-case setup slack is -14.004" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584364515 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584364515 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -14.004 -820.600 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " -14.004 -820.600 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584364515 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.541 -36337.093 downclocker:dc\|clk_out " " -4.541 -36337.093 downclocker:dc\|clk_out " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584364515 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.859 -5.427 fpga_clk " " -2.859 -5.427 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584364515 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712584364515 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.138 " "Worst-case hold slack is 0.138" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584364696 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584364696 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.138 0.000 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " 0.138 0.000 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584364696 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.164 0.000 downclocker:dc\|clk_out " " 0.164 0.000 downclocker:dc\|clk_out " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584364696 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.289 0.000 fpga_clk " " 0.289 0.000 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584364696 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712584364696 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1712584364696 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1712584364697 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.174 " "Worst-case minimum pulse width slack is -2.174" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584364710 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584364710 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.174 -534.258 downclocker:dc\|clk_out " " -2.174 -534.258 downclocker:dc\|clk_out " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584364710 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.533 -2.899 fpga_clk " " -0.533 -2.899 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584364710 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.057 -2.411 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " -0.057 -2.411 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584364710 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712584364710 ""}
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 8 synchronizer chains. " "Report Metastability: Found 8 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Design MTBF is not calculated because the design doesn't meet its timing requirements. " "Design MTBF is not calculated because the design doesn't meet its timing requirements." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1712584364752 ""} } { } 0 332114 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1712584364752 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1712584365431 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1712584365432 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1312 " "Peak virtual memory: 1312 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1712584365561 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 8 08:52:45 2024 " "Processing ended: Mon Apr 8 08:52:45 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1712584365561 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:19 " "Elapsed time: 00:00:19" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1712584365561 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:01:25 " "Total CPU time (on all processors): 00:01:25" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1712584365561 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1712584365561 ""}

BIN
db/chip8.sta.rdb
View file

Binary file not shown.

BIN
db/chip8.sta_cmp.7_slow_1100mv_100c.tdb
View file

Binary file not shown.

BIN
db/chip8.tiscmp.fast_1100mv_100c.ddb
View file

Binary file not shown.

BIN
db/chip8.tiscmp.fast_1100mv_n40c.ddb
View file

Binary file not shown.

BIN
db/chip8.tiscmp.fastest_slow_1100mv_85c.ddb
View file

Binary file not shown.

BIN
db/chip8.tiscmp.fastest_slow_1100mv_n40c.ddb
View file

Binary file not shown.

BIN
db/chip8.tiscmp.slow_1100mv_100c.ddb
View file

Binary file not shown.

BIN
db/chip8.tiscmp.slow_1100mv_n40c.ddb
View file

Binary file not shown.

BIN
db/chip8.vpr.ammdb
View file

Binary file not shown.

4
db/chip8_partition_pins.json
View file

@ -27,10 +27,6 @@
"name" : "led[3]",
"strict" : false
},
{
"name" : "led[4]",
"strict" : false
},
{
"name" : "fpga_clk",
"strict" : false

BIN
incremental_db/compiled_partitions/chip8.root_partition.cmp.ammdb
View file

Binary file not shown.

BIN
incremental_db/compiled_partitions/chip8.root_partition.cmp.cdb
View file

Binary file not shown.

BIN
incremental_db/compiled_partitions/chip8.root_partition.cmp.hbdb.cdb
View file

Binary file not shown.

BIN
incremental_db/compiled_partitions/chip8.root_partition.cmp.hbdb.hdb
View file

Binary file not shown.

BIN
incremental_db/compiled_partitions/chip8.root_partition.cmp.hdb
View file

Binary file not shown.

BIN
incremental_db/compiled_partitions/chip8.root_partition.cmp.rcfdb
View file

Binary file not shown.

BIN
incremental_db/compiled_partitions/chip8.root_partition.map.cdb
View file

Binary file not shown.

BIN
incremental_db/compiled_partitions/chip8.root_partition.map.dpi
View file

Binary file not shown.

BIN
incremental_db/compiled_partitions/chip8.root_partition.map.hbdb.cdb
View file

Binary file not shown.

BIN
incremental_db/compiled_partitions/chip8.root_partition.map.hbdb.hdb
View file

Binary file not shown.

BIN
incremental_db/compiled_partitions/chip8.root_partition.map.hdb
View file

Binary file not shown.

BIN
incremental_db/compiled_partitions/chip8.root_partition.map.kpt
View file

Binary file not shown.

BIN
incremental_db/compiled_partitions/chip8.rrp.hdb
View file

Binary file not shown.

BIN
incremental_db/compiled_partitions/chip8.rrs.cdb
View file

Binary file not shown.

16
output_files/chip8.asm.rpt
View file

@ -1,5 +1,5 @@
Assembler report for chip8
Sun Apr 7 23:52:17 2024
Mon Apr 8 08:52:25 2024
Quartus Prime Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition
@ -38,7 +38,7 @@ https://fpgasoftware.intel.com/eula.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Sun Apr 7 23:52:17 2024 ;
; Assembler Status ; Successful - Mon Apr 8 08:52:25 2024 ;
; Revision Name ; chip8 ;
; Top-level Entity Name ; chip8 ;
; Family ; Cyclone V ;
@ -67,8 +67,8 @@ https://fpgasoftware.intel.com/eula.
+----------------+--------------------+
; Option ; Setting ;
+----------------+--------------------+
; JTAG usercode ; 0x02233A94 ;
; Checksum ; 0x02233A94 ;
; JTAG usercode ; 0x0223939A ;
; Checksum ; 0x0223939A ;
+----------------+--------------------+
@ -78,14 +78,14 @@ https://fpgasoftware.intel.com/eula.
Info: *******************************************************************
Info: Running Quartus Prime Assembler
Info: Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition
Info: Processing started: Sun Apr 7 23:52:10 2024
Info: Processing started: Mon Apr 8 08:52:19 2024
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off chip8 -c chip8
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (115030): Assembler is generating device programming files
Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
Info: Peak virtual memory: 631 megabytes
Info: Processing ended: Sun Apr 7 23:52:17 2024
Info: Elapsed time: 00:00:07
Info: Peak virtual memory: 628 megabytes
Info: Processing ended: Mon Apr 8 08:52:25 2024
Info: Elapsed time: 00:00:06
Info: Total CPU time (on all processors): 00:00:07

2
output_files/chip8.done
View file

@ -1 +1 @@
Sun Apr 7 23:52:44 2024
Mon Apr 8 08:52:46 2024

2367
output_files/chip8.fit.rpt
View file

File diff suppressed because it is too large Load diff

6
output_files/chip8.fit.summary
View file

@ -1,12 +1,12 @@
Fitter Status : Successful - Sun Apr 7 23:52:05 2024
Fitter Status : Successful - Mon Apr 8 08:52:14 2024
Quartus Prime Version : 23.1std.0 Build 991 11/28/2023 SC Lite Edition
Revision Name : chip8
Top-level Entity Name : chip8
Family : Cyclone V
Device : 5CSEBA6U23I7
Timing Models : Final
Logic utilization (in ALMs) : 10,549 / 41,910 ( 25 % )
Total registers : 10004
Logic utilization (in ALMs) : 10,693 / 41,910 ( 26 % )
Total registers : 10165
Total pins : 10 / 314 ( 3 % )
Total virtual pins : 0
Total block memory bits : 32,768 / 5,662,720 ( < 1 % )

22
output_files/chip8.flow.rpt
View file

@ -1,5 +1,5 @@
Flow report for chip8
Sun Apr 7 23:52:43 2024
Mon Apr 8 08:52:45 2024
Quartus Prime Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition
@ -41,15 +41,15 @@ https://fpgasoftware.intel.com/eula.
+----------------------------------------------------------------------------------+
; Flow Summary ;
+---------------------------------+------------------------------------------------+
; Flow Status ; Successful - Sun Apr 7 23:52:17 2024 ;
; Flow Status ; Successful - Mon Apr 8 08:52:25 2024 ;
; Quartus Prime Version ; 23.1std.0 Build 991 11/28/2023 SC Lite Edition ;
; Revision Name ; chip8 ;
; Top-level Entity Name ; chip8 ;
; Family ; Cyclone V ;
; Device ; 5CSEBA6U23I7 ;
; Timing Models ; Final ;
; Logic utilization (in ALMs) ; 10,549 / 41,910 ( 25 % ) ;
; Total registers ; 10004 ;
; Logic utilization (in ALMs) ; 10,693 / 41,910 ( 26 % ) ;
; Total registers ; 10165 ;
; Total pins ; 10 / 314 ( 3 % ) ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 32,768 / 5,662,720 ( < 1 % ) ;
@ -68,7 +68,7 @@ https://fpgasoftware.intel.com/eula.
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 04/07/2024 23:44:51 ;
; Start date & time ; 04/08/2024 08:46:51 ;
; Main task ; Compilation ;
; Revision Name ; chip8 ;
+-------------------+---------------------+
@ -79,7 +79,7 @@ https://fpgasoftware.intel.com/eula.
+-------------------------------------+----------------------------------------+---------------+-------------+----------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+----------------------------------------+---------------+-------------+----------------+
; COMPILER_SIGNATURE_ID ; 346662554261.171255149111146 ; -- ; -- ; -- ;
; COMPILER_SIGNATURE_ID ; 346662554261.171258401122441 ; -- ; -- ; -- ;
; EDA_OUTPUT_DATA_FORMAT ; None ; -- ; -- ; eda_simulation ;
; MAX_CORE_JUNCTION_TEMP ; 100 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; -40 ; -- ; -- ; -- ;
@ -97,11 +97,11 @@ https://fpgasoftware.intel.com/eula.
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:01:01 ; 3.7 ; 698 MB ; 00:01:45 ;
; Fitter ; 00:06:11 ; 1.6 ; 2797 MB ; 00:14:15 ;
; Assembler ; 00:00:07 ; 1.0 ; 631 MB ; 00:00:07 ;
; Timing Analyzer ; 00:00:25 ; 5.7 ; 1353 MB ; 00:01:44 ;
; Total ; 00:07:44 ; -- ; -- ; 00:17:51 ;
; Analysis & Synthesis ; 00:00:54 ; 3.7 ; 775 MB ; 00:01:32 ;
; Fitter ; 00:04:26 ; 1.6 ; 2824 MB ; 00:11:35 ;
; Assembler ; 00:00:06 ; 1.0 ; 628 MB ; 00:00:06 ;
; Timing Analyzer ; 00:00:19 ; 5.5 ; 1312 MB ; 00:01:25 ;
; Total ; 00:05:45 ; -- ; -- ; 00:14:38 ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+

287
output_files/chip8.map.rpt
View file

@ -1,5 +1,5 @@
Analysis & Synthesis report for chip8
Sun Apr 7 23:45:53 2024
Mon Apr 8 08:47:47 2024
Quartus Prime Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition
@ -21,14 +21,16 @@ Quartus Prime Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition
13. Registers Packed Into Inferred Megafunctions
14. Multiplexer Restructuring Statistics (Restructuring Performed)
15. Source assignments for memory:mem|altsyncram:mem_rtl_0|altsyncram_dsq1:auto_generated
16. Parameter Settings for User Entity Instance: memory:mem
17. Parameter Settings for Inferred Entity Instance: memory:mem|altsyncram:mem_rtl_0
18. altsyncram Parameter Settings by Entity Instance
19. Port Connectivity Checks: "cpu:cpu|st7920_serial_driver:gpu"
20. Port Connectivity Checks: "cpu:cpu"
21. Post-Synthesis Netlist Statistics for Top Partition
22. Elapsed Time Per Partition
23. Analysis & Synthesis Messages
16. Parameter Settings for User Entity Instance: downclocker:dc
17. Parameter Settings for User Entity Instance: memory:mem
18. Parameter Settings for Inferred Entity Instance: memory:mem|altsyncram:mem_rtl_0
19. altsyncram Parameter Settings by Entity Instance
20. Port Connectivity Checks: "cpu:cpu|st7920_serial_driver:gpu"
21. Port Connectivity Checks: "cpu:cpu"
22. Post-Synthesis Netlist Statistics for Top Partition
23. Elapsed Time Per Partition
24. Analysis & Synthesis Messages
25. Analysis & Synthesis Suppressed Messages
@ -55,13 +57,13 @@ https://fpgasoftware.intel.com/eula.
+----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+---------------------------------+------------------------------------------------+
; Analysis & Synthesis Status ; Successful - Sun Apr 7 23:45:53 2024 ;
; Analysis & Synthesis Status ; Successful - Mon Apr 8 08:47:47 2024 ;
; Quartus Prime Version ; 23.1std.0 Build 991 11/28/2023 SC Lite Edition ;
; Revision Name ; chip8 ;
; Top-level Entity Name ; chip8 ;
; Family ; Cyclone V ;
; Logic utilization (in ALMs) ; N/A ;
; Total registers ; 8728 ;
; Total registers ; 8836 ;
; Total pins ; 10 ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 32,768 ;
@ -170,22 +172,22 @@ https://fpgasoftware.intel.com/eula.
; Number detected on machine ; 12 ;
; Maximum allowed ; 12 ;
; ; ;
; Average used ; 3.71 ;
; Average used ; 3.67 ;
; Maximum used ; 12 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
; Processor 2 ; 48.5% ;
; Processor 3 ; 48.3% ;
; Processor 4 ; 24.0% ;
; Processor 5 ; 24.0% ;
; Processor 6 ; 24.0% ;
; Processor 7 ; 19.2% ;
; Processor 8 ; 19.2% ;
; Processor 9 ; 19.2% ;
; Processor 10 ; 18.8% ;
; Processor 11 ; 18.8% ;
; Processor 12 ; 7.5% ;
; Processor 2 ; 40.2% ;
; Processor 3 ; 40.2% ;
; Processor 4 ; 35.9% ;
; Processor 5 ; 35.8% ;
; Processor 6 ; 35.8% ;
; Processor 7 ; 25.7% ;
; Processor 8 ; 25.7% ;
; Processor 9 ; 6.9% ;
; Processor 10 ; 6.9% ;
; Processor 11 ; 6.9% ;
; Processor 12 ; 6.8% ;
+----------------------------+-------------+
@ -197,6 +199,9 @@ https://fpgasoftware.intel.com/eula.
; the-bomb/st7920_serial_driver.sv ; yes ; User SystemVerilog HDL File ; /home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv ; ;
; chip8.sv ; yes ; User SystemVerilog HDL File ; /home/nickorlow/programming/school/warminster/yayacemu/chip8.sv ; ;
; cpu.sv ; yes ; User SystemVerilog HDL File ; /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv ; ;
; alu.sv ; yes ; User SystemVerilog HDL File ; /home/nickorlow/programming/school/warminster/yayacemu/alu.sv ; ;
; aastructs.sv ; yes ; User SystemVerilog HDL File ; /home/nickorlow/programming/school/warminster/yayacemu/aastructs.sv ; ;
; downclocker.sv ; yes ; User SystemVerilog HDL File ; /home/nickorlow/programming/school/warminster/yayacemu/downclocker.sv ; ;
; memory.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/nickorlow/programming/school/warminster/yayacemu/memory.sv ; ;
; rom.bin ; yes ; Auto-Found Unspecified File ; /home/nickorlow/programming/school/warminster/yayacemu/rom.bin ; ;
; fontset.bin ; yes ; Auto-Found Unspecified File ; /home/nickorlow/programming/school/warminster/yayacemu/fontset.bin ; ;
@ -214,21 +219,21 @@ https://fpgasoftware.intel.com/eula.
+---------------------------------------+-----------------+-------------------------------------------------------+----------------------------------------------------------------------------------------------+---------+
+--------------------------------------------------------------+
+----------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+----------------+
+---------------------------------------------+------------------------+
; Resource ; Usage ;
+---------------------------------------------+----------------+
; Estimate of Logic utilization (ALMs needed) ; 10412 ;
+---------------------------------------------+------------------------+
; Estimate of Logic utilization (ALMs needed) ; 10507 ;
; ; ;
; Combinational ALUT usage for logic ; 17065 ;
; -- 7 input functions ; 58 ;
; -- 6 input functions ; 3654 ;
; -- 5 input functions ; 5900 ;
; -- 4 input functions ; 2000 ;
; -- <=3 input functions ; 5453 ;
; Combinational ALUT usage for logic ; 17207 ;
; -- 7 input functions ; 56 ;
; -- 6 input functions ; 3707 ;
; -- 5 input functions ; 5934 ;
; -- 4 input functions ; 2008 ;
; -- <=3 input functions ; 5502 ;
; ; ;
; Dedicated logic registers ; 8728 ;
; Dedicated logic registers ; 8836 ;
; ; ;
; I/O pins ; 10 ;
; Total MLAB memory bits ; 0 ;
@ -236,11 +241,11 @@ https://fpgasoftware.intel.com/eula.
; ; ;
; Total DSP Blocks ; 0 ;
; ; ;
; Maximum fan-out node ; fpga_clk~input ;
; Maximum fan-out ; 8564 ;
; Total fan-out ; 102143 ;
; Average fan-out ; 3.96 ;
+---------------------------------------------+----------------+
; Maximum fan-out node ; downclocker:dc|clk_out ;
; Maximum fan-out ; 8652 ;
; Total fan-out ; 103021 ;
; Average fan-out ; 3.95 ;
+---------------------------------------------+------------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
@ -248,10 +253,12 @@ https://fpgasoftware.intel.com/eula.
+-------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+-----------------------------------------------------------------------+----------------------+--------------+
; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
+-------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+-----------------------------------------------------------------------+----------------------+--------------+
; |chip8 ; 17065 (1) ; 8728 (0) ; 32768 ; 0 ; 10 ; 0 ; |chip8 ; chip8 ; work ;
; |cpu:cpu| ; 17064 (11448) ; 8728 (8546) ; 0 ; 0 ; 0 ; 0 ; |chip8|cpu:cpu ; cpu ; work ;
; |st7920_serial_driver:gpu| ; 5616 (5570) ; 182 (129) ; 0 ; 0 ; 0 ; 0 ; |chip8|cpu:cpu|st7920_serial_driver:gpu ; st7920_serial_driver ; work ;
; |chip8 ; 17207 (1) ; 8836 (0) ; 32768 ; 0 ; 10 ; 0 ; |chip8 ; chip8 ; work ;
; |cpu:cpu| ; 17195 (11517) ; 8825 (8594) ; 0 ; 0 ; 0 ; 0 ; |chip8|cpu:cpu ; cpu ; work ;
; |alu:alu| ; 47 (47) ; 49 (49) ; 0 ; 0 ; 0 ; 0 ; |chip8|cpu:cpu|alu:alu ; alu ; work ;
; |st7920_serial_driver:gpu| ; 5631 (5585) ; 182 (129) ; 0 ; 0 ; 0 ; 0 ; |chip8|cpu:cpu|st7920_serial_driver:gpu ; st7920_serial_driver ; work ;
; |commander:com| ; 46 (46) ; 53 (53) ; 0 ; 0 ; 0 ; 0 ; |chip8|cpu:cpu|st7920_serial_driver:gpu|commander:com ; commander ; work ;
; |downclocker:dc| ; 11 (11) ; 11 (11) ; 0 ; 0 ; 0 ; 0 ; |chip8|downclocker:dc ; downclocker ; work ;
; |memory:mem| ; 0 (0) ; 0 (0) ; 32768 ; 0 ; 0 ; 0 ; |chip8|memory:mem ; memory ; work ;
; |altsyncram:mem_rtl_0| ; 0 (0) ; 0 (0) ; 32768 ; 0 ; 0 ; 0 ; |chip8|memory:mem|altsyncram:mem_rtl_0 ; altsyncram ; work ;
; |altsyncram_dsq1:auto_generated| ; 0 (0) ; 0 (0) ; 32768 ; 0 ; 0 ; 0 ; |chip8|memory:mem|altsyncram:mem_rtl_0|altsyncram_dsq1:auto_generated ; altsyncram_dsq1 ; work ;
@ -275,23 +282,26 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+------------------------------------------------------------------------+---------------------------------------------+
; cpu:cpu|st7920_serial_driver:gpu|d_flip_flop:dff|data_out ; Stuck at VCC due to stuck port data_in ;
; cpu:cpu|wr_memory_address[0..11] ; Stuck at GND due to stuck port data_in ;
; cpu:cpu|compute_of ; Stuck at GND due to stuck port data_in ;
; cpu:cpu|instr.src_sprite_sz[4] ; Stuck at GND due to stuck port data_in ;
; cpu:cpu|instr.src_sprite_y[5..7] ; Stuck at GND due to stuck port data_in ;
; cpu:cpu|instr.src_sprite_x[6,7] ; Stuck at GND due to stuck port data_in ;
; cpu:cpu|instr.dst[1..31] ; Stuck at GND due to stuck port data_in ;
; cpu:cpu|instr.op[2..31] ; Stuck at GND due to stuck port data_in ;
; cpu:cpu|instr.op[3..31] ; Stuck at GND due to stuck port data_in ;
; cpu:cpu|alu:alu|overflow ; Lost fanout ;
; cpu:cpu|alu:alu|result_int[8] ; Lost fanout ;
; cpu:cpu|wr_memory_data[0..7] ; Stuck at GND due to stuck port clock_enable ;
; cpu:cpu|draw_state.stage[1..9,11..31] ; Merged with cpu:cpu|draw_state.stage[10] ;
; cpu:cpu|state[4..9,11..31] ; Merged with cpu:cpu|state[10] ;
; cpu:cpu|instr.src[3..31] ; Merged with cpu:cpu|instr.src[0] ;
; cpu:cpu|draw_state.stage[1..9,11..31] ; Merged with cpu:cpu|draw_state.stage[10] ;
; cpu:cpu|st7920_serial_driver:gpu|command[8] ; Stuck at GND due to stuck port data_in ;
; cpu:cpu|st7920_serial_driver:gpu|commander:com|full_command_bits[0..3] ; Stuck at GND due to stuck port data_in ;
; cpu:cpu|wr_go ; Stuck at GND due to stuck port data_in ;
; cpu:cpu|draw_state.stage[10] ; Stuck at GND due to stuck port data_in ;
; cpu:cpu|instr.src[0] ; Stuck at GND due to stuck port data_in ;
; cpu:cpu|state[10] ; Stuck at GND due to stuck port data_in ;
; cpu:cpu|program_counter[12..15] ; Lost fanout ;
; Total Number of Removed Registers = 187 ; ;
; cpu:cpu|instr.src[0] ; Stuck at GND due to stuck port data_in ;
; Total Number of Removed Registers = 189 ; ;
+------------------------------------------------------------------------+---------------------------------------------+
@ -309,8 +319,12 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; cpu:cpu|st7920_serial_driver:gpu|commander:com|full_command_bits[0] ; Stuck at GND ; cpu:cpu|st7920_serial_driver:gpu|commander:com|full_command_bits[1], ;
; ; due to stuck port data_in ; cpu:cpu|st7920_serial_driver:gpu|commander:com|full_command_bits[2], ;
; ; ; cpu:cpu|st7920_serial_driver:gpu|commander:com|full_command_bits[3] ;
; cpu:cpu|compute_of ; Stuck at GND ; cpu:cpu|alu:alu|overflow, cpu:cpu|alu:alu|result_int[8] ;
; ; due to stuck port data_in ; ;
; cpu:cpu|st7920_serial_driver:gpu|d_flip_flop:dff|data_out ; Stuck at VCC ; cpu:cpu|st7920_serial_driver:gpu|command[8] ;
; ; due to stuck port data_in ; ;
; cpu:cpu|instr.op[3] ; Stuck at GND ; cpu:cpu|instr.src[0] ;
; ; due to stuck port data_in ; ;
+---------------------------------------------------------------------+---------------------------+----------------------------------------------------------------------------------+
@ -319,12 +333,12 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 8728 ;
; Number of registers using Synchronous Clear ; 118 ;
; Number of registers using Synchronous Load ; 29 ;
; Total registers ; 8836 ;
; Number of registers using Synchronous Clear ; 169 ;
; Number of registers using Synchronous Load ; 21 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 8631 ;
; Number of registers using Clock Enable ; 8673 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
@ -334,8 +348,9 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+----------------------------------------+---------+
; Inverted Register ; Fan out ;
+----------------------------------------+---------+
; cpu:cpu|alu_rst ; 34 ;
; cpu:cpu|program_counter[9] ; 5 ;
; Total number of inverted registers = 1 ; ;
; Total number of inverted registers = 2 ; ;
+----------------------------------------+---------+
@ -353,27 +368,28 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------------------+
; 3:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|commander:com|full_command_bits[22] ;
; 3:1 ; 8 bits ; 16 LEs ; 0 LEs ; 16 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|commander:com|full_command_bits[17] ;
; 3:1 ; 38 bits ; 76 LEs ; 0 LEs ; 76 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|commander:com|i[9] ;
; 4:1 ; 32 bits ; 64 LEs ; 0 LEs ; 64 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|line_cnt[23] ;
; 4:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|x[5] ;
; 3:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|commander:com|full_command_bits[21] ;
; 3:1 ; 8 bits ; 16 LEs ; 0 LEs ; 16 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|commander:com|full_command_bits[5] ;
; 3:1 ; 38 bits ; 76 LEs ; 0 LEs ; 76 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|commander:com|i[15] ;
; 4:1 ; 32 bits ; 64 LEs ; 0 LEs ; 64 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|line_cnt[15] ;
; 4:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|x[4] ;
; 4:1 ; 7 bits ; 14 LEs ; 7 LEs ; 7 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|y[6] ;
; 5:1 ; 32 bits ; 96 LEs ; 32 LEs ; 64 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|i[1] ;
; 5:1 ; 32 bits ; 96 LEs ; 32 LEs ; 64 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|i[16] ;
; 1029:1 ; 2 bits ; 1372 LEs ; 1368 LEs ; 4 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|command[6] ;
; 1059:1 ; 5 bits ; 3530 LEs ; 3445 LEs ; 85 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|command[5] ;
; 3:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; Yes ; |chip8|cpu:cpu|draw_state.r[4] ;
; 4:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; Yes ; |chip8|cpu:cpu|draw_state.c[1] ;
; 16:1 ; 5 bits ; 50 LEs ; 50 LEs ; 0 LEs ; Yes ; |chip8|cpu:cpu|instr.src_sprite_y[4] ;
; 16:1 ; 6 bits ; 60 LEs ; 60 LEs ; 0 LEs ; Yes ; |chip8|cpu:cpu|instr.src_sprite_x[2] ;
; 4:1 ; 12 bits ; 24 LEs ; 0 LEs ; 24 LEs ; Yes ; |chip8|cpu:cpu|rd_memory_address[3] ;
; 5:1 ; 5 bits ; 15 LEs ; 5 LEs ; 10 LEs ; Yes ; |chip8|cpu:cpu|instr.src_sprite_idx[1] ;
; 5:1 ; 6 bits ; 18 LEs ; 6 LEs ; 12 LEs ; Yes ; |chip8|cpu:cpu|instr.src_byte[9] ;
; 5:1 ; 2 bits ; 6 LEs ; 2 LEs ; 4 LEs ; Yes ; |chip8|cpu:cpu|draw_state.stage[10] ;
; 6:1 ; 8 bits ; 32 LEs ; 0 LEs ; 32 LEs ; Yes ; |chip8|cpu:cpu|instr.src_byte[2] ;
; 6:1 ; 6 bits ; 24 LEs ; 12 LEs ; 12 LEs ; Yes ; |chip8|cpu:cpu|registers[15][5] ;
; 10:1 ; 4 bits ; 24 LEs ; 8 LEs ; 16 LEs ; Yes ; |chip8|cpu:cpu|program_counter[15] ;
; 10:1 ; 10 bits ; 60 LEs ; 20 LEs ; 40 LEs ; Yes ; |chip8|cpu:cpu|program_counter[1] ;
; 3:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; Yes ; |chip8|cpu:cpu|draw_state.r[0] ;
; 4:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; Yes ; |chip8|cpu:cpu|draw_state.c[3] ;
; 16:1 ; 8 bits ; 80 LEs ; 80 LEs ; 0 LEs ; Yes ; |chip8|cpu:cpu|instr.alu_i.operand_b[0] ;
; 16:1 ; 5 bits ; 50 LEs ; 50 LEs ; 0 LEs ; Yes ; |chip8|cpu:cpu|instr.src_sprite_y[0] ;
; 16:1 ; 6 bits ; 60 LEs ; 60 LEs ; 0 LEs ; Yes ; |chip8|cpu:cpu|instr.src_sprite_x[1] ;
; 4:1 ; 12 bits ; 24 LEs ; 0 LEs ; 24 LEs ; Yes ; |chip8|cpu:cpu|rd_memory_address[8] ;
; 5:1 ; 5 bits ; 15 LEs ; 5 LEs ; 10 LEs ; Yes ; |chip8|cpu:cpu|instr.src_sprite_idx[3] ;
; 5:1 ; 2 bits ; 6 LEs ; 2 LEs ; 4 LEs ; Yes ; |chip8|cpu:cpu|draw_state.stage[0] ;
; 7:1 ; 8 bits ; 32 LEs ; 8 LEs ; 24 LEs ; Yes ; |chip8|cpu:cpu|registers[15][5] ;
; 8:1 ; 6 bits ; 30 LEs ; 6 LEs ; 24 LEs ; Yes ; |chip8|cpu:cpu|instr.src_byte[11] ;
; 9:1 ; 4 bits ; 24 LEs ; 8 LEs ; 16 LEs ; Yes ; |chip8|cpu:cpu|program_counter[15] ;
; 9:1 ; 8 bits ; 48 LEs ; 16 LEs ; 32 LEs ; Yes ; |chip8|cpu:cpu|instr.src_byte[1] ;
; 12:1 ; 10 bits ; 80 LEs ; 20 LEs ; 60 LEs ; Yes ; |chip8|cpu:cpu|program_counter[10] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------------------+
@ -386,6 +402,16 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+---------------------------------+--------------------+------+-------------------------+
+-------------------------------------------------------------+
; Parameter Settings for User Entity Instance: downclocker:dc ;
+----------------+-------+------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+------------------------------------+
; DC_BITS ; 10 ; Signed Integer ;
+----------------+-------+------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+---------------------------------------------------------+
; Parameter Settings for User Entity Instance: memory:mem ;
+----------------+-------+--------------------------------+
@ -477,13 +503,14 @@ Note: In order to hide this table in the UI and the text report file, please set
+-------------------------------------------+---------------------------------+
+--------------------------------------------------------------+
+------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "cpu:cpu|st7920_serial_driver:gpu" ;
+--------------+-------+----------+----------------------------+
+--------------+--------+----------+-------------------------------------------------------------------------------------+
; Port ; Type ; Severity ; Details ;
+--------------+-------+----------+----------------------------+
+--------------+--------+----------+-------------------------------------------------------------------------------------+
; sys_rst_n_ms ; Input ; Info ; Stuck at VCC ;
+--------------+-------+----------+----------------------------+
; led ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+--------------+--------+----------+-------------------------------------------------------------------------------------+
+-------------------------------------------------------------------------------------------------------------------------+
@ -500,38 +527,38 @@ Note: In order to hide this table in the UI and the text report file, please set
+-----------------------+-----------------------------+
; Type ; Count ;
+-----------------------+-----------------------------+
; arriav_ff ; 8728 ;
; ENA ; 8526 ;
; ENA SCLR ; 77 ;
; ENA SLD ; 28 ;
; SCLR ; 41 ;
; arriav_ff ; 8836 ;
; ENA ; 8568 ;
; ENA SCLR ; 85 ;
; ENA SLD ; 20 ;
; SCLR ; 84 ;
; SLD ; 1 ;
; plain ; 55 ;
; arriav_lcell_comb ; 17066 ;
; arith ; 257 ;
; plain ; 78 ;
; arriav_lcell_comb ; 17207 ;
; arith ; 307 ;
; 0 data inputs ; 7 ;
; 1 data inputs ; 229 ;
; 2 data inputs ; 17 ;
; 1 data inputs ; 271 ;
; 2 data inputs ; 25 ;
; 3 data inputs ; 1 ;
; 4 data inputs ; 1 ;
; 5 data inputs ; 2 ;
; extend ; 58 ;
; 7 data inputs ; 58 ;
; normal ; 16745 ;
; 0 data inputs ; 2 ;
; extend ; 56 ;
; 7 data inputs ; 56 ;
; normal ; 16838 ;
; 0 data inputs ; 1 ;
; 1 data inputs ; 1 ;
; 2 data inputs ; 176 ;
; 3 data inputs ; 5015 ;
; 4 data inputs ; 1999 ;
; 5 data inputs ; 5898 ;
; 6 data inputs ; 3654 ;
; 2 data inputs ; 198 ;
; 3 data inputs ; 4992 ;
; 4 data inputs ; 2007 ;
; 5 data inputs ; 5932 ;
; 6 data inputs ; 3707 ;
; shared ; 6 ;
; 2 data inputs ; 6 ;
; boundary_port ; 10 ;
; stratixv_ram_block ; 8 ;
; ; ;
; Max LUT depth ; 55.00 ;
; Average LUT depth ; 17.90 ;
; Average LUT depth ; 17.74 ;
+-----------------------+-----------------------------+
@ -540,7 +567,7 @@ Note: In order to hide this table in the UI and the text report file, please set
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top ; 00:00:53 ;
; Top ; 00:00:44 ;
+----------------+--------------+
@ -550,7 +577,7 @@ Note: In order to hide this table in the UI and the text report file, please set
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
Info: Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition
Info: Processing started: Sun Apr 7 23:44:51 2024
Info: Processing started: Mon Apr 8 08:46:51 2024
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off chip8 -c chip8
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 12 of the 12 processors detected
@ -561,27 +588,37 @@ Info (12021): Found 3 design units, including 3 entities, in source file the-bom
Info (12021): Found 1 design units, including 1 entities, in source file chip8.sv
Info (12023): Found entity 1: chip8 File: /home/nickorlow/programming/school/warminster/yayacemu/chip8.sv Line: 1
Info (12021): Found 1 design units, including 1 entities, in source file cpu.sv
Info (12023): Found entity 1: cpu File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 1
Info (12023): Found entity 1: cpu File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 3
Info (12021): Found 1 design units, including 1 entities, in source file alu.sv
Info (12023): Found entity 1: alu File: /home/nickorlow/programming/school/warminster/yayacemu/alu.sv Line: 3
Info (12021): Found 1 design units, including 0 entities, in source file aastructs.sv
Info (12022): Found design unit 1: structs (SystemVerilog) File: /home/nickorlow/programming/school/warminster/yayacemu/aastructs.sv Line: 1
Info (12021): Found 1 design units, including 1 entities, in source file downclocker.sv
Info (12023): Found entity 1: downclocker File: /home/nickorlow/programming/school/warminster/yayacemu/downclocker.sv Line: 1
Info (12127): Elaborating entity "chip8" for the top level hierarchy
Info (12128): Elaborating entity "downclocker" for hierarchy "downclocker:dc" File: /home/nickorlow/programming/school/warminster/yayacemu/chip8.sv Line: 14
Warning (10230): Verilog HDL assignment warning at downclocker.sv(18): truncated value with size 32 to match size of target (10) File: /home/nickorlow/programming/school/warminster/yayacemu/downclocker.sv Line: 18
Warning (12125): Using design file memory.sv, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info (12023): Found entity 1: memory File: /home/nickorlow/programming/school/warminster/yayacemu/memory.sv Line: 1
Info (12128): Elaborating entity "memory" for hierarchy "memory:mem" File: /home/nickorlow/programming/school/warminster/yayacemu/chip8.sv Line: 21
Info (12128): Elaborating entity "memory" for hierarchy "memory:mem" File: /home/nickorlow/programming/school/warminster/yayacemu/chip8.sv Line: 29
Warning (10850): Verilog HDL warning at memory.sv(14): number of words (80) in memory file does not match the number of elements in the address range [0:4095] File: /home/nickorlow/programming/school/warminster/yayacemu/memory.sv Line: 14
Warning (10850): Verilog HDL warning at memory.sv(15): number of words (260) in memory file does not match the number of elements in the address range [512:4095] File: /home/nickorlow/programming/school/warminster/yayacemu/memory.sv Line: 15
Info (12128): Elaborating entity "cpu" for hierarchy "cpu:cpu" File: /home/nickorlow/programming/school/warminster/yayacemu/chip8.sv Line: 35
Warning (10230): Verilog HDL assignment warning at cpu.sv(124): truncated value with size 32 to match size of target (16) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 124
Warning (10230): Verilog HDL assignment warning at cpu.sv(130): truncated value with size 32 to match size of target (16) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 130
Warning (10230): Verilog HDL assignment warning at cpu.sv(147): truncated value with size 32 to match size of target (16) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 147
Warning (10230): Verilog HDL assignment warning at cpu.sv(210): truncated value with size 32 to match size of target (5) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 210
Warning (10230): Verilog HDL assignment warning at cpu.sv(213): truncated value with size 32 to match size of target (5) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 213
Warning (10230): Verilog HDL assignment warning at cpu.sv(242): truncated value with size 32 to match size of target (16) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 242
Warning (10230): Verilog HDL assignment warning at cpu.sv(246): truncated value with size 32 to match size of target (5) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 246
Warning (10230): Verilog HDL assignment warning at cpu.sv(257): truncated value with size 32 to match size of target (5) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 257
Warning (10230): Verilog HDL assignment warning at cpu.sv(284): truncated value with size 32 to match size of target (16) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 284
Warning (10030): Net "instr.src_reg" at cpu.sv(108) has no driver or initial value, using a default initial value '0' File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 108
Warning (10030): Net "instr.src_addr" at cpu.sv(108) has no driver or initial value, using a default initial value '0' File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 108
Warning (10030): Net "instr.dst_addr" at cpu.sv(108) has no driver or initial value, using a default initial value '0' File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 108
Info (12128): Elaborating entity "st7920_serial_driver" for hierarchy "cpu:cpu|st7920_serial_driver:gpu" File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 28
Warning (10850): Verilog HDL warning at memory.sv(15): number of words (132) in memory file does not match the number of elements in the address range [512:4095] File: /home/nickorlow/programming/school/warminster/yayacemu/memory.sv Line: 15
Info (12128): Elaborating entity "cpu" for hierarchy "cpu:cpu" File: /home/nickorlow/programming/school/warminster/yayacemu/chip8.sv Line: 44
Warning (10230): Verilog HDL assignment warning at cpu.sv(148): truncated value with size 32 to match size of target (16) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 148
Warning (10230): Verilog HDL assignment warning at cpu.sv(154): truncated value with size 32 to match size of target (16) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 154
Warning (10230): Verilog HDL assignment warning at cpu.sv(171): truncated value with size 32 to match size of target (16) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 171
Warning (10230): Verilog HDL assignment warning at cpu.sv(249): truncated value with size 32 to match size of target (5) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 249
Warning (10230): Verilog HDL assignment warning at cpu.sv(252): truncated value with size 32 to match size of target (5) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 252
Warning (10230): Verilog HDL assignment warning at cpu.sv(281): truncated value with size 32 to match size of target (16) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 281
Warning (10230): Verilog HDL assignment warning at cpu.sv(285): truncated value with size 32 to match size of target (5) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 285
Warning (10230): Verilog HDL assignment warning at cpu.sv(296): truncated value with size 32 to match size of target (5) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 296
Warning (10230): Verilog HDL assignment warning at cpu.sv(323): truncated value with size 32 to match size of target (16) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 323
Warning (10230): Verilog HDL assignment warning at cpu.sv(333): truncated value with size 32 to match size of target (16) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 333
Warning (10030): Net "instr.src_reg" at cpu.sv(131) has no driver or initial value, using a default initial value '0' File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 131
Warning (10030): Net "instr.src_addr" at cpu.sv(131) has no driver or initial value, using a default initial value '0' File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 131
Warning (10030): Net "instr.dst_addr" at cpu.sv(131) has no driver or initial value, using a default initial value '0' File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 131
Info (12128): Elaborating entity "alu" for hierarchy "cpu:cpu|alu:alu" File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 33
Info (12128): Elaborating entity "st7920_serial_driver" for hierarchy "cpu:cpu|st7920_serial_driver:gpu" File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 49
Warning (10036): Verilog HDL or VHDL warning at st7920_serial_driver.sv(23): object "line_idx" assigned a value but never read File: /home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv Line: 23
Warning (10230): Verilog HDL assignment warning at st7920_serial_driver.sv(71): truncated value with size 32 to match size of target (7) File: /home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv Line: 71
Warning (10230): Verilog HDL assignment warning at st7920_serial_driver.sv(84): truncated value with size 32 to match size of target (7) File: /home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv Line: 84
@ -629,22 +666,30 @@ Info (12133): Instantiated megafunction "memory:mem|altsyncram:mem_rtl_0" with t
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_dsq1.tdf
Info (12023): Found entity 1: altsyncram_dsq1 File: /home/nickorlow/programming/school/warminster/yayacemu/db/altsyncram_dsq1.tdf Line: 28
Warning (13024): Output pins are stuck at VCC or GND
Warning (13410): Pin "led[5]" is stuck at VCC File: /home/nickorlow/programming/school/warminster/yayacemu/chip8.sv Line: 7
Warning (13410): Pin "led[4]" is stuck at GND File: /home/nickorlow/programming/school/warminster/yayacemu/chip8.sv Line: 7
Warning (13410): Pin "led[5]" is stuck at GND File: /home/nickorlow/programming/school/warminster/yayacemu/chip8.sv Line: 7
Info (286030): Timing-Driven Synthesis is running
Info (17049): 4 registers lost all their fanouts during netlist optimizations.
Info (17049): 6 registers lost all their fanouts during netlist optimizations.
Info (144001): Generated suppressed messages file /home/nickorlow/programming/school/warminster/yayacemu/output_files/chip8.map.smsg
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
Warning (21074): Design contains 1 input pin(s) that do not drive logic
Warning (15610): No output dependent on input pin "rst_in" File: /home/nickorlow/programming/school/warminster/yayacemu/chip8.sv Line: 3
Info (21057): Implemented 17374 device resources after synthesis - the final resource count might be different
Info (21057): Implemented 17552 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 2 input pins
Info (21059): Implemented 8 output pins
Info (21061): Implemented 17356 logic cells
Info (21061): Implemented 17534 logic cells
Info (21064): Implemented 8 RAM segments
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 26 warnings
Info: Peak virtual memory: 698 megabytes
Info: Processing ended: Sun Apr 7 23:45:53 2024
Info: Elapsed time: 00:01:02
Info: Total CPU time (on all processors): 00:01:46
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 29 warnings
Info: Peak virtual memory: 775 megabytes
Info: Processing ended: Mon Apr 8 08:47:47 2024
Info: Elapsed time: 00:00:56
Info: Total CPU time (on all processors): 00:01:34
+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in /home/nickorlow/programming/school/warminster/yayacemu/output_files/chip8.map.smsg.

4
output_files/chip8.map.summary
View file

@ -1,10 +1,10 @@
Analysis & Synthesis Status : Successful - Sun Apr 7 23:45:53 2024
Analysis & Synthesis Status : Successful - Mon Apr 8 08:47:47 2024
Quartus Prime Version : 23.1std.0 Build 991 11/28/2023 SC Lite Edition
Revision Name : chip8
Top-level Entity Name : chip8
Family : Cyclone V
Logic utilization (in ALMs) : N/A
Total registers : 8728
Total registers : 8836
Total pins : 10
Total virtual pins : 0
Total block memory bits : 32,768

BIN
output_files/chip8.sof
View file

Binary file not shown.

235
output_files/chip8.sta.rpt
View file

@ -1,5 +1,5 @@
Timing Analyzer report for chip8
Sun Apr 7 23:52:43 2024
Mon Apr 8 08:52:45 2024
Quartus Prime Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition
@ -98,22 +98,22 @@ https://fpgasoftware.intel.com/eula.
; Number detected on machine ; 12 ;
; Maximum allowed ; 12 ;
; ; ;
; Average used ; 5.73 ;
; Average used ; 5.48 ;
; Maximum used ; 12 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
; Processor 2 ; 60.4% ;
; Processor 3 ; 57.0% ;
; Processor 4 ; 55.9% ;
; Processor 5 ; 37.5% ;
; Processor 6 ; 37.5% ;
; Processor 7 ; 37.5% ;
; Processor 8 ; 37.5% ;
; Processor 9 ; 37.5% ;
; Processor 10 ; 37.5% ;
; Processor 11 ; 37.5% ;
; Processor 12 ; 37.5% ;
; Processor 2 ; 56.2% ;
; Processor 3 ; 54.6% ;
; Processor 4 ; 54.0% ;
; Processor 5 ; 35.4% ;
; Processor 6 ; 35.4% ;
; Processor 7 ; 35.4% ;
; Processor 8 ; 35.4% ;
; Processor 9 ; 35.4% ;
; Processor 10 ; 35.4% ;
; Processor 11 ; 35.4% ;
; Processor 12 ; 35.4% ;
+----------------------------+-------------+
@ -123,18 +123,20 @@ https://fpgasoftware.intel.com/eula.
; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
+------------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------------------------------------------+
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { cpu:cpu|st7920_serial_driver:gpu|lcd_clk } ;
; downclocker:dc|clk_out ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { downclocker:dc|clk_out } ;
; fpga_clk ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { fpga_clk } ;
+------------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------------------------------------------+
+-------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1100mV 100C Model Fmax Summary ;
+-----------+-----------------+------------------------------------------+------+
+------------+-----------------+------------------------------------------+------+
; Fmax ; Restricted Fmax ; Clock Name ; Note ;
+-----------+-----------------+------------------------------------------+------+
; 34.01 MHz ; 34.01 MHz ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; ;
; 82.06 MHz ; 82.06 MHz ; fpga_clk ; ;
+-----------+-----------------+------------------------------------------+------+
+------------+-----------------+------------------------------------------+------+
; 31.39 MHz ; 31.39 MHz ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; ;
; 82.93 MHz ; 82.93 MHz ; downclocker:dc|clk_out ; ;
; 189.18 MHz ; 189.18 MHz ; fpga_clk ; ;
+------------+-----------------+------------------------------------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
@ -149,8 +151,9 @@ HTML report is unavailable in plain text report export.
+------------------------------------------+---------+---------------+
; Clock ; Slack ; End Point TNS ;
+------------------------------------------+---------+---------------+
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -28.406 ; -1742.530 ;
; fpga_clk ; -11.186 ; -95769.392 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -31.412 ; -1884.356 ;
; downclocker:dc|clk_out ; -11.058 ; -87363.415 ;
; fpga_clk ; -4.953 ; -27.713 ;
+------------------------------------------+---------+---------------+
@ -159,8 +162,9 @@ HTML report is unavailable in plain text report export.
+------------------------------------------+-------+---------------+
; Clock ; Slack ; End Point TNS ;
+------------------------------------------+-------+---------------+
; fpga_clk ; 0.429 ; 0.000 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 0.476 ; 0.000 ;
; downclocker:dc|clk_out ; 0.429 ; 0.000 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 0.501 ; 0.000 ;
; fpga_clk ; 0.814 ; 0.000 ;
+------------------------------------------+-------+---------------+
@ -181,8 +185,9 @@ No paths to report.
+------------------------------------------+--------+---------------+
; Clock ; Slack ; End Point TNS ;
+------------------------------------------+--------+---------------+
; fpga_clk ; -2.636 ; -8463.323 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -0.538 ; -185.389 ;
; downclocker:dc|clk_out ; -2.636 ; -8430.055 ;
; fpga_clk ; -0.622 ; -17.105 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -0.538 ; -172.550 ;
+------------------------------------------+--------+---------------+
@ -193,14 +198,15 @@ Design MTBF is not calculated because the design doesn't meet its timing require
+-------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1100mV -40C Model Fmax Summary ;
+-----------+-----------------+------------------------------------------+------+
+------------+-----------------+------------------------------------------+------+
; Fmax ; Restricted Fmax ; Clock Name ; Note ;
+-----------+-----------------+------------------------------------------+------+
; 35.8 MHz ; 35.8 MHz ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; ;
; 81.78 MHz ; 81.78 MHz ; fpga_clk ; ;
+-----------+-----------------+------------------------------------------+------+
+------------+-----------------+------------------------------------------+------+
; 33.23 MHz ; 33.23 MHz ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; ;
; 82.94 MHz ; 82.94 MHz ; downclocker:dc|clk_out ; ;
; 185.36 MHz ; 185.36 MHz ; fpga_clk ; ;
+------------+-----------------+------------------------------------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
@ -209,8 +215,9 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
+------------------------------------------+---------+---------------+
; Clock ; Slack ; End Point TNS ;
+------------------------------------------+---------+---------------+
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -26.933 ; -1684.576 ;
; fpga_clk ; -11.228 ; -94100.779 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -29.494 ; -1798.010 ;
; downclocker:dc|clk_out ; -11.057 ; -87142.095 ;
; fpga_clk ; -4.658 ; -29.299 ;
+------------------------------------------+---------+---------------+
@ -219,8 +226,9 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
+------------------------------------------+-------+---------------+
; Clock ; Slack ; End Point TNS ;
+------------------------------------------+-------+---------------+
; fpga_clk ; 0.484 ; 0.000 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 0.565 ; 0.000 ;
; downclocker:dc|clk_out ; 0.483 ; 0.000 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 0.546 ; 0.000 ;
; fpga_clk ; 0.786 ; 0.000 ;
+------------------------------------------+-------+---------------+
@ -241,8 +249,9 @@ No paths to report.
+------------------------------------------+--------+---------------+
; Clock ; Slack ; End Point TNS ;
+------------------------------------------+--------+---------------+
; fpga_clk ; -2.636 ; -8927.522 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -0.538 ; -184.012 ;
; downclocker:dc|clk_out ; -2.636 ; -8301.987 ;
; fpga_clk ; -0.627 ; -18.184 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -0.538 ; -170.070 ;
+------------------------------------------+--------+---------------+
@ -258,8 +267,9 @@ Design MTBF is not calculated because the design doesn't meet its timing require
+------------------------------------------+---------+---------------+
; Clock ; Slack ; End Point TNS ;
+------------------------------------------+---------+---------------+
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -14.774 ; -901.498 ;
; fpga_clk ; -6.214 ; -50560.530 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -16.301 ; -1018.017 ;
; downclocker:dc|clk_out ; -5.608 ; -44394.911 ;
; fpga_clk ; -3.718 ; -8.178 ;
+------------------------------------------+---------+---------------+
@ -268,8 +278,9 @@ Design MTBF is not calculated because the design doesn't meet its timing require
+------------------------------------------+-------+---------------+
; Clock ; Slack ; End Point TNS ;
+------------------------------------------+-------+---------------+
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 0.162 ; 0.000 ;
; fpga_clk ; 0.177 ; 0.000 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 0.160 ; 0.000 ;
; downclocker:dc|clk_out ; 0.177 ; 0.000 ;
; fpga_clk ; 0.303 ; 0.000 ;
+------------------------------------------+-------+---------------+
@ -290,8 +301,9 @@ No paths to report.
+------------------------------------------+--------+---------------+
; Clock ; Slack ; End Point TNS ;
+------------------------------------------+--------+---------------+
; fpga_clk ; -2.174 ; -1371.543 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -0.192 ; -9.702 ;
; downclocker:dc|clk_out ; -2.174 ; -537.344 ;
; fpga_clk ; -0.517 ; -2.901 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -0.144 ; -6.507 ;
+------------------------------------------+--------+---------------+
@ -307,8 +319,9 @@ Design MTBF is not calculated because the design doesn't meet its timing require
+------------------------------------------+---------+---------------+
; Clock ; Slack ; End Point TNS ;
+------------------------------------------+---------+---------------+
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -12.462 ; -739.747 ;
; fpga_clk ; -4.930 ; -40871.978 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -14.004 ; -820.600 ;
; downclocker:dc|clk_out ; -4.541 ; -36337.093 ;
; fpga_clk ; -2.859 ; -5.427 ;
+------------------------------------------+---------+---------------+
@ -317,8 +330,9 @@ Design MTBF is not calculated because the design doesn't meet its timing require
+------------------------------------------+-------+---------------+
; Clock ; Slack ; End Point TNS ;
+------------------------------------------+-------+---------------+
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 0.140 ; 0.000 ;
; fpga_clk ; 0.164 ; 0.000 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 0.138 ; 0.000 ;
; downclocker:dc|clk_out ; 0.164 ; 0.000 ;
; fpga_clk ; 0.289 ; 0.000 ;
+------------------------------------------+-------+---------------+
@ -339,8 +353,9 @@ No paths to report.
+------------------------------------------+--------+---------------+
; Clock ; Slack ; End Point TNS ;
+------------------------------------------+--------+---------------+
; fpga_clk ; -2.174 ; -1373.239 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -0.137 ; -3.355 ;
; downclocker:dc|clk_out ; -2.174 ; -534.258 ;
; fpga_clk ; -0.533 ; -2.899 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -0.057 ; -2.411 ;
+------------------------------------------+--------+---------------+
@ -356,12 +371,14 @@ Design MTBF is not calculated because the design doesn't meet its timing require
+-------------------------------------------+------------+-------+----------+---------+---------------------+
; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
+-------------------------------------------+------------+-------+----------+---------+---------------------+
; Worst-case Slack ; -28.406 ; 0.140 ; N/A ; N/A ; -2.636 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -28.406 ; 0.140 ; N/A ; N/A ; -0.538 ;
; fpga_clk ; -11.228 ; 0.164 ; N/A ; N/A ; -2.636 ;
; Design-wide TNS ; -97511.922 ; 0.0 ; 0.0 ; 0.0 ; -9111.534 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -1742.530 ; 0.000 ; N/A ; N/A ; -185.389 ;
; fpga_clk ; -95769.392 ; 0.000 ; N/A ; N/A ; -8927.522 ;
; Worst-case Slack ; -31.412 ; 0.138 ; N/A ; N/A ; -2.636 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -31.412 ; 0.138 ; N/A ; N/A ; -0.538 ;
; downclocker:dc|clk_out ; -11.058 ; 0.164 ; N/A ; N/A ; -2.636 ;
; fpga_clk ; -4.953 ; 0.289 ; N/A ; N/A ; -0.627 ;
; Design-wide TNS ; -89275.484 ; 0.0 ; 0.0 ; 0.0 ; -8619.71 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -1884.356 ; 0.000 ; N/A ; N/A ; -172.550 ;
; downclocker:dc|clk_out ; -87363.415 ; 0.000 ; N/A ; N/A ; -8430.055 ;
; fpga_clk ; -29.299 ; 0.000 ; N/A ; N/A ; -18.184 ;
+-------------------------------------------+------------+-------+----------+---------+---------------------+
@ -460,10 +477,12 @@ Design MTBF is not calculated because the design doesn't meet its timing require
+------------------------------------------+------------------------------------------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------------------------------------+------------------------------------------+----------+----------+----------+----------+
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 2667 ; 137 ; 0 ; 1681347 ;
; fpga_clk ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 0 ; 0 ; 9878 ; 0 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 2393 ; 126 ; 0 ; 1681819 ;
; downclocker:dc|clk_out ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 0 ; 0 ; 9878 ; 0 ;
; downclocker:dc|clk_out ; downclocker:dc|clk_out ; 13182899 ; 148 ; 48 ; 0 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; fpga_clk ; 1 ; 1 ; 0 ; 0 ;
; fpga_clk ; fpga_clk ; 12902566 ; 152 ; 48 ; 0 ;
; downclocker:dc|clk_out ; fpga_clk ; 1 ; 1 ; 0 ; 0 ;
; fpga_clk ; fpga_clk ; 121 ; 0 ; 0 ; 0 ;
+------------------------------------------+------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
@ -473,10 +492,12 @@ Entries labeled "false path" only account for clock-to-clock false paths and not
+------------------------------------------+------------------------------------------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------------------------------------+------------------------------------------+----------+----------+----------+----------+
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 2667 ; 137 ; 0 ; 1681347 ;
; fpga_clk ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 0 ; 0 ; 9878 ; 0 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 2393 ; 126 ; 0 ; 1681819 ;
; downclocker:dc|clk_out ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 0 ; 0 ; 9878 ; 0 ;
; downclocker:dc|clk_out ; downclocker:dc|clk_out ; 13182899 ; 148 ; 48 ; 0 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; fpga_clk ; 1 ; 1 ; 0 ; 0 ;
; fpga_clk ; fpga_clk ; 12902566 ; 152 ; 48 ; 0 ;
; downclocker:dc|clk_out ; fpga_clk ; 1 ; 1 ; 0 ; 0 ;
; fpga_clk ; fpga_clk ; 121 ; 0 ; 0 ; 0 ;
+------------------------------------------+------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
@ -502,8 +523,8 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
; Unconstrained Clocks ; 0 ; 0 ;
; Unconstrained Input Ports ; 0 ; 0 ;
; Unconstrained Input Port Paths ; 0 ; 0 ;
; Unconstrained Output Ports ; 7 ; 7 ;
; Unconstrained Output Port Paths ; 7 ; 7 ;
; Unconstrained Output Ports ; 6 ; 6 ;
; Unconstrained Output Port Paths ; 6 ; 6 ;
+---------------------------------+-------+------+
@ -513,6 +534,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
; Target ; Clock ; Type ; Status ;
+------------------------------------------+------------------------------------------+------+-------------+
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; Base ; Constrained ;
; downclocker:dc|clk_out ; downclocker:dc|clk_out ; Base ; Constrained ;
; fpga_clk ; fpga_clk ; Base ; Constrained ;
+------------------------------------------+------------------------------------------+------+-------------+
@ -528,7 +550,6 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
; led[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; led[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; led[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; led[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+-------------+---------------------------------------------------------------------------------------+
@ -543,7 +564,6 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
; led[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; led[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; led[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; led[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+-------------+---------------------------------------------------------------------------------------+
@ -553,7 +573,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
Info: *******************************************************************
Info: Running Quartus Prime Timing Analyzer
Info: Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition
Info: Processing started: Sun Apr 7 23:52:18 2024
Info: Processing started: Mon Apr 8 08:52:26 2024
Info: Command: quartus_sta chip8 -c chip8
Info: qsta_default_script.tcl version: #1
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
@ -565,29 +585,33 @@ Info (332142): No user constrained base clocks found in the design. Calling "der
Info (332105): Deriving Clocks
Info (332105): create_clock -period 1.000 -name fpga_clk fpga_clk
Info (332105): create_clock -period 1.000 -name cpu:cpu|st7920_serial_driver:gpu|lcd_clk cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332105): create_clock -period 1.000 -name downclocker:dc|clk_out downclocker:dc|clk_out
Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Analyzing Slow 1100mV 100C Model
Critical Warning (332148): Timing requirements not met
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer.
Info (332146): Worst-case setup slack is -28.406
Info (332146): Worst-case setup slack is -31.412
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -28.406 -1742.530 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332119): -11.186 -95769.392 fpga_clk
Info (332119): -31.412 -1884.356 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332119): -11.058 -87363.415 downclocker:dc|clk_out
Info (332119): -4.953 -27.713 fpga_clk
Info (332146): Worst-case hold slack is 0.429
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 0.429 0.000 fpga_clk
Info (332119): 0.476 0.000 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332119): 0.429 0.000 downclocker:dc|clk_out
Info (332119): 0.501 0.000 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332119): 0.814 0.000 fpga_clk
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is -2.636
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -2.636 -8463.323 fpga_clk
Info (332119): -0.538 -185.389 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332119): -2.636 -8430.055 downclocker:dc|clk_out
Info (332119): -0.622 -17.105 fpga_clk
Info (332119): -0.538 -172.550 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332114): Report Metastability: Found 8 synchronizer chains.
Info (332114): Design MTBF is not calculated because the design doesn't meet its timing requirements.
Info: Analyzing Slow 1100mV -40C Model
@ -596,23 +620,26 @@ Info (334004): Delay annotation completed successfully
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer.
Info (332146): Worst-case setup slack is -26.933
Info (332146): Worst-case setup slack is -29.494
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -26.933 -1684.576 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332119): -11.228 -94100.779 fpga_clk
Info (332146): Worst-case hold slack is 0.484
Info (332119): -29.494 -1798.010 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332119): -11.057 -87142.095 downclocker:dc|clk_out
Info (332119): -4.658 -29.299 fpga_clk
Info (332146): Worst-case hold slack is 0.483
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 0.484 0.000 fpga_clk
Info (332119): 0.565 0.000 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332119): 0.483 0.000 downclocker:dc|clk_out
Info (332119): 0.546 0.000 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332119): 0.786 0.000 fpga_clk
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is -2.636
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -2.636 -8927.522 fpga_clk
Info (332119): -0.538 -184.012 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332119): -2.636 -8301.987 downclocker:dc|clk_out
Info (332119): -0.627 -18.184 fpga_clk
Info (332119): -0.538 -170.070 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332114): Report Metastability: Found 8 synchronizer chains.
Info (332114): Design MTBF is not calculated because the design doesn't meet its timing requirements.
Info: Analyzing Fast 1100mV 100C Model
@ -621,54 +648,60 @@ Info (334004): Delay annotation completed successfully
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer.
Info (332146): Worst-case setup slack is -14.774
Info (332146): Worst-case setup slack is -16.301
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -14.774 -901.498 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332119): -6.214 -50560.530 fpga_clk
Info (332146): Worst-case hold slack is 0.162
Info (332119): -16.301 -1018.017 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332119): -5.608 -44394.911 downclocker:dc|clk_out
Info (332119): -3.718 -8.178 fpga_clk
Info (332146): Worst-case hold slack is 0.160
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 0.162 0.000 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332119): 0.177 0.000 fpga_clk
Info (332119): 0.160 0.000 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332119): 0.177 0.000 downclocker:dc|clk_out
Info (332119): 0.303 0.000 fpga_clk
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is -2.174
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -2.174 -1371.543 fpga_clk
Info (332119): -0.192 -9.702 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332119): -2.174 -537.344 downclocker:dc|clk_out
Info (332119): -0.517 -2.901 fpga_clk
Info (332119): -0.144 -6.507 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332114): Report Metastability: Found 8 synchronizer chains.
Info (332114): Design MTBF is not calculated because the design doesn't meet its timing requirements.
Info: Analyzing Fast 1100mV -40C Model
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer.
Info (332146): Worst-case setup slack is -12.462
Info (332146): Worst-case setup slack is -14.004
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -12.462 -739.747 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332119): -4.930 -40871.978 fpga_clk
Info (332146): Worst-case hold slack is 0.140
Info (332119): -14.004 -820.600 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332119): -4.541 -36337.093 downclocker:dc|clk_out
Info (332119): -2.859 -5.427 fpga_clk
Info (332146): Worst-case hold slack is 0.138
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 0.140 0.000 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332119): 0.164 0.000 fpga_clk
Info (332119): 0.138 0.000 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332119): 0.164 0.000 downclocker:dc|clk_out
Info (332119): 0.289 0.000 fpga_clk
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is -2.174
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -2.174 -1373.239 fpga_clk
Info (332119): -0.137 -3.355 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332119): -2.174 -534.258 downclocker:dc|clk_out
Info (332119): -0.533 -2.899 fpga_clk
Info (332119): -0.057 -2.411 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332114): Report Metastability: Found 8 synchronizer chains.
Info (332114): Design MTBF is not calculated because the design doesn't meet its timing requirements.
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings
Info: Peak virtual memory: 1353 megabytes
Info: Processing ended: Sun Apr 7 23:52:43 2024
Info: Elapsed time: 00:00:25
Info: Total CPU time (on all processors): 00:01:44
Info: Peak virtual memory: 1312 megabytes
Info: Processing ended: Mon Apr 8 08:52:45 2024
Info: Elapsed time: 00:00:19
Info: Total CPU time (on all processors): 00:01:25

144
output_files/chip8.sta.summary
View file

@ -3,99 +3,147 @@ Timing Analyzer Summary
------------------------------------------------------------
Type : Slow 1100mV 100C Model Setup 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk'
Slack : -28.406
TNS : -1742.530
Slack : -31.412
TNS : -1884.356
Type : Slow 1100mV 100C Model Setup 'downclocker:dc|clk_out'
Slack : -11.058
TNS : -87363.415
Type : Slow 1100mV 100C Model Setup 'fpga_clk'
Slack : -11.186
TNS : -95769.392
Slack : -4.953
TNS : -27.713
Type : Slow 1100mV 100C Model Hold 'fpga_clk'
Type : Slow 1100mV 100C Model Hold 'downclocker:dc|clk_out'
Slack : 0.429
TNS : 0.000
Type : Slow 1100mV 100C Model Hold 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk'
Slack : 0.476
Slack : 0.501
TNS : 0.000
Type : Slow 1100mV 100C Model Minimum Pulse Width 'fpga_clk'
Type : Slow 1100mV 100C Model Hold 'fpga_clk'
Slack : 0.814
TNS : 0.000
Type : Slow 1100mV 100C Model Minimum Pulse Width 'downclocker:dc|clk_out'
Slack : -2.636
TNS : -8463.323
TNS : -8430.055
Type : Slow 1100mV 100C Model Minimum Pulse Width 'fpga_clk'
Slack : -0.622
TNS : -17.105
Type : Slow 1100mV 100C Model Minimum Pulse Width 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk'
Slack : -0.538
TNS : -185.389
TNS : -172.550
Type : Slow 1100mV -40C Model Setup 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk'
Slack : -26.933
TNS : -1684.576
Slack : -29.494
TNS : -1798.010
Type : Slow 1100mV -40C Model Setup 'downclocker:dc|clk_out'
Slack : -11.057
TNS : -87142.095
Type : Slow 1100mV -40C Model Setup 'fpga_clk'
Slack : -11.228
TNS : -94100.779
Slack : -4.658
TNS : -29.299
Type : Slow 1100mV -40C Model Hold 'fpga_clk'
Slack : 0.484
Type : Slow 1100mV -40C Model Hold 'downclocker:dc|clk_out'
Slack : 0.483
TNS : 0.000
Type : Slow 1100mV -40C Model Hold 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk'
Slack : 0.565
Slack : 0.546
TNS : 0.000
Type : Slow 1100mV -40C Model Minimum Pulse Width 'fpga_clk'
Type : Slow 1100mV -40C Model Hold 'fpga_clk'
Slack : 0.786
TNS : 0.000
Type : Slow 1100mV -40C Model Minimum Pulse Width 'downclocker:dc|clk_out'
Slack : -2.636
TNS : -8927.522
TNS : -8301.987
Type : Slow 1100mV -40C Model Minimum Pulse Width 'fpga_clk'
Slack : -0.627
TNS : -18.184
Type : Slow 1100mV -40C Model Minimum Pulse Width 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk'
Slack : -0.538
TNS : -184.012
TNS : -170.070
Type : Fast 1100mV 100C Model Setup 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk'
Slack : -14.774
TNS : -901.498
Slack : -16.301
TNS : -1018.017
Type : Fast 1100mV 100C Model Setup 'downclocker:dc|clk_out'
Slack : -5.608
TNS : -44394.911
Type : Fast 1100mV 100C Model Setup 'fpga_clk'
Slack : -6.214
TNS : -50560.530
Slack : -3.718
TNS : -8.178
Type : Fast 1100mV 100C Model Hold 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk'
Slack : 0.162
Slack : 0.160
TNS : 0.000
Type : Fast 1100mV 100C Model Hold 'fpga_clk'
Type : Fast 1100mV 100C Model Hold 'downclocker:dc|clk_out'
Slack : 0.177
TNS : 0.000
Type : Fast 1100mV 100C Model Minimum Pulse Width 'fpga_clk'
Slack : -2.174
TNS : -1371.543
Type : Fast 1100mV 100C Model Minimum Pulse Width 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk'
Slack : -0.192
TNS : -9.702
Type : Fast 1100mV -40C Model Setup 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk'
Slack : -12.462
TNS : -739.747
Type : Fast 1100mV -40C Model Setup 'fpga_clk'
Slack : -4.930
TNS : -40871.978
Type : Fast 1100mV -40C Model Hold 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk'
Slack : 0.140
Type : Fast 1100mV 100C Model Hold 'fpga_clk'
Slack : 0.303
TNS : 0.000
Type : Fast 1100mV -40C Model Hold 'fpga_clk'
Type : Fast 1100mV 100C Model Minimum Pulse Width 'downclocker:dc|clk_out'
Slack : -2.174
TNS : -537.344
Type : Fast 1100mV 100C Model Minimum Pulse Width 'fpga_clk'
Slack : -0.517
TNS : -2.901
Type : Fast 1100mV 100C Model Minimum Pulse Width 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk'
Slack : -0.144
TNS : -6.507
Type : Fast 1100mV -40C Model Setup 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk'
Slack : -14.004
TNS : -820.600
Type : Fast 1100mV -40C Model Setup 'downclocker:dc|clk_out'
Slack : -4.541
TNS : -36337.093
Type : Fast 1100mV -40C Model Setup 'fpga_clk'
Slack : -2.859
TNS : -5.427
Type : Fast 1100mV -40C Model Hold 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk'
Slack : 0.138
TNS : 0.000
Type : Fast 1100mV -40C Model Hold 'downclocker:dc|clk_out'
Slack : 0.164
TNS : 0.000
Type : Fast 1100mV -40C Model Minimum Pulse Width 'fpga_clk'
Type : Fast 1100mV -40C Model Hold 'fpga_clk'
Slack : 0.289
TNS : 0.000
Type : Fast 1100mV -40C Model Minimum Pulse Width 'downclocker:dc|clk_out'
Slack : -2.174
TNS : -1373.239
TNS : -534.258
Type : Fast 1100mV -40C Model Minimum Pulse Width 'fpga_clk'
Slack : -0.533
TNS : -2.899
Type : Fast 1100mV -40C Model Minimum Pulse Width 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk'
Slack : -0.137
TNS : -3.355
Slack : -0.057
TNS : -2.411
------------------------------------------------------------