48 lines
853 B
Systemverilog
48 lines
853 B
Systemverilog
module chip8 (
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input wire fpga_clk,
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input wire rst_in,
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output logic lcd_clk,
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output logic lcd_data,
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output logic [5:0] led
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);
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logic slow_clk;
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`ifdef FAST_CLK
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assign slow_clk = fpga_clk;
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`endif
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`ifndef FAST_CLK
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downclocker #(10) dc(fpga_clk, slow_clk);
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`endif
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logic [7:0] rd_memory_data;
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logic [11:0] rd_memory_address;
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logic [11:0] wr_memory_address;
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logic [7:0] wr_memory_data;
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logic wr_go;
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memory #(4096) mem (
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slow_clk,
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wr_go,
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wr_memory_address,
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wr_memory_data,
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rd_memory_address,
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rd_memory_data
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);
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int cycle_counter;
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cpu cpu (
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slow_clk,
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fpga_clk,
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rd_memory_data,
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cycle_counter,
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rd_memory_address,
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wr_memory_address,
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wr_memory_data,
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wr_go,
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lcd_clk,
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lcd_data,
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led
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);
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endmodule
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