diff --git a/aastructs.sv b/aastructs.sv index 9f6b459..d45aee1 100644 --- a/aastructs.sv +++ b/aastructs.sv @@ -2,7 +2,7 @@ package structs; typedef enum {ADD} alu_op; - typedef struct { + typedef struct packed { logic [7:0] operand_a; logic [7:0] operand_b; alu_op op; diff --git a/alu.sv b/alu.sv index 26d4c0f..99fcbaf 100644 --- a/alu.sv +++ b/alu.sv @@ -33,7 +33,7 @@ module alu( result_int <= in.operand_a + in.operand_b; result <= result_int[7:0]; overflow <= result_int[8]; - if (cnt == 2) begin + if (cnt >= 2) begin $display("%b %b + %b %b ya", result, in.operand_a, in.operand_b, result_int); done <= 1; end diff --git a/chip8.qsf b/chip8.qsf index 420d270..0184d35 100644 --- a/chip8.qsf +++ b/chip8.qsf @@ -31,6 +31,9 @@ set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name SYSTEMVERILOG_FILE "./the-bomb/st7920_serial_driver.sv" set_global_assignment -name SYSTEMVERILOG_FILE chip8.sv set_global_assignment -name SYSTEMVERILOG_FILE cpu.sv +set_global_assignment -name SYSTEMVERILOG_FILE alu.sv +set_global_assignment -name SYSTEMVERILOG_FILE aastructs.sv +set_global_assignment -name SYSTEMVERILOG_FILE downclocker.sv set_global_assignment -name SDC_FILE chip8.sdc set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" @@ -61,4 +64,4 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to lcd_data set_location_assignment PIN_W20 -to rst_in -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top diff --git a/chip8.sv b/chip8.sv index 5fce684..ea337a2 100644 --- a/chip8.sv +++ b/chip8.sv @@ -5,6 +5,14 @@ module chip8 ( output logic lcd_data, output logic [5:0] led ); +logic slow_clk; +`ifdef FAST_CLK + assign slow_clk = fpga_clk; +`endif + +`ifndef FAST_CLK + downclocker #(10) dc(fpga_clk, slow_clk); +`endif logic [7:0] rd_memory_data; logic [11:0] rd_memory_address; @@ -12,7 +20,7 @@ module chip8 ( logic [7:0] wr_memory_data; logic wr_go; memory #(4096) mem ( - fpga_clk, + slow_clk, wr_go, wr_memory_address, wr_memory_data, @@ -22,6 +30,7 @@ module chip8 ( int cycle_counter; cpu cpu ( + slow_clk, fpga_clk, rd_memory_data, cycle_counter, diff --git a/cpu.sv b/cpu.sv index 859dff4..52f42e3 100644 --- a/cpu.sv +++ b/cpu.sv @@ -2,6 +2,7 @@ import structs::*; module cpu ( input wire clk_in, + input wire fpga_clk, input wire [7:0] rd_memory_data, output int cycle_counter, output logic [11:0] rd_memory_address, @@ -13,12 +14,15 @@ module cpu ( output logic [5:0] led ); +logic [5:0] lcd_led; logic alu_rst; logic [7:0] alu_result; logic alu_overflow; logic alu_done; logic compute_of; + assign led = state[5:0]; + alu alu ( alu_rst, clk_in, @@ -36,12 +40,12 @@ module cpu ( `ifndef DUMMY_GPU st7920_serial_driver gpu( `endif - clk_in, + fpga_clk, 1'b1, vram, lcd_clk, lcd_data, - led + lcd_led ); task write_pixels; @@ -101,7 +105,7 @@ module cpu ( } draw_state; - struct { + struct packed { cpu_opcode op; data_type src; data_type dst; diff --git a/db/.cmp.kpt b/db/.cmp.kpt index 9c21138..a3a4a1c 100644 Binary files a/db/.cmp.kpt and b/db/.cmp.kpt differ diff --git a/db/chip8.(0).cnf.cdb b/db/chip8.(0).cnf.cdb index 8ca0c9d..0b4f397 100644 Binary files a/db/chip8.(0).cnf.cdb and b/db/chip8.(0).cnf.cdb differ diff --git a/db/chip8.(0).cnf.hdb b/db/chip8.(0).cnf.hdb index 3d5bc12..474c52c 100644 Binary files a/db/chip8.(0).cnf.hdb and b/db/chip8.(0).cnf.hdb differ diff --git a/db/chip8.(1).cnf.cdb b/db/chip8.(1).cnf.cdb index 4ebb3d3..bc658cc 100644 Binary files a/db/chip8.(1).cnf.cdb and b/db/chip8.(1).cnf.cdb differ diff --git a/db/chip8.(1).cnf.hdb b/db/chip8.(1).cnf.hdb index b66b72f..728a696 100644 Binary files a/db/chip8.(1).cnf.hdb and b/db/chip8.(1).cnf.hdb differ diff --git a/db/chip8.(2).cnf.cdb b/db/chip8.(2).cnf.cdb index 04498c5..fae202b 100644 Binary files a/db/chip8.(2).cnf.cdb and b/db/chip8.(2).cnf.cdb differ diff --git a/db/chip8.(2).cnf.hdb b/db/chip8.(2).cnf.hdb index bbcc347..ccd65b7 100644 Binary files a/db/chip8.(2).cnf.hdb and b/db/chip8.(2).cnf.hdb differ diff --git a/db/chip8.asm.qmsg b/db/chip8.asm.qmsg index dbf09a5..dbc681b 100644 --- a/db/chip8.asm.qmsg +++ b/db/chip8.asm.qmsg @@ -1,6 +1,6 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1712551930527 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition " "Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1712551930527 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 7 23:52:10 2024 " "Processing started: Sun Apr 7 23:52:10 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1712551930527 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1712551930527 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off chip8 -c chip8 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off chip8 -c chip8" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1712551930527 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1712551931223 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1712551937283 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "631 " "Peak virtual memory: 631 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1712551937598 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 7 23:52:17 2024 " "Processing ended: Sun Apr 7 23:52:17 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1712551937598 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1712551937598 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1712551937598 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1712551937598 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1712584339260 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition " "Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1712584339260 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Apr 8 08:52:19 2024 " "Processing started: Mon Apr 8 08:52:19 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1712584339260 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1712584339260 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off chip8 -c chip8 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off chip8 -c chip8" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1712584339260 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1712584340042 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1712584345507 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "628 " "Peak virtual memory: 628 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1712584345784 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 8 08:52:25 2024 " "Processing ended: Mon Apr 8 08:52:25 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1712584345784 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1712584345784 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1712584345784 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1712584345784 ""} diff --git a/db/chip8.asm.rdb b/db/chip8.asm.rdb index 64b8e19..a1f58f6 100644 Binary files a/db/chip8.asm.rdb and b/db/chip8.asm.rdb differ diff --git a/db/chip8.cmp.bpm b/db/chip8.cmp.bpm index 7906c4c..3dfa27c 100644 Binary files a/db/chip8.cmp.bpm and b/db/chip8.cmp.bpm differ diff --git a/db/chip8.cmp.cdb b/db/chip8.cmp.cdb index 631d3a8..dc9bc62 100644 Binary files a/db/chip8.cmp.cdb and b/db/chip8.cmp.cdb differ diff --git a/db/chip8.cmp.hdb b/db/chip8.cmp.hdb index a7c3b6a..5529edf 100644 Binary files a/db/chip8.cmp.hdb and b/db/chip8.cmp.hdb differ diff --git a/db/chip8.cmp.idb b/db/chip8.cmp.idb index b2d2924..7d52da9 100644 Binary files a/db/chip8.cmp.idb and b/db/chip8.cmp.idb differ diff --git a/db/chip8.cmp.rdb b/db/chip8.cmp.rdb index d4dbc3b..1bd08b1 100644 Binary files a/db/chip8.cmp.rdb and b/db/chip8.cmp.rdb differ diff --git a/db/chip8.fit.qmsg b/db/chip8.fit.qmsg index 0066c95..6c85139 100644 --- a/db/chip8.fit.qmsg +++ b/db/chip8.fit.qmsg @@ -1,47 +1,47 @@ -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1712551555206 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "12 12 " "Parallel compilation is enabled and will use 12 of the 12 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1712551555206 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "chip8 5CSEBA6U23I7 " "Selected device 5CSEBA6U23I7 for design \"chip8\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1712551555269 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature -40 degrees C " "Low junction temperature is -40 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1712551555292 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 100 degrees C " "High junction temperature is 100 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1712551555292 ""} -{ "Warning" "WMPP_MPP_RAM_IS_ACTUALLY_ROM_TOP" "" "Found RAM instances implemented as ROM because the write logic is disabled. One instance is listed below as an example." { { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "memory:mem\|altsyncram:mem_rtl_0\|altsyncram_dsq1:auto_generated\|ram_block1a4 " "Atom \"memory:mem\|altsyncram:mem_rtl_0\|altsyncram_dsq1:auto_generated\|ram_block1a4\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Design Software" 0 -1 1712551555358 "|chip8|memory:mem|altsyncram:mem_rtl_0|altsyncram_dsq1:auto_generated|ram_block1a4"} } { } 0 18550 "Found RAM instances implemented as ROM because the write logic is disabled. One instance is listed below as an example." 0 0 "Fitter" 0 -1 1712551555358 ""} -{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1712551555754 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1712551555775 ""} -{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1712551556100 ""} -{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1712551556280 ""} -{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1712551564414 ""} -{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1 (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "fpga_clk~inputCLKENA0 8563 global CLKCTRL_G5 " "fpga_clk~inputCLKENA0 with 8563 fanout uses global clock CLKCTRL_G5" { } { } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1712551564875 ""} } { } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1712551564875 ""} -{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1712551564876 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1712551564962 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1712551564999 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1712551565068 ""} -{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1712551565142 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1712551565142 ""} -{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1712551565178 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "chip8.sdc " "Synopsys Design Constraints File file not found: 'chip8.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1712551566238 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1712551566238 ""} -{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1712551566558 ""} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1712551566558 ""} -{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1712551566563 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1712551568020 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1712551568056 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1712551568056 ""} -{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "lcd_cs " "Node \"lcd_cs\" is assigned to location or region, but does not exist in design" { } { { "/opt/intelFPGA/23.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/opt/intelFPGA/23.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "lcd_cs" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1712551568422 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1712551568422 ""} -{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:13 " "Fitter preparation operations ending: elapsed time is 00:00:13" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1712551568422 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1712551572577 ""} -{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1712551575144 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:52 " "Fitter placement preparation operations ending: elapsed time is 00:00:52" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1712551625159 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1712551662013 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1712551685328 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:24 " "Fitter placement operations ending: elapsed time is 00:00:24" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1712551685328 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1712551687722 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "12 " "Router estimated average interconnect usage is 12% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "57 X22_Y23 X32_Y34 " "Router estimated peak interconnect usage is 57% of the available device resources in the region that extends from location X22_Y23 to location X32_Y34" { } { { "loc" "" { Generic "/home/nickorlow/programming/school/warminster/yayacemu/" { { 1 { 0 "Router estimated peak interconnect usage is 57% of the available device resources in the region that extends from location X22_Y23 to location X32_Y34"} { { 12 { 0 ""} 22 23 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1712551718020 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1712551718020 ""} -{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1712551878467 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1712551878467 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:03:08 " "Fitter routing operations ending: elapsed time is 00:03:08" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1712551878471 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 49.90 " "Total time spent on timing analysis during the Fitter is 49.90 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1712551894479 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1712551894660 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1712551899814 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1712551899828 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1712551905639 ""} -{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:29 " "Fitter post-fit operations ending: elapsed time is 00:00:29" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1712551923094 ""} -{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1712551923931 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/nickorlow/programming/school/warminster/yayacemu/output_files/chip8.fit.smsg " "Generated suppressed messages file /home/nickorlow/programming/school/warminster/yayacemu/output_files/chip8.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1712551925355 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 8 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2797 " "Peak virtual memory: 2797 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1712551929265 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 7 23:52:09 2024 " "Processing ended: Sun Apr 7 23:52:09 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1712551929265 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:06:15 " "Elapsed time: 00:06:15" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1712551929265 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:14:19 " "Total CPU time (on all processors): 00:14:19" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1712551929265 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1712551929265 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1712584068646 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "12 12 " "Parallel compilation is enabled and will use 12 of the 12 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1712584068647 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "chip8 5CSEBA6U23I7 " "Selected device 5CSEBA6U23I7 for design \"chip8\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1712584068695 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature -40 degrees C " "Low junction temperature is -40 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1712584068718 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 100 degrees C " "High junction temperature is 100 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1712584068719 ""} +{ "Warning" "WMPP_MPP_RAM_IS_ACTUALLY_ROM_TOP" "" "Found RAM instances implemented as ROM because the write logic is disabled. One instance is listed below as an example." { { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "memory:mem\|altsyncram:mem_rtl_0\|altsyncram_dsq1:auto_generated\|ram_block1a4 " "Atom \"memory:mem\|altsyncram:mem_rtl_0\|altsyncram_dsq1:auto_generated\|ram_block1a4\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Design Software" 0 -1 1712584068781 "|chip8|memory:mem|altsyncram:mem_rtl_0|altsyncram_dsq1:auto_generated|ram_block1a4"} } { } 0 18550 "Found RAM instances implemented as ROM because the write logic is disabled. One instance is listed below as an example." 0 0 "Fitter" 0 -1 1712584068781 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1712584069129 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1712584069151 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1712584069410 ""} +{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1712584069535 ""} +{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1712584076794 ""} +{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "2 s (2 global) " "Automatically promoted 2 clocks (2 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "downclocker:dc\|clk_out~CLKENA0 8651 global CLKCTRL_G2 " "downclocker:dc\|clk_out~CLKENA0 with 8651 fanout uses global clock CLKCTRL_G2" { { "Info" "ICCLK_UNLOCKED_FOR_VPR" "" "This signal is driven by core routing -- it may be moved during placement to reduce routing delays" { } { } 0 12525 "This signal is driven by core routing -- it may be moved during placement to reduce routing delays" 0 0 "Design Software" 0 -1 1712584077135 ""} } { } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1712584077135 ""} { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "fpga_clk~inputCLKENA0 19 global CLKCTRL_G5 " "fpga_clk~inputCLKENA0 with 19 fanout uses global clock CLKCTRL_G5" { } { } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1712584077135 ""} } { } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1712584077135 ""} +{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1712584077136 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1712584077211 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1712584077246 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1712584077302 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1712584077356 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1712584077356 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1712584077382 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "chip8.sdc " "Synopsys Design Constraints File file not found: 'chip8.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1712584078336 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1712584078336 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1712584078556 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1712584078557 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1712584078562 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1712584079519 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1712584079542 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1712584079542 ""} +{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "lcd_cs " "Node \"lcd_cs\" is assigned to location or region, but does not exist in design" { } { { "/opt/intelFPGA/23.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/opt/intelFPGA/23.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "lcd_cs" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1712584079755 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1712584079755 ""} +{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:10 " "Fitter preparation operations ending: elapsed time is 00:00:10" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1712584079756 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1712584082588 ""} +{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1712584084069 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:39 " "Fitter placement preparation operations ending: elapsed time is 00:00:39" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1712584121786 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1712584149944 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1712584168529 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:19 " "Fitter placement operations ending: elapsed time is 00:00:19" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1712584168529 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1712584170647 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "12 " "Router estimated average interconnect usage is 12% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "58 X22_Y11 X32_Y22 " "Router estimated peak interconnect usage is 58% of the available device resources in the region that extends from location X22_Y11 to location X32_Y22" { } { { "loc" "" { Generic "/home/nickorlow/programming/school/warminster/yayacemu/" { { 1 { 0 "Router estimated peak interconnect usage is 58% of the available device resources in the region that extends from location X22_Y11 to location X32_Y22"} { { 12 { 0 ""} 22 11 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1712584194284 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1712584194284 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1712584298166 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1712584298166 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:02:05 " "Fitter routing operations ending: elapsed time is 00:02:05" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1712584298172 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 36.34 " "Total time spent on timing analysis during the Fitter is 36.34 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1712584310458 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1712584310576 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1712584314203 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1712584314216 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1712584318324 ""} +{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:23 " "Fitter post-fit operations ending: elapsed time is 00:00:23" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1712584333182 ""} +{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1712584333786 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/nickorlow/programming/school/warminster/yayacemu/output_files/chip8.fit.smsg " "Generated suppressed messages file /home/nickorlow/programming/school/warminster/yayacemu/output_files/chip8.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1712584334741 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 8 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2824 " "Peak virtual memory: 2824 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1712584338184 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 8 08:52:18 2024 " "Processing ended: Mon Apr 8 08:52:18 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1712584338184 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:04:30 " "Elapsed time: 00:04:30" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1712584338184 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:11:39 " "Total CPU time (on all processors): 00:11:39" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1712584338184 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1712584338184 ""} diff --git a/db/chip8.hier_info b/db/chip8.hier_info index d816ecb..7c38e41 100644 --- a/db/chip8.hier_info +++ b/db/chip8.hier_info @@ -1,14 +1,29 @@ |chip8 fpga_clk => fpga_clk.IN2 rst_in => ~NO_FANOUT~ -lcd_clk << cpu:cpu.port7 -lcd_data << cpu:cpu.port8 -led[0] << cpu:cpu.port9 -led[1] << cpu:cpu.port9 -led[2] << cpu:cpu.port9 -led[3] << cpu:cpu.port9 -led[4] << cpu:cpu.port9 -led[5] << cpu:cpu.port9 +lcd_clk << cpu:cpu.port8 +lcd_data << cpu:cpu.port9 +led[0] << cpu:cpu.port10 +led[1] << cpu:cpu.port10 +led[2] << cpu:cpu.port10 +led[3] << cpu:cpu.port10 +led[4] << cpu:cpu.port10 +led[5] << cpu:cpu.port10 + + +|chip8|downclocker:dc +clk_in => counter[0].CLK +clk_in => counter[1].CLK +clk_in => counter[2].CLK +clk_in => counter[3].CLK +clk_in => counter[4].CLK +clk_in => counter[5].CLK +clk_in => counter[6].CLK +clk_in => counter[7].CLK +clk_in => counter[8].CLK +clk_in => counter[9].CLK +clk_in => clk_out~reg0.CLK +clk_out <= clk_out~reg0.DB_MAX_OUTPUT_PORT_TYPE |chip8|memory:mem @@ -107,7 +122,7 @@ data_out[7] <= data_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE |chip8|cpu:cpu -clk_in => st7920_serial_driver:gpu.sys_clk +clk_in => alu:alu.clk_in clk_in => cycle_counter[0]~reg0.CLK clk_in => cycle_counter[1]~reg0.CLK clk_in => cycle_counter[2]~reg0.CLK @@ -173,6 +188,7 @@ clk_in => wr_memory_address[8]~reg0.CLK clk_in => wr_memory_address[9]~reg0.CLK clk_in => wr_memory_address[10]~reg0.CLK clk_in => wr_memory_address[11]~reg0.CLK +clk_in => alu_rst.CLK clk_in => vram[1023][0].CLK clk_in => vram[1023][1].CLK clk_in => vram[1023][2].CLK @@ -8535,6 +8551,7 @@ clk_in => draw_state.stage[28].CLK clk_in => draw_state.stage[29].CLK clk_in => draw_state.stage[30].CLK clk_in => draw_state.stage[31].CLK +clk_in => compute_of.CLK clk_in => instr.src_sprite_idx[0].CLK clk_in => instr.src_sprite_idx[1].CLK clk_in => instr.src_sprite_idx[2].CLK @@ -8721,6 +8738,54 @@ clk_in => instr.src_byte[8].CLK clk_in => instr.src_byte[9].CLK clk_in => instr.src_byte[10].CLK clk_in => instr.src_byte[11].CLK +clk_in => instr.alu_i.op[0].CLK +clk_in => instr.alu_i.op[1].CLK +clk_in => instr.alu_i.op[2].CLK +clk_in => instr.alu_i.op[3].CLK +clk_in => instr.alu_i.op[4].CLK +clk_in => instr.alu_i.op[5].CLK +clk_in => instr.alu_i.op[6].CLK +clk_in => instr.alu_i.op[7].CLK +clk_in => instr.alu_i.op[8].CLK +clk_in => instr.alu_i.op[9].CLK +clk_in => instr.alu_i.op[10].CLK +clk_in => instr.alu_i.op[11].CLK +clk_in => instr.alu_i.op[12].CLK +clk_in => instr.alu_i.op[13].CLK +clk_in => instr.alu_i.op[14].CLK +clk_in => instr.alu_i.op[15].CLK +clk_in => instr.alu_i.op[16].CLK +clk_in => instr.alu_i.op[17].CLK +clk_in => instr.alu_i.op[18].CLK +clk_in => instr.alu_i.op[19].CLK +clk_in => instr.alu_i.op[20].CLK +clk_in => instr.alu_i.op[21].CLK +clk_in => instr.alu_i.op[22].CLK +clk_in => instr.alu_i.op[23].CLK +clk_in => instr.alu_i.op[24].CLK +clk_in => instr.alu_i.op[25].CLK +clk_in => instr.alu_i.op[26].CLK +clk_in => instr.alu_i.op[27].CLK +clk_in => instr.alu_i.op[28].CLK +clk_in => instr.alu_i.op[29].CLK +clk_in => instr.alu_i.op[30].CLK +clk_in => instr.alu_i.op[31].CLK +clk_in => instr.alu_i.operand_b[0].CLK +clk_in => instr.alu_i.operand_b[1].CLK +clk_in => instr.alu_i.operand_b[2].CLK +clk_in => instr.alu_i.operand_b[3].CLK +clk_in => instr.alu_i.operand_b[4].CLK +clk_in => instr.alu_i.operand_b[5].CLK +clk_in => instr.alu_i.operand_b[6].CLK +clk_in => instr.alu_i.operand_b[7].CLK +clk_in => instr.alu_i.operand_a[0].CLK +clk_in => instr.alu_i.operand_a[1].CLK +clk_in => instr.alu_i.operand_a[2].CLK +clk_in => instr.alu_i.operand_a[3].CLK +clk_in => instr.alu_i.operand_a[4].CLK +clk_in => instr.alu_i.operand_a[5].CLK +clk_in => instr.alu_i.operand_a[6].CLK +clk_in => instr.alu_i.operand_a[7].CLK clk_in => instr.dst_reg[0].CLK clk_in => instr.dst_reg[1].CLK clk_in => instr.dst_reg[2].CLK @@ -8897,6 +8962,7 @@ clk_in => rd_memory_address[8]~reg0.CLK clk_in => rd_memory_address[9]~reg0.CLK clk_in => rd_memory_address[10]~reg0.CLK clk_in => rd_memory_address[11]~reg0.CLK +fpga_clk => st7920_serial_driver:gpu.sys_clk rd_memory_data[0] => instr.DATAB rd_memory_data[0] => src_sprite.DATAB rd_memory_data[0] => src_sprite.DATAB @@ -8914,7 +8980,7 @@ rd_memory_data[0] => src_sprite.DATAB rd_memory_data[0] => src_sprite.DATAB rd_memory_data[0] => src_sprite.DATAB rd_memory_data[0] => src_sprite.DATAB -rd_memory_data[0] => Selector79.IN4 +rd_memory_data[0] => Selector171.IN4 rd_memory_data[0] => opcode[8].DATAIN rd_memory_data[1] => instr.DATAB rd_memory_data[1] => src_sprite.DATAB @@ -8933,7 +8999,7 @@ rd_memory_data[1] => src_sprite.DATAB rd_memory_data[1] => src_sprite.DATAB rd_memory_data[1] => src_sprite.DATAB rd_memory_data[1] => src_sprite.DATAB -rd_memory_data[1] => Selector78.IN4 +rd_memory_data[1] => Selector170.IN4 rd_memory_data[1] => opcode[9].DATAIN rd_memory_data[2] => instr.DATAB rd_memory_data[2] => src_sprite.DATAB @@ -8952,7 +9018,7 @@ rd_memory_data[2] => src_sprite.DATAB rd_memory_data[2] => src_sprite.DATAB rd_memory_data[2] => src_sprite.DATAB rd_memory_data[2] => src_sprite.DATAB -rd_memory_data[2] => Selector77.IN4 +rd_memory_data[2] => Selector169.IN4 rd_memory_data[2] => opcode[10].DATAIN rd_memory_data[3] => instr.DATAB rd_memory_data[3] => src_sprite.DATAB @@ -8971,7 +9037,7 @@ rd_memory_data[3] => src_sprite.DATAB rd_memory_data[3] => src_sprite.DATAB rd_memory_data[3] => src_sprite.DATAB rd_memory_data[3] => src_sprite.DATAB -rd_memory_data[3] => Selector76.IN4 +rd_memory_data[3] => Selector168.IN4 rd_memory_data[3] => opcode[11].DATAIN rd_memory_data[4] => instr.DATAB rd_memory_data[4] => src_sprite.DATAB @@ -8990,7 +9056,7 @@ rd_memory_data[4] => src_sprite.DATAB rd_memory_data[4] => src_sprite.DATAB rd_memory_data[4] => src_sprite.DATAB rd_memory_data[4] => src_sprite.DATAB -rd_memory_data[4] => Selector75.IN4 +rd_memory_data[4] => Selector167.IN4 rd_memory_data[4] => opcode[12].DATAIN rd_memory_data[5] => instr.DATAB rd_memory_data[5] => src_sprite.DATAB @@ -9009,7 +9075,7 @@ rd_memory_data[5] => src_sprite.DATAB rd_memory_data[5] => src_sprite.DATAB rd_memory_data[5] => src_sprite.DATAB rd_memory_data[5] => src_sprite.DATAB -rd_memory_data[5] => Selector74.IN4 +rd_memory_data[5] => Selector166.IN4 rd_memory_data[5] => opcode[13].DATAIN rd_memory_data[6] => instr.DATAB rd_memory_data[6] => src_sprite.DATAB @@ -9028,7 +9094,7 @@ rd_memory_data[6] => src_sprite.DATAB rd_memory_data[6] => src_sprite.DATAB rd_memory_data[6] => src_sprite.DATAB rd_memory_data[6] => src_sprite.DATAB -rd_memory_data[6] => Selector73.IN4 +rd_memory_data[6] => Selector165.IN4 rd_memory_data[6] => opcode[14].DATAIN rd_memory_data[7] => instr.DATAB rd_memory_data[7] => src_sprite.DATAB @@ -9047,7 +9113,7 @@ rd_memory_data[7] => src_sprite.DATAB rd_memory_data[7] => src_sprite.DATAB rd_memory_data[7] => src_sprite.DATAB rd_memory_data[7] => src_sprite.DATAB -rd_memory_data[7] => Selector72.IN4 +rd_memory_data[7] => Selector164.IN4 rd_memory_data[7] => opcode[15].DATAIN cycle_counter[0] <= cycle_counter[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE cycle_counter[1] <= cycle_counter[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE @@ -9116,12 +9182,157 @@ wr_memory_data[7] <= wr_memory_data[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE wr_go <= wr_go~reg0.DB_MAX_OUTPUT_PORT_TYPE lcd_clk <= st7920_serial_driver:gpu.lcd_clk lcd_data <= st7920_serial_driver:gpu.lcd_data -led[0] <= st7920_serial_driver:gpu.led[0] -led[1] <= st7920_serial_driver:gpu.led[1] -led[2] <= st7920_serial_driver:gpu.led[2] -led[3] <= st7920_serial_driver:gpu.led[3] -led[4] <= st7920_serial_driver:gpu.led[4] -led[5] <= st7920_serial_driver:gpu.led[5] +led[0] <= state[0].DB_MAX_OUTPUT_PORT_TYPE +led[1] <= state[1].DB_MAX_OUTPUT_PORT_TYPE +led[2] <= state[2].DB_MAX_OUTPUT_PORT_TYPE +led[3] <= state[3].DB_MAX_OUTPUT_PORT_TYPE +led[4] <= state[4].DB_MAX_OUTPUT_PORT_TYPE +led[5] <= state[5].DB_MAX_OUTPUT_PORT_TYPE + + +|chip8|cpu:cpu|alu:alu +rst_in => done.OUTPUTSELECT +rst_in => cnt.OUTPUTSELECT +rst_in => cnt.OUTPUTSELECT +rst_in => cnt.OUTPUTSELECT +rst_in => cnt.OUTPUTSELECT +rst_in => cnt.OUTPUTSELECT +rst_in => cnt.OUTPUTSELECT +rst_in => cnt.OUTPUTSELECT +rst_in => cnt.OUTPUTSELECT +rst_in => cnt.OUTPUTSELECT +rst_in => cnt.OUTPUTSELECT +rst_in => cnt.OUTPUTSELECT +rst_in => cnt.OUTPUTSELECT +rst_in => cnt.OUTPUTSELECT +rst_in => cnt.OUTPUTSELECT +rst_in => cnt.OUTPUTSELECT +rst_in => cnt.OUTPUTSELECT +rst_in => cnt.OUTPUTSELECT +rst_in => cnt.OUTPUTSELECT +rst_in => cnt.OUTPUTSELECT +rst_in => cnt.OUTPUTSELECT +rst_in => cnt.OUTPUTSELECT +rst_in => cnt.OUTPUTSELECT +rst_in => cnt.OUTPUTSELECT +rst_in => cnt.OUTPUTSELECT +rst_in => cnt.OUTPUTSELECT +rst_in => cnt.OUTPUTSELECT +rst_in => cnt.OUTPUTSELECT +rst_in => cnt.OUTPUTSELECT +rst_in => cnt.OUTPUTSELECT +rst_in => cnt.OUTPUTSELECT +rst_in => cnt.OUTPUTSELECT +rst_in => cnt.OUTPUTSELECT +clk_in => cnt[0].CLK +clk_in => cnt[1].CLK +clk_in => cnt[2].CLK +clk_in => cnt[3].CLK +clk_in => cnt[4].CLK +clk_in => cnt[5].CLK +clk_in => cnt[6].CLK +clk_in => cnt[7].CLK +clk_in => cnt[8].CLK +clk_in => cnt[9].CLK +clk_in => cnt[10].CLK +clk_in => cnt[11].CLK +clk_in => cnt[12].CLK +clk_in => cnt[13].CLK +clk_in => cnt[14].CLK +clk_in => cnt[15].CLK +clk_in => cnt[16].CLK +clk_in => cnt[17].CLK +clk_in => cnt[18].CLK +clk_in => cnt[19].CLK +clk_in => cnt[20].CLK +clk_in => cnt[21].CLK +clk_in => cnt[22].CLK +clk_in => cnt[23].CLK +clk_in => cnt[24].CLK +clk_in => cnt[25].CLK +clk_in => cnt[26].CLK +clk_in => cnt[27].CLK +clk_in => cnt[28].CLK +clk_in => cnt[29].CLK +clk_in => cnt[30].CLK +clk_in => cnt[31].CLK +clk_in => result_int[0].CLK +clk_in => result_int[1].CLK +clk_in => result_int[2].CLK +clk_in => result_int[3].CLK +clk_in => result_int[4].CLK +clk_in => result_int[5].CLK +clk_in => result_int[6].CLK +clk_in => result_int[7].CLK +clk_in => result_int[8].CLK +clk_in => result[0]~reg0.CLK +clk_in => result[1]~reg0.CLK +clk_in => result[2]~reg0.CLK +clk_in => result[3]~reg0.CLK +clk_in => result[4]~reg0.CLK +clk_in => result[5]~reg0.CLK +clk_in => result[6]~reg0.CLK +clk_in => result[7]~reg0.CLK +clk_in => overflow~reg0.CLK +clk_in => done~reg0.CLK +in.op[0] => ~NO_FANOUT~ +in.op[1] => ~NO_FANOUT~ +in.op[2] => ~NO_FANOUT~ +in.op[3] => ~NO_FANOUT~ +in.op[4] => ~NO_FANOUT~ +in.op[5] => ~NO_FANOUT~ +in.op[6] => ~NO_FANOUT~ +in.op[7] => ~NO_FANOUT~ +in.op[8] => ~NO_FANOUT~ +in.op[9] => ~NO_FANOUT~ +in.op[10] => ~NO_FANOUT~ +in.op[11] => ~NO_FANOUT~ +in.op[12] => ~NO_FANOUT~ +in.op[13] => ~NO_FANOUT~ +in.op[14] => ~NO_FANOUT~ +in.op[15] => ~NO_FANOUT~ +in.op[16] => ~NO_FANOUT~ +in.op[17] => ~NO_FANOUT~ +in.op[18] => ~NO_FANOUT~ +in.op[19] => ~NO_FANOUT~ +in.op[20] => ~NO_FANOUT~ +in.op[21] => ~NO_FANOUT~ +in.op[22] => ~NO_FANOUT~ +in.op[23] => ~NO_FANOUT~ +in.op[24] => ~NO_FANOUT~ +in.op[25] => ~NO_FANOUT~ +in.op[26] => ~NO_FANOUT~ +in.op[27] => ~NO_FANOUT~ +in.op[28] => ~NO_FANOUT~ +in.op[29] => ~NO_FANOUT~ +in.op[30] => ~NO_FANOUT~ +in.op[31] => ~NO_FANOUT~ +in.operand_b[0] => Add0.IN16 +in.operand_b[1] => Add0.IN15 +in.operand_b[2] => Add0.IN14 +in.operand_b[3] => Add0.IN13 +in.operand_b[4] => Add0.IN12 +in.operand_b[5] => Add0.IN11 +in.operand_b[6] => Add0.IN10 +in.operand_b[7] => Add0.IN9 +in.operand_a[0] => Add0.IN8 +in.operand_a[1] => Add0.IN7 +in.operand_a[2] => Add0.IN6 +in.operand_a[3] => Add0.IN5 +in.operand_a[4] => Add0.IN4 +in.operand_a[5] => Add0.IN3 +in.operand_a[6] => Add0.IN2 +in.operand_a[7] => Add0.IN1 +result[0] <= result[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +result[1] <= result[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +result[2] <= result[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +result[3] <= result[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +result[4] <= result[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +result[5] <= result[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +result[6] <= result[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +result[7] <= result[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +overflow <= overflow~reg0.DB_MAX_OUTPUT_PORT_TYPE +done <= done~reg0.DB_MAX_OUTPUT_PORT_TYPE |chip8|cpu:cpu|st7920_serial_driver:gpu diff --git a/db/chip8.hif b/db/chip8.hif index b4b8e4a..76eb843 100644 Binary files a/db/chip8.hif and b/db/chip8.hif differ diff --git a/db/chip8.lpc.html b/db/chip8.lpc.html index 7f93fb7..0ee11d3 100644 --- a/db/chip8.lpc.html +++ b/db/chip8.lpc.html @@ -50,13 +50,29 @@ cpu|gpu 8194 -1 +7 0 -1 +7 8 -1 -1 -1 +7 +7 +7 +0 +0 +0 +0 +0 + + +cpu|alu +50 +0 +32 +0 +10 +0 +0 +0 0 0 0 @@ -65,7 +81,7 @@ cpu -9 +10 0 0 0 @@ -95,4 +111,20 @@ 0 0 + +dc +1 +0 +0 +0 +1 +0 +0 +0 +0 +0 +0 +0 +0 + diff --git a/db/chip8.lpc.rdb b/db/chip8.lpc.rdb index bc332bc..f762d88 100644 Binary files a/db/chip8.lpc.rdb and b/db/chip8.lpc.rdb differ diff --git a/db/chip8.lpc.txt b/db/chip8.lpc.txt index 21d6d21..5e0035e 100644 --- a/db/chip8.lpc.txt +++ b/db/chip8.lpc.txt @@ -5,7 +5,9 @@ +-------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ ; cpu|gpu|dff ; 2 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; ; cpu|gpu|com ; 12 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; cpu|gpu ; 8194 ; 1 ; 0 ; 1 ; 8 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; cpu ; 9 ; 0 ; 0 ; 0 ; 73 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; cpu|gpu ; 8194 ; 7 ; 0 ; 7 ; 8 ; 7 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; cpu|alu ; 50 ; 0 ; 32 ; 0 ; 10 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; cpu ; 10 ; 0 ; 0 ; 0 ; 73 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; ; mem ; 34 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; dc ; 1 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +-------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ diff --git a/db/chip8.map.bpm b/db/chip8.map.bpm index 42237c2..2e81a05 100644 Binary files a/db/chip8.map.bpm and b/db/chip8.map.bpm differ diff --git a/db/chip8.map.cdb b/db/chip8.map.cdb index 8636b0f..9213240 100644 Binary files a/db/chip8.map.cdb and b/db/chip8.map.cdb differ diff --git a/db/chip8.map.hdb b/db/chip8.map.hdb index 18c1887..bef42fb 100644 Binary files a/db/chip8.map.hdb and b/db/chip8.map.hdb differ diff --git a/db/chip8.map.kpt b/db/chip8.map.kpt index 06092ea..41b22bb 100644 Binary files a/db/chip8.map.kpt and b/db/chip8.map.kpt differ diff --git a/db/chip8.map.qmsg b/db/chip8.map.qmsg index 6e94577..0a05aa9 100644 --- a/db/chip8.map.qmsg +++ b/db/chip8.map.qmsg @@ -1,46 +1,55 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1712551491860 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition " "Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1712551491860 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 7 23:44:51 2024 " "Processing started: Sun Apr 7 23:44:51 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1712551491860 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712551491860 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off chip8 -c chip8 " "Command: quartus_map --read_settings_files=on --write_settings_files=off chip8 -c chip8" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712551491860 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1712551492019 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "12 12 " "Parallel compilation is enabled and will use 12 of the 12 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1712551492019 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "the-bomb/st7920_serial_driver.sv 3 3 " "Found 3 design units, including 3 entities, in source file the-bomb/st7920_serial_driver.sv" { { "Info" "ISGN_ENTITY_NAME" "1 st7920_serial_driver " "Found entity 1: st7920_serial_driver" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712551496896 ""} { "Info" "ISGN_ENTITY_NAME" "2 d_flip_flop " "Found entity 2: d_flip_flop" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 137 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712551496896 ""} { "Info" "ISGN_ENTITY_NAME" "3 commander " "Found entity 3: commander" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 147 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712551496896 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712551496896 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "chip8.sv 1 1 " "Found 1 design units, including 1 entities, in source file chip8.sv" { { "Info" "ISGN_ENTITY_NAME" "1 chip8 " "Found entity 1: chip8" { } { { "chip8.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/chip8.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712551496897 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712551496897 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu.sv 1 1 " "Found 1 design units, including 1 entities, in source file cpu.sv" { { "Info" "ISGN_ENTITY_NAME" "1 cpu " "Found entity 1: cpu" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712551496898 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712551496898 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "chip8 " "Elaborating entity \"chip8\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1712551496936 ""} -{ "Warning" "WSGN_SEARCH_FILE" "memory.sv 1 1 " "Using design file memory.sv, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 memory " "Found entity 1: memory" { } { { "memory.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/memory.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712551496940 ""} } { } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1712551496940 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "memory memory:mem " "Elaborating entity \"memory\" for hierarchy \"memory:mem\"" { } { { "chip8.sv" "mem" { Text "/home/nickorlow/programming/school/warminster/yayacemu/chip8.sv" 21 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712551496940 ""} -{ "Warning" "WVRFX_VERI_2111_UNCONVERTED" "80 0 4095 memory.sv(14) " "Verilog HDL warning at memory.sv(14): number of words (80) in memory file does not match the number of elements in the address range \[0:4095\]" { } { { "memory.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/memory.sv" 14 0 0 } } } 0 10850 "Verilog HDL warning at %4!s!: number of words (%1!d!) in memory file does not match the number of elements in the address range \[%2!d!:%3!d!\]" 0 0 "Analysis & Synthesis" 0 -1 1712551496941 "|chip8|memory:mem"} -{ "Warning" "WVRFX_VERI_2111_UNCONVERTED" "260 512 4095 memory.sv(15) " "Verilog HDL warning at memory.sv(15): number of words (260) in memory file does not match the number of elements in the address range \[512:4095\]" { } { { "memory.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/memory.sv" 15 0 0 } } } 0 10850 "Verilog HDL warning at %4!s!: number of words (%1!d!) in memory file does not match the number of elements in the address range \[%2!d!:%3!d!\]" 0 0 "Analysis & Synthesis" 0 -1 1712551496941 "|chip8|memory:mem"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu cpu:cpu " "Elaborating entity \"cpu\" for hierarchy \"cpu:cpu\"" { } { { "chip8.sv" "cpu" { Text "/home/nickorlow/programming/school/warminster/yayacemu/chip8.sv" 35 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712551496941 ""} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(124) " "Verilog HDL assignment warning at cpu.sv(124): truncated value with size 32 to match size of target (16)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 124 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712551497024 "|chip8|cpu:cpu"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(130) " "Verilog HDL assignment warning at cpu.sv(130): truncated value with size 32 to match size of target (16)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 130 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712551497024 "|chip8|cpu:cpu"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(147) " "Verilog HDL assignment warning at cpu.sv(147): truncated value with size 32 to match size of target (16)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 147 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712551497024 "|chip8|cpu:cpu"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 cpu.sv(210) " "Verilog HDL assignment warning at cpu.sv(210): truncated value with size 32 to match size of target (5)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 210 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712551497024 "|chip8|cpu:cpu"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 cpu.sv(213) " "Verilog HDL assignment warning at cpu.sv(213): truncated value with size 32 to match size of target (5)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 213 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712551497024 "|chip8|cpu:cpu"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(242) " "Verilog HDL assignment warning at cpu.sv(242): truncated value with size 32 to match size of target (16)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 242 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712551497024 "|chip8|cpu:cpu"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 cpu.sv(246) " "Verilog HDL assignment warning at cpu.sv(246): truncated value with size 32 to match size of target (5)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 246 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712551497024 "|chip8|cpu:cpu"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 cpu.sv(257) " "Verilog HDL assignment warning at cpu.sv(257): truncated value with size 32 to match size of target (5)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 257 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712551497024 "|chip8|cpu:cpu"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(284) " "Verilog HDL assignment warning at cpu.sv(284): truncated value with size 32 to match size of target (16)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 284 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712551497024 "|chip8|cpu:cpu"} -{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "instr.src_reg 0 cpu.sv(108) " "Net \"instr.src_reg\" at cpu.sv(108) has no driver or initial value, using a default initial value '0'" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 108 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1712551497024 "|chip8|cpu:cpu"} -{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "instr.src_addr 0 cpu.sv(108) " "Net \"instr.src_addr\" at cpu.sv(108) has no driver or initial value, using a default initial value '0'" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 108 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1712551497024 "|chip8|cpu:cpu"} -{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "instr.dst_addr 0 cpu.sv(108) " "Net \"instr.dst_addr\" at cpu.sv(108) has no driver or initial value, using a default initial value '0'" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 108 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1712551497024 "|chip8|cpu:cpu"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "st7920_serial_driver cpu:cpu\|st7920_serial_driver:gpu " "Elaborating entity \"st7920_serial_driver\" for hierarchy \"cpu:cpu\|st7920_serial_driver:gpu\"" { } { { "cpu.sv" "gpu" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 28 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712551497028 ""} -{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "line_idx st7920_serial_driver.sv(23) " "Verilog HDL or VHDL warning at st7920_serial_driver.sv(23): object \"line_idx\" assigned a value but never read" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 23 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1712551497040 "|chip8|cpu:cpu|st7920_serial_driver:gpu"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 st7920_serial_driver.sv(71) " "Verilog HDL assignment warning at st7920_serial_driver.sv(71): truncated value with size 32 to match size of target (7)" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 71 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712551497040 "|chip8|cpu:cpu|st7920_serial_driver:gpu"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 st7920_serial_driver.sv(84) " "Verilog HDL assignment warning at st7920_serial_driver.sv(84): truncated value with size 32 to match size of target (7)" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 84 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712551497040 "|chip8|cpu:cpu|st7920_serial_driver:gpu"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 st7920_serial_driver.sv(103) " "Verilog HDL assignment warning at st7920_serial_driver.sv(103): truncated value with size 32 to match size of target (6)" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 103 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712551497040 "|chip8|cpu:cpu|st7920_serial_driver:gpu"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 9 st7920_serial_driver.sv(131) " "Verilog HDL assignment warning at st7920_serial_driver.sv(131): truncated value with size 32 to match size of target (9)" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 131 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712551497040 "|chip8|cpu:cpu|st7920_serial_driver:gpu"} -{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "commands\[6..10\] 0 st7920_serial_driver.sv(26) " "Net \"commands\[6..10\]\" at st7920_serial_driver.sv(26) has no driver or initial value, using a default initial value '0'" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 26 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1712551497040 "|chip8|cpu:cpu|st7920_serial_driver:gpu"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "commander cpu:cpu\|st7920_serial_driver:gpu\|commander:com " "Elaborating entity \"commander\" for hierarchy \"cpu:cpu\|st7920_serial_driver:gpu\|commander:com\"" { } { { "the-bomb/st7920_serial_driver.sv" "com" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 42 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712551497041 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "d_flip_flop cpu:cpu\|st7920_serial_driver:gpu\|d_flip_flop:dff " "Elaborating entity \"d_flip_flop\" for hierarchy \"cpu:cpu\|st7920_serial_driver:gpu\|d_flip_flop:dff\"" { } { { "the-bomb/st7920_serial_driver.sv" "dff" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 50 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712551497041 ""} -{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "IINFER_ALTSYNCRAM_INFERRED" "memory:mem\|mem_rtl_0 " "Inferred altsyncram megafunction from the following design logic: \"memory:mem\|mem_rtl_0\" " { { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OPERATION_MODE DUAL_PORT " "Parameter OPERATION_MODE set to DUAL_PORT" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712551516726 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_A 8 " "Parameter WIDTH_A set to 8" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712551516726 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_A 12 " "Parameter WIDTHAD_A set to 12" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712551516726 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_A 4096 " "Parameter NUMWORDS_A set to 4096" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712551516726 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_B 8 " "Parameter WIDTH_B set to 8" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712551516726 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_B 12 " "Parameter WIDTHAD_B set to 12" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712551516726 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_B 4096 " "Parameter NUMWORDS_B set to 4096" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712551516726 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_A NONE " "Parameter ADDRESS_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712551516726 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_REG_B UNREGISTERED " "Parameter OUTDATA_REG_B set to UNREGISTERED" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712551516726 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_B NONE " "Parameter ADDRESS_ACLR_B set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712551516726 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_ACLR_B NONE " "Parameter OUTDATA_ACLR_B set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712551516726 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_REG_B CLOCK0 " "Parameter ADDRESS_REG_B set to CLOCK0" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712551516726 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "INDATA_ACLR_A NONE " "Parameter INDATA_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712551516726 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WRCONTROL_ACLR_A NONE " "Parameter WRCONTROL_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712551516726 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "INIT_FILE db/chip8.ram0_memory_e9e85012.hdl.mif " "Parameter INIT_FILE set to db/chip8.ram0_memory_e9e85012.hdl.mif" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712551516726 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "READ_DURING_WRITE_MODE_MIXED_PORTS OLD_DATA " "Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712551516726 ""} } { } 0 276029 "Inferred altsyncram megafunction from the following design logic: \"%1!s!\" " 0 0 "Design Software" 0 -1 1712551516726 ""} } { } 0 19000 "Inferred %1!d! megafunctions from design logic" 0 0 "Analysis & Synthesis" 0 -1 1712551516726 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "memory:mem\|altsyncram:mem_rtl_0 " "Elaborated megafunction instantiation \"memory:mem\|altsyncram:mem_rtl_0\"" { } { } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712551516773 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "memory:mem\|altsyncram:mem_rtl_0 " "Instantiated megafunction \"memory:mem\|altsyncram:mem_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "OPERATION_MODE DUAL_PORT " "Parameter \"OPERATION_MODE\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712551516773 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_A 8 " "Parameter \"WIDTH_A\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712551516773 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_A 12 " "Parameter \"WIDTHAD_A\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712551516773 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_A 4096 " "Parameter \"NUMWORDS_A\" = \"4096\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712551516773 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_B 8 " "Parameter \"WIDTH_B\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712551516773 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_B 12 " "Parameter \"WIDTHAD_B\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712551516773 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_B 4096 " "Parameter \"NUMWORDS_B\" = \"4096\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712551516773 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_A NONE " "Parameter \"ADDRESS_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712551516773 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_REG_B UNREGISTERED " "Parameter \"OUTDATA_REG_B\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712551516773 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_B NONE " "Parameter \"ADDRESS_ACLR_B\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712551516773 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_ACLR_B NONE " "Parameter \"OUTDATA_ACLR_B\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712551516773 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_REG_B CLOCK0 " "Parameter \"ADDRESS_REG_B\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712551516773 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INDATA_ACLR_A NONE " "Parameter \"INDATA_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712551516773 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WRCONTROL_ACLR_A NONE " "Parameter \"WRCONTROL_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712551516773 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INIT_FILE db/chip8.ram0_memory_e9e85012.hdl.mif " "Parameter \"INIT_FILE\" = \"db/chip8.ram0_memory_e9e85012.hdl.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712551516773 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "READ_DURING_WRITE_MODE_MIXED_PORTS OLD_DATA " "Parameter \"READ_DURING_WRITE_MODE_MIXED_PORTS\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712551516773 ""} } { } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1712551516773 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_dsq1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_dsq1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_dsq1 " "Found entity 1: altsyncram_dsq1" { } { { "db/altsyncram_dsq1.tdf" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/db/altsyncram_dsq1.tdf" 28 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712551516796 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712551516796 ""} -{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "led\[5\] VCC " "Pin \"led\[5\]\" is stuck at VCC" { } { { "chip8.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/chip8.sv" 7 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1712551532666 "|chip8|led[5]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1712551532666 ""} -{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1712551533595 ""} -{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "4 " "4 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1712551551646 ""} -{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1712551552875 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712551552875 ""} -{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "1 " "Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "rst_in " "No output dependent on input pin \"rst_in\"" { } { { "chip8.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/chip8.sv" 3 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1712551553790 "|chip8|rst_in"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1712551553790 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "17374 " "Implemented 17374 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Implemented 2 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1712551553847 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1712551553847 ""} { "Info" "ICUT_CUT_TM_LCELLS" "17356 " "Implemented 17356 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1712551553847 ""} { "Info" "ICUT_CUT_TM_RAMS" "8 " "Implemented 8 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Design Software" 0 -1 1712551553847 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1712551553847 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 26 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 26 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "698 " "Peak virtual memory: 698 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1712551553879 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 7 23:45:53 2024 " "Processing ended: Sun Apr 7 23:45:53 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1712551553879 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:01:02 " "Elapsed time: 00:01:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1712551553879 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:01:46 " "Total CPU time (on all processors): 00:01:46" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1712551553879 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1712551553879 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1712584011618 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition " "Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1712584011618 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Apr 8 08:46:51 2024 " "Processing started: Mon Apr 8 08:46:51 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1712584011618 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712584011618 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off chip8 -c chip8 " "Command: quartus_map --read_settings_files=on --write_settings_files=off chip8 -c chip8" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712584011618 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1712584011793 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "12 12 " "Parallel compilation is enabled and will use 12 of the 12 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1712584011793 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "the-bomb/st7920_serial_driver.sv 3 3 " "Found 3 design units, including 3 entities, in source file the-bomb/st7920_serial_driver.sv" { { "Info" "ISGN_ENTITY_NAME" "1 st7920_serial_driver " "Found entity 1: st7920_serial_driver" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712584016098 ""} { "Info" "ISGN_ENTITY_NAME" "2 d_flip_flop " "Found entity 2: d_flip_flop" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 137 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712584016098 ""} { "Info" "ISGN_ENTITY_NAME" "3 commander " "Found entity 3: commander" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 147 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712584016098 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712584016098 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "chip8.sv 1 1 " "Found 1 design units, including 1 entities, in source file chip8.sv" { { "Info" "ISGN_ENTITY_NAME" "1 chip8 " "Found entity 1: chip8" { } { { "chip8.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/chip8.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712584016099 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712584016099 ""} +{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "alu ALU cpu.sv(33) " "Verilog HDL Declaration information at cpu.sv(33): object \"alu\" differs only in case from object \"ALU\" in the same scope" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 33 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1712584016100 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu.sv 1 1 " "Found 1 design units, including 1 entities, in source file cpu.sv" { { "Info" "ISGN_ENTITY_NAME" "1 cpu " "Found entity 1: cpu" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712584016100 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712584016100 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "alu.sv 1 1 " "Found 1 design units, including 1 entities, in source file alu.sv" { { "Info" "ISGN_ENTITY_NAME" "1 alu " "Found entity 1: alu" { } { { "alu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/alu.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712584016100 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712584016100 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "aastructs.sv 1 0 " "Found 1 design units, including 0 entities, in source file aastructs.sv" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 structs (SystemVerilog) " "Found design unit 1: structs (SystemVerilog)" { } { { "aastructs.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/aastructs.sv" 1 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712584016101 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712584016101 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "downclocker.sv 1 1 " "Found 1 design units, including 1 entities, in source file downclocker.sv" { { "Info" "ISGN_ENTITY_NAME" "1 downclocker " "Found entity 1: downclocker" { } { { "downclocker.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/downclocker.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712584016101 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712584016101 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "chip8 " "Elaborating entity \"chip8\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1712584016136 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "downclocker downclocker:dc " "Elaborating entity \"downclocker\" for hierarchy \"downclocker:dc\"" { } { { "chip8.sv" "dc" { Text "/home/nickorlow/programming/school/warminster/yayacemu/chip8.sv" 14 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712584016138 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 downclocker.sv(18) " "Verilog HDL assignment warning at downclocker.sv(18): truncated value with size 32 to match size of target (10)" { } { { "downclocker.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/downclocker.sv" 18 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712584016138 "|chip8|downclocker:dc"} +{ "Warning" "WSGN_SEARCH_FILE" "memory.sv 1 1 " "Using design file memory.sv, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 memory " "Found entity 1: memory" { } { { "memory.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/memory.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712584016142 ""} } { } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1712584016142 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "memory memory:mem " "Elaborating entity \"memory\" for hierarchy \"memory:mem\"" { } { { "chip8.sv" "mem" { Text "/home/nickorlow/programming/school/warminster/yayacemu/chip8.sv" 29 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712584016143 ""} +{ "Warning" "WVRFX_VERI_2111_UNCONVERTED" "80 0 4095 memory.sv(14) " "Verilog HDL warning at memory.sv(14): number of words (80) in memory file does not match the number of elements in the address range \[0:4095\]" { } { { "memory.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/memory.sv" 14 0 0 } } } 0 10850 "Verilog HDL warning at %4!s!: number of words (%1!d!) in memory file does not match the number of elements in the address range \[%2!d!:%3!d!\]" 0 0 "Analysis & Synthesis" 0 -1 1712584016143 "|chip8|memory:mem"} +{ "Warning" "WVRFX_VERI_2111_UNCONVERTED" "132 512 4095 memory.sv(15) " "Verilog HDL warning at memory.sv(15): number of words (132) in memory file does not match the number of elements in the address range \[512:4095\]" { } { { "memory.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/memory.sv" 15 0 0 } } } 0 10850 "Verilog HDL warning at %4!s!: number of words (%1!d!) in memory file does not match the number of elements in the address range \[%2!d!:%3!d!\]" 0 0 "Analysis & Synthesis" 0 -1 1712584016143 "|chip8|memory:mem"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu cpu:cpu " "Elaborating entity \"cpu\" for hierarchy \"cpu:cpu\"" { } { { "chip8.sv" "cpu" { Text "/home/nickorlow/programming/school/warminster/yayacemu/chip8.sv" 44 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712584016144 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(148) " "Verilog HDL assignment warning at cpu.sv(148): truncated value with size 32 to match size of target (16)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 148 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712584016275 "|chip8|cpu:cpu"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(154) " "Verilog HDL assignment warning at cpu.sv(154): truncated value with size 32 to match size of target (16)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 154 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712584016275 "|chip8|cpu:cpu"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(171) " "Verilog HDL assignment warning at cpu.sv(171): truncated value with size 32 to match size of target (16)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 171 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712584016275 "|chip8|cpu:cpu"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 cpu.sv(249) " "Verilog HDL assignment warning at cpu.sv(249): truncated value with size 32 to match size of target (5)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 249 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712584016277 "|chip8|cpu:cpu"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 cpu.sv(252) " "Verilog HDL assignment warning at cpu.sv(252): truncated value with size 32 to match size of target (5)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 252 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712584016277 "|chip8|cpu:cpu"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(281) " "Verilog HDL assignment warning at cpu.sv(281): truncated value with size 32 to match size of target (16)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 281 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712584016282 "|chip8|cpu:cpu"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 cpu.sv(285) " "Verilog HDL assignment warning at cpu.sv(285): truncated value with size 32 to match size of target (5)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 285 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712584016282 "|chip8|cpu:cpu"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 cpu.sv(296) " "Verilog HDL assignment warning at cpu.sv(296): truncated value with size 32 to match size of target (5)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 296 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712584016642 "|chip8|cpu:cpu"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(323) " "Verilog HDL assignment warning at cpu.sv(323): truncated value with size 32 to match size of target (16)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 323 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712584016663 "|chip8|cpu:cpu"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(333) " "Verilog HDL assignment warning at cpu.sv(333): truncated value with size 32 to match size of target (16)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 333 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712584016664 "|chip8|cpu:cpu"} +{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "instr.src_reg 0 cpu.sv(131) " "Net \"instr.src_reg\" at cpu.sv(131) has no driver or initial value, using a default initial value '0'" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 131 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1712584017054 "|chip8|cpu:cpu"} +{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "instr.src_addr 0 cpu.sv(131) " "Net \"instr.src_addr\" at cpu.sv(131) has no driver or initial value, using a default initial value '0'" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 131 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1712584017054 "|chip8|cpu:cpu"} +{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "instr.dst_addr 0 cpu.sv(131) " "Net \"instr.dst_addr\" at cpu.sv(131) has no driver or initial value, using a default initial value '0'" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 131 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1712584017054 "|chip8|cpu:cpu"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alu cpu:cpu\|alu:alu " "Elaborating entity \"alu\" for hierarchy \"cpu:cpu\|alu:alu\"" { } { { "cpu.sv" "alu" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 33 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712584019602 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "st7920_serial_driver cpu:cpu\|st7920_serial_driver:gpu " "Elaborating entity \"st7920_serial_driver\" for hierarchy \"cpu:cpu\|st7920_serial_driver:gpu\"" { } { { "cpu.sv" "gpu" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 49 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712584019606 ""} +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "line_idx st7920_serial_driver.sv(23) " "Verilog HDL or VHDL warning at st7920_serial_driver.sv(23): object \"line_idx\" assigned a value but never read" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 23 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1712584019620 "|chip8|cpu:cpu|st7920_serial_driver:gpu"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 st7920_serial_driver.sv(71) " "Verilog HDL assignment warning at st7920_serial_driver.sv(71): truncated value with size 32 to match size of target (7)" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 71 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712584019620 "|chip8|cpu:cpu|st7920_serial_driver:gpu"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 st7920_serial_driver.sv(84) " "Verilog HDL assignment warning at st7920_serial_driver.sv(84): truncated value with size 32 to match size of target (7)" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 84 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712584019620 "|chip8|cpu:cpu|st7920_serial_driver:gpu"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 st7920_serial_driver.sv(103) " "Verilog HDL assignment warning at st7920_serial_driver.sv(103): truncated value with size 32 to match size of target (6)" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 103 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712584019620 "|chip8|cpu:cpu|st7920_serial_driver:gpu"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 9 st7920_serial_driver.sv(131) " "Verilog HDL assignment warning at st7920_serial_driver.sv(131): truncated value with size 32 to match size of target (9)" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 131 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712584019620 "|chip8|cpu:cpu|st7920_serial_driver:gpu"} +{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "commands\[6..10\] 0 st7920_serial_driver.sv(26) " "Net \"commands\[6..10\]\" at st7920_serial_driver.sv(26) has no driver or initial value, using a default initial value '0'" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 26 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1712584019620 "|chip8|cpu:cpu|st7920_serial_driver:gpu"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "commander cpu:cpu\|st7920_serial_driver:gpu\|commander:com " "Elaborating entity \"commander\" for hierarchy \"cpu:cpu\|st7920_serial_driver:gpu\|commander:com\"" { } { { "the-bomb/st7920_serial_driver.sv" "com" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 42 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712584019621 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "d_flip_flop cpu:cpu\|st7920_serial_driver:gpu\|d_flip_flop:dff " "Elaborating entity \"d_flip_flop\" for hierarchy \"cpu:cpu\|st7920_serial_driver:gpu\|d_flip_flop:dff\"" { } { { "the-bomb/st7920_serial_driver.sv" "dff" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 50 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712584019622 ""} +{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "IINFER_ALTSYNCRAM_INFERRED" "memory:mem\|mem_rtl_0 " "Inferred altsyncram megafunction from the following design logic: \"memory:mem\|mem_rtl_0\" " { { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OPERATION_MODE DUAL_PORT " "Parameter OPERATION_MODE set to DUAL_PORT" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712584036621 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_A 8 " "Parameter WIDTH_A set to 8" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712584036621 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_A 12 " "Parameter WIDTHAD_A set to 12" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712584036621 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_A 4096 " "Parameter NUMWORDS_A set to 4096" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712584036621 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_B 8 " "Parameter WIDTH_B set to 8" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712584036621 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_B 12 " "Parameter WIDTHAD_B set to 12" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712584036621 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_B 4096 " "Parameter NUMWORDS_B set to 4096" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712584036621 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_A NONE " "Parameter ADDRESS_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712584036621 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_REG_B UNREGISTERED " "Parameter OUTDATA_REG_B set to UNREGISTERED" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712584036621 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_B NONE " "Parameter ADDRESS_ACLR_B set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712584036621 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_ACLR_B NONE " "Parameter OUTDATA_ACLR_B set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712584036621 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_REG_B CLOCK0 " "Parameter ADDRESS_REG_B set to CLOCK0" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712584036621 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "INDATA_ACLR_A NONE " "Parameter INDATA_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712584036621 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WRCONTROL_ACLR_A NONE " "Parameter WRCONTROL_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712584036621 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "INIT_FILE db/chip8.ram0_memory_e9e85012.hdl.mif " "Parameter INIT_FILE set to db/chip8.ram0_memory_e9e85012.hdl.mif" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712584036621 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "READ_DURING_WRITE_MODE_MIXED_PORTS OLD_DATA " "Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1712584036621 ""} } { } 0 276029 "Inferred altsyncram megafunction from the following design logic: \"%1!s!\" " 0 0 "Design Software" 0 -1 1712584036621 ""} } { } 0 19000 "Inferred %1!d! megafunctions from design logic" 0 0 "Analysis & Synthesis" 0 -1 1712584036621 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "memory:mem\|altsyncram:mem_rtl_0 " "Elaborated megafunction instantiation \"memory:mem\|altsyncram:mem_rtl_0\"" { } { } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712584036659 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "memory:mem\|altsyncram:mem_rtl_0 " "Instantiated megafunction \"memory:mem\|altsyncram:mem_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "OPERATION_MODE DUAL_PORT " "Parameter \"OPERATION_MODE\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712584036659 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_A 8 " "Parameter \"WIDTH_A\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712584036659 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_A 12 " "Parameter \"WIDTHAD_A\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712584036659 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_A 4096 " "Parameter \"NUMWORDS_A\" = \"4096\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712584036659 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_B 8 " "Parameter \"WIDTH_B\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712584036659 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_B 12 " "Parameter \"WIDTHAD_B\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712584036659 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_B 4096 " "Parameter \"NUMWORDS_B\" = \"4096\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712584036659 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_A NONE " "Parameter \"ADDRESS_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712584036659 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_REG_B UNREGISTERED " "Parameter \"OUTDATA_REG_B\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712584036659 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_B NONE " "Parameter \"ADDRESS_ACLR_B\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712584036659 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_ACLR_B NONE " "Parameter \"OUTDATA_ACLR_B\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712584036659 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_REG_B CLOCK0 " "Parameter \"ADDRESS_REG_B\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712584036659 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INDATA_ACLR_A NONE " "Parameter \"INDATA_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712584036659 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WRCONTROL_ACLR_A NONE " "Parameter \"WRCONTROL_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712584036659 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INIT_FILE db/chip8.ram0_memory_e9e85012.hdl.mif " "Parameter \"INIT_FILE\" = \"db/chip8.ram0_memory_e9e85012.hdl.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712584036659 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "READ_DURING_WRITE_MODE_MIXED_PORTS OLD_DATA " "Parameter \"READ_DURING_WRITE_MODE_MIXED_PORTS\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712584036659 ""} } { } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1712584036659 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_dsq1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_dsq1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_dsq1 " "Found entity 1: altsyncram_dsq1" { } { { "db/altsyncram_dsq1.tdf" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/db/altsyncram_dsq1.tdf" 28 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712584036680 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712584036680 ""} +{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "led\[4\] GND " "Pin \"led\[4\]\" is stuck at GND" { } { { "chip8.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/chip8.sv" 7 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1712584046983 "|chip8|led[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "led\[5\] GND " "Pin \"led\[5\]\" is stuck at GND" { } { { "chip8.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/chip8.sv" 7 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1712584046983 "|chip8|led[5]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1712584046983 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1712584047706 ""} +{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "6 " "6 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1712584065406 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/nickorlow/programming/school/warminster/yayacemu/output_files/chip8.map.smsg " "Generated suppressed messages file /home/nickorlow/programming/school/warminster/yayacemu/output_files/chip8.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712584065742 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1712584066477 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712584066477 ""} +{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "1 " "Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "rst_in " "No output dependent on input pin \"rst_in\"" { } { { "chip8.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/chip8.sv" 3 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1712584067334 "|chip8|rst_in"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1712584067334 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "17552 " "Implemented 17552 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Implemented 2 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1712584067389 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1712584067389 ""} { "Info" "ICUT_CUT_TM_LCELLS" "17534 " "Implemented 17534 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1712584067389 ""} { "Info" "ICUT_CUT_TM_RAMS" "8 " "Implemented 8 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Design Software" 0 -1 1712584067389 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1712584067389 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 29 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 29 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "775 " "Peak virtual memory: 775 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1712584067421 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 8 08:47:47 2024 " "Processing ended: Mon Apr 8 08:47:47 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1712584067421 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:56 " "Elapsed time: 00:00:56" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1712584067421 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:01:34 " "Total CPU time (on all processors): 00:01:34" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1712584067421 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1712584067421 ""} diff --git a/db/chip8.map.rdb b/db/chip8.map.rdb index 48ee38a..23d87c4 100644 Binary files a/db/chip8.map.rdb and b/db/chip8.map.rdb differ diff --git a/db/chip8.map_bb.cdb b/db/chip8.map_bb.cdb index d5dc6ea..07a9b20 100644 Binary files a/db/chip8.map_bb.cdb and b/db/chip8.map_bb.cdb differ diff --git a/db/chip8.map_bb.hdb b/db/chip8.map_bb.hdb index dfc64b7..ff054c2 100644 Binary files a/db/chip8.map_bb.hdb and b/db/chip8.map_bb.hdb differ diff --git a/db/chip8.pre_map.hdb b/db/chip8.pre_map.hdb index 32b5edb..432d4e8 100644 Binary files a/db/chip8.pre_map.hdb and b/db/chip8.pre_map.hdb differ diff --git a/db/chip8.ram0_memory_e9e85012.hdl.mif b/db/chip8.ram0_memory_e9e85012.hdl.mif index 60514e3..3a8a82c 100644 --- a/db/chip8.ram0_memory_e9e85012.hdl.mif +++ b/db/chip8.ram0_memory_e9e85012.hdl.mif @@ -3333,264 +3333,264 @@ CONTENT BEGIN 774 : XXXXXXXX; 773 : XXXXXXXX; 772 : XXXXXXXX; - 771 : 01110000; - 770 : 10000000; - 769 : 11110000; - 768 : 10010000; - 767 : 01100000; - 766 : 00000000; - 765 : 00000000; - 764 : 11111100; - 763 : 11111110; - 762 : 10000111; - 761 : 00000011; - 760 : 00000011; - 759 : 00000011; - 758 : 10000111; - 757 : 11001110; - 756 : 10100110; - 755 : 10101000; - 754 : 10101000; - 753 : 10001110; - 752 : 00101000; - 751 : 00000000; - 750 : 00000000; - 749 : 01110001; - 748 : 00100011; - 747 : 01100111; - 746 : 00100111; - 745 : 00000111; - 744 : 00000111; - 743 : 00000011; - 742 : 11110001; - 741 : 01100011; - 740 : 00010100; - 739 : 00100100; - 738 : 01000100; - 737 : 00110000; - 736 : 00000000; - 735 : 00000000; - 734 : 11000101; - 733 : 11000100; - 732 : 11011100; - 731 : 11010100; - 730 : 11000000; - 729 : 11111000; - 728 : 11111100; - 727 : 11001110; - 726 : 00011000; - 725 : 10100000; - 724 : 00100000; - 723 : 00111000; - 722 : 10100000; - 721 : 00000000; - 720 : 00000000; - 719 : 11011101; - 718 : 11011101; - 717 : 11011101; - 716 : 11011101; - 715 : 11011101; - 714 : 11011101; - 713 : 11011101; - 712 : 11011101; - 711 : 00111011; - 710 : 01000000; - 709 : 01111001; - 708 : 01001010; - 707 : 00110001; - 706 : 00000000; - 705 : 00000000; - 704 : 00111000; - 703 : 10111000; - 702 : 10111000; - 701 : 00111000; - 700 : 00111000; - 699 : 00111000; - 698 : 00111000; - 697 : 00111001; - 696 : 00000010; - 695 : 00000010; - 694 : 00000010; - 693 : 00000010; - 692 : 00000111; - 691 : 00000000; - 690 : 00000000; - 689 : 00011111; - 688 : 00111111; - 687 : 01110001; - 686 : 11100000; - 685 : 11100000; - 684 : 11100000; - 683 : 11100000; - 682 : 11100111; - 681 : 11111100; - 680 : 11000110; - 679 : 10000011; - 678 : 10000011; - 677 : 10000011; - 676 : 11000111; - 675 : 11111110; - 674 : 00000000; - 673 : 00000000; - 672 : 00000000; - 671 : 10000000; - 670 : 00000000; - 669 : 00000000; - 668 : 10010000; - 667 : 00110000; - 666 : 11110000; - 665 : 00000001; - 664 : 00000011; - 663 : 00000011; - 662 : 00000011; - 661 : 00000001; - 660 : 00000000; - 659 : 00000000; - 658 : 00000000; - 657 : 00111011; - 656 : 01001000; - 655 : 01001001; - 654 : 01001010; - 653 : 01001001; - 652 : 00000000; - 651 : 11000110; - 650 : 11000110; - 649 : 11000110; - 648 : 11000110; - 647 : 11001110; - 646 : 11111100; - 645 : 11111000; - 644 : 00000000; - 643 : 00000000; - 642 : 00100111; - 641 : 00101001; - 640 : 00101001; - 639 : 00101001; - 638 : 11000111; - 637 : 00000001; - 636 : 10011101; - 635 : 00011101; - 634 : 00001101; - 633 : 00000001; - 632 : 00011101; - 631 : 00011101; - 630 : 00001100; - 629 : 00000000; - 628 : 00000000; - 627 : 10011101; - 626 : 10100001; - 625 : 10111101; - 624 : 10100101; - 623 : 00011001; - 622 : 00000000; - 621 : 10111111; - 620 : 00111111; - 619 : 00111000; - 618 : 00111000; - 617 : 10111000; - 616 : 10111000; - 615 : 00011000; - 614 : 00000000; - 613 : 00000000; - 612 : 00101000; - 611 : 00101000; - 610 : 00101000; - 609 : 00101010; - 608 : 00001101; - 607 : 10100000; - 606 : 11101000; - 605 : 11100000; - 604 : 11100101; - 603 : 11100000; - 602 : 01110001; - 601 : 00111111; - 600 : 00011111; - 599 : 00000000; - 598 : 00000000; - 597 : 00000010; - 596 : 00000010; - 595 : 00000010; - 594 : 00000010; - 593 : 00000010; - 592 : 00001111; - 591 : 01001110; - 590 : 00010010; - 589 : 00011111; - 588 : 11010000; - 587 : 11110101; - 586 : 10100010; - 585 : 00110000; - 584 : 01100000; - 583 : 00011111; - 582 : 11010000; - 581 : 11100110; - 580 : 10100010; - 579 : 00101000; - 578 : 01100000; - 577 : 00011111; - 576 : 11010000; - 575 : 11010111; - 574 : 10100010; - 573 : 00100000; - 572 : 01100000; - 571 : 00011111; - 570 : 11010000; - 569 : 11001000; - 568 : 10100010; - 567 : 00011000; - 566 : 01100000; - 565 : 00011111; - 564 : 11010000; - 563 : 10111001; - 562 : 10100010; - 561 : 00010000; - 560 : 01100000; - 559 : 00011111; - 558 : 11010000; - 557 : 10101010; - 556 : 10100010; - 555 : 00001000; - 554 : 01100000; - 553 : 00010000; - 552 : 01100001; + 771 : XXXXXXXX; + 770 : XXXXXXXX; + 769 : XXXXXXXX; + 768 : XXXXXXXX; + 767 : XXXXXXXX; + 766 : XXXXXXXX; + 765 : XXXXXXXX; + 764 : XXXXXXXX; + 763 : XXXXXXXX; + 762 : XXXXXXXX; + 761 : XXXXXXXX; + 760 : XXXXXXXX; + 759 : XXXXXXXX; + 758 : XXXXXXXX; + 757 : XXXXXXXX; + 756 : XXXXXXXX; + 755 : XXXXXXXX; + 754 : XXXXXXXX; + 753 : XXXXXXXX; + 752 : XXXXXXXX; + 751 : XXXXXXXX; + 750 : XXXXXXXX; + 749 : XXXXXXXX; + 748 : XXXXXXXX; + 747 : XXXXXXXX; + 746 : XXXXXXXX; + 745 : XXXXXXXX; + 744 : XXXXXXXX; + 743 : XXXXXXXX; + 742 : XXXXXXXX; + 741 : XXXXXXXX; + 740 : XXXXXXXX; + 739 : XXXXXXXX; + 738 : XXXXXXXX; + 737 : XXXXXXXX; + 736 : XXXXXXXX; + 735 : XXXXXXXX; + 734 : XXXXXXXX; + 733 : XXXXXXXX; + 732 : XXXXXXXX; + 731 : XXXXXXXX; + 730 : XXXXXXXX; + 729 : XXXXXXXX; + 728 : XXXXXXXX; + 727 : XXXXXXXX; + 726 : XXXXXXXX; + 725 : XXXXXXXX; + 724 : XXXXXXXX; + 723 : XXXXXXXX; + 722 : XXXXXXXX; + 721 : XXXXXXXX; + 720 : XXXXXXXX; + 719 : XXXXXXXX; + 718 : XXXXXXXX; + 717 : XXXXXXXX; + 716 : XXXXXXXX; + 715 : XXXXXXXX; + 714 : XXXXXXXX; + 713 : XXXXXXXX; + 712 : XXXXXXXX; + 711 : XXXXXXXX; + 710 : XXXXXXXX; + 709 : XXXXXXXX; + 708 : XXXXXXXX; + 707 : XXXXXXXX; + 706 : XXXXXXXX; + 705 : XXXXXXXX; + 704 : XXXXXXXX; + 703 : XXXXXXXX; + 702 : XXXXXXXX; + 701 : XXXXXXXX; + 700 : XXXXXXXX; + 699 : XXXXXXXX; + 698 : XXXXXXXX; + 697 : XXXXXXXX; + 696 : XXXXXXXX; + 695 : XXXXXXXX; + 694 : XXXXXXXX; + 693 : XXXXXXXX; + 692 : XXXXXXXX; + 691 : XXXXXXXX; + 690 : XXXXXXXX; + 689 : XXXXXXXX; + 688 : XXXXXXXX; + 687 : XXXXXXXX; + 686 : XXXXXXXX; + 685 : XXXXXXXX; + 684 : XXXXXXXX; + 683 : XXXXXXXX; + 682 : XXXXXXXX; + 681 : XXXXXXXX; + 680 : XXXXXXXX; + 679 : XXXXXXXX; + 678 : XXXXXXXX; + 677 : XXXXXXXX; + 676 : XXXXXXXX; + 675 : XXXXXXXX; + 674 : XXXXXXXX; + 673 : XXXXXXXX; + 672 : XXXXXXXX; + 671 : XXXXXXXX; + 670 : XXXXXXXX; + 669 : XXXXXXXX; + 668 : XXXXXXXX; + 667 : XXXXXXXX; + 666 : XXXXXXXX; + 665 : XXXXXXXX; + 664 : XXXXXXXX; + 663 : XXXXXXXX; + 662 : XXXXXXXX; + 661 : XXXXXXXX; + 660 : XXXXXXXX; + 659 : XXXXXXXX; + 658 : XXXXXXXX; + 657 : XXXXXXXX; + 656 : XXXXXXXX; + 655 : XXXXXXXX; + 654 : XXXXXXXX; + 653 : XXXXXXXX; + 652 : XXXXXXXX; + 651 : XXXXXXXX; + 650 : XXXXXXXX; + 649 : XXXXXXXX; + 648 : XXXXXXXX; + 647 : XXXXXXXX; + 646 : XXXXXXXX; + 645 : XXXXXXXX; + 644 : XXXXXXXX; + 643 : 11100111; + 642 : 00000010; + 641 : 11100110; + 640 : 00000010; + 639 : 10000000; + 638 : 00000010; + 637 : 10000000; + 636 : 00000001; + 635 : 10000001; + 634 : 00000111; + 633 : 10000101; + 632 : 00000000; + 631 : 11100010; + 630 : 00000101; + 629 : 11100101; + 628 : 01000011; + 627 : 00000000; + 626 : 11100011; + 625 : 00000000; + 624 : 11110011; + 623 : 00000000; + 622 : 11111011; + 621 : 00000000; + 620 : 10111111; + 619 : 00000000; + 618 : 00001111; + 617 : 00000000; + 616 : 00000111; + 615 : 00000000; + 614 : 00000011; + 613 : 11111000; + 612 : 00000000; + 611 : 11111000; + 610 : 00000000; + 609 : 00111001; + 608 : 00000000; + 607 : 00111011; + 606 : 00000000; + 605 : 00111111; + 604 : 00000000; + 603 : 00111110; + 602 : 00000000; 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- 546 : 01100000; + 547 : 00001000; + 546 : 01110000; 545 : 00011111; 544 : 11010000; - 543 : 10001100; + 543 : 01100110; 542 : 10100010; - 541 : 00101000; - 540 : 01100000; + 541 : 00001000; + 540 : 01110000; 539 : 00011111; 538 : 11010000; - 537 : 01111101; + 537 : 01010111; 536 : 10100010; - 535 : 00100000; - 534 : 01100000; + 535 : 00000100; + 534 : 01110000; 533 : 00011111; 532 : 11010000; - 531 : 01101110; - 530 : 10100010; - 529 : 00011000; - 528 : 01100000; + 531 : 00001000; + 530 : 01110000; + 529 : 01001000; + 528 : 10100010; 527 : 00011111; 526 : 11010000; - 525 : 01011111; + 525 : 00111001; 524 : 10100010; - 523 : 00010000; - 522 : 01100000; + 523 : 00001001; + 522 : 01110000; 521 : 00011111; 520 : 11010000; - 519 : 01010000; - 518 : 10100010; - 517 : 00001000; + 519 : 00001000; + 518 : 01100001; + 517 : 00001100; 516 : 01100000; - 515 : 00000001; - 514 : 01100001; + 515 : 00101010; + 514 : 10100010; 513 : 11100000; 512 : 00000000; 511 : XXXXXXXX; diff --git a/db/chip8.root_partition.map.reg_db.cdb b/db/chip8.root_partition.map.reg_db.cdb index bad7845..4398baf 100644 Binary files a/db/chip8.root_partition.map.reg_db.cdb and b/db/chip8.root_partition.map.reg_db.cdb differ diff --git a/db/chip8.routing.rdb b/db/chip8.routing.rdb index bba26b9..ddf829e 100644 Binary files a/db/chip8.routing.rdb and b/db/chip8.routing.rdb differ diff --git a/db/chip8.rtlv.hdb b/db/chip8.rtlv.hdb index 1888c73..4ba007c 100644 Binary files a/db/chip8.rtlv.hdb and b/db/chip8.rtlv.hdb differ diff --git a/db/chip8.rtlv_sg.cdb b/db/chip8.rtlv_sg.cdb index 5af4269..e3418d3 100644 Binary files a/db/chip8.rtlv_sg.cdb and b/db/chip8.rtlv_sg.cdb differ diff --git a/db/chip8.rtlv_sg_swap.cdb b/db/chip8.rtlv_sg_swap.cdb index 4912bd8..433848b 100644 Binary files a/db/chip8.rtlv_sg_swap.cdb and b/db/chip8.rtlv_sg_swap.cdb differ diff --git a/db/chip8.sta.qmsg b/db/chip8.sta.qmsg index df15159..f9b11d9 100644 --- a/db/chip8.sta.qmsg +++ b/db/chip8.sta.qmsg @@ -1,56 +1,56 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1712551938749 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition " "Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1712551938749 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 7 23:52:18 2024 " "Processing started: Sun Apr 7 23:52:18 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1712551938749 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1712551938749 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta chip8 -c chip8 " "Command: quartus_sta chip8 -c chip8" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1712551938749 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1712551938772 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1712551939456 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "12 12 " "Parallel compilation is enabled and will use 12 of the 12 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1712551939456 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature -40 degrees C " "Low junction temperature is -40 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712551939481 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 100 degrees C " "High junction temperature is 100 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712551939481 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "chip8.sdc " "Synopsys Design Constraints File file not found: 'chip8.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1712551940847 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1712551940847 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name fpga_clk fpga_clk " "create_clock -period 1.000 -name fpga_clk fpga_clk" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1712551940934 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " "create_clock -period 1.000 -name cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1712551940934 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1712551940934 ""} -{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1712551941197 ""} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1712551941259 ""} -{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1712551941263 ""} -{ "Info" "0" "" "Analyzing Slow 1100mV 100C Model" { } { } 0 0 "Analyzing Slow 1100mV 100C Model" 0 0 "Timing Analyzer" 0 0 1712551941268 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1712551945434 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1712551945434 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -28.406 " "Worst-case setup slack is -28.406" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551945434 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551945434 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -28.406 -1742.530 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " -28.406 -1742.530 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551945434 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -11.186 -95769.392 fpga_clk " " -11.186 -95769.392 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551945434 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712551945434 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.429 " "Worst-case hold slack is 0.429" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551945664 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551945664 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.429 0.000 fpga_clk " " 0.429 0.000 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551945664 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.476 0.000 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " 0.476 0.000 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551945664 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712551945664 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1712551945666 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1712551945667 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.636 " "Worst-case minimum pulse width slack is -2.636" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551945672 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551945672 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.636 -8463.323 fpga_clk " " -2.636 -8463.323 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551945672 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.538 -185.389 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " -0.538 -185.389 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551945672 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712551945672 ""} -{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 8 synchronizer chains. " "Report Metastability: Found 8 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Design MTBF is not calculated because the design doesn't meet its timing requirements. " "Design MTBF is not calculated because the design doesn't meet its timing requirements." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1712551945720 ""} } { } 0 332114 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1712551945720 ""} -{ "Info" "0" "" "Analyzing Slow 1100mV -40C Model" { } { } 0 0 "Analyzing Slow 1100mV -40C Model" 0 0 "Timing Analyzer" 0 0 1712551945722 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1712551945782 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1712551951737 ""} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1712551952797 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1712551953465 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1712551953465 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -26.933 " "Worst-case setup slack is -26.933" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551953465 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551953465 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -26.933 -1684.576 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " -26.933 -1684.576 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551953465 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -11.228 -94100.779 fpga_clk " " -11.228 -94100.779 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551953465 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712551953465 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.484 " "Worst-case hold slack is 0.484" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551953711 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551953711 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.484 0.000 fpga_clk " " 0.484 0.000 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551953711 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.565 0.000 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " 0.565 0.000 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551953711 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712551953711 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1712551953712 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1712551953713 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.636 " "Worst-case minimum pulse width slack is -2.636" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551953723 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551953723 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.636 -8927.522 fpga_clk " " -2.636 -8927.522 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551953723 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.538 -184.012 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " -0.538 -184.012 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551953723 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712551953723 ""} -{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 8 synchronizer chains. " "Report Metastability: Found 8 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Design MTBF is not calculated because the design doesn't meet its timing requirements. " "Design MTBF is not calculated because the design doesn't meet its timing requirements." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1712551953779 ""} } { } 0 332114 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1712551953779 ""} -{ "Info" "0" "" "Analyzing Fast 1100mV 100C Model" { } { } 0 0 "Analyzing Fast 1100mV 100C Model" 0 0 "Timing Analyzer" 0 0 1712551953781 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1712551954065 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1712551959681 ""} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1712551960616 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1712551960917 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1712551960917 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -14.774 " "Worst-case setup slack is -14.774" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551960918 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551960918 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -14.774 -901.498 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " -14.774 -901.498 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551960918 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -6.214 -50560.530 fpga_clk " " -6.214 -50560.530 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551960918 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712551960918 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.162 " "Worst-case hold slack is 0.162" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551961180 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551961180 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.162 0.000 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " 0.162 0.000 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551961180 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.177 0.000 fpga_clk " " 0.177 0.000 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551961180 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712551961180 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1712551961181 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1712551961181 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.174 " "Worst-case minimum pulse width slack is -2.174" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551961192 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551961192 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.174 -1371.543 fpga_clk " " -2.174 -1371.543 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551961192 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.192 -9.702 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " -0.192 -9.702 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551961192 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712551961192 ""} -{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 8 synchronizer chains. " "Report Metastability: Found 8 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Design MTBF is not calculated because the design doesn't meet its timing requirements. " "Design MTBF is not calculated because the design doesn't meet its timing requirements." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1712551961244 ""} } { } 0 332114 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1712551961244 ""} -{ "Info" "0" "" "Analyzing Fast 1100mV -40C Model" { } { } 0 0 "Analyzing Fast 1100mV -40C Model" 0 0 "Timing Analyzer" 0 0 1712551961245 ""} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1712551961832 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1712551962139 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1712551962139 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -12.462 " "Worst-case setup slack is -12.462" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551962139 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551962139 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -12.462 -739.747 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " -12.462 -739.747 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551962139 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.930 -40871.978 fpga_clk " " -4.930 -40871.978 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551962139 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712551962139 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.140 " "Worst-case hold slack is 0.140" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551962440 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551962440 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.140 0.000 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " 0.140 0.000 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551962440 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.164 0.000 fpga_clk " " 0.164 0.000 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551962440 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712551962440 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1712551962441 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1712551962441 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.174 " "Worst-case minimum pulse width slack is -2.174" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551962451 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551962451 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.174 -1373.239 fpga_clk " " -2.174 -1373.239 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551962451 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.137 -3.355 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " -0.137 -3.355 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551962451 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712551962451 ""} -{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 8 synchronizer chains. " "Report Metastability: Found 8 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Design MTBF is not calculated because the design doesn't meet its timing requirements. " "Design MTBF is not calculated because the design doesn't meet its timing requirements." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1712551962500 ""} } { } 0 332114 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1712551962500 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1712551963345 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1712551963345 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1353 " "Peak virtual memory: 1353 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1712551963512 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 7 23:52:43 2024 " "Processing ended: Sun Apr 7 23:52:43 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1712551963512 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:25 " "Elapsed time: 00:00:25" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1712551963512 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:01:44 " "Total CPU time (on all processors): 00:01:44" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1712551963512 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1712551963512 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1712584346749 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition " "Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1712584346749 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Apr 8 08:52:26 2024 " "Processing started: Mon Apr 8 08:52:26 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1712584346749 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1712584346749 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta chip8 -c chip8 " "Command: quartus_sta chip8 -c chip8" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1712584346749 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1712584346775 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1712584347519 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "12 12 " "Parallel compilation is enabled and will use 12 of the 12 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1712584347519 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature -40 degrees C " "Low junction temperature is -40 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712584347540 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 100 degrees C " "High junction temperature is 100 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712584347540 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "chip8.sdc " "Synopsys Design Constraints File file not found: 'chip8.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1712584348745 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1712584348745 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name fpga_clk fpga_clk " "create_clock -period 1.000 -name fpga_clk fpga_clk" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1712584348809 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " "create_clock -period 1.000 -name cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1712584348809 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name downclocker:dc\|clk_out downclocker:dc\|clk_out " "create_clock -period 1.000 -name downclocker:dc\|clk_out downclocker:dc\|clk_out" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1712584348809 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1712584348809 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1712584348957 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1712584349002 ""} +{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1712584349007 ""} +{ "Info" "0" "" "Analyzing Slow 1100mV 100C Model" { } { } 0 0 "Analyzing Slow 1100mV 100C Model" 0 0 "Timing Analyzer" 0 0 1712584349012 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1712584352097 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1712584352097 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -31.412 " "Worst-case setup slack is -31.412" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584352098 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584352098 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -31.412 -1884.356 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " -31.412 -1884.356 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584352098 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -11.058 -87363.415 downclocker:dc\|clk_out " " -11.058 -87363.415 downclocker:dc\|clk_out " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584352098 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.953 -27.713 fpga_clk " " -4.953 -27.713 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584352098 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712584352098 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.429 " "Worst-case hold slack is 0.429" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584352292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584352292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.429 0.000 downclocker:dc\|clk_out " " 0.429 0.000 downclocker:dc\|clk_out " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584352292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.501 0.000 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " 0.501 0.000 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584352292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.814 0.000 fpga_clk " " 0.814 0.000 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584352292 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712584352292 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1712584352293 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1712584352294 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.636 " "Worst-case minimum pulse width slack is -2.636" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584352305 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584352305 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.636 -8430.055 downclocker:dc\|clk_out " " -2.636 -8430.055 downclocker:dc\|clk_out " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584352305 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.622 -17.105 fpga_clk " " -0.622 -17.105 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584352305 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.538 -172.550 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " -0.538 -172.550 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584352305 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712584352305 ""} +{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 8 synchronizer chains. " "Report Metastability: Found 8 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Design MTBF is not calculated because the design doesn't meet its timing requirements. " "Design MTBF is not calculated because the design doesn't meet its timing requirements." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1712584352352 ""} } { } 0 332114 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1712584352352 ""} +{ "Info" "0" "" "Analyzing Slow 1100mV -40C Model" { } { } 0 0 "Analyzing Slow 1100mV -40C Model" 0 0 "Timing Analyzer" 0 0 1712584352354 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1712584352416 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1712584357006 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1712584357723 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1712584358182 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1712584358182 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -29.494 " "Worst-case setup slack is -29.494" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584358183 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584358183 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.494 -1798.010 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " -29.494 -1798.010 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584358183 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -11.057 -87142.095 downclocker:dc\|clk_out " " -11.057 -87142.095 downclocker:dc\|clk_out " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584358183 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.658 -29.299 fpga_clk " " -4.658 -29.299 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584358183 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712584358183 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.483 " "Worst-case hold slack is 0.483" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584358364 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584358364 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.483 0.000 downclocker:dc\|clk_out " " 0.483 0.000 downclocker:dc\|clk_out " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584358364 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.546 0.000 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " 0.546 0.000 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584358364 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.786 0.000 fpga_clk " " 0.786 0.000 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584358364 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712584358364 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1712584358365 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1712584358367 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.636 " "Worst-case minimum pulse width slack is -2.636" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584358379 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584358379 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.636 -8301.987 downclocker:dc\|clk_out " " -2.636 -8301.987 downclocker:dc\|clk_out " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584358379 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.627 -18.184 fpga_clk " " -0.627 -18.184 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584358379 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.538 -170.070 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " -0.538 -170.070 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584358379 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712584358379 ""} +{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 8 synchronizer chains. " "Report Metastability: Found 8 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Design MTBF is not calculated because the design doesn't meet its timing requirements. " "Design MTBF is not calculated because the design doesn't meet its timing requirements." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1712584358423 ""} } { } 0 332114 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1712584358423 ""} +{ "Info" "0" "" "Analyzing Fast 1100mV 100C Model" { } { } 0 0 "Analyzing Fast 1100mV 100C Model" 0 0 "Timing Analyzer" 0 0 1712584358424 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1712584358636 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1712584362578 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1712584363407 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1712584363595 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1712584363595 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -16.301 " "Worst-case setup slack is -16.301" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584363596 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584363596 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.301 -1018.017 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " -16.301 -1018.017 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584363596 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -5.608 -44394.911 downclocker:dc\|clk_out " " -5.608 -44394.911 downclocker:dc\|clk_out " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584363596 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.718 -8.178 fpga_clk " " -3.718 -8.178 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584363596 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712584363596 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.160 " "Worst-case hold slack is 0.160" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584363790 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584363790 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.160 0.000 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " 0.160 0.000 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584363790 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.177 0.000 downclocker:dc\|clk_out " " 0.177 0.000 downclocker:dc\|clk_out " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584363790 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.303 0.000 fpga_clk " " 0.303 0.000 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584363790 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712584363790 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1712584363791 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1712584363791 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.174 " "Worst-case minimum pulse width slack is -2.174" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584363803 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584363803 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.174 -537.344 downclocker:dc\|clk_out " " -2.174 -537.344 downclocker:dc\|clk_out " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584363803 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.517 -2.901 fpga_clk " " -0.517 -2.901 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584363803 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.144 -6.507 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " -0.144 -6.507 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584363803 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712584363803 ""} +{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 8 synchronizer chains. " "Report Metastability: Found 8 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Design MTBF is not calculated because the design doesn't meet its timing requirements. " "Design MTBF is not calculated because the design doesn't meet its timing requirements." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1712584363846 ""} } { } 0 332114 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1712584363846 ""} +{ "Info" "0" "" "Analyzing Fast 1100mV -40C Model" { } { } 0 0 "Analyzing Fast 1100mV -40C Model" 0 0 "Timing Analyzer" 0 0 1712584363847 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1712584364332 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1712584364514 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1712584364514 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -14.004 " "Worst-case setup slack is -14.004" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584364515 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584364515 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -14.004 -820.600 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " -14.004 -820.600 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584364515 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.541 -36337.093 downclocker:dc\|clk_out " " -4.541 -36337.093 downclocker:dc\|clk_out " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584364515 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.859 -5.427 fpga_clk " " -2.859 -5.427 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584364515 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712584364515 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.138 " "Worst-case hold slack is 0.138" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584364696 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584364696 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.138 0.000 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " 0.138 0.000 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584364696 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.164 0.000 downclocker:dc\|clk_out " " 0.164 0.000 downclocker:dc\|clk_out " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584364696 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.289 0.000 fpga_clk " " 0.289 0.000 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584364696 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712584364696 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1712584364696 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1712584364697 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.174 " "Worst-case minimum pulse width slack is -2.174" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584364710 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584364710 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.174 -534.258 downclocker:dc\|clk_out " " -2.174 -534.258 downclocker:dc\|clk_out " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584364710 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.533 -2.899 fpga_clk " " -0.533 -2.899 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584364710 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.057 -2.411 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " -0.057 -2.411 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712584364710 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712584364710 ""} +{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 8 synchronizer chains. " "Report Metastability: Found 8 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Design MTBF is not calculated because the design doesn't meet its timing requirements. " "Design MTBF is not calculated because the design doesn't meet its timing requirements." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1712584364752 ""} } { } 0 332114 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1712584364752 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1712584365431 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1712584365432 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1312 " "Peak virtual memory: 1312 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1712584365561 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 8 08:52:45 2024 " "Processing ended: Mon Apr 8 08:52:45 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1712584365561 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:19 " "Elapsed time: 00:00:19" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1712584365561 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:01:25 " "Total CPU time (on all processors): 00:01:25" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1712584365561 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1712584365561 ""} diff --git a/db/chip8.sta.rdb b/db/chip8.sta.rdb index 403eaee..5555e92 100644 Binary files a/db/chip8.sta.rdb and b/db/chip8.sta.rdb differ diff --git a/db/chip8.sta_cmp.7_slow_1100mv_100c.tdb b/db/chip8.sta_cmp.7_slow_1100mv_100c.tdb index 7c19512..a766d34 100644 Binary files a/db/chip8.sta_cmp.7_slow_1100mv_100c.tdb and b/db/chip8.sta_cmp.7_slow_1100mv_100c.tdb differ diff --git a/db/chip8.tiscmp.fast_1100mv_100c.ddb b/db/chip8.tiscmp.fast_1100mv_100c.ddb index 7b0f644..8da32e3 100644 Binary files a/db/chip8.tiscmp.fast_1100mv_100c.ddb and b/db/chip8.tiscmp.fast_1100mv_100c.ddb differ diff --git a/db/chip8.tiscmp.fast_1100mv_n40c.ddb b/db/chip8.tiscmp.fast_1100mv_n40c.ddb index 5516421..4dfe68e 100644 Binary files a/db/chip8.tiscmp.fast_1100mv_n40c.ddb and b/db/chip8.tiscmp.fast_1100mv_n40c.ddb differ diff --git a/db/chip8.tiscmp.fastest_slow_1100mv_85c.ddb b/db/chip8.tiscmp.fastest_slow_1100mv_85c.ddb index bd7eb78..4da5e57 100644 Binary files a/db/chip8.tiscmp.fastest_slow_1100mv_85c.ddb and b/db/chip8.tiscmp.fastest_slow_1100mv_85c.ddb differ diff --git a/db/chip8.tiscmp.fastest_slow_1100mv_n40c.ddb b/db/chip8.tiscmp.fastest_slow_1100mv_n40c.ddb index 248c52a..ae86b39 100644 Binary files a/db/chip8.tiscmp.fastest_slow_1100mv_n40c.ddb and b/db/chip8.tiscmp.fastest_slow_1100mv_n40c.ddb differ diff --git a/db/chip8.tiscmp.slow_1100mv_100c.ddb b/db/chip8.tiscmp.slow_1100mv_100c.ddb index 90b065f..6db8842 100644 Binary files a/db/chip8.tiscmp.slow_1100mv_100c.ddb and b/db/chip8.tiscmp.slow_1100mv_100c.ddb differ diff --git a/db/chip8.tiscmp.slow_1100mv_n40c.ddb b/db/chip8.tiscmp.slow_1100mv_n40c.ddb index 5220654..9d251b1 100644 Binary files a/db/chip8.tiscmp.slow_1100mv_n40c.ddb and b/db/chip8.tiscmp.slow_1100mv_n40c.ddb differ diff --git a/db/chip8.vpr.ammdb b/db/chip8.vpr.ammdb index a6ccb91..42bbe9b 100644 Binary files a/db/chip8.vpr.ammdb and b/db/chip8.vpr.ammdb differ diff --git a/db/chip8_partition_pins.json b/db/chip8_partition_pins.json index e0777fa..8e5fe40 100644 --- a/db/chip8_partition_pins.json +++ b/db/chip8_partition_pins.json @@ -27,10 +27,6 @@ "name" : "led[3]", "strict" : false }, - { - "name" : "led[4]", - "strict" : false - }, { "name" : "fpga_clk", "strict" : false diff --git a/incremental_db/compiled_partitions/chip8.root_partition.cmp.ammdb b/incremental_db/compiled_partitions/chip8.root_partition.cmp.ammdb index db46419..5d6f893 100644 Binary files a/incremental_db/compiled_partitions/chip8.root_partition.cmp.ammdb and b/incremental_db/compiled_partitions/chip8.root_partition.cmp.ammdb differ diff --git a/incremental_db/compiled_partitions/chip8.root_partition.cmp.cdb b/incremental_db/compiled_partitions/chip8.root_partition.cmp.cdb index 2544e0d..bb206ac 100644 Binary files a/incremental_db/compiled_partitions/chip8.root_partition.cmp.cdb and b/incremental_db/compiled_partitions/chip8.root_partition.cmp.cdb differ diff --git a/incremental_db/compiled_partitions/chip8.root_partition.cmp.hbdb.cdb b/incremental_db/compiled_partitions/chip8.root_partition.cmp.hbdb.cdb index 5be6049..866259f 100644 Binary files a/incremental_db/compiled_partitions/chip8.root_partition.cmp.hbdb.cdb and b/incremental_db/compiled_partitions/chip8.root_partition.cmp.hbdb.cdb differ diff --git a/incremental_db/compiled_partitions/chip8.root_partition.cmp.hbdb.hdb b/incremental_db/compiled_partitions/chip8.root_partition.cmp.hbdb.hdb index 6c77492..0c34fcb 100644 Binary files a/incremental_db/compiled_partitions/chip8.root_partition.cmp.hbdb.hdb and b/incremental_db/compiled_partitions/chip8.root_partition.cmp.hbdb.hdb differ diff --git a/incremental_db/compiled_partitions/chip8.root_partition.cmp.hdb b/incremental_db/compiled_partitions/chip8.root_partition.cmp.hdb index eda732a..d2780cf 100644 Binary files a/incremental_db/compiled_partitions/chip8.root_partition.cmp.hdb and b/incremental_db/compiled_partitions/chip8.root_partition.cmp.hdb differ diff --git a/incremental_db/compiled_partitions/chip8.root_partition.cmp.rcfdb b/incremental_db/compiled_partitions/chip8.root_partition.cmp.rcfdb index 39adc53..edcf7e3 100644 Binary files a/incremental_db/compiled_partitions/chip8.root_partition.cmp.rcfdb and b/incremental_db/compiled_partitions/chip8.root_partition.cmp.rcfdb differ diff --git a/incremental_db/compiled_partitions/chip8.root_partition.map.cdb b/incremental_db/compiled_partitions/chip8.root_partition.map.cdb index a266ccf..ecf5488 100644 Binary files a/incremental_db/compiled_partitions/chip8.root_partition.map.cdb and b/incremental_db/compiled_partitions/chip8.root_partition.map.cdb differ diff --git a/incremental_db/compiled_partitions/chip8.root_partition.map.dpi b/incremental_db/compiled_partitions/chip8.root_partition.map.dpi index bca7725..4306b9e 100644 Binary files a/incremental_db/compiled_partitions/chip8.root_partition.map.dpi and b/incremental_db/compiled_partitions/chip8.root_partition.map.dpi differ diff --git a/incremental_db/compiled_partitions/chip8.root_partition.map.hbdb.cdb b/incremental_db/compiled_partitions/chip8.root_partition.map.hbdb.cdb index 2ee26bf..2ef0ac4 100644 Binary files a/incremental_db/compiled_partitions/chip8.root_partition.map.hbdb.cdb and b/incremental_db/compiled_partitions/chip8.root_partition.map.hbdb.cdb differ diff --git a/incremental_db/compiled_partitions/chip8.root_partition.map.hbdb.hdb b/incremental_db/compiled_partitions/chip8.root_partition.map.hbdb.hdb index 93a7e6a..98d4ff8 100644 Binary files a/incremental_db/compiled_partitions/chip8.root_partition.map.hbdb.hdb and b/incremental_db/compiled_partitions/chip8.root_partition.map.hbdb.hdb differ diff --git a/incremental_db/compiled_partitions/chip8.root_partition.map.hdb b/incremental_db/compiled_partitions/chip8.root_partition.map.hdb index 6d0e424..6937d3b 100644 Binary files a/incremental_db/compiled_partitions/chip8.root_partition.map.hdb and b/incremental_db/compiled_partitions/chip8.root_partition.map.hdb differ diff --git a/incremental_db/compiled_partitions/chip8.root_partition.map.kpt b/incremental_db/compiled_partitions/chip8.root_partition.map.kpt index 652ddcb..f9f2c66 100644 Binary files a/incremental_db/compiled_partitions/chip8.root_partition.map.kpt and b/incremental_db/compiled_partitions/chip8.root_partition.map.kpt differ diff --git a/incremental_db/compiled_partitions/chip8.rrp.hdb b/incremental_db/compiled_partitions/chip8.rrp.hdb index 2c2963d..bb88b10 100644 Binary files a/incremental_db/compiled_partitions/chip8.rrp.hdb and b/incremental_db/compiled_partitions/chip8.rrp.hdb differ diff --git a/incremental_db/compiled_partitions/chip8.rrs.cdb b/incremental_db/compiled_partitions/chip8.rrs.cdb index 881e967..1627c2c 100644 Binary files a/incremental_db/compiled_partitions/chip8.rrs.cdb and b/incremental_db/compiled_partitions/chip8.rrs.cdb differ diff --git a/output_files/chip8.asm.rpt b/output_files/chip8.asm.rpt index 851cabd..f9cdbd8 100644 --- a/output_files/chip8.asm.rpt +++ b/output_files/chip8.asm.rpt @@ -1,5 +1,5 @@ Assembler report for chip8 -Sun Apr 7 23:52:17 2024 +Mon Apr 8 08:52:25 2024 Quartus Prime Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition @@ -38,7 +38,7 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Sun Apr 7 23:52:17 2024 ; +; Assembler Status ; Successful - Mon Apr 8 08:52:25 2024 ; ; Revision Name ; chip8 ; ; Top-level Entity Name ; chip8 ; ; Family ; Cyclone V ; @@ -67,8 +67,8 @@ https://fpgasoftware.intel.com/eula. +----------------+--------------------+ ; Option ; Setting ; +----------------+--------------------+ -; JTAG usercode ; 0x02233A94 ; -; Checksum ; 0x02233A94 ; +; JTAG usercode ; 0x0223939A ; +; Checksum ; 0x0223939A ; +----------------+--------------------+ @@ -78,14 +78,14 @@ https://fpgasoftware.intel.com/eula. Info: ******************************************************************* Info: Running Quartus Prime Assembler Info: Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition - Info: Processing started: Sun Apr 7 23:52:10 2024 + Info: Processing started: Mon Apr 8 08:52:19 2024 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off chip8 -c chip8 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (115030): Assembler is generating device programming files Info: Quartus Prime Assembler was successful. 0 errors, 1 warning - Info: Peak virtual memory: 631 megabytes - Info: Processing ended: Sun Apr 7 23:52:17 2024 - Info: Elapsed time: 00:00:07 + Info: Peak virtual memory: 628 megabytes + Info: Processing ended: Mon Apr 8 08:52:25 2024 + Info: Elapsed time: 00:00:06 Info: Total CPU time (on all processors): 00:00:07 diff --git a/output_files/chip8.done b/output_files/chip8.done index 3153271..6b5e839 100644 --- a/output_files/chip8.done +++ b/output_files/chip8.done @@ -1 +1 @@ -Sun Apr 7 23:52:44 2024 +Mon Apr 8 08:52:46 2024 diff --git a/output_files/chip8.fit.rpt b/output_files/chip8.fit.rpt index 73b2250..4343fc1 100644 --- a/output_files/chip8.fit.rpt +++ b/output_files/chip8.fit.rpt @@ -1,5 +1,5 @@ Fitter report for chip8 -Sun Apr 7 23:52:05 2024 +Mon Apr 8 08:52:14 2024 Quartus Prime Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition @@ -66,15 +66,15 @@ https://fpgasoftware.intel.com/eula. +----------------------------------------------------------------------------------+ ; Fitter Summary ; +---------------------------------+------------------------------------------------+ -; Fitter Status ; Successful - Sun Apr 7 23:52:05 2024 ; +; Fitter Status ; Successful - Mon Apr 8 08:52:14 2024 ; ; Quartus Prime Version ; 23.1std.0 Build 991 11/28/2023 SC Lite Edition ; ; Revision Name ; chip8 ; ; Top-level Entity Name ; chip8 ; ; Family ; Cyclone V ; ; Device ; 5CSEBA6U23I7 ; ; Timing Models ; Final ; -; Logic utilization (in ALMs) ; 10,549 / 41,910 ( 25 % ) ; -; Total registers ; 10004 ; +; Logic utilization (in ALMs) ; 10,693 / 41,910 ( 26 % ) ; +; Total registers ; 10165 ; ; Total pins ; 10 / 314 ( 3 % ) ; ; Total virtual pins ; 0 ; ; Total block memory bits ; 32,768 / 5,662,720 ( < 1 % ) ; @@ -156,1308 +156,1362 @@ https://fpgasoftware.intel.com/eula. ; Number detected on machine ; 12 ; ; Maximum allowed ; 12 ; ; ; ; -; Average used ; 1.61 ; +; Average used ; 1.57 ; ; Maximum used ; 12 ; ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; -; Processor 2 ; 10.6% ; -; Processor 3 ; 8.3% ; -; Processor 4 ; 7.9% ; -; Processor 5 ; 4.6% ; -; Processor 6 ; 4.5% ; -; Processor 7 ; 4.5% ; -; Processor 8 ; 4.4% ; -; Processor 9 ; 4.1% ; -; Processor 10 ; 4.1% ; -; Processor 11 ; 4.1% ; -; Processor 12 ; 4.1% ; +; Processor 2 ; 8.6% ; +; Processor 3 ; 8.2% ; +; Processor 4 ; 7.6% ; +; Processor 5 ; 4.4% ; +; Processor 6 ; 4.4% ; +; Processor 7 ; 4.3% ; +; Processor 8 ; 4.3% ; +; Processor 9 ; 3.9% ; +; Processor 10 ; 3.9% ; +; Processor 11 ; 3.9% ; +; Processor 12 ; 3.9% ; +----------------------------+-------------+ -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Fitter Netlist Optimizations ; -+------------------------------------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+----------------------------------------------------------------+------------------+-----------------------+ -; Node ; Action ; Operation ; Reason ; Node Port ; Node Port Name ; Destination Node ; Destination Port ; Destination Port Name ; -+------------------------------------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+----------------------------------------------------------------+------------------+-----------------------+ -; fpga_clk~inputCLKENA0 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; -; cpu:cpu|draw_state.c[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|draw_state.c[0]~DUPLICATE ; ; ; -; cpu:cpu|draw_state.c[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|draw_state.c[1]~DUPLICATE ; ; ; -; cpu:cpu|draw_state.c[3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|draw_state.c[3]~DUPLICATE ; ; ; -; cpu:cpu|draw_state.r[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|draw_state.r[0]~DUPLICATE ; ; ; -; cpu:cpu|draw_state.r[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|draw_state.r[1]~DUPLICATE ; ; ; -; cpu:cpu|draw_state.r[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|draw_state.r[2]~DUPLICATE ; ; ; -; cpu:cpu|draw_state.r[3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|draw_state.r[3]~DUPLICATE ; ; ; -; cpu:cpu|draw_state.r[4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|draw_state.r[4]~DUPLICATE ; ; ; -; cpu:cpu|instr.dst_reg[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|instr.dst_reg[1]~DUPLICATE ; ; ; -; cpu:cpu|instr.dst_reg[3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|instr.dst_reg[3]~DUPLICATE ; ; ; -; cpu:cpu|instr.op[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|instr.op[1]~DUPLICATE ; ; ; -; cpu:cpu|instr.src_byte[7] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|instr.src_byte[7]~DUPLICATE ; ; ; -; cpu:cpu|instr.src_byte[8] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|instr.src_byte[8]~DUPLICATE ; ; ; -; cpu:cpu|instr.src_byte[10] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|instr.src_byte[10]~DUPLICATE ; ; ; -; cpu:cpu|instr.src_byte[11] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|instr.src_byte[11]~DUPLICATE ; ; ; -; cpu:cpu|instr.src_sprite_idx[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|instr.src_sprite_idx[0]~DUPLICATE ; ; ; -; cpu:cpu|instr.src_sprite_idx[3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|instr.src_sprite_idx[3]~DUPLICATE ; ; ; -; cpu:cpu|instr.src_sprite_idx[4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|instr.src_sprite_idx[4]~DUPLICATE ; ; ; -; cpu:cpu|instr.src_sprite_vx[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|instr.src_sprite_vx[1]~DUPLICATE ; ; ; -; cpu:cpu|opcode[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|opcode[0]~DUPLICATE ; ; ; -; cpu:cpu|opcode[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|opcode[1]~DUPLICATE ; ; ; -; cpu:cpu|opcode[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|opcode[2]~DUPLICATE ; ; ; -; cpu:cpu|opcode[4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|opcode[4]~DUPLICATE ; ; ; -; cpu:cpu|opcode[5] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|opcode[5]~DUPLICATE ; ; ; -; cpu:cpu|opcode[9] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|opcode[9]~DUPLICATE ; ; ; -; cpu:cpu|opcode[10] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|opcode[10]~DUPLICATE ; ; ; -; cpu:cpu|opcode[15] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|opcode[15]~DUPLICATE ; ; ; -; cpu:cpu|program_counter[9] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|program_counter[9]~DUPLICATE ; ; ; -; cpu:cpu|registers[0][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|registers[0][0]~DUPLICATE ; ; ; -; cpu:cpu|registers[0][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|registers[0][2]~DUPLICATE ; ; ; -; cpu:cpu|registers[0][3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|registers[0][3]~DUPLICATE ; ; ; -; cpu:cpu|registers[0][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|registers[0][4]~DUPLICATE ; ; ; -; cpu:cpu|registers[8][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|registers[8][2]~DUPLICATE ; ; ; -; cpu:cpu|registers[8][3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|registers[8][3]~DUPLICATE ; ; ; -; cpu:cpu|registers[8][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|registers[8][4]~DUPLICATE ; ; ; -; cpu:cpu|st7920_serial_driver:gpu|c[12] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|c[12]~DUPLICATE ; ; ; -; cpu:cpu|st7920_serial_driver:gpu|commander:com|i[3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|commander:com|i[3]~DUPLICATE ; ; ; -; cpu:cpu|st7920_serial_driver:gpu|commander:com|i[6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|commander:com|i[6]~DUPLICATE ; ; ; -; cpu:cpu|st7920_serial_driver:gpu|commander:com|i[10] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|commander:com|i[10]~DUPLICATE ; ; ; -; cpu:cpu|st7920_serial_driver:gpu|commander:com|i[13] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|commander:com|i[13]~DUPLICATE ; ; ; -; cpu:cpu|st7920_serial_driver:gpu|commander:com|i[14] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|commander:com|i[14]~DUPLICATE ; ; ; -; cpu:cpu|st7920_serial_driver:gpu|commander:com|i[21] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|commander:com|i[21]~DUPLICATE ; ; ; -; cpu:cpu|st7920_serial_driver:gpu|commander:com|i[22] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|commander:com|i[22]~DUPLICATE ; ; ; -; cpu:cpu|st7920_serial_driver:gpu|commander:com|i[23] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|commander:com|i[23]~DUPLICATE ; ; ; -; cpu:cpu|st7920_serial_driver:gpu|commander:com|i[25] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|commander:com|i[25]~DUPLICATE ; ; ; -; cpu:cpu|st7920_serial_driver:gpu|commander:com|i[26] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|commander:com|i[26]~DUPLICATE ; ; ; -; cpu:cpu|st7920_serial_driver:gpu|commander:com|i[28] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|commander:com|i[28]~DUPLICATE ; ; ; -; cpu:cpu|st7920_serial_driver:gpu|commander:com|i[29] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|commander:com|i[29]~DUPLICATE ; ; ; -; cpu:cpu|st7920_serial_driver:gpu|i[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|i[0]~DUPLICATE ; ; ; -; cpu:cpu|st7920_serial_driver:gpu|i[10] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|i[10]~DUPLICATE ; ; ; -; cpu:cpu|st7920_serial_driver:gpu|i[13] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|i[13]~DUPLICATE ; ; ; -; cpu:cpu|st7920_serial_driver:gpu|i[16] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|i[16]~DUPLICATE ; ; ; -; cpu:cpu|st7920_serial_driver:gpu|i[22] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|i[22]~DUPLICATE ; ; ; -; cpu:cpu|st7920_serial_driver:gpu|i[29] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|i[29]~DUPLICATE ; ; ; -; cpu:cpu|st7920_serial_driver:gpu|i[30] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|i[30]~DUPLICATE ; ; ; -; cpu:cpu|st7920_serial_driver:gpu|i[31] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|i[31]~DUPLICATE ; ; ; -; cpu:cpu|st7920_serial_driver:gpu|line_cnt[4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|line_cnt[4]~DUPLICATE ; ; ; -; cpu:cpu|st7920_serial_driver:gpu|line_cnt[5] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|line_cnt[5]~DUPLICATE ; ; ; -; cpu:cpu|st7920_serial_driver:gpu|line_cnt[6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|line_cnt[6]~DUPLICATE ; ; ; -; cpu:cpu|st7920_serial_driver:gpu|line_cnt[7] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|line_cnt[7]~DUPLICATE ; ; ; -; cpu:cpu|st7920_serial_driver:gpu|line_cnt[8] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|line_cnt[8]~DUPLICATE ; ; ; -; cpu:cpu|st7920_serial_driver:gpu|line_cnt[9] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|line_cnt[9]~DUPLICATE ; ; ; -; cpu:cpu|st7920_serial_driver:gpu|line_cnt[10] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|line_cnt[10]~DUPLICATE ; ; ; -; cpu:cpu|st7920_serial_driver:gpu|line_cnt[11] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|line_cnt[11]~DUPLICATE ; ; ; -; cpu:cpu|st7920_serial_driver:gpu|line_cnt[13] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|line_cnt[13]~DUPLICATE ; ; ; -; cpu:cpu|st7920_serial_driver:gpu|line_cnt[14] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|line_cnt[14]~DUPLICATE ; ; ; -; cpu:cpu|st7920_serial_driver:gpu|line_cnt[16] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|line_cnt[16]~DUPLICATE ; ; ; -; cpu:cpu|st7920_serial_driver:gpu|line_cnt[18] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|line_cnt[18]~DUPLICATE ; ; ; -; cpu:cpu|st7920_serial_driver:gpu|line_cnt[19] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|line_cnt[19]~DUPLICATE ; ; ; -; cpu:cpu|st7920_serial_driver:gpu|line_cnt[20] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|line_cnt[20]~DUPLICATE ; ; ; -; cpu:cpu|st7920_serial_driver:gpu|line_cnt[21] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|line_cnt[21]~DUPLICATE ; ; ; -; cpu:cpu|st7920_serial_driver:gpu|line_cnt[22] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|line_cnt[22]~DUPLICATE ; ; ; -; cpu:cpu|st7920_serial_driver:gpu|line_cnt[24] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|line_cnt[24]~DUPLICATE ; ; ; -; cpu:cpu|st7920_serial_driver:gpu|line_cnt[31] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|line_cnt[31]~DUPLICATE ; ; ; -; cpu:cpu|st7920_serial_driver:gpu|x[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|x[0]~DUPLICATE ; ; ; -; cpu:cpu|st7920_serial_driver:gpu|x[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|x[2]~DUPLICATE ; ; ; -; cpu:cpu|st7920_serial_driver:gpu|y[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|y[0]~DUPLICATE ; ; ; -; cpu:cpu|st7920_serial_driver:gpu|y[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|y[1]~DUPLICATE ; ; ; -; cpu:cpu|st7920_serial_driver:gpu|y[3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|y[3]~DUPLICATE ; ; ; -; cpu:cpu|state[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|state[2]~DUPLICATE ; ; ; -; cpu:cpu|vram[0][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[0][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[1][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[1][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[2][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[2][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[5][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[5][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[5][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[5][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[5][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[5][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[7][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[7][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[7][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[7][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[8][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[8][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[9][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[9][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[9][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[9][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[11][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[11][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[11][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[11][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[12][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[12][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[14][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[14][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[15][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[15][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[17][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[17][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[17][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[17][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[18][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[18][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[18][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[18][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[18][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[18][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[19][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[19][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[19][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[19][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[22][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[22][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[22][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[22][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[26][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[26][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[27][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[27][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[27][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[27][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[28][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[28][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[28][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[28][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[29][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[29][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[30][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[30][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[30][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[30][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[31][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[31][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[32][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[32][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[33][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[33][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[36][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[36][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[37][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[37][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[39][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[39][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[39][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[39][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[39][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[39][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[40][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[40][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[41][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[41][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[41][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[41][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[43][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[43][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[43][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[43][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[44][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[44][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[46][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[46][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[47][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[47][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[47][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[47][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[48][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[48][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[49][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[49][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[49][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[49][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[50][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[50][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[52][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[52][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[53][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[53][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[54][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[54][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[55][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[55][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[56][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[56][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[57][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[57][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[57][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[57][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[58][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[58][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[59][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[59][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[60][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[60][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[62][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[62][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[63][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[63][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[63][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[63][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[63][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[63][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[64][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[64][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[65][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[65][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[65][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[65][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[66][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[66][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[66][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[66][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[66][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[66][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[67][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[67][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[67][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[67][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[70][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[70][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[71][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[71][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[72][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[72][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[73][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[73][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[75][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[75][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[76][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[76][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[76][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[76][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[78][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[78][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[79][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[79][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[79][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[79][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[80][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[80][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[80][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[80][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[82][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[82][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[83][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[83][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[88][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[88][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[88][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[88][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[88][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[88][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[89][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[89][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[90][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[90][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[90][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[90][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[92][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[92][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[93][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[93][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[97][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[97][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[99][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[99][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[101][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[101][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[102][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[102][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[103][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[103][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[104][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[104][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[106][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[106][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[107][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[107][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[110][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[110][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[110][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[110][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[111][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[111][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[112][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[112][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[115][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[115][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[116][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[116][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[117][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[117][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[118][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[118][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[120][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[120][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[122][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[122][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[122][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[122][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[122][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[122][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[122][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[122][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[124][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[124][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[126][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[126][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[128][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[128][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[132][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[132][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[133][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[133][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[134][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[134][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[135][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[135][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[136][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[136][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[137][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[137][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[139][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[139][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[140][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[140][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[141][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[141][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[141][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[141][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[145][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[145][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[146][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[146][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[147][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[147][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[147][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[147][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[148][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[148][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[149][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[149][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[150][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[150][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[150][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[150][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[155][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[155][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[156][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[156][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[157][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[157][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[157][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[157][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[161][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[161][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[161][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[161][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[161][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[161][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[166][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[166][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[168][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[168][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[168][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[168][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[174][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[174][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[174][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[174][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[174][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[174][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[175][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[175][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[175][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[175][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[176][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[176][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[176][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[176][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[177][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[177][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[178][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[178][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[180][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[180][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[181][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[181][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[182][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[182][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[185][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[185][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[186][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[186][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[187][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[187][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[187][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[187][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[190][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[190][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[192][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[192][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[193][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[193][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[197][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[197][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[197][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[197][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[198][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[198][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[200][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[200][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[203][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[203][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[204][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[204][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[205][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[205][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[205][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[205][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[205][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[205][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[206][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[206][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[213][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[213][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[216][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[216][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[217][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[217][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[217][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[217][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[217][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[217][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[218][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[218][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[219][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[219][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[219][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[219][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[220][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[220][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[223][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[223][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[224][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[224][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[225][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[225][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[226][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[226][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[226][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[226][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[227][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[227][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[228][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[228][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[229][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[229][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[230][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[230][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[231][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[231][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[231][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[231][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[231][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[231][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[232][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[232][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[234][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[234][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[235][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[235][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[236][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[236][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[237][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[237][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[237][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[237][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[238][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[238][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[239][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[239][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[241][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[241][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[241][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[241][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[241][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[241][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[244][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[244][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[244][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[244][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[245][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[245][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[245][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[245][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[245][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[245][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[246][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[246][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[247][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[247][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[248][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[248][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[249][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[249][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[249][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[249][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[250][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[250][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[250][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[250][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[257][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[257][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[258][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[258][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[260][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[260][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[261][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[261][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[262][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[262][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[264][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[264][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[264][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[264][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[265][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[265][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[266][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[266][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[266][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[266][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[267][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[267][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[267][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[267][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[267][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[267][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[268][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[268][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[269][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[269][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[270][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[270][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[270][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[270][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[272][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[272][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[272][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[272][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[273][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[273][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[273][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[273][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[274][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[274][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[275][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[275][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[275][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[275][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[276][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[276][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[277][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[277][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[278][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[278][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[279][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[279][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[279][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[279][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[280][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[280][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[280][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[280][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[281][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[281][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[281][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[281][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[282][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[282][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[282][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[282][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[282][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[282][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[283][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[283][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[284][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[284][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[284][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[284][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[286][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[286][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[288][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[288][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[288][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[288][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[289][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[289][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[289][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[289][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[292][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[292][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[292][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[292][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[293][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[293][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[293][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[293][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[294][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[294][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[294][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[294][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[295][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[295][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[295][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[295][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[295][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[295][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[297][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[297][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[297][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[297][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[298][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[298][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[298][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[298][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[298][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[298][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[299][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[299][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[301][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[301][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[302][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[302][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[302][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[302][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[303][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[303][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[304][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[304][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[305][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[305][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[305][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[305][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[305][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[305][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[306][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[306][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[307][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[307][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[309][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[309][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[309][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[309][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[310][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[310][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[312][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[312][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[313][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[313][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[315][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[315][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[315][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[315][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[316][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[316][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[316][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[316][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[317][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[317][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[318][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[318][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[318][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[318][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[319][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[319][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[319][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[319][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[320][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[320][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[321][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[321][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[321][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[321][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[322][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[322][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[323][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[323][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[324][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[324][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[325][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[325][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[326][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[326][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[329][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[329][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[330][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[330][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[331][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[331][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[331][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[331][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[331][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[331][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[332][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[332][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[334][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[334][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[334][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[334][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[335][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[335][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[336][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[336][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[336][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[336][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[337][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[337][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[337][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[337][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[340][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[340][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[340][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[340][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[341][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[341][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[342][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[342][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[342][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[342][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[342][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[342][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[343][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[343][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[343][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[343][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[344][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[344][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[347][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[347][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[349][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[349][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[351][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[351][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[351][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[351][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[352][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[352][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[354][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[354][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[354][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[354][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[355][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[355][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[356][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[356][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[356][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[356][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[356][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[356][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[360][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[360][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[361][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[361][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[362][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[362][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[362][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[362][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[364][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[364][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[365][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[365][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[367][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[367][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[368][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[368][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[369][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[369][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[370][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[370][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[372][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[372][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[372][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[372][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[373][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[373][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[373][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[373][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[373][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[373][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[374][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[374][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[374][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[374][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[374][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[374][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[375][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[375][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[375][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[375][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[375][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[375][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[376][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[376][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[377][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[377][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[378][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[378][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[378][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[378][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[379][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[379][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[379][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[379][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[380][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[380][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[380][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[380][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[381][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[381][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[381][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[381][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[383][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[383][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[384][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[384][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[385][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[385][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[386][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[386][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[387][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[387][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[388][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[388][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[388][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[388][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[390][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[390][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[392][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[392][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[393][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[393][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[394][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[394][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[394][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[394][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[394][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[394][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[395][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[395][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[395][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[395][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[397][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[397][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[397][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[397][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[401][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[401][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[403][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[403][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[403][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[403][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[405][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[405][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[405][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[405][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[406][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[406][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[407][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[407][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[407][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[407][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[408][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[408][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[408][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[408][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[409][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[409][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[409][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[409][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[411][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[411][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[411][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[411][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[412][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[412][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[414][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[414][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[418][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[418][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[418][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[418][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[418][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[418][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[421][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[421][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[422][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[422][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[423][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[423][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[424][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[424][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[425][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[425][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[425][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[425][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[426][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[426][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[426][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[426][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[429][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[429][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[429][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[429][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[430][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[430][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[431][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[431][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[432][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[432][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[432][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[432][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[433][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[433][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[433][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[433][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[433][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[433][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[434][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[434][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[434][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[434][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[435][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[435][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[437][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[437][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[438][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[438][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[438][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[438][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[439][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[439][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[443][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[443][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[443][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[443][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[444][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[444][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[444][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[444][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[445][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[445][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[445][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[445][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[447][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[447][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[448][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[448][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[448][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[448][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[449][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[449][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[449][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[449][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[451][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[451][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[454][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[454][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[455][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[455][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[457][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[457][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[458][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[458][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[458][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[458][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[458][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[458][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[460][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[460][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[460][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[460][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[461][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[461][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[462][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[462][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[463][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[463][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[466][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[466][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[466][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[466][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[466][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[466][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[467][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[467][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[467][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[467][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[467][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[467][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[470][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[470][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[471][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[471][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[474][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[474][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[477][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[477][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[477][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[477][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[477][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[477][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[480][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[480][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[481][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[481][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[482][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[482][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[482][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[482][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[485][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[485][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[486][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[486][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[487][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[487][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[488][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[488][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[488][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[488][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[490][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[490][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[490][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[490][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[493][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[493][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[493][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[493][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[494][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[494][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[495][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[495][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[496][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[496][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[498][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[498][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[499][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[499][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[500][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[500][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[502][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[502][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[502][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[502][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[502][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[502][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[503][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[503][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[503][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[503][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[504][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[504][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[505][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[505][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[505][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[505][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[506][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[506][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[507][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[507][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[507][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[507][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[510][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[510][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[511][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[511][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[512][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[512][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[514][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[514][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[515][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[515][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[516][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[516][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[516][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[516][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[518][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[518][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[518][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[518][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[519][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[519][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[519][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[519][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[520][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[520][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[520][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[520][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[521][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[521][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[521][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[521][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[522][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[522][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[522][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[522][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[522][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[522][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[523][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[523][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[524][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[524][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[525][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[525][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[527][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[527][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[528][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[528][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[529][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[529][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[529][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[529][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[529][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[529][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[531][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[531][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[533][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[533][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[533][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[533][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[534][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[534][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[535][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[535][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[536][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[536][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[536][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[536][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[537][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[537][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[537][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[537][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[539][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[539][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[539][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[539][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[539][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[539][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[540][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[540][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[540][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[540][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[541][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[541][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[545][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[545][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[547][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[547][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[547][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[547][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[549][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[549][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[550][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[550][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[552][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[552][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[552][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[552][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[553][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[553][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[554][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[554][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[554][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[554][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[555][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[555][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[556][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[556][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[557][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[557][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[557][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[557][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[557][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[557][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[557][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[557][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[558][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[558][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[559][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[559][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[560][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[560][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[561][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[561][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[561][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[561][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[563][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[563][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[563][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[563][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[564][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[564][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[565][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[565][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[565][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[565][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[565][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[565][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[567][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[567][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[571][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[571][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[571][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[571][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[572][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[572][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[574][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[574][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[575][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[575][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[575][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[575][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[580][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[580][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[581][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[581][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[581][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[581][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[582][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[582][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[583][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[583][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[584][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[584][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[584][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[584][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[584][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[584][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[584][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[584][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[585][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[585][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[587][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[587][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[588][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[588][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[589][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[589][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[590][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[590][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[592][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[592][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[592][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[592][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[594][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[594][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[596][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[596][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[596][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[596][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[598][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[598][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[598][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[598][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[598][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[598][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[599][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[599][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[600][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[600][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[601][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[601][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[601][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[601][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[602][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[602][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[603][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[603][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[608][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[608][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[608][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[608][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[609][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[609][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[609][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[609][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[610][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[610][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[610][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[610][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[611][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[611][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[612][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[612][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[612][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[612][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[613][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[613][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[613][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[613][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[614][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[614][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[614][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[614][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[617][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[617][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[617][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[617][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[618][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[618][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[620][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[620][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[620][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[620][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[621][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[621][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[621][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[621][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[623][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[623][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[624][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[624][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[624][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[624][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[626][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[626][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[627][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[627][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[627][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[627][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[627][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[627][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[628][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[628][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[628][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[628][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[628][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[628][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[629][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[629][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[629][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[629][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[631][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[631][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[632][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[632][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[632][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[632][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[632][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[632][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[636][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[636][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[639][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[639][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[640][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[640][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[640][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[640][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[641][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[641][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[641][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[641][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[641][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[641][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[642][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[642][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[642][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[642][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[643][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[643][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[643][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[643][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[644][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[644][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[646][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[646][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[647][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[647][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[648][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[648][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[649][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[649][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[650][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[650][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[650][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[650][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[650][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[650][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[651][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[651][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[652][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[652][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[652][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[652][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[652][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[652][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[653][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[653][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[653][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[653][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[654][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[654][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[656][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[656][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[659][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[659][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[659][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[659][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[660][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[660][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[660][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[660][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[662][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[662][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[662][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[662][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[664][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[664][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[664][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[664][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[665][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[665][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[665][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[665][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[665][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[665][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[666][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[666][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[668][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[668][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[668][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[668][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[670][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[670][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[670][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[670][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[671][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[671][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[672][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[672][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[673][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[673][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[673][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[673][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[673][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[673][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[674][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[674][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[676][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[676][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[678][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[678][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[679][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[679][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[679][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[679][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[680][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[680][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[680][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[680][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[680][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[680][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[683][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[683][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[685][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[685][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[685][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[685][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[685][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[685][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[687][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[687][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[687][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[687][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[687][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[687][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[688][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[688][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[688][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[688][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[690][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[690][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[691][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[691][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[691][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[691][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[692][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[692][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[695][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[695][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[696][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[696][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[698][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[698][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[698][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[698][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[701][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[701][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[702][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[702][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[703][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[703][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[704][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[704][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[704][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[704][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[704][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[704][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[705][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[705][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[707][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[707][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[707][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[707][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[707][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[707][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[708][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[708][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[708][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[708][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[708][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[708][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[711][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[711][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[711][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[711][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[712][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[712][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[712][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[712][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[712][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[712][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[713][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[713][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[713][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[713][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[714][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[714][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[714][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[714][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[715][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[715][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[715][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[715][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[715][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[715][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[717][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[717][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[718][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[718][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[719][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[719][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[720][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[720][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[720][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[720][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[720][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[720][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[721][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[721][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[722][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[722][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[723][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[723][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[724][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[724][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[725][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[725][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[725][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[725][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[726][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[726][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[727][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[727][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[727][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[727][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[728][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[728][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[729][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[729][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[730][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[730][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[730][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[730][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[730][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[730][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[731][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[731][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[731][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[731][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[736][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[736][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[737][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[737][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[738][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[738][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[738][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[738][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[740][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[740][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[741][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[741][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[744][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[744][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[744][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[744][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[745][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[745][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[746][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[746][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[748][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[748][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[748][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[748][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[752][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[752][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[752][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[752][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[753][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[753][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[753][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[753][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[754][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[754][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[754][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[754][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[755][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[755][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[755][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[755][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[756][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[756][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[757][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[757][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[758][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[758][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[758][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[758][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[759][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[759][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[759][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[759][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[759][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[759][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[761][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[761][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[762][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[762][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[762][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[762][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[762][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[762][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[763][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[763][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[763][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[763][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[765][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[765][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[765][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[765][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[766][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[766][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[766][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[766][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[767][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[767][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[768][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[768][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[769][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[769][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[770][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[770][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[770][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[770][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[770][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[770][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[771][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[771][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[771][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[771][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[773][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[773][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[773][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[773][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[774][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[774][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[774][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[774][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[774][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[774][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[775][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[775][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[775][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[775][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[775][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[775][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[775][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[775][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[776][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[776][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[778][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[778][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[778][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[778][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[778][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[778][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[779][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[779][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[779][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[779][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[780][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[780][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[780][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[780][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[781][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[781][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[782][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[782][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[783][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[783][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[784][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[784][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[785][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[785][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[787][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[787][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[788][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[788][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[788][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[788][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[788][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[788][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[789][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[789][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[789][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[789][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[790][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[790][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[791][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[791][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[791][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[791][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[792][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[792][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[792][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[792][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[794][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[794][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[795][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[795][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[795][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[795][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[796][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[796][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[796][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[796][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[797][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[797][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[797][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[797][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[799][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[799][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[801][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[801][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[801][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[801][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[802][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[802][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[802][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[802][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[803][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[803][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[803][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[803][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[804][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[804][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[804][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[804][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[805][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[805][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[805][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[805][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[806][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[806][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[807][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[807][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[808][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[808][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[808][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[808][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[808][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[808][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[809][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[809][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[810][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[810][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[810][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[810][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[810][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[810][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[811][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[811][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[812][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[812][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[812][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[812][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[812][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[812][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[813][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[813][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[813][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[813][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[815][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[815][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[818][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[818][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[820][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[820][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[821][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[821][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[821][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[821][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[822][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[822][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[822][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[822][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[823][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[823][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[823][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[823][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[824][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[824][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[825][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[825][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[825][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[825][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[825][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[825][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[827][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[827][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[828][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[828][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[830][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[830][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[831][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[831][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[831][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[831][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[832][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[832][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[832][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[832][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[833][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[833][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[834][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[834][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[835][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[835][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[836][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[836][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[836][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[836][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[838][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[838][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[840][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[840][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[841][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[841][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[841][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[841][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[842][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[842][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[842][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[842][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[843][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[843][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[843][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[843][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[844][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[844][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[845][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[845][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[846][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[846][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[846][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[846][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[847][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[847][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[848][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[848][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[849][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[849][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[849][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[849][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[849][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[849][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[850][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[850][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[850][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[850][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[852][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[852][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[852][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[852][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[853][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[853][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[853][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[853][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[855][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[855][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[855][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[855][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[856][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[856][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[856][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[856][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[857][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[857][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[858][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[858][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[858][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[858][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[860][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[860][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[861][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[861][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[861][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[861][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[861][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[861][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[862][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[862][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[864][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[864][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[864][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[864][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[864][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[864][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[866][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[866][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[867][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[867][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[868][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[868][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[869][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[869][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[870][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[870][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[871][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[871][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[873][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[873][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[874][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[874][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[875][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[875][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[876][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[876][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[877][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[877][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[877][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[877][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[878][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[878][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[880][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[880][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[880][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[880][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[881][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[881][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[882][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[882][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[882][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[882][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[882][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[882][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[883][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[883][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[883][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[883][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[884][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[884][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[884][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[884][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[884][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[884][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[884][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[884][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[885][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[885][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[885][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[885][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[885][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[885][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[885][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[885][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[886][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[886][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[886][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[886][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[889][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[889][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[890][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[890][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[891][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[891][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[891][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[891][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[892][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[892][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[892][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[892][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[893][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[893][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[894][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[894][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[894][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[894][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[895][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[895][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[895][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[895][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[896][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[896][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[897][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[897][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[897][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[897][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[898][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[898][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[898][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[898][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[899][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[899][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[899][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[899][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[900][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[900][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[900][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[900][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[901][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[901][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[901][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[901][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[903][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[903][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[904][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[904][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[905][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[905][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[905][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[905][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[906][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[906][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[906][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[906][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[906][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[906][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[907][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[907][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[907][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[907][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[908][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[908][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[908][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[908][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[910][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[910][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[910][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[910][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[910][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[910][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[911][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[911][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[912][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[912][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[912][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[912][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[913][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[913][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[913][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[913][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[914][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[914][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[914][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[914][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[914][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[914][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[915][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[915][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[915][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[915][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[915][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[915][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[916][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[916][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[917][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[917][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[917][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[917][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[918][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[918][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[918][3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[918][3]~DUPLICATE ; ; ; -; cpu:cpu|vram[919][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[919][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[919][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[919][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[919][5] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[919][5]~DUPLICATE ; ; ; -; cpu:cpu|vram[919][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[919][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[920][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[920][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[921][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[921][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[922][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[922][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[922][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[922][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[923][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[923][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[924][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[924][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[925][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[925][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[927][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[927][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[928][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[928][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[928][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[928][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[929][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[929][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[929][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[929][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[929][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[929][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[930][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[930][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[930][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[930][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[931][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[931][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[932][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[932][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[932][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[932][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[933][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[933][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[935][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[935][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[935][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[935][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[936][3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[936][3]~DUPLICATE ; ; ; -; cpu:cpu|vram[937][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[937][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[938][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[938][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[938][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[938][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[939][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[939][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[940][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[940][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[940][3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[940][3]~DUPLICATE ; ; ; -; cpu:cpu|vram[940][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[940][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[940][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[940][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[941][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[941][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[941][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[941][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[942][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[942][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[942][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[942][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[943][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[943][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[944][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[944][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[944][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[944][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[945][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[945][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[945][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[945][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[946][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[946][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[946][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[946][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[946][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[946][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[947][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[947][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[947][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[947][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[947][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[947][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[948][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[948][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[948][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[948][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[949][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[949][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[949][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[949][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[950][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[950][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[950][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[950][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[950][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[950][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[951][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[951][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[951][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[951][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[952][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[952][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[955][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[955][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[955][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[955][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[956][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[956][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[957][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[957][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[957][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[957][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[958][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[958][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[959][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[959][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[959][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[959][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[959][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[959][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[960][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[960][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[960][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[960][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[961][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[961][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[962][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[962][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[962][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[962][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[963][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[963][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[963][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[963][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[964][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[964][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[965][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[965][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[965][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[965][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[965][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[965][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[966][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[966][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[966][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[966][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[967][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[967][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[968][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[968][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[968][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[968][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[969][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[969][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[969][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[969][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[969][5] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[969][5]~DUPLICATE ; ; ; -; cpu:cpu|vram[970][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[970][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[970][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[970][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[971][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[971][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[971][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[971][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[971][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[971][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[972][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[972][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[973][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[973][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[973][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[973][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[973][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[973][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[974][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[974][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[974][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[974][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[974][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[974][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[975][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[975][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[977][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[977][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[978][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[978][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[979][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[979][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[980][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[980][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[980][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[980][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[980][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[980][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[980][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[980][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[981][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[981][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[981][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[981][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[981][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[981][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[982][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[982][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[982][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[982][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[982][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[982][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[983][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[983][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[983][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[983][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[984][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[984][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[984][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[984][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[984][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[984][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[984][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[984][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[986][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[986][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[987][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[987][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[988][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[988][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[988][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[988][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[989][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[989][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[989][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[989][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[989][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[989][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[990][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[990][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[990][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[990][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[991][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[991][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[992][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[992][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[992][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[992][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[993][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[993][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[994][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[994][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[995][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[995][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[995][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[995][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[995][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[995][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[996][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[996][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[999][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[999][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[1001][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1001][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[1002][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1002][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[1003][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1003][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[1004][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1004][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[1004][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1004][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[1007][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1007][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[1007][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1007][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[1007][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1007][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[1008][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1008][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[1008][3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1008][3]~DUPLICATE ; ; ; -; cpu:cpu|vram[1008][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1008][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[1009][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1009][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[1009][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1009][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[1009][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1009][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[1010][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1010][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[1011][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1011][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[1011][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1011][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[1012][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1012][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[1012][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1012][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[1012][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1012][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[1012][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1012][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[1013][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1013][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[1014][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1014][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[1015][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1015][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[1015][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1015][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[1015][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1015][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[1016][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1016][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[1016][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1016][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[1016][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1016][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[1017][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1017][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[1018][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1018][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[1019][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1019][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[1019][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1019][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[1019][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1019][6]~DUPLICATE ; ; ; -; cpu:cpu|vram[1021][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1021][4]~DUPLICATE ; ; ; -; cpu:cpu|vram[1022][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1022][2]~DUPLICATE ; ; ; -; cpu:cpu|vram[1023][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1023][0]~DUPLICATE ; ; ; -; cpu:cpu|vram[1023][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1023][6]~DUPLICATE ; ; ; -+------------------------------------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+----------------------------------------------------------------+------------------+-----------------------+ ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Netlist Optimizations ; ++---------------------------------------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+-------------------------------------------------------------------+------------------+-----------------------+ +; Node ; Action ; Operation ; Reason ; Node Port ; Node Port Name ; Destination Node ; Destination Port ; Destination Port Name ; ++---------------------------------------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+-------------------------------------------------------------------+------------------+-----------------------+ +; downclocker:dc|clk_out~CLKENA0 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; +; fpga_clk~inputCLKENA0 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; +; cpu:cpu|alu:alu|cnt[23] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|alu:alu|cnt[23]~DUPLICATE ; ; ; +; cpu:cpu|alu:alu|cnt[28] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|alu:alu|cnt[28]~DUPLICATE ; ; ; +; cpu:cpu|alu:alu|cnt[30] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|alu:alu|cnt[30]~DUPLICATE ; ; ; +; cpu:cpu|draw_state.c[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|draw_state.c[1]~DUPLICATE ; ; ; +; cpu:cpu|draw_state.c[4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|draw_state.c[4]~DUPLICATE ; ; ; +; cpu:cpu|draw_state.r[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|draw_state.r[0]~DUPLICATE ; ; ; +; cpu:cpu|draw_state.r[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|draw_state.r[1]~DUPLICATE ; ; ; +; cpu:cpu|draw_state.r[3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|draw_state.r[3]~DUPLICATE ; ; ; +; cpu:cpu|instr.dst_reg[3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|instr.dst_reg[3]~DUPLICATE ; ; ; +; cpu:cpu|instr.src_sprite_idx[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|instr.src_sprite_idx[0]~DUPLICATE ; ; ; +; cpu:cpu|instr.src_sprite_idx[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|instr.src_sprite_idx[2]~DUPLICATE ; ; ; +; cpu:cpu|instr.src_sprite_idx[3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|instr.src_sprite_idx[3]~DUPLICATE ; ; ; +; cpu:cpu|instr.src_sprite_idx[4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|instr.src_sprite_idx[4]~DUPLICATE ; ; ; +; cpu:cpu|instr.src_sprite_sz[3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|instr.src_sprite_sz[3]~DUPLICATE ; ; ; +; cpu:cpu|instr.src_sprite_vx[3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|instr.src_sprite_vx[3]~DUPLICATE ; ; ; +; cpu:cpu|instr.src_sprite_vy[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|instr.src_sprite_vy[1]~DUPLICATE ; ; ; +; cpu:cpu|instr.src_sprite_vy[3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|instr.src_sprite_vy[3]~DUPLICATE ; ; ; +; cpu:cpu|opcode[3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|opcode[3]~DUPLICATE ; ; ; +; cpu:cpu|opcode[4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|opcode[4]~DUPLICATE ; ; ; +; cpu:cpu|opcode[7] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|opcode[7]~DUPLICATE ; ; ; +; cpu:cpu|opcode[13] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|opcode[13]~DUPLICATE ; ; ; +; cpu:cpu|program_counter[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|program_counter[2]~DUPLICATE ; ; ; +; cpu:cpu|program_counter[6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|program_counter[6]~DUPLICATE ; ; ; +; cpu:cpu|program_counter[7] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|program_counter[7]~DUPLICATE ; ; ; +; cpu:cpu|program_counter[8] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|program_counter[8]~DUPLICATE ; ; ; +; cpu:cpu|registers[0][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|registers[0][0]~DUPLICATE ; ; ; +; cpu:cpu|registers[1][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|registers[1][0]~DUPLICATE ; ; ; +; cpu:cpu|registers[2][5] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|registers[2][5]~DUPLICATE ; ; ; +; cpu:cpu|registers[8][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|registers[8][0]~DUPLICATE ; ; ; +; cpu:cpu|registers[10][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|registers[10][0]~DUPLICATE ; ; ; +; cpu:cpu|registers[10][1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|registers[10][1]~DUPLICATE ; ; ; +; cpu:cpu|registers[11][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|registers[11][0]~DUPLICATE ; ; ; +; cpu:cpu|registers[11][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|registers[11][2]~DUPLICATE ; ; ; +; cpu:cpu|registers[14][1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|registers[14][1]~DUPLICATE ; ; ; +; cpu:cpu|registers[14][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|registers[14][2]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|c[22] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|c[22]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|c[26] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|c[26]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|c[29] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|c[29]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|c[30] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|c[30]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|commander:com|i[6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|commander:com|i[6]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|commander:com|i[7] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|commander:com|i[7]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|commander:com|i[10] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|commander:com|i[10]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|commander:com|i[21] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|commander:com|i[21]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|commander:com|i[22] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|commander:com|i[22]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|commander:com|i[29] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|commander:com|i[29]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|commander:com|lcd_data ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|commander:com|lcd_data~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|i[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|i[0]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|i[4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|i[4]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|i[18] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|i[18]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|line_cnt[6]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[7] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|line_cnt[7]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[8] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|line_cnt[8]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[10] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|line_cnt[10]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[14] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|line_cnt[14]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[15] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|line_cnt[15]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[17] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|line_cnt[17]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[18] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|line_cnt[18]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[21] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|line_cnt[21]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[23] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|line_cnt[23]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[25] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|line_cnt[25]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[29] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|line_cnt[29]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[30] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|line_cnt[30]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[31] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|line_cnt[31]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|x[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|x[0]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|x[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|x[1]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|x[3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|x[3]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|x[4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|x[4]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|y[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|y[0]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|y[5] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|y[5]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|y[6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|y[6]~DUPLICATE ; ; ; +; cpu:cpu|state[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|state[0]~DUPLICATE ; ; ; +; cpu:cpu|state[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|state[1]~DUPLICATE ; ; ; +; cpu:cpu|state[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|state[2]~DUPLICATE ; ; ; +; cpu:cpu|state[3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|state[3]~DUPLICATE ; ; ; +; cpu:cpu|vram[0][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[0][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[0][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[0][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[4][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[4][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[4][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[4][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[5][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[5][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[7][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[7][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[8][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[8][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[9][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[9][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[10][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[10][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[11][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[11][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[11][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[11][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[12][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[12][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[16][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[16][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[18][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[18][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[18][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[18][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[19][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[19][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[19][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[19][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[22][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[22][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[22][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[22][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[22][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[22][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[22][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[22][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[23][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[23][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[24][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[24][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[25][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[25][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[25][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[25][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[25][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[25][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[27][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[27][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[28][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[28][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[29][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[29][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[31][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[31][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[32][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[32][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[34][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[34][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[36][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[36][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[39][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[39][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[40][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[40][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[41][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[41][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[44][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[44][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[45][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[45][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[46][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[46][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[47][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[47][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[47][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[47][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[47][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[47][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[48][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[48][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[49][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[49][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[49][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[49][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[50][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[50][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[51][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[51][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[52][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[52][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[52][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[52][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[53][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[53][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[53][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[53][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[54][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[54][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[54][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[54][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[55][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[55][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[55][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[55][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[56][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[56][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[57][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[57][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[57][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[57][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[58][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[58][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[60][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[60][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[61][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[61][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[63][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[63][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[64][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[64][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[64][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[64][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[65][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[65][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[66][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[66][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[67][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[67][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[68][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[68][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[70][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[70][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[70][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[70][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[71][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[71][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[72][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[72][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[72][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[72][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[72][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[72][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[72][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[72][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[73][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[73][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[73][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[73][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[74][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[74][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[75][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[75][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[76][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[76][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[76][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[76][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[78][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[78][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[79][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[79][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[80][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[80][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[83][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[83][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[85][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[85][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[86][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[86][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[87][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[87][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[87][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[87][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[88][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[88][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[90][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[90][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[92][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[92][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[92][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[92][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[95][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[95][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[95][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[95][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[98][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[98][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[99][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[99][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[100][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[100][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[101][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[101][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[102][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[102][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[102][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[102][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[103][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[103][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[104][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[104][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[105][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[105][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[106][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[106][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[108][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[108][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[108][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[108][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[109][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[109][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[109][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[109][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[112][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[112][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[115][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[115][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[116][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[116][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[117][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[117][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[118][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[118][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[119][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[119][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[119][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[119][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[121][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[121][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[121][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[121][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[122][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[122][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[122][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[122][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[123][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[123][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[123][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[123][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[125][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[125][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[125][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[125][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[126][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[126][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[126][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[126][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[127][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[127][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[128][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[128][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[129][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[129][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[132][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[132][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[133][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[133][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[133][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[133][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[134][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[134][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[135][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[135][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[135][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[135][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[136][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[136][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[137][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[137][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[138][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[138][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[140][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[140][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[140][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[140][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[142][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[142][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[143][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[143][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[143][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[143][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[145][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[145][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[145][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[145][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[145][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[145][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[146][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[146][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[146][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[146][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[147][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[147][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[148][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[148][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[149][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[149][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[149][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[149][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[150][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[150][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[150][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[150][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[151][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[151][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[151][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[151][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[151][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[151][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[152][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[152][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[152][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[152][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[154][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[154][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[155][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[155][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[156][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[156][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[159][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[159][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[160][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[160][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[161][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[161][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[161][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[161][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[161][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[161][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[162][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[162][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[165][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[165][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[166][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[166][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[166][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[166][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[167][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[167][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[169][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[169][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[169][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[169][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[170][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[170][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[170][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[170][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[171][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[171][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[172][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[172][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[174][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[174][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[174][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[174][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[174][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[174][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[175][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[175][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[175][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[175][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[176][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[176][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[177][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[177][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[178][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[178][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[178][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[178][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[179][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[179][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[180][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[180][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[180][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[180][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[182][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[182][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[183][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[183][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[184][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[184][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[184][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[184][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[184][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[184][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[184][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[184][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[185][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[185][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[185][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[185][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[186][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[186][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[186][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[186][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[188][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[188][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[188][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[188][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[189][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[189][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[190][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[190][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[190][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[190][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[190][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[190][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[192][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[192][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[193][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[193][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[193][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[193][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[195][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[195][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[195][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[195][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[196][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[196][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[196][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[196][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[197][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[197][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[198][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[198][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[199][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[199][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[201][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[201][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[202][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[202][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[202][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[202][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[202][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[202][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[203][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[203][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[204][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[204][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[205][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[205][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[206][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[206][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[209][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[209][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[210][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[210][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[211][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[211][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[212][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[212][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[214][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[214][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[214][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[214][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[216][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[216][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[216][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[216][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[216][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[216][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[217][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[217][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[217][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[217][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[217][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[217][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[219][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[219][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[221][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[221][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[224][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[224][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[225][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[225][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[225][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[225][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[226][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[226][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[228][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[228][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[229][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[229][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[229][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[229][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[230][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[230][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[231][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[231][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[233][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[233][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[236][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[236][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[237][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[237][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[238][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[238][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[238][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[238][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[238][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[238][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[239][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[239][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[240][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[240][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[240][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[240][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[241][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[241][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[242][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[242][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[242][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[242][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[248][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[248][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[248][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[248][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[250][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[250][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[254][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[254][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[256][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[256][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[256][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[256][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[257][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[257][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[258][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[258][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[258][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[258][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[259][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[259][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[259][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[259][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[260][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[260][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[260][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[260][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[263][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[263][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[263][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[263][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[263][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[263][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[264][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[264][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[264][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[264][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[265][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[265][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[266][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[266][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[266][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[266][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[267][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[267][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[267][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[267][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[268][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[268][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[269][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[269][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[271][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[271][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[272][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[272][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[273][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[273][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[274][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[274][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[274][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[274][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[275][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[275][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[276][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[276][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[276][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[276][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[277][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[277][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[278][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[278][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[279][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[279][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[281][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[281][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[283][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[283][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[284][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[284][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[286][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[286][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[286][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[286][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[286][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[286][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[286][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[286][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[287][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[287][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[287][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[287][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[287][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[287][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[289][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[289][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[292][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[292][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[294][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[294][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[296][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[296][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[296][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[296][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[296][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[296][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[298][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[298][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[298][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[298][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[298][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[298][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[298][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[298][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[299][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[299][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[300][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[300][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[301][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[301][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[302][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[302][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[302][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[302][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[302][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[302][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[304][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[304][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[304][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[304][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[304][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[304][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[305][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[305][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[305][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[305][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[306][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[306][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[306][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[306][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[307][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[307][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[308][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[308][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[309][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[309][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[309][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[309][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[310][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[310][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[310][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[310][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[312][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[312][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[312][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[312][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[312][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[312][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[313][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[313][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[313][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[313][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[315][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[315][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[317][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[317][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[317][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[317][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[318][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[318][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[319][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[319][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[321][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[321][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[322][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[322][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[323][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[323][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[323][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[323][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[324][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[324][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[325][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[325][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[326][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[326][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[327][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[327][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[327][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[327][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[329][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[329][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[332][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[332][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[332][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[332][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[333][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[333][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[336][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[336][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[338][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[338][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[339][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[339][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[339][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[339][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[339][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[339][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[340][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[340][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[340][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[340][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[341][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[341][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[341][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[341][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[341][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[341][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[342][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[342][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[343][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[343][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[344][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[344][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[347][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[347][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[347][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[347][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[348][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[348][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[349][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[349][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[349][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[349][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[350][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[350][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[350][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[350][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[352][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[352][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[353][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[353][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[354][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[354][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[355][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[355][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[357][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[357][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[359][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[359][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[360][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[360][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[361][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[361][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[362][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[362][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[363][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[363][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[363][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[363][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[365][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[365][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[365][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[365][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[367][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[367][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[368][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[368][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[371][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[371][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[371][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[371][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[371][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[371][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[372][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[372][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[373][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[373][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[373][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[373][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[373][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[373][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[374][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[374][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[374][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[374][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[376][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[376][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[376][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[376][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[377][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[377][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[378][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[378][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[379][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[379][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[379][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[379][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[380][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[380][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[381][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[381][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[381][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[381][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[382][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[382][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[383][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[383][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[383][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[383][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[384][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[384][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[384][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[384][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[385][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[385][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[385][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[385][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[386][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[386][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[388][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[388][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[389][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[389][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[389][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[389][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[391][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[391][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[392][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[392][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[392][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[392][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[393][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[393][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[396][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[396][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[396][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[396][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[397][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[397][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[400][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[400][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[400][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[400][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[400][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[400][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[401][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[401][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[401][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[401][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[402][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[402][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[403][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[403][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[403][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[403][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[404][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[404][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[405][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[405][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[405][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[405][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[405][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[405][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[407][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[407][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[408][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[408][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[409][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[409][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[409][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[409][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[413][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[413][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[413][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[413][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[415][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[415][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[417][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[417][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[418][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[418][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[418][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[418][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[420][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[420][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[420][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[420][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[421][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[421][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[422][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[422][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[423][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[423][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[423][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[423][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[423][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[423][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[424][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[424][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[426][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[426][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[427][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[427][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[427][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[427][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[428][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[428][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[428][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[428][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[429][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[429][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[429][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[429][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[430][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[430][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[430][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[430][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[431][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[431][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[433][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[433][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[435][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[435][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[438][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[438][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[440][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[440][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[441][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[441][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[442][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[442][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[443][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[443][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[444][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[444][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[445][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[445][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[445][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[445][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[445][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[445][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[447][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[447][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[448][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[448][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[448][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[448][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[449][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[449][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[454][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[454][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[456][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[456][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[456][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[456][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[457][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[457][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[459][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[459][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[460][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[460][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[460][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[460][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[460][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[460][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[460][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[460][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[461][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[461][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[463][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[463][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[464][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[464][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[466][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[466][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[466][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[466][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[467][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[467][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[468][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[468][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[469][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[469][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[469][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[469][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[470][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[470][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[470][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[470][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[471][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[471][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[472][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[472][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[474][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[474][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[475][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[475][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[475][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[475][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[478][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[478][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[480][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[480][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[481][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[481][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[482][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[482][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[484][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[484][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[485][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[485][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[486][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[486][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[488][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[488][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[488][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[488][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[489][7] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[489][7]~DUPLICATE ; ; ; +; cpu:cpu|vram[490][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[490][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[491][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[491][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[494][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[494][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[494][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[494][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[496][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[496][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[498][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[498][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[499][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[499][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[500][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[500][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[500][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[500][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[501][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[501][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[502][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[502][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[504][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[504][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[507][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[507][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[509][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[509][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[509][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[509][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[510][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[510][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[510][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[510][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[510][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[510][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[513][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[513][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[513][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[513][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[514][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[514][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[514][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[514][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[516][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[516][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[519][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[519][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[519][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[519][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[520][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[520][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[520][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[520][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[521][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[521][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[522][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[522][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[522][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[522][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[522][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[522][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[523][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[523][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[525][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[525][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[526][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[526][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[526][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[526][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[527][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[527][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[528][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[528][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[528][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[528][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[529][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[529][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[531][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[531][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[532][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[532][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[533][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[533][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[534][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[534][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[540][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[540][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[540][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[540][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[542][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[542][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[543][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[543][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[543][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[543][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[543][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[543][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[544][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[544][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[545][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[545][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[546][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[546][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[546][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[546][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[547][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[547][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[547][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[547][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[548][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[548][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[549][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[549][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[550][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[550][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[551][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[551][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[553][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[553][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[554][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[554][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[554][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[554][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[555][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[555][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[555][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[555][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[556][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[556][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[558][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[558][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[560][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[560][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[563][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[563][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[564][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[564][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[565][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[565][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[566][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[566][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[566][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[566][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[566][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[566][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[566][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[566][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[568][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[568][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[568][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[568][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[569][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[569][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[569][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[569][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[569][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[569][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[571][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[571][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[571][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[571][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[572][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[572][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[573][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[573][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[575][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[575][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[576][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[576][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[577][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[577][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[577][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[577][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[578][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[578][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[579][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[579][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[580][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[580][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[580][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[580][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[582][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[582][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[583][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[583][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[583][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[583][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[586][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[586][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[587][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[587][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[588][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[588][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[589][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[589][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[589][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[589][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[590][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[590][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[591][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[591][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[592][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[592][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[593][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[593][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[594][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[594][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[595][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[595][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[596][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[596][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[597][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[597][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[597][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[597][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[598][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[598][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[598][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[598][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[599][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[599][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[599][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[599][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[600][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[600][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[601][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[601][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[604][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[604][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[604][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[604][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[604][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[604][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[605][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[605][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[606][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[606][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[606][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[606][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[607][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[607][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[608][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[608][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[608][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[608][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[611][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[611][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[611][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[611][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[612][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[612][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[613][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[613][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[613][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[613][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[613][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[613][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[614][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[614][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[614][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[614][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[615][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[615][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[616][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[616][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[616][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[616][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[617][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[617][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[618][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[618][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[618][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[618][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[619][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[619][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[619][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[619][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[621][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[621][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[621][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[621][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[627][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[627][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[628][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[628][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[628][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[628][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[630][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[630][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[632][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[632][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[634][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[634][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[634][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[634][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[634][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[634][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[635][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[635][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[635][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[635][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[636][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[636][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[636][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[636][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[636][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[636][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[637][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[637][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[637][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[637][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[638][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[638][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[639][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[639][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[639][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[639][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[639][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[639][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[640][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[640][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[640][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[640][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[642][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[642][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[643][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[643][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[644][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[644][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[645][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[645][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[647][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[647][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[647][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[647][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[648][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[648][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[649][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[649][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[650][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[650][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[652][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[652][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[655][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[655][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[656][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[656][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[658][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[658][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[659][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[659][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[659][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[659][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[660][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[660][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[661][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[661][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[661][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[661][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[661][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[661][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[663][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[663][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[664][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[664][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[664][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[664][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[665][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[665][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[665][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[665][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[666][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[666][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[667][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[667][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[667][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[667][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[668][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[668][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[669][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[669][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[671][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[671][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[672][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[672][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[672][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[672][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[674][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[674][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[674][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[674][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[675][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[675][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[677][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[677][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[677][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[677][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[681][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[681][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[681][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[681][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[682][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[682][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[682][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[682][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[683][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[683][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[684][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[684][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[687][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[687][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[687][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[687][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[687][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[687][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[689][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[689][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[690][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[690][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[696][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[696][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[697][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[697][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[698][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[698][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[700][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[700][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[702][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[702][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[703][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[703][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[704][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[704][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[705][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[705][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[705][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[705][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[707][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[707][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[709][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[709][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[711][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[711][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[712][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[712][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[713][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[713][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[714][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[714][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[718][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[718][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[718][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[718][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[719][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[719][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[720][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[720][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[720][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[720][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[721][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[721][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[721][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[721][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[722][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[722][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[723][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[723][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[724][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[724][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[724][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[724][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[724][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[724][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[725][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[725][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[725][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[725][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[725][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[725][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[727][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[727][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[727][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[727][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[727][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[727][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[728][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[728][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[728][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[728][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[729][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[729][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[729][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[729][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[729][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[729][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[730][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[730][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[731][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[731][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[732][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[732][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[732][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[732][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[733][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[733][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[733][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[733][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[734][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[734][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[735][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[735][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[736][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[736][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[736][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[736][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[736][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[736][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[736][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[736][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[737][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[737][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[737][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[737][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[738][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[738][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[739][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[739][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[739][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[739][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[739][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[739][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[740][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[740][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[740][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[740][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[741][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[741][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[742][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[742][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[742][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[742][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[743][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[743][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[743][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[743][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[743][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[743][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[744][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[744][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[744][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[744][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[744][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[744][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[745][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[745][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[745][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[745][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[746][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[746][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[747][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[747][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[747][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[747][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[748][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[748][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[748][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[748][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[749][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[749][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[749][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[749][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[750][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[750][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[751][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[751][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[752][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[752][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[752][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[752][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[753][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[753][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[753][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[753][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[754][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[754][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[754][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[754][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[755][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[755][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[757][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[757][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[758][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[758][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[759][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[759][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[760][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[760][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[761][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[761][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[762][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[762][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[762][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[762][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[762][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[762][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[762][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[762][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[763][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[763][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[763][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[763][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[763][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[763][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[764][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[764][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[764][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[764][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[765][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[765][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[765][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[765][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[767][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[767][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[767][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[767][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[768][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[768][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[768][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[768][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[769][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[769][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[770][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[770][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[772][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[772][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[772][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[772][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[773][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[773][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[773][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[773][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[773][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[773][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[776][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[776][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[776][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[776][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[777][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[777][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[777][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[777][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[779][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[779][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[780][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[780][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[780][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[780][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[781][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[781][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[782][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[782][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[783][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[783][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[783][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[783][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[784][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[784][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[784][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[784][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[785][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[785][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[785][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[785][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[786][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[786][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[786][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[786][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[787][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[787][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[788][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[788][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[788][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[788][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[791][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[791][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[792][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[792][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[792][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[792][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[793][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[793][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[793][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[793][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[794][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[794][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[795][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[795][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[796][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[796][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[797][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[797][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[797][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[797][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[800][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[800][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[800][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[800][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[801][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[801][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[801][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[801][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[802][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[802][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[802][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[802][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[803][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[803][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[803][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[803][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[804][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[804][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[804][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[804][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[805][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[805][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[805][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[805][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[806][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[806][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[806][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[806][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[807][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[807][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[808][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[808][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[808][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[808][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[809][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[809][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[809][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[809][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[810][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[810][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[811][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[811][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[811][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[811][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[811][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[811][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[812][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[812][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[813][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[813][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[813][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[813][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[816][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[816][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[817][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[817][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[817][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[817][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[817][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[817][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[819][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[819][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[819][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[819][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[819][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[819][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[820][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[820][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[820][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[820][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[822][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[822][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[822][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[822][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[823][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[823][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[823][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[823][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[824][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[824][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[824][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[824][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[825][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[825][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[825][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[825][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[825][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[825][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[826][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[826][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[827][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[827][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[827][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[827][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[828][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[828][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[828][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[828][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[829][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[829][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[829][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[829][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[830][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[830][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[830][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[830][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[832][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[832][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[833][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[833][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[833][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[833][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[834][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[834][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[835][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[835][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[836][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[836][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[838][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[838][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[838][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[838][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[839][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[839][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[841][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[841][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[841][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[841][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[843][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[843][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[843][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[843][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[844][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[844][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[845][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[845][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[846][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[846][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[847][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[847][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[848][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[848][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[848][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[848][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[849][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[849][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[849][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[849][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[850][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[850][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[850][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[850][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[851][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[851][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[851][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[851][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[852][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[852][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[852][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[852][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[852][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[852][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[853][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[853][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[853][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[853][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[853][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[853][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[854][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[854][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[855][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[855][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[855][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[855][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[855][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[855][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[856][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[856][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[856][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[856][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[857][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[857][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[857][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[857][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[858][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[858][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[861][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[861][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[862][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[862][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[864][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[864][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[865][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[865][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[865][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[865][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[866][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[866][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[866][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[866][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[867][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[867][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[867][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[867][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[868][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[868][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[868][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[868][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[869][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[869][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[869][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[869][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[869][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[869][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[870][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[870][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[870][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[870][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[871][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[871][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[872][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[872][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[873][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[873][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[873][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[873][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[874][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[874][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[875][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[875][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[875][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[875][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[876][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[876][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[877][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[877][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[880][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[880][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[880][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[880][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[881][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[881][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[883][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[883][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[883][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[883][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[883][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[883][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[884][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[884][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[885][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[885][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[885][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[885][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[886][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[886][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[888][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[888][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[890][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[890][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[890][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[890][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[891][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[891][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[892][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[892][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[892][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[892][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[892][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[892][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[893][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[893][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[894][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[894][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[895][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[895][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[897][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[897][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[897][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[897][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[897][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[897][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[898][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[898][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[898][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[898][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[898][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[898][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[899][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[899][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[899][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[899][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[900][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[900][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[900][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[900][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[901][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[901][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[901][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[901][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[901][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[901][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[902][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[902][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[902][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[902][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[903][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[903][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[904][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[904][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[904][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[904][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[904][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[904][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[905][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[905][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[905][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[905][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[906][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[906][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[906][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[906][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[907][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[907][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[907][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[907][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[908][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[908][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[909][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[909][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[910][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[910][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[911][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[911][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[913][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[913][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[915][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[915][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[916][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[916][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[916][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[916][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[917][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[917][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[917][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[917][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[918][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[918][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[918][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[918][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[919][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[919][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[920][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[920][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[921][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[921][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[922][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[922][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[923][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[923][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[923][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[923][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[924][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[924][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[925][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[925][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[925][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[925][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[926][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[926][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[926][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[926][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[926][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[926][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[926][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[926][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[927][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[927][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[927][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[927][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[928][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[928][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[928][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[928][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[929][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[929][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[929][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[929][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[930][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[930][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[930][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[930][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[931][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[931][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[932][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[932][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[933][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[933][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[933][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[933][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[933][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[933][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[934][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[934][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[935][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[935][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[936][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[936][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[936][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[936][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[936][5] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[936][5]~DUPLICATE ; ; ; +; cpu:cpu|vram[936][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[936][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[937][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[937][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[938][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[938][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[939][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[939][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[939][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[939][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[939][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[939][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[940][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[940][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[940][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[940][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[941][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[941][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[942][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[942][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[942][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[942][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[942][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[942][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[943][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[943][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[943][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[943][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[943][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[943][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[943][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[943][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[944][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[944][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[944][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[944][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[945][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[945][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[945][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[945][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[946][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[946][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[947][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[947][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[947][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[947][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[948][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[948][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[948][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[948][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[948][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[948][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[949][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[949][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[949][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[949][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[950][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[950][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[950][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[950][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[950][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[950][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[951][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[951][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[951][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[951][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[952][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[952][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[954][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[954][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[954][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[954][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[955][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[955][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[956][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[956][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[956][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[956][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[956][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[956][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[957][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[957][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[957][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[957][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[958][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[958][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[958][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[958][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[958][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[958][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[959][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[959][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[959][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[959][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[960][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[960][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[960][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[960][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[961][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[961][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[961][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[961][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[962][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[962][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[962][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[962][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[963][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[963][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[963][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[963][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[964][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[964][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[964][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[964][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[965][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[965][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[965][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[965][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[965][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[965][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[966][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[966][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[966][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[966][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[967][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[967][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[968][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[968][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[968][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[968][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[969][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[969][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[969][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[969][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[970][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[970][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[970][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[970][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[971][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[971][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[971][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[971][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[971][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[971][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[971][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[971][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[972][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[972][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[972][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[972][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[973][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[973][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[973][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[973][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[974][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[974][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[974][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[974][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[974][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[974][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[975][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[975][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[975][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[975][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[975][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[975][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[976][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[976][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[976][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[976][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[977][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[977][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[977][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[977][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[977][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[977][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[978][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[978][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[978][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[978][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[978][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[978][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[979][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[979][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[979][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[979][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[979][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[979][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[980][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[980][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[980][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[980][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[980][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[980][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[981][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[981][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[982][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[982][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[982][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[982][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[983][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[983][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[983][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[983][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[984][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[984][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[984][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[984][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[985][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[985][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[986][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[986][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[987][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[987][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[988][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[988][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[988][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[988][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[988][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[988][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[988][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[988][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[989][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[989][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[990][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[990][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[991][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[991][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[992][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[992][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[993][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[993][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[994][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[994][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[994][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[994][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[995][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[995][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[995][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[995][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[995][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[995][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[996][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[996][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[996][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[996][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[997][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[997][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[997][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[997][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[997][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[997][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[998][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[998][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[998][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[998][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[998][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[998][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[998][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[998][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[999][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[999][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[999][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[999][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[1000][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1000][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[1000][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1000][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[1001][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1001][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[1002][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1002][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[1002][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1002][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[1002][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1002][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[1003][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1003][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[1003][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1003][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[1004][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1004][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[1004][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1004][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[1004][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1004][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[1005][1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1005][1]~DUPLICATE ; ; ; +; cpu:cpu|vram[1005][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1005][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[1005][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1005][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[1005][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1005][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[1006][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1006][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[1006][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1006][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[1007][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1007][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[1008][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1008][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[1008][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1008][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[1009][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1009][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[1009][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1009][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[1010][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1010][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[1010][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1010][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[1010][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1010][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[1010][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1010][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[1011][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1011][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[1011][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1011][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[1012][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1012][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[1012][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1012][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[1012][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1012][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[1013][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1013][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[1013][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1013][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[1013][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1013][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[1013][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1013][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[1014][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1014][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[1014][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1014][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[1014][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1014][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[1015][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1015][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[1016][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1016][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[1016][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1016][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[1017][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1017][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[1017][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1017][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[1017][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1017][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[1018][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1018][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[1021][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1021][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[1022][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1022][6]~DUPLICATE ; ; ; ++---------------------------------------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+-------------------------------------------------------------------+------------------+-----------------------+ +--------------------------------------------------------------------------------------------+ @@ -1478,8 +1532,8 @@ https://fpgasoftware.intel.com/eula. ; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ; +---------------------+----------------------+----------------------------+--------------------------+ ; Placement (by node) ; ; ; ; -; -- Requested ; 0.00 % ( 0 / 25822 ) ; 0.00 % ( 0 / 25822 ) ; 0.00 % ( 0 / 25822 ) ; -; -- Achieved ; 0.00 % ( 0 / 25822 ) ; 0.00 % ( 0 / 25822 ) ; 0.00 % ( 0 / 25822 ) ; +; -- Requested ; 0.00 % ( 0 / 26073 ) ; 0.00 % ( 0 / 26073 ) ; 0.00 % ( 0 / 26073 ) ; +; -- Achieved ; 0.00 % ( 0 / 26073 ) ; 0.00 % ( 0 / 26073 ) ; 0.00 % ( 0 / 26073 ) ; ; ; ; ; ; ; Routing (by net) ; ; ; ; ; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; @@ -1502,7 +1556,7 @@ https://fpgasoftware.intel.com/eula. +--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ ; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ; +--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ -; Top ; 0.00 % ( 0 / 25822 ) ; N/A ; Source File ; N/A ; ; +; Top ; 0.00 % ( 0 / 26073 ) ; N/A ; Source File ; N/A ; ; ; hard_block:auto_generated_inst ; 0.00 % ( 0 / 0 ) ; N/A ; Source File ; N/A ; ; +--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ @@ -1518,41 +1572,41 @@ The pin-out file can be found in /home/nickorlow/programming/school/warminster/y +-------------------------------------------------------------+-----------------------+-------+ ; Resource ; Usage ; % ; +-------------------------------------------------------------+-----------------------+-------+ -; Logic utilization (ALMs needed / total ALMs on device) ; 10,549 / 41,910 ; 25 % ; -; ALMs needed [=A-B+C] ; 10,549 ; ; -; [A] ALMs used in final placement [=a+b+c+d] ; 11,599 / 41,910 ; 28 % ; -; [a] ALMs used for LUT logic and registers ; 4,235 ; ; -; [b] ALMs used for LUT logic ; 7,235 ; ; -; [c] ALMs used for registers ; 129 ; ; +; Logic utilization (ALMs needed / total ALMs on device) ; 10,693 / 41,910 ; 26 % ; +; ALMs needed [=A-B+C] ; 10,693 ; ; +; [A] ALMs used in final placement [=a+b+c+d] ; 11,707 / 41,910 ; 28 % ; +; [a] ALMs used for LUT logic and registers ; 4,258 ; ; +; [b] ALMs used for LUT logic ; 7,290 ; ; +; [c] ALMs used for registers ; 159 ; ; ; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; ; -; [B] Estimate of ALMs recoverable by dense packing ; 1,192 / 41,910 ; 3 % ; -; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 142 / 41,910 ; < 1 % ; +; [B] Estimate of ALMs recoverable by dense packing ; 1,199 / 41,910 ; 3 % ; +; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 185 / 41,910 ; < 1 % ; ; [a] Due to location constrained logic ; 0 ; ; ; [b] Due to LAB-wide signal conflicts ; 0 ; ; -; [c] Due to LAB input limits ; 142 ; ; +; [c] Due to LAB input limits ; 185 ; ; ; [d] Due to virtual I/Os ; 0 ; ; ; ; ; ; ; Difficulty packing design ; Low ; ; ; ; ; ; -; Total LABs: partially or completely used ; 1,382 / 4,191 ; 33 % ; -; -- Logic LABs ; 1,382 ; ; +; Total LABs: partially or completely used ; 1,438 / 4,191 ; 34 % ; +; -- Logic LABs ; 1,438 ; ; ; -- Memory LABs (up to half of total LABs) ; 0 ; ; ; ; ; ; -; Combinational ALUT usage for logic ; 17,065 ; ; -; -- 7 input functions ; 58 ; ; -; -- 6 input functions ; 3,654 ; ; -; -- 5 input functions ; 5,900 ; ; -; -- 4 input functions ; 2,000 ; ; -; -- <=3 input functions ; 5,453 ; ; -; Combinational ALUT usage for route-throughs ; 106 ; ; +; Combinational ALUT usage for logic ; 17,207 ; ; +; -- 7 input functions ; 56 ; ; +; -- 6 input functions ; 3,707 ; ; +; -- 5 input functions ; 5,934 ; ; +; -- 4 input functions ; 2,008 ; ; +; -- <=3 input functions ; 5,502 ; ; +; Combinational ALUT usage for route-throughs ; 95 ; ; ; ; ; ; -; Dedicated logic registers ; 10,004 ; ; +; Dedicated logic registers ; 10,165 ; ; ; -- By type: ; ; ; -; -- Primary logic registers ; 8,728 / 83,820 ; 10 % ; -; -- Secondary logic registers ; 1,276 / 83,820 ; 2 % ; +; -- Primary logic registers ; 8,832 / 83,820 ; 11 % ; +; -- Secondary logic registers ; 1,333 / 83,820 ; 2 % ; ; -- By function: ; ; ; -; -- Design implementation registers ; 8,728 ; ; -; -- Routing optimization registers ; 1,276 ; ; +; -- Design implementation registers ; 8,836 ; ; +; -- Routing optimization registers ; 1,329 ; ; ; ; ; ; ; Virtual pins ; 0 ; ; ; I/O pins ; 10 / 314 ; 3 % ; @@ -1594,8 +1648,8 @@ The pin-out file can be found in /home/nickorlow/programming/school/warminster/y ; Total DSP Blocks ; 0 / 112 ; 0 % ; ; ; ; ; ; Fractional PLLs ; 0 / 6 ; 0 % ; -; Global signals ; 1 ; ; -; -- Global clocks ; 1 / 16 ; 6 % ; +; Global signals ; 2 ; ; +; -- Global clocks ; 2 / 16 ; 13 % ; ; -- Quadrant clocks ; 0 / 66 ; 0 % ; ; -- Horizontal periphery clocks ; 0 / 18 ; 0 % ; ; SERDES Transmitters ; 0 / 100 ; 0 % ; @@ -1607,12 +1661,12 @@ The pin-out file can be found in /home/nickorlow/programming/school/warminster/y ; Oscillator blocks ; 0 / 1 ; 0 % ; ; Impedance control blocks ; 0 / 4 ; 0 % ; ; Hard Memory Controllers ; 0 / 1 ; 0 % ; -; Average interconnect usage (total/H/V) ; 14.5% / 14.3% / 14.9% ; ; -; Peak interconnect usage (total/H/V) ; 63.5% / 63.1% / 64.9% ; ; -; Maximum fan-out ; 9791 ; ; -; Highest non-global fan-out ; 9095 ; ; -; Total fan-out ; 106041 ; ; -; Average fan-out ; 3.90 ; ; +; Average interconnect usage (total/H/V) ; 14.1% / 14.1% / 14.2% ; ; +; Peak interconnect usage (total/H/V) ; 63.8% / 64.3% / 65.7% ; ; +; Maximum fan-out ; 9941 ; ; +; Highest non-global fan-out ; 9160 ; ; +; Total fan-out ; 107054 ; ; +; Average fan-out ; 3.89 ; ; +-------------------------------------------------------------+-----------------------+-------+ @@ -1621,44 +1675,44 @@ The pin-out file can be found in /home/nickorlow/programming/school/warminster/y +-------------------------------------------------------------+------------------------+--------------------------------+ ; Statistic ; Top ; hard_block:auto_generated_inst ; +-------------------------------------------------------------+------------------------+--------------------------------+ -; Logic utilization (ALMs needed / total ALMs on device) ; 10549 / 41910 ( 25 % ) ; 0 / 41910 ( 0 % ) ; -; ALMs needed [=A-B+C] ; 10549 ; 0 ; -; [A] ALMs used in final placement [=a+b+c+d] ; 11599 / 41910 ( 28 % ) ; 0 / 41910 ( 0 % ) ; -; [a] ALMs used for LUT logic and registers ; 4235 ; 0 ; -; [b] ALMs used for LUT logic ; 7235 ; 0 ; -; [c] ALMs used for registers ; 129 ; 0 ; +; Logic utilization (ALMs needed / total ALMs on device) ; 10693 / 41910 ( 26 % ) ; 0 / 41910 ( 0 % ) ; +; ALMs needed [=A-B+C] ; 10693 ; 0 ; +; [A] ALMs used in final placement [=a+b+c+d] ; 11707 / 41910 ( 28 % ) ; 0 / 41910 ( 0 % ) ; +; [a] ALMs used for LUT logic and registers ; 4258 ; 0 ; +; [b] ALMs used for LUT logic ; 7290 ; 0 ; +; [c] ALMs used for registers ; 159 ; 0 ; ; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; 0 ; -; [B] Estimate of ALMs recoverable by dense packing ; 1192 / 41910 ( 3 % ) ; 0 / 41910 ( 0 % ) ; -; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 142 / 41910 ( < 1 % ) ; 0 / 41910 ( 0 % ) ; +; [B] Estimate of ALMs recoverable by dense packing ; 1199 / 41910 ( 3 % ) ; 0 / 41910 ( 0 % ) ; +; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 185 / 41910 ( < 1 % ) ; 0 / 41910 ( 0 % ) ; ; [a] Due to location constrained logic ; 0 ; 0 ; ; [b] Due to LAB-wide signal conflicts ; 0 ; 0 ; -; [c] Due to LAB input limits ; 142 ; 0 ; +; [c] Due to LAB input limits ; 185 ; 0 ; ; [d] Due to virtual I/Os ; 0 ; 0 ; ; ; ; ; ; Difficulty packing design ; Low ; Low ; ; ; ; ; -; Total LABs: partially or completely used ; 1382 / 4191 ( 33 % ) ; 0 / 4191 ( 0 % ) ; -; -- Logic LABs ; 1382 ; 0 ; +; Total LABs: partially or completely used ; 1438 / 4191 ( 34 % ) ; 0 / 4191 ( 0 % ) ; +; -- Logic LABs ; 1438 ; 0 ; ; -- Memory LABs (up to half of total LABs) ; 0 ; 0 ; ; ; ; ; -; Combinational ALUT usage for logic ; 17065 ; 0 ; -; -- 7 input functions ; 58 ; 0 ; -; -- 6 input functions ; 3654 ; 0 ; -; -- 5 input functions ; 5900 ; 0 ; -; -- 4 input functions ; 2000 ; 0 ; -; -- <=3 input functions ; 5453 ; 0 ; -; Combinational ALUT usage for route-throughs ; 106 ; 0 ; +; Combinational ALUT usage for logic ; 17207 ; 0 ; +; -- 7 input functions ; 56 ; 0 ; +; -- 6 input functions ; 3707 ; 0 ; +; -- 5 input functions ; 5934 ; 0 ; +; -- 4 input functions ; 2008 ; 0 ; +; -- <=3 input functions ; 5502 ; 0 ; +; Combinational ALUT usage for route-throughs ; 95 ; 0 ; ; Memory ALUT usage ; 0 ; 0 ; ; -- 64-address deep ; 0 ; 0 ; ; -- 32-address deep ; 0 ; 0 ; ; ; ; ; ; Dedicated logic registers ; 0 ; 0 ; ; -- By type: ; ; ; -; -- Primary logic registers ; 8728 / 83820 ( 10 % ) ; 0 / 83820 ( 0 % ) ; -; -- Secondary logic registers ; 1276 / 83820 ( 2 % ) ; 0 / 83820 ( 0 % ) ; +; -- Primary logic registers ; 8832 / 83820 ( 11 % ) ; 0 / 83820 ( 0 % ) ; +; -- Secondary logic registers ; 1333 / 83820 ( 2 % ) ; 0 / 83820 ( 0 % ) ; ; -- By function: ; ; ; -; -- Design implementation registers ; 8728 ; 0 ; -; -- Routing optimization registers ; 1276 ; 0 ; +; -- Design implementation registers ; 8836 ; 0 ; +; -- Routing optimization registers ; 1329 ; 0 ; ; ; ; ; ; ; ; ; ; Virtual pins ; 0 ; 0 ; @@ -1667,7 +1721,7 @@ The pin-out file can be found in /home/nickorlow/programming/school/warminster/y ; Total block memory bits ; 32768 ; 0 ; ; Total block memory implementation bits ; 40960 ; 0 ; ; M10K block ; 4 / 553 ( < 1 % ) ; 0 / 553 ( 0 % ) ; -; Clock enable block ; 1 / 116 ( < 1 % ) ; 0 / 116 ( 0 % ) ; +; Clock enable block ; 2 / 116 ( 1 % ) ; 0 / 116 ( 0 % ) ; ; ; ; ; ; Connections ; ; ; ; -- Input Connections ; 0 ; 0 ; @@ -1676,8 +1730,8 @@ The pin-out file can be found in /home/nickorlow/programming/school/warminster/y ; -- Registered Output Connections ; 0 ; 0 ; ; ; ; ; ; Internal Connections ; ; ; -; -- Total Connections ; 106154 ; 0 ; -; -- Registered Connections ; 24291 ; 0 ; +; -- Total Connections ; 107167 ; 0 ; +; -- Registered Connections ; 24776 ; 0 ; ; ; ; ; ; External Connections ; ; ; ; -- Top ; 0 ; 0 ; @@ -1709,7 +1763,7 @@ The pin-out file can be found in /home/nickorlow/programming/school/warminster/y +----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+ ; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ; +----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+ -; fpga_clk ; V11 ; 3B ; 32 ; 0 ; 0 ; 9792 ; 0 ; yes ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; User ; no ; +; fpga_clk ; V11 ; 3B ; 32 ; 0 ; 0 ; 21 ; 0 ; yes ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; User ; no ; ; rst_in ; W20 ; 5B ; 89 ; 23 ; 20 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; User ; no ; +----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+ @@ -2456,10 +2510,12 @@ Note: Pin directions (input, output or bidir) are based on device operating in u +-------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-----------------------------------------------------------------------+----------------------+--------------+ ; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ; +-------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-----------------------------------------------------------------------+----------------------+--------------+ -; |chip8 ; 10548.6 (0.5) ; 11599.5 (0.5) ; 1192.4 (0.0) ; 141.5 (0.0) ; 0.0 (0.0) ; 17065 (1) ; 10004 (0) ; 0 (0) ; 32768 ; 4 ; 0 ; 10 ; 0 ; |chip8 ; chip8 ; work ; -; |cpu:cpu| ; 10548.1 (6640.6) ; 11599.0 (7583.7) ; 1192.4 (997.1) ; 141.5 (54.0) ; 0.0 (0.0) ; 17064 (11448) ; 10004 (9778) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |chip8|cpu:cpu ; cpu ; work ; -; |st7920_serial_driver:gpu| ; 3907.5 (3877.7) ; 4015.3 (3982.5) ; 195.4 (192.4) ; 87.5 (87.5) ; 0.0 (0.0) ; 5616 (5570) ; 226 (161) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |chip8|cpu:cpu|st7920_serial_driver:gpu ; st7920_serial_driver ; work ; -; |commander:com| ; 29.8 (29.8) ; 32.8 (32.8) ; 3.0 (3.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 46 (46) ; 65 (65) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |chip8|cpu:cpu|st7920_serial_driver:gpu|commander:com ; commander ; work ; +; |chip8 ; 10693.1 (0.5) ; 11706.5 (0.5) ; 1198.4 (0.0) ; 185.0 (0.0) ; 0.0 (0.0) ; 17207 (1) ; 10165 (0) ; 0 (0) ; 32768 ; 4 ; 0 ; 10 ; 0 ; |chip8 ; chip8 ; work ; +; |cpu:cpu| ; 10687.0 (6736.9) ; 11699.5 (7691.4) ; 1197.4 (1037.4) ; 185.0 (82.9) ; 0.0 (0.0) ; 17195 (11517) ; 10154 (9885) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |chip8|cpu:cpu ; cpu ; work ; +; |alu:alu| ; 26.3 (26.3) ; 29.6 (29.6) ; 3.3 (3.3) ; 0.1 (0.1) ; 0.0 (0.0) ; 47 (47) ; 52 (52) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |chip8|cpu:cpu|alu:alu ; alu ; work ; +; |st7920_serial_driver:gpu| ; 3923.8 (3893.6) ; 3978.5 (3944.8) ; 156.7 (153.2) ; 102.0 (102.0) ; 0.0 (0.0) ; 5631 (5585) ; 217 (157) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |chip8|cpu:cpu|st7920_serial_driver:gpu ; st7920_serial_driver ; work ; +; |commander:com| ; 30.2 (30.2) ; 33.7 (33.7) ; 3.5 (3.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 46 (46) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |chip8|cpu:cpu|st7920_serial_driver:gpu|commander:com ; commander ; work ; +; |downclocker:dc| ; 5.5 (5.5) ; 6.5 (6.5) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 11 (11) ; 11 (11) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |chip8|downclocker:dc ; downclocker ; work ; ; |memory:mem| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 32768 ; 4 ; 0 ; 0 ; 0 ; |chip8|memory:mem ; memory ; work ; ; |altsyncram:mem_rtl_0| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 32768 ; 4 ; 0 ; 0 ; 0 ; |chip8|memory:mem|altsyncram:mem_rtl_0 ; altsyncram ; work ; ; |altsyncram_dsq1:auto_generated| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 32768 ; 4 ; 0 ; 0 ; 0 ; |chip8|memory:mem|altsyncram:mem_rtl_0|altsyncram_dsq1:auto_generated ; altsyncram_dsq1 ; work ; @@ -2493,6 +2549,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; rst_in ; ; ; ; fpga_clk ; ; ; ; - cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 0 ; 0 ; +; - downclocker:dc|clk_out ; 0 ; 0 ; +-------------------------------------------------+-------------------+---------+ @@ -2501,77 +2558,81 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +------------------------------------------------------------------------+----------------------+---------+---------------------------+--------+----------------------+------------------+---------------------------+ ; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; +------------------------------------------------------------------------+----------------------+---------+---------------------------+--------+----------------------+------------------+---------------------------+ -; cpu:cpu|Decoder0~10 ; MLABCELL_X72_Y24_N39 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; cpu:cpu|Decoder0~11 ; LABCELL_X73_Y25_N57 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; cpu:cpu|Decoder0~12 ; LABCELL_X68_Y22_N30 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; cpu:cpu|Decoder0~13 ; MLABCELL_X72_Y24_N27 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; cpu:cpu|Decoder0~15 ; MLABCELL_X72_Y24_N6 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; cpu:cpu|Decoder0~17 ; MLABCELL_X72_Y24_N33 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; cpu:cpu|Decoder0~18 ; MLABCELL_X72_Y24_N3 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; cpu:cpu|Decoder0~19 ; MLABCELL_X72_Y24_N18 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; cpu:cpu|Decoder0~20 ; MLABCELL_X72_Y24_N15 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; cpu:cpu|Decoder0~21 ; MLABCELL_X72_Y24_N21 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; cpu:cpu|Decoder0~22 ; MLABCELL_X72_Y24_N54 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; cpu:cpu|Decoder0~23 ; MLABCELL_X72_Y24_N51 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; cpu:cpu|Decoder0~3 ; LABCELL_X66_Y22_N42 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; cpu:cpu|Decoder0~5 ; MLABCELL_X72_Y26_N57 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; cpu:cpu|Decoder0~7 ; LABCELL_X66_Y22_N33 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; cpu:cpu|Decoder0~9 ; MLABCELL_X72_Y24_N45 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; cpu:cpu|Equal17~1 ; LABCELL_X75_Y26_N51 ; 13 ; Clock enable ; no ; -- ; -- ; -- ; -; cpu:cpu|Equal19~0 ; LABCELL_X74_Y26_N48 ; 14 ; Clock enable ; no ; -- ; -- ; -- ; -; cpu:cpu|Equal20~0 ; LABCELL_X74_Y26_N45 ; 23 ; Sync. load ; no ; -- ; -- ; -- ; -; cpu:cpu|Equal23~0 ; LABCELL_X74_Y26_N51 ; 23 ; Sync. load ; no ; -- ; -- ; -- ; -; cpu:cpu|draw_state.r[4]~0 ; LABCELL_X51_Y22_N33 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; -; cpu:cpu|index_reg[11]~0 ; MLABCELL_X78_Y26_N3 ; 12 ; Clock enable ; no ; -- ; -- ; -- ; -; cpu:cpu|instr.dst_reg[3]~0 ; LABCELL_X77_Y28_N21 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; -; cpu:cpu|instr.src_byte[2]~2 ; MLABCELL_X72_Y25_N51 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; -; cpu:cpu|instr.src_byte[9]~1 ; MLABCELL_X72_Y25_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; -; cpu:cpu|instr.src_sprite_addr[0]~0 ; MLABCELL_X72_Y25_N45 ; 26 ; Clock enable ; no ; -- ; -- ; -- ; -; cpu:cpu|instr.src_sprite_idx[1]~0 ; MLABCELL_X72_Y26_N0 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; cpu:cpu|instr.src_sprite_y[0]~0 ; MLABCELL_X72_Y26_N45 ; 11 ; Clock enable ; no ; -- ; -- ; -- ; -; cpu:cpu|program_counter[1]~1 ; LABCELL_X75_Y26_N30 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; -; cpu:cpu|rd_memory_address[3]~1 ; MLABCELL_X72_Y26_N3 ; 12 ; Clock enable ; no ; -- ; -- ; -- ; -; cpu:cpu|registers[0][0]~3 ; MLABCELL_X78_Y28_N54 ; 12 ; Clock enable ; no ; -- ; -- ; -- ; -; cpu:cpu|registers[10][0]~15 ; MLABCELL_X78_Y28_N48 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; -; cpu:cpu|registers[11][0]~19 ; LABCELL_X81_Y28_N12 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; -; cpu:cpu|registers[12][0]~6 ; MLABCELL_X78_Y28_N24 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; -; cpu:cpu|registers[13][0]~12 ; MLABCELL_X78_Y28_N18 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; -; cpu:cpu|registers[14][0]~16 ; MLABCELL_X78_Y28_N0 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; -; cpu:cpu|registers[15][5]~0 ; LABCELL_X77_Y26_N45 ; 12 ; Clock enable ; no ; -- ; -- ; -- ; -; cpu:cpu|registers[15][5]~20 ; LABCELL_X29_Y27_N12 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; -; cpu:cpu|registers[1][0]~9 ; LABCELL_X81_Y28_N42 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; -; cpu:cpu|registers[2][0]~13 ; MLABCELL_X78_Y28_N30 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; -; cpu:cpu|registers[3][0]~17 ; LABCELL_X81_Y28_N9 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; -; cpu:cpu|registers[4][0]~4 ; MLABCELL_X78_Y28_N27 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; -; cpu:cpu|registers[5][0]~10 ; MLABCELL_X78_Y28_N3 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; -; cpu:cpu|registers[6][0]~14 ; MLABCELL_X78_Y28_N9 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; -; cpu:cpu|registers[7][0]~18 ; MLABCELL_X78_Y28_N33 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; -; cpu:cpu|registers[8][0]~5 ; MLABCELL_X78_Y28_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; -; cpu:cpu|registers[9][0]~11 ; LABCELL_X81_Y28_N36 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; -; cpu:cpu|st7920_serial_driver:gpu|always0~0 ; LABCELL_X77_Y27_N3 ; 44 ; Clock enable, Sync. clear ; no ; -- ; -- ; -- ; -; cpu:cpu|st7920_serial_driver:gpu|commander:com|full_command_bits[22]~1 ; LABCELL_X73_Y31_N36 ; 63 ; Clock enable ; no ; -- ; -- ; -- ; -; cpu:cpu|st7920_serial_driver:gpu|counter[8] ; FF_X75_Y27_N26 ; 11 ; Sync. clear ; no ; -- ; -- ; -- ; -; cpu:cpu|st7920_serial_driver:gpu|i[1]~2 ; LABCELL_X67_Y27_N48 ; 33 ; Clock enable ; no ; -- ; -- ; -- ; -; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; FF_X74_Y30_N59 ; 218 ; Clock ; no ; -- ; -- ; -- ; -; cpu:cpu|st7920_serial_driver:gpu|line_cnt[23]~0 ; LABCELL_X70_Y26_N48 ; 57 ; Sync. clear ; no ; -- ; -- ; -- ; -; cpu:cpu|st7920_serial_driver:gpu|line_cnt[23]~2 ; LABCELL_X67_Y27_N36 ; 50 ; Clock enable ; no ; -- ; -- ; -- ; -; cpu:cpu|st7920_serial_driver:gpu|start ; FF_X74_Y28_N14 ; 66 ; Sync. clear, Sync. load ; no ; -- ; -- ; -- ; -; cpu:cpu|st7920_serial_driver:gpu|y[0]~2 ; LABCELL_X70_Y27_N54 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; -; cpu:cpu|st7920_serial_driver:gpu|y[6]~0 ; LABCELL_X67_Y27_N45 ; 11 ; Sync. clear ; no ; -- ; -- ; -- ; -; cpu:cpu|vram[188][7]~2 ; LABCELL_X51_Y22_N48 ; 9095 ; Clock enable ; no ; -- ; -- ; -- ; -; cpu:cpu|vram[890][6]~1184 ; LABCELL_X61_Y22_N39 ; 293 ; Clock enable ; no ; -- ; -- ; -- ; -; fpga_clk ; PIN_V11 ; 2 ; Clock ; no ; -- ; -- ; -- ; -; fpga_clk ; PIN_V11 ; 9791 ; Clock ; yes ; Global Clock ; GCLK5 ; -- ; +; cpu:cpu|Decoder0~11 ; LABCELL_X53_Y18_N21 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|Decoder0~12 ; LABCELL_X53_Y18_N30 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|Decoder0~13 ; LABCELL_X53_Y18_N48 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|Decoder0~14 ; LABCELL_X53_Y18_N51 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|Decoder0~15 ; LABCELL_X53_Y18_N54 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|Decoder0~16 ; LABCELL_X53_Y18_N45 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|Decoder0~17 ; LABCELL_X53_Y18_N18 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|Decoder0~18 ; LABCELL_X53_Y18_N24 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|Decoder0~19 ; LABCELL_X53_Y18_N6 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|Decoder0~2 ; LABCELL_X53_Y18_N36 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|Decoder0~20 ; LABCELL_X53_Y18_N9 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|Decoder0~3 ; LABCELL_X53_Y18_N57 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|Decoder0~5 ; LABCELL_X53_Y18_N27 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|Decoder0~6 ; LABCELL_X53_Y18_N42 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|Decoder0~8 ; LABCELL_X48_Y18_N15 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|Decoder0~9 ; LABCELL_X48_Y18_N45 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|Equal17~0 ; LABCELL_X51_Y13_N30 ; 16 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|Equal17~1 ; LABCELL_X51_Y13_N39 ; 24 ; Sync. load ; no ; -- ; -- ; -- ; +; cpu:cpu|Equal17~5 ; LABCELL_X51_Y13_N3 ; 14 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|Selector163~1 ; LABCELL_X51_Y15_N51 ; 11 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|alu_rst ; FF_X52_Y12_N50 ; 37 ; Sync. clear ; no ; -- ; -- ; -- ; +; cpu:cpu|draw_state.r[4]~0 ; LABCELL_X46_Y20_N33 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|index_reg[11]~0 ; MLABCELL_X52_Y14_N39 ; 12 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|instr.alu_i.operand_a[0]~0 ; LABCELL_X50_Y15_N15 ; 16 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|instr.dst_reg[0]~0 ; LABCELL_X50_Y15_N48 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|instr.src_byte[11]~2 ; LABCELL_X51_Y16_N27 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|instr.src_byte[1]~4 ; LABCELL_X51_Y16_N6 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|instr.src_sprite_sz[0]~0 ; LABCELL_X51_Y15_N33 ; 29 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|instr.src_sprite_x[5]~0 ; LABCELL_X50_Y16_N24 ; 11 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|program_counter[10]~4 ; LABCELL_X50_Y16_N54 ; 14 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|rd_memory_address[8]~1 ; LABCELL_X50_Y16_N3 ; 12 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|registers[0][0]~1 ; LABCELL_X55_Y16_N15 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|registers[10][0]~11 ; LABCELL_X55_Y16_N39 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|registers[11][0]~12 ; LABCELL_X55_Y16_N6 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|registers[12][0]~13 ; LABCELL_X55_Y16_N9 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|registers[13][0]~14 ; LABCELL_X55_Y16_N21 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|registers[14][0]~15 ; LABCELL_X55_Y16_N33 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|registers[15][5]~16 ; LABCELL_X29_Y23_N12 ; 8 ; Sync. clear ; no ; -- ; -- ; -- ; +; cpu:cpu|registers[15][5]~19 ; LABCELL_X29_Y23_N21 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|registers[1][0]~2 ; LABCELL_X55_Y16_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|registers[2][0]~3 ; LABCELL_X55_Y16_N3 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|registers[3][0]~4 ; LABCELL_X55_Y16_N54 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|registers[4][0]~5 ; LABCELL_X55_Y16_N57 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|registers[5][0]~6 ; LABCELL_X55_Y16_N24 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|registers[6][0]~7 ; LABCELL_X55_Y16_N27 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|registers[7][0]~8 ; LABCELL_X55_Y16_N30 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|registers[8][0]~9 ; LABCELL_X55_Y16_N51 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|registers[9][0]~10 ; LABCELL_X55_Y16_N36 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|st7920_serial_driver:gpu|always0~0 ; MLABCELL_X65_Y34_N21 ; 48 ; Clock enable, Sync. clear ; no ; -- ; -- ; -- ; +; cpu:cpu|st7920_serial_driver:gpu|commander:com|full_command_bits[21]~1 ; LABCELL_X68_Y34_N33 ; 57 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|st7920_serial_driver:gpu|counter[8] ; FF_X50_Y34_N56 ; 11 ; Sync. clear ; no ; -- ; -- ; -- ; +; cpu:cpu|st7920_serial_driver:gpu|i[16]~1 ; MLABCELL_X65_Y34_N6 ; 33 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; FF_X63_Y34_N50 ; 209 ; Clock ; no ; -- ; -- ; -- ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[15]~0 ; MLABCELL_X39_Y36_N48 ; 53 ; Sync. clear ; no ; -- ; -- ; -- ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[15]~1 ; MLABCELL_X65_Y34_N48 ; 46 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|st7920_serial_driver:gpu|start ; FF_X63_Y34_N47 ; 60 ; Sync. clear, Sync. load ; no ; -- ; -- ; -- ; +; cpu:cpu|st7920_serial_driver:gpu|y[0]~8 ; MLABCELL_X65_Y34_N24 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|st7920_serial_driver:gpu|y[6]~0 ; LABCELL_X61_Y34_N54 ; 11 ; Sync. clear ; no ; -- ; -- ; -- ; +; cpu:cpu|vram[181][7]~3 ; LABCELL_X46_Y20_N36 ; 9160 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|vram[890][6]~1184 ; LABCELL_X46_Y20_N54 ; 287 ; Clock enable ; no ; -- ; -- ; -- ; +; downclocker:dc|clk_out ; FF_X37_Y1_N29 ; 9941 ; Clock ; yes ; Global Clock ; GCLK6 ; -- ; +; downclocker:dc|counter[9] ; FF_X37_Y1_N59 ; 12 ; Sync. clear ; no ; -- ; -- ; -- ; +; fpga_clk ; PIN_V11 ; 3 ; Clock ; no ; -- ; -- ; -- ; +; fpga_clk ; PIN_V11 ; 19 ; Clock ; yes ; Global Clock ; GCLK5 ; -- ; +------------------------------------------------------------------------+----------------------+---------+---------------------------+--------+----------------------+------------------+---------------------------+ -+-----------------------------------------------------------------------------------------------------+ -; Global & Other Fast Signals ; -+----------+----------+---------+----------------------+------------------+---------------------------+ -; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; -+----------+----------+---------+----------------------+------------------+---------------------------+ -; fpga_clk ; PIN_V11 ; 9791 ; Global Clock ; GCLK5 ; -- ; -+----------+----------+---------+----------------------+------------------+---------------------------+ ++------------------------------------------------------------------------------------------------------------------------+ +; Global & Other Fast Signals ; ++------------------------+---------------+---------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++------------------------+---------------+---------+----------------------+------------------+---------------------------+ +; downclocker:dc|clk_out ; FF_X37_Y1_N29 ; 9941 ; Global Clock ; GCLK6 ; -- ; +; fpga_clk ; PIN_V11 ; 19 ; Global Clock ; GCLK5 ; -- ; ++------------------------+---------------+---------+----------------------+------------------+---------------------------+ +-----------------------------------------------------------+ @@ -2579,15 +2640,14 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +-------------------------------------------------+---------+ ; Name ; Fan-Out ; +-------------------------------------------------+---------+ -; cpu:cpu|vram[188][7]~2 ; 9095 ; +; cpu:cpu|vram[181][7]~3 ; 9160 ; +; cpu:cpu|st7920_serial_driver:gpu|i[0]~DUPLICATE ; 1104 ; ; cpu:cpu|Decoder11~0 ; 1024 ; ; cpu:cpu|Decoder11~1 ; 1024 ; ; cpu:cpu|Decoder11~2 ; 1024 ; ; cpu:cpu|Decoder11~3 ; 1024 ; -; cpu:cpu|st7920_serial_driver:gpu|i[0] ; 823 ; -; cpu:cpu|st7920_serial_driver:gpu|i[0]~DUPLICATE ; 636 ; -; cpu:cpu|Add11~1 ; 570 ; -; cpu:cpu|Add11~5 ; 570 ; +; cpu:cpu|Add11~9 ; 570 ; +; cpu:cpu|Add11~13 ; 570 ; +-------------------------------------------------+---------+ @@ -2596,7 +2656,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +---------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------------+-------+---------------------------------------+--------------------------------------------------------------------+----------------------+-----------------+-----------------+----------+------------------------+-----------------------+ ; Name ; Type ; Mode ; Clock Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M10K blocks ; MLABs ; MIF ; Location ; Mixed Width RDW Mode ; Port A RDW Mode ; Port B RDW Mode ; ECC Mode ; ECC Pipeline Registers ; Fits in MLABs ; +---------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------------+-------+---------------------------------------+--------------------------------------------------------------------+----------------------+-----------------+-----------------+----------+------------------------+-----------------------+ -; memory:mem|altsyncram:mem_rtl_0|altsyncram_dsq1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 4096 ; 8 ; 4096 ; 8 ; yes ; no ; yes ; no ; 32768 ; 4096 ; 8 ; 4096 ; 8 ; 32768 ; 4 ; 0 ; db/chip8.ram0_memory_e9e85012.hdl.mif ; M10K_X69_Y24_N0, M10K_X69_Y25_N0, M10K_X69_Y23_N0, M10K_X69_Y22_N0 ; Old data ; New data ; New data ; Off ; No ; No - Address Too Wide ; +; memory:mem|altsyncram:mem_rtl_0|altsyncram_dsq1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 4096 ; 8 ; 4096 ; 8 ; yes ; no ; yes ; no ; 32768 ; 4096 ; 8 ; 4096 ; 8 ; 32768 ; 4 ; 0 ; db/chip8.ram0_memory_e9e85012.hdl.mif ; M10K_X49_Y18_N0, M10K_X49_Y19_N0, M10K_X49_Y16_N0, M10K_X49_Y17_N0 ; Old data ; New data ; New data ; Off ; No ; No - Address Too Wide ; +---------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------------+-------+---------------------------------------+--------------------------------------------------------------------+----------------------+-----------------+-----------------+----------+------------------------+-----------------------+ Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section. @@ -2606,15 +2666,15 @@ Note: Fitter may spread logical memories into multiple blocks to improve timing. +---------------------------------------------+---------------------------+ ; Routing Resource Type ; Usage ; +---------------------------------------------+---------------------------+ -; Block interconnects ; 38,285 / 289,320 ( 13 % ) ; -; C12 interconnects ; 1,962 / 13,420 ( 15 % ) ; -; C2 interconnects ; 14,750 / 119,108 ( 12 % ) ; -; C4 interconnects ; 8,316 / 56,300 ( 15 % ) ; +; Block interconnects ; 38,143 / 289,320 ( 13 % ) ; +; C12 interconnects ; 1,796 / 13,420 ( 13 % ) ; +; C2 interconnects ; 14,170 / 119,108 ( 12 % ) ; +; C4 interconnects ; 7,967 / 56,300 ( 14 % ) ; ; DQS bus muxes ; 0 / 25 ( 0 % ) ; ; DQS-18 I/O buses ; 0 / 25 ( 0 % ) ; ; DQS-9 I/O buses ; 0 / 25 ( 0 % ) ; -; Direct links ; 2,082 / 289,320 ( < 1 % ) ; -; Global clocks ; 1 / 16 ( 6 % ) ; +; Direct links ; 2,035 / 289,320 ( < 1 % ) ; +; Global clocks ; 2 / 16 ( 13 % ) ; ; HPS SDRAM PLL inputs ; 0 / 1 ( 0 % ) ; ; HPS SDRAM PLL outputs ; 0 / 1 ( 0 % ) ; ; HPS_INTERFACE_BOOT_FROM_FPGA_INPUTs ; 0 / 9 ( 0 % ) ; @@ -2669,13 +2729,13 @@ Note: Fitter may spread logical memories into multiple blocks to improve timing. ; HPS_INTERFACE_TPIU_TRACE_INPUTs ; 0 / 2 ( 0 % ) ; ; HPS_INTERFACE_TPIU_TRACE_OUTPUTs ; 0 / 33 ( 0 % ) ; ; Horizontal periphery clocks ; 0 / 72 ( 0 % ) ; -; Local interconnects ; 8,860 / 84,580 ( 10 % ) ; +; Local interconnects ; 9,017 / 84,580 ( 11 % ) ; ; Quadrant clocks ; 0 / 66 ( 0 % ) ; -; R14 interconnects ; 2,626 / 12,676 ( 21 % ) ; -; R14/C12 interconnect drivers ; 4,060 / 20,720 ( 20 % ) ; -; R3 interconnects ; 17,868 / 130,992 ( 14 % ) ; -; R6 interconnects ; 32,054 / 266,960 ( 12 % ) ; -; Spine clocks ; 9 / 360 ( 3 % ) ; +; R14 interconnects ; 2,518 / 12,676 ( 20 % ) ; +; R14/C12 interconnect drivers ; 3,774 / 20,720 ( 18 % ) ; +; R3 interconnects ; 17,751 / 130,992 ( 14 % ) ; +; R6 interconnects ; 30,710 / 266,960 ( 12 % ) ; +; Spine clocks ; 12 / 360 ( 3 % ) ; ; Wire stub REs ; 0 / 15,858 ( 0 % ) ; +---------------------------------------------+---------------------------+ @@ -2800,9 +2860,10 @@ Note: Fitter may spread logical memories into multiple blocks to improve timing. +------------------------------------------+------------------------------------------+-------------------+ ; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ; +------------------------------------------+------------------------------------------+-------------------+ -; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 124.3 ; -; fpga_clk ; fpga_clk ; 57.4 ; -; fpga_clk ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 29.5 ; +; downclocker:dc|clk_out ; downclocker:dc|clk_out ; 288.4 ; +; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 106.5 ; +; downclocker:dc|clk_out ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 62.6 ; +; fpga_clk ; fpga_clk ; 13.8 ; +------------------------------------------+------------------------------------------+-------------------+ Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off. This will disable optimization of problematic paths and expose them for further analysis using the Timing Analyzer. @@ -2813,106 +2874,106 @@ This will disable optimization of problematic paths and expose them for further +-----------------------------------------------+------------------------------------------+-------------------+ ; Source Register ; Destination Register ; Delay Added in ns ; +-----------------------------------------------+------------------------------------------+-------------------+ -; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 7.432 ; -; cpu:cpu|st7920_serial_driver:gpu|counter[8] ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 3.716 ; -; cpu:cpu|st7920_serial_driver:gpu|x[3] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.655 ; -; cpu:cpu|st7920_serial_driver:gpu|x[2] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.653 ; -; cpu:cpu|st7920_serial_driver:gpu|i[2] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.622 ; -; cpu:cpu|st7920_serial_driver:gpu|x[4] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.584 ; -; cpu:cpu|st7920_serial_driver:gpu|x[0] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.504 ; -; cpu:cpu|st7920_serial_driver:gpu|line_cnt[30] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.374 ; -; cpu:cpu|st7920_serial_driver:gpu|line_cnt[29] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.374 ; -; cpu:cpu|st7920_serial_driver:gpu|line_cnt[27] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.374 ; -; cpu:cpu|st7920_serial_driver:gpu|line_cnt[23] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.374 ; -; cpu:cpu|st7920_serial_driver:gpu|line_cnt[6] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.374 ; -; cpu:cpu|st7920_serial_driver:gpu|line_cnt[4] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.374 ; -; cpu:cpu|st7920_serial_driver:gpu|i[31] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.363 ; -; cpu:cpu|st7920_serial_driver:gpu|line_cnt[12] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.343 ; -; cpu:cpu|st7920_serial_driver:gpu|line_cnt[11] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.343 ; -; cpu:cpu|st7920_serial_driver:gpu|line_cnt[10] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.343 ; -; cpu:cpu|st7920_serial_driver:gpu|line_cnt[9] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.343 ; -; cpu:cpu|st7920_serial_driver:gpu|line_cnt[8] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.343 ; -; cpu:cpu|st7920_serial_driver:gpu|line_cnt[7] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.343 ; -; cpu:cpu|st7920_serial_driver:gpu|line_cnt[28] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.323 ; -; cpu:cpu|st7920_serial_driver:gpu|line_cnt[26] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.323 ; -; cpu:cpu|st7920_serial_driver:gpu|line_cnt[25] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.323 ; -; cpu:cpu|st7920_serial_driver:gpu|line_cnt[24] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.323 ; -; cpu:cpu|st7920_serial_driver:gpu|line_cnt[14] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.323 ; -; cpu:cpu|st7920_serial_driver:gpu|line_cnt[13] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.323 ; -; cpu:cpu|st7920_serial_driver:gpu|c[31] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.280 ; -; cpu:cpu|st7920_serial_driver:gpu|i[20] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.241 ; -; cpu:cpu|st7920_serial_driver:gpu|i[17] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.213 ; -; cpu:cpu|st7920_serial_driver:gpu|i[18] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.213 ; -; cpu:cpu|st7920_serial_driver:gpu|i[19] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.213 ; -; cpu:cpu|st7920_serial_driver:gpu|i[21] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.213 ; -; cpu:cpu|st7920_serial_driver:gpu|i[22] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.213 ; -; cpu:cpu|st7920_serial_driver:gpu|i[23] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.185 ; -; cpu:cpu|st7920_serial_driver:gpu|i[24] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.185 ; -; cpu:cpu|st7920_serial_driver:gpu|i[25] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.185 ; -; cpu:cpu|st7920_serial_driver:gpu|i[26] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.185 ; -; cpu:cpu|st7920_serial_driver:gpu|i[27] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.185 ; -; cpu:cpu|st7920_serial_driver:gpu|i[28] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.185 ; -; cpu:cpu|st7920_serial_driver:gpu|c[29] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.160 ; -; cpu:cpu|st7920_serial_driver:gpu|c[28] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.160 ; -; cpu:cpu|st7920_serial_driver:gpu|c[27] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.160 ; -; cpu:cpu|st7920_serial_driver:gpu|c[30] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.160 ; -; cpu:cpu|st7920_serial_driver:gpu|c[25] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.160 ; -; cpu:cpu|st7920_serial_driver:gpu|c[24] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.160 ; -; cpu:cpu|st7920_serial_driver:gpu|c[23] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.160 ; -; cpu:cpu|st7920_serial_driver:gpu|c[22] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.160 ; -; cpu:cpu|st7920_serial_driver:gpu|c[21] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.160 ; -; cpu:cpu|st7920_serial_driver:gpu|c[20] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.160 ; -; cpu:cpu|st7920_serial_driver:gpu|c[19] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.160 ; -; cpu:cpu|st7920_serial_driver:gpu|c[18] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.160 ; -; cpu:cpu|st7920_serial_driver:gpu|c[17] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.160 ; -; cpu:cpu|st7920_serial_driver:gpu|c[16] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.160 ; -; cpu:cpu|st7920_serial_driver:gpu|c[15] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.160 ; -; cpu:cpu|st7920_serial_driver:gpu|c[14] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.160 ; -; cpu:cpu|st7920_serial_driver:gpu|c[13] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.160 ; -; cpu:cpu|st7920_serial_driver:gpu|c[12] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.160 ; -; cpu:cpu|st7920_serial_driver:gpu|c[11] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.160 ; -; cpu:cpu|st7920_serial_driver:gpu|c[10] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.160 ; -; cpu:cpu|st7920_serial_driver:gpu|c[9] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.160 ; -; cpu:cpu|st7920_serial_driver:gpu|c[8] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.160 ; -; cpu:cpu|st7920_serial_driver:gpu|c[7] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.160 ; -; cpu:cpu|st7920_serial_driver:gpu|c[6] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.160 ; -; cpu:cpu|st7920_serial_driver:gpu|c[5] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.160 ; -; cpu:cpu|st7920_serial_driver:gpu|c[4] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.160 ; -; cpu:cpu|st7920_serial_driver:gpu|c[3] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.160 ; -; cpu:cpu|st7920_serial_driver:gpu|c[26] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.160 ; -; cpu:cpu|st7920_serial_driver:gpu|line_cnt[16] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.153 ; -; cpu:cpu|st7920_serial_driver:gpu|line_cnt[15] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.153 ; -; cpu:cpu|st7920_serial_driver:gpu|i[1] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.089 ; -; cpu:cpu|st7920_serial_driver:gpu|i[11] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.089 ; -; cpu:cpu|st7920_serial_driver:gpu|i[12] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.089 ; -; cpu:cpu|st7920_serial_driver:gpu|i[13] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.089 ; -; cpu:cpu|st7920_serial_driver:gpu|i[14] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.089 ; -; cpu:cpu|st7920_serial_driver:gpu|i[15] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.089 ; -; cpu:cpu|st7920_serial_driver:gpu|i[16] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.089 ; -; cpu:cpu|st7920_serial_driver:gpu|i[5] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.089 ; -; cpu:cpu|st7920_serial_driver:gpu|i[6] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.089 ; -; cpu:cpu|st7920_serial_driver:gpu|i[7] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.089 ; -; cpu:cpu|st7920_serial_driver:gpu|i[8] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.089 ; -; cpu:cpu|st7920_serial_driver:gpu|i[9] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.089 ; -; cpu:cpu|st7920_serial_driver:gpu|i[10] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.089 ; -; cpu:cpu|st7920_serial_driver:gpu|i[3] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.089 ; -; cpu:cpu|st7920_serial_driver:gpu|i[4] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.089 ; -; cpu:cpu|st7920_serial_driver:gpu|i[29] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.089 ; -; cpu:cpu|st7920_serial_driver:gpu|i[30] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.089 ; -; cpu:cpu|st7920_serial_driver:gpu|i[0] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.089 ; -; cpu:cpu|st7920_serial_driver:gpu|line_cnt[22] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 1.999 ; -; cpu:cpu|st7920_serial_driver:gpu|line_cnt[21] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 1.999 ; -; cpu:cpu|st7920_serial_driver:gpu|line_cnt[20] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 1.999 ; -; cpu:cpu|st7920_serial_driver:gpu|line_cnt[19] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 1.999 ; -; cpu:cpu|st7920_serial_driver:gpu|line_cnt[18] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 1.999 ; -; cpu:cpu|st7920_serial_driver:gpu|line_cnt[17] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 1.999 ; -; cpu:cpu|st7920_serial_driver:gpu|line_cnt[31] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 1.999 ; -; cpu:cpu|st7920_serial_driver:gpu|line_cnt[5] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 1.999 ; -; cpu:cpu|st7920_serial_driver:gpu|line_cnt[3] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 1.999 ; -; cpu:cpu|st7920_serial_driver:gpu|line_cnt[2] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 1.999 ; -; cpu:cpu|st7920_serial_driver:gpu|line_cnt[1] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 1.999 ; -; cpu:cpu|st7920_serial_driver:gpu|x[1] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 1.999 ; -; cpu:cpu|st7920_serial_driver:gpu|y[5] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 1.999 ; +; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 7.550 ; +; downclocker:dc|clk_out ; downclocker:dc|clk_out ; 6.220 ; +; cpu:cpu|st7920_serial_driver:gpu|i[31] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.886 ; +; cpu:cpu|st7920_serial_driver:gpu|counter[8] ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 2.498 ; +; cpu:cpu|st7920_serial_driver:gpu|c[31] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.491 ; +; cpu:cpu|st7920_serial_driver:gpu|i[16] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.460 ; +; cpu:cpu|st7920_serial_driver:gpu|i[17] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.460 ; +; cpu:cpu|st7920_serial_driver:gpu|i[18] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.460 ; +; cpu:cpu|st7920_serial_driver:gpu|i[19] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.460 ; +; cpu:cpu|st7920_serial_driver:gpu|i[20] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.460 ; +; cpu:cpu|st7920_serial_driver:gpu|i[15] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.460 ; +; cpu:cpu|st7920_serial_driver:gpu|i[23] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.383 ; +; cpu:cpu|st7920_serial_driver:gpu|i[24] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.383 ; +; cpu:cpu|st7920_serial_driver:gpu|i[25] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.383 ; +; cpu:cpu|st7920_serial_driver:gpu|i[26] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.383 ; +; cpu:cpu|st7920_serial_driver:gpu|i[22] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.383 ; +; cpu:cpu|st7920_serial_driver:gpu|i[21] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.383 ; +; cpu:cpu|st7920_serial_driver:gpu|c[30] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.344 ; +; cpu:cpu|st7920_serial_driver:gpu|c[29] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.344 ; +; cpu:cpu|st7920_serial_driver:gpu|c[28] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.344 ; +; cpu:cpu|st7920_serial_driver:gpu|c[27] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.344 ; +; cpu:cpu|st7920_serial_driver:gpu|c[26] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.344 ; +; cpu:cpu|st7920_serial_driver:gpu|c[25] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.344 ; +; cpu:cpu|st7920_serial_driver:gpu|c[23] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.344 ; +; cpu:cpu|st7920_serial_driver:gpu|c[22] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.344 ; +; cpu:cpu|st7920_serial_driver:gpu|c[21] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.344 ; +; cpu:cpu|st7920_serial_driver:gpu|c[20] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.344 ; +; cpu:cpu|st7920_serial_driver:gpu|c[19] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.344 ; +; cpu:cpu|st7920_serial_driver:gpu|c[24] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.344 ; +; cpu:cpu|st7920_serial_driver:gpu|c[17] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.344 ; +; cpu:cpu|st7920_serial_driver:gpu|c[16] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.344 ; +; cpu:cpu|st7920_serial_driver:gpu|c[15] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.344 ; +; cpu:cpu|st7920_serial_driver:gpu|c[14] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.344 ; +; cpu:cpu|st7920_serial_driver:gpu|c[13] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.344 ; +; cpu:cpu|st7920_serial_driver:gpu|c[12] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.344 ; +; cpu:cpu|st7920_serial_driver:gpu|c[11] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.344 ; +; cpu:cpu|st7920_serial_driver:gpu|c[10] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.344 ; +; cpu:cpu|st7920_serial_driver:gpu|c[9] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.344 ; +; cpu:cpu|st7920_serial_driver:gpu|c[8] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.344 ; +; cpu:cpu|st7920_serial_driver:gpu|c[7] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.344 ; +; cpu:cpu|st7920_serial_driver:gpu|c[6] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.344 ; +; cpu:cpu|st7920_serial_driver:gpu|c[5] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.344 ; +; cpu:cpu|st7920_serial_driver:gpu|c[4] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.344 ; +; cpu:cpu|st7920_serial_driver:gpu|c[3] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.344 ; +; cpu:cpu|st7920_serial_driver:gpu|c[18] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.344 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[26] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.165 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[25] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.165 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[24] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.165 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[19] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.165 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[18] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.165 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[17] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.165 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[30] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.149 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[4] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.149 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[27] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.131 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[15] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.131 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[14] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.131 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[13] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.131 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[12] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.131 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[11] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.131 ; +; downclocker:dc|counter[9] ; downclocker:dc|clk_out ; 2.114 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[29] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.100 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[28] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.100 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[23] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.100 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[22] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.100 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[21] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.100 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[20] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.100 ; +; cpu:cpu|st7920_serial_driver:gpu|x[3] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.045 ; +; cpu:cpu|st7920_serial_driver:gpu|x[2] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.043 ; +; cpu:cpu|st7920_serial_driver:gpu|x[0] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.008 ; +; cpu:cpu|st7920_serial_driver:gpu|x[4] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 1.998 ; +; cpu:cpu|st7920_serial_driver:gpu|y[5] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 1.976 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[16] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 1.957 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[10] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 1.957 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[9] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 1.957 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[8] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 1.957 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[7] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 1.957 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[6] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 1.957 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[31] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 1.957 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[3] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 1.957 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[2] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 1.957 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[1] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 1.957 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[0] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 1.957 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[5] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 1.957 ; +; cpu:cpu|st7920_serial_driver:gpu|x[1] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 1.937 ; +; cpu:cpu|st7920_serial_driver:gpu|y[4] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 1.918 ; +; cpu:cpu|st7920_serial_driver:gpu|y[3] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 1.918 ; +; cpu:cpu|st7920_serial_driver:gpu|y[6] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 1.918 ; +; cpu:cpu|st7920_serial_driver:gpu|y[1] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 1.918 ; +; cpu:cpu|st7920_serial_driver:gpu|y[0] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 1.918 ; +; cpu:cpu|st7920_serial_driver:gpu|y[2] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 1.918 ; +; cpu:cpu|st7920_serial_driver:gpu|i[9] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 1.782 ; +; cpu:cpu|st7920_serial_driver:gpu|i[12] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 1.782 ; +; cpu:cpu|st7920_serial_driver:gpu|i[13] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 1.782 ; +; cpu:cpu|st7920_serial_driver:gpu|i[14] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 1.782 ; +; cpu:cpu|st7920_serial_driver:gpu|i[11] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 1.782 ; +; cpu:cpu|st7920_serial_driver:gpu|i[10] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 1.782 ; +; cpu:cpu|st7920_serial_driver:gpu|i[1] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 1.770 ; +; cpu:cpu|st7920_serial_driver:gpu|i[2] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 1.770 ; +; cpu:cpu|st7920_serial_driver:gpu|i[3] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 1.770 ; +; cpu:cpu|st7920_serial_driver:gpu|i[4] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 1.770 ; +-----------------------------------------------+------------------------------------------+-------------------+ Note: This table only shows the top 100 path(s) that have the largest delay added for hold. @@ -2932,8 +2993,10 @@ Warning (292013): Feature LogicLock is only available with a valid subscription Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements. Info (184020): Starting Fitter periphery placement operations -Info (11191): Automatically promoted 1 clock (1 global) - Info (11162): fpga_clk~inputCLKENA0 with 8563 fanout uses global clock CLKCTRL_G5 +Info (11191): Automatically promoted 2 clocks (2 global) + Info (11162): downclocker:dc|clk_out~CLKENA0 with 8651 fanout uses global clock CLKCTRL_G2 + Info (12525): This signal is driven by core routing -- it may be moved during placement to reduce routing delays + Info (11162): fpga_clk~inputCLKENA0 with 19 fanout uses global clock CLKCTRL_G5 Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00 Info (176233): Starting register packing Critical Warning (332012): Synopsys Design Constraints File file not found: 'chip8.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. @@ -2945,32 +3008,32 @@ Info (176235): Finished register packing Extra Info (176219): No registers were packed into other blocks Warning (15705): Ignored locations or region assignments to the following nodes Warning (15706): Node "lcd_cs" is assigned to location or region, but does not exist in design -Info (11798): Fitter preparation operations ending: elapsed time is 00:00:13 +Info (11798): Fitter preparation operations ending: elapsed time is 00:00:10 Info (170189): Fitter placement preparation operations beginning Info (14951): The Fitter is using Advanced Physical Optimization. -Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:52 +Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:39 Info (170191): Fitter placement operations beginning Info (170137): Fitter placement was successful -Info (170192): Fitter placement operations ending: elapsed time is 00:00:24 +Info (170192): Fitter placement operations ending: elapsed time is 00:00:19 Info (170193): Fitter routing operations beginning Info (170195): Router estimated average interconnect usage is 12% of the available device resources - Info (170196): Router estimated peak interconnect usage is 57% of the available device resources in the region that extends from location X22_Y23 to location X32_Y34 + Info (170196): Router estimated peak interconnect usage is 58% of the available device resources in the region that extends from location X22_Y11 to location X32_Y22 Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. Info (170201): Optimizations that may affect the design's routability were skipped -Info (170194): Fitter routing operations ending: elapsed time is 00:03:08 -Info (11888): Total time spent on timing analysis during the Fitter is 49.90 seconds. +Info (170194): Fitter routing operations ending: elapsed time is 00:02:05 +Info (11888): Total time spent on timing analysis during the Fitter is 36.34 seconds. Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully -Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:29 +Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:23 Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. Info (144001): Generated suppressed messages file /home/nickorlow/programming/school/warminster/yayacemu/output_files/chip8.fit.smsg Info: Quartus Prime Fitter was successful. 0 errors, 8 warnings - Info: Peak virtual memory: 2797 megabytes - Info: Processing ended: Sun Apr 7 23:52:09 2024 - Info: Elapsed time: 00:06:15 - Info: Total CPU time (on all processors): 00:14:19 + Info: Peak virtual memory: 2824 megabytes + Info: Processing ended: Mon Apr 8 08:52:18 2024 + Info: Elapsed time: 00:04:30 + Info: Total CPU time (on all processors): 00:11:39 +----------------------------+ diff --git a/output_files/chip8.fit.summary b/output_files/chip8.fit.summary index 2da5d4b..b749e3d 100644 --- a/output_files/chip8.fit.summary +++ b/output_files/chip8.fit.summary @@ -1,12 +1,12 @@ -Fitter Status : Successful - Sun Apr 7 23:52:05 2024 +Fitter Status : Successful - Mon Apr 8 08:52:14 2024 Quartus Prime Version : 23.1std.0 Build 991 11/28/2023 SC Lite Edition Revision Name : chip8 Top-level Entity Name : chip8 Family : Cyclone V Device : 5CSEBA6U23I7 Timing Models : Final -Logic utilization (in ALMs) : 10,549 / 41,910 ( 25 % ) -Total registers : 10004 +Logic utilization (in ALMs) : 10,693 / 41,910 ( 26 % ) +Total registers : 10165 Total pins : 10 / 314 ( 3 % ) Total virtual pins : 0 Total block memory bits : 32,768 / 5,662,720 ( < 1 % ) diff --git a/output_files/chip8.flow.rpt b/output_files/chip8.flow.rpt index 06c7a16..afc2408 100644 --- a/output_files/chip8.flow.rpt +++ b/output_files/chip8.flow.rpt @@ -1,5 +1,5 @@ Flow report for chip8 -Sun Apr 7 23:52:43 2024 +Mon Apr 8 08:52:45 2024 Quartus Prime Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition @@ -41,15 +41,15 @@ https://fpgasoftware.intel.com/eula. +----------------------------------------------------------------------------------+ ; Flow Summary ; +---------------------------------+------------------------------------------------+ -; Flow Status ; Successful - Sun Apr 7 23:52:17 2024 ; +; Flow Status ; Successful - Mon Apr 8 08:52:25 2024 ; ; Quartus Prime Version ; 23.1std.0 Build 991 11/28/2023 SC Lite Edition ; ; Revision Name ; chip8 ; ; Top-level Entity Name ; chip8 ; ; Family ; Cyclone V ; ; Device ; 5CSEBA6U23I7 ; ; Timing Models ; Final ; -; Logic utilization (in ALMs) ; 10,549 / 41,910 ( 25 % ) ; -; Total registers ; 10004 ; +; Logic utilization (in ALMs) ; 10,693 / 41,910 ( 26 % ) ; +; Total registers ; 10165 ; ; Total pins ; 10 / 314 ( 3 % ) ; ; Total virtual pins ; 0 ; ; Total block memory bits ; 32,768 / 5,662,720 ( < 1 % ) ; @@ -68,7 +68,7 @@ https://fpgasoftware.intel.com/eula. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 04/07/2024 23:44:51 ; +; Start date & time ; 04/08/2024 08:46:51 ; ; Main task ; Compilation ; ; Revision Name ; chip8 ; +-------------------+---------------------+ @@ -79,7 +79,7 @@ https://fpgasoftware.intel.com/eula. +-------------------------------------+----------------------------------------+---------------+-------------+----------------+ ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; +-------------------------------------+----------------------------------------+---------------+-------------+----------------+ -; COMPILER_SIGNATURE_ID ; 346662554261.171255149111146 ; -- ; -- ; -- ; +; COMPILER_SIGNATURE_ID ; 346662554261.171258401122441 ; -- ; -- ; -- ; ; EDA_OUTPUT_DATA_FORMAT ; None ; -- ; -- ; eda_simulation ; ; MAX_CORE_JUNCTION_TEMP ; 100 ; -- ; -- ; -- ; ; MIN_CORE_JUNCTION_TEMP ; -40 ; -- ; -- ; -- ; @@ -97,11 +97,11 @@ https://fpgasoftware.intel.com/eula. +----------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:01:01 ; 3.7 ; 698 MB ; 00:01:45 ; -; Fitter ; 00:06:11 ; 1.6 ; 2797 MB ; 00:14:15 ; -; Assembler ; 00:00:07 ; 1.0 ; 631 MB ; 00:00:07 ; -; Timing Analyzer ; 00:00:25 ; 5.7 ; 1353 MB ; 00:01:44 ; -; Total ; 00:07:44 ; -- ; -- ; 00:17:51 ; +; Analysis & Synthesis ; 00:00:54 ; 3.7 ; 775 MB ; 00:01:32 ; +; Fitter ; 00:04:26 ; 1.6 ; 2824 MB ; 00:11:35 ; +; Assembler ; 00:00:06 ; 1.0 ; 628 MB ; 00:00:06 ; +; Timing Analyzer ; 00:00:19 ; 5.5 ; 1312 MB ; 00:01:25 ; +; Total ; 00:05:45 ; -- ; -- ; 00:14:38 ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ diff --git a/output_files/chip8.map.rpt b/output_files/chip8.map.rpt index 1ae0da8..5675988 100644 --- a/output_files/chip8.map.rpt +++ b/output_files/chip8.map.rpt @@ -1,5 +1,5 @@ Analysis & Synthesis report for chip8 -Sun Apr 7 23:45:53 2024 +Mon Apr 8 08:47:47 2024 Quartus Prime Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition @@ -21,14 +21,16 @@ Quartus Prime Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition 13. Registers Packed Into Inferred Megafunctions 14. Multiplexer Restructuring Statistics (Restructuring Performed) 15. Source assignments for memory:mem|altsyncram:mem_rtl_0|altsyncram_dsq1:auto_generated - 16. Parameter Settings for User Entity Instance: memory:mem - 17. Parameter Settings for Inferred Entity Instance: memory:mem|altsyncram:mem_rtl_0 - 18. altsyncram Parameter Settings by Entity Instance - 19. Port Connectivity Checks: "cpu:cpu|st7920_serial_driver:gpu" - 20. Port Connectivity Checks: "cpu:cpu" - 21. Post-Synthesis Netlist Statistics for Top Partition - 22. Elapsed Time Per Partition - 23. Analysis & Synthesis Messages + 16. Parameter Settings for User Entity Instance: downclocker:dc + 17. Parameter Settings for User Entity Instance: memory:mem + 18. Parameter Settings for Inferred Entity Instance: memory:mem|altsyncram:mem_rtl_0 + 19. altsyncram Parameter Settings by Entity Instance + 20. Port Connectivity Checks: "cpu:cpu|st7920_serial_driver:gpu" + 21. Port Connectivity Checks: "cpu:cpu" + 22. Post-Synthesis Netlist Statistics for Top Partition + 23. Elapsed Time Per Partition + 24. Analysis & Synthesis Messages + 25. Analysis & Synthesis Suppressed Messages @@ -55,13 +57,13 @@ https://fpgasoftware.intel.com/eula. +----------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +---------------------------------+------------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Sun Apr 7 23:45:53 2024 ; +; Analysis & Synthesis Status ; Successful - Mon Apr 8 08:47:47 2024 ; ; Quartus Prime Version ; 23.1std.0 Build 991 11/28/2023 SC Lite Edition ; ; Revision Name ; chip8 ; ; Top-level Entity Name ; chip8 ; ; Family ; Cyclone V ; ; Logic utilization (in ALMs) ; N/A ; -; Total registers ; 8728 ; +; Total registers ; 8836 ; ; Total pins ; 10 ; ; Total virtual pins ; 0 ; ; Total block memory bits ; 32,768 ; @@ -170,22 +172,22 @@ https://fpgasoftware.intel.com/eula. ; Number detected on machine ; 12 ; ; Maximum allowed ; 12 ; ; ; ; -; Average used ; 3.71 ; +; Average used ; 3.67 ; ; Maximum used ; 12 ; ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; -; Processor 2 ; 48.5% ; -; Processor 3 ; 48.3% ; -; Processor 4 ; 24.0% ; -; Processor 5 ; 24.0% ; -; Processor 6 ; 24.0% ; -; Processor 7 ; 19.2% ; -; Processor 8 ; 19.2% ; -; Processor 9 ; 19.2% ; -; Processor 10 ; 18.8% ; -; Processor 11 ; 18.8% ; -; Processor 12 ; 7.5% ; +; Processor 2 ; 40.2% ; +; Processor 3 ; 40.2% ; +; Processor 4 ; 35.9% ; +; Processor 5 ; 35.8% ; +; Processor 6 ; 35.8% ; +; Processor 7 ; 25.7% ; +; Processor 8 ; 25.7% ; +; Processor 9 ; 6.9% ; +; Processor 10 ; 6.9% ; +; Processor 11 ; 6.9% ; +; Processor 12 ; 6.8% ; +----------------------------+-------------+ @@ -197,6 +199,9 @@ https://fpgasoftware.intel.com/eula. ; the-bomb/st7920_serial_driver.sv ; yes ; User SystemVerilog HDL File ; /home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv ; ; ; chip8.sv ; yes ; User SystemVerilog HDL File ; /home/nickorlow/programming/school/warminster/yayacemu/chip8.sv ; ; ; cpu.sv ; yes ; User SystemVerilog HDL File ; /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv ; ; +; alu.sv ; yes ; User SystemVerilog HDL File ; /home/nickorlow/programming/school/warminster/yayacemu/alu.sv ; ; +; aastructs.sv ; yes ; User SystemVerilog HDL File ; /home/nickorlow/programming/school/warminster/yayacemu/aastructs.sv ; ; +; downclocker.sv ; yes ; User SystemVerilog HDL File ; /home/nickorlow/programming/school/warminster/yayacemu/downclocker.sv ; ; ; memory.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/nickorlow/programming/school/warminster/yayacemu/memory.sv ; ; ; rom.bin ; yes ; Auto-Found Unspecified File ; /home/nickorlow/programming/school/warminster/yayacemu/rom.bin ; ; ; fontset.bin ; yes ; Auto-Found Unspecified File ; /home/nickorlow/programming/school/warminster/yayacemu/fontset.bin ; ; @@ -214,33 +219,33 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------+-----------------+-------------------------------------------------------+----------------------------------------------------------------------------------------------+---------+ -+--------------------------------------------------------------+ -; Analysis & Synthesis Resource Usage Summary ; -+---------------------------------------------+----------------+ -; Resource ; Usage ; -+---------------------------------------------+----------------+ -; Estimate of Logic utilization (ALMs needed) ; 10412 ; -; ; ; -; Combinational ALUT usage for logic ; 17065 ; -; -- 7 input functions ; 58 ; -; -- 6 input functions ; 3654 ; -; -- 5 input functions ; 5900 ; -; -- 4 input functions ; 2000 ; -; -- <=3 input functions ; 5453 ; -; ; ; -; Dedicated logic registers ; 8728 ; -; ; ; -; I/O pins ; 10 ; -; Total MLAB memory bits ; 0 ; -; Total block memory bits ; 32768 ; -; ; ; -; Total DSP Blocks ; 0 ; -; ; ; -; Maximum fan-out node ; fpga_clk~input ; -; Maximum fan-out ; 8564 ; -; Total fan-out ; 102143 ; -; Average fan-out ; 3.96 ; -+---------------------------------------------+----------------+ ++----------------------------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+------------------------+ +; Resource ; Usage ; ++---------------------------------------------+------------------------+ +; Estimate of Logic utilization (ALMs needed) ; 10507 ; +; ; ; +; Combinational ALUT usage for logic ; 17207 ; +; -- 7 input functions ; 56 ; +; -- 6 input functions ; 3707 ; +; -- 5 input functions ; 5934 ; +; -- 4 input functions ; 2008 ; +; -- <=3 input functions ; 5502 ; +; ; ; +; Dedicated logic registers ; 8836 ; +; ; ; +; I/O pins ; 10 ; +; Total MLAB memory bits ; 0 ; +; Total block memory bits ; 32768 ; +; ; ; +; Total DSP Blocks ; 0 ; +; ; ; +; Maximum fan-out node ; downclocker:dc|clk_out ; +; Maximum fan-out ; 8652 ; +; Total fan-out ; 103021 ; +; Average fan-out ; 3.95 ; ++---------------------------------------------+------------------------+ +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ @@ -248,10 +253,12 @@ https://fpgasoftware.intel.com/eula. +-------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+-----------------------------------------------------------------------+----------------------+--------------+ ; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ; +-------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+-----------------------------------------------------------------------+----------------------+--------------+ -; |chip8 ; 17065 (1) ; 8728 (0) ; 32768 ; 0 ; 10 ; 0 ; |chip8 ; chip8 ; work ; -; |cpu:cpu| ; 17064 (11448) ; 8728 (8546) ; 0 ; 0 ; 0 ; 0 ; |chip8|cpu:cpu ; cpu ; work ; -; |st7920_serial_driver:gpu| ; 5616 (5570) ; 182 (129) ; 0 ; 0 ; 0 ; 0 ; |chip8|cpu:cpu|st7920_serial_driver:gpu ; st7920_serial_driver ; work ; +; |chip8 ; 17207 (1) ; 8836 (0) ; 32768 ; 0 ; 10 ; 0 ; |chip8 ; chip8 ; work ; +; |cpu:cpu| ; 17195 (11517) ; 8825 (8594) ; 0 ; 0 ; 0 ; 0 ; |chip8|cpu:cpu ; cpu ; work ; +; |alu:alu| ; 47 (47) ; 49 (49) ; 0 ; 0 ; 0 ; 0 ; |chip8|cpu:cpu|alu:alu ; alu ; work ; +; |st7920_serial_driver:gpu| ; 5631 (5585) ; 182 (129) ; 0 ; 0 ; 0 ; 0 ; |chip8|cpu:cpu|st7920_serial_driver:gpu ; st7920_serial_driver ; work ; ; |commander:com| ; 46 (46) ; 53 (53) ; 0 ; 0 ; 0 ; 0 ; |chip8|cpu:cpu|st7920_serial_driver:gpu|commander:com ; commander ; work ; +; |downclocker:dc| ; 11 (11) ; 11 (11) ; 0 ; 0 ; 0 ; 0 ; |chip8|downclocker:dc ; downclocker ; work ; ; |memory:mem| ; 0 (0) ; 0 (0) ; 32768 ; 0 ; 0 ; 0 ; |chip8|memory:mem ; memory ; work ; ; |altsyncram:mem_rtl_0| ; 0 (0) ; 0 (0) ; 32768 ; 0 ; 0 ; 0 ; |chip8|memory:mem|altsyncram:mem_rtl_0 ; altsyncram ; work ; ; |altsyncram_dsq1:auto_generated| ; 0 (0) ; 0 (0) ; 32768 ; 0 ; 0 ; 0 ; |chip8|memory:mem|altsyncram:mem_rtl_0|altsyncram_dsq1:auto_generated ; altsyncram_dsq1 ; work ; @@ -275,23 +282,26 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +------------------------------------------------------------------------+---------------------------------------------+ ; cpu:cpu|st7920_serial_driver:gpu|d_flip_flop:dff|data_out ; Stuck at VCC due to stuck port data_in ; ; cpu:cpu|wr_memory_address[0..11] ; Stuck at GND due to stuck port data_in ; +; cpu:cpu|compute_of ; Stuck at GND due to stuck port data_in ; ; cpu:cpu|instr.src_sprite_sz[4] ; Stuck at GND due to stuck port data_in ; ; cpu:cpu|instr.src_sprite_y[5..7] ; Stuck at GND due to stuck port data_in ; ; cpu:cpu|instr.src_sprite_x[6,7] ; Stuck at GND due to stuck port data_in ; ; cpu:cpu|instr.dst[1..31] ; Stuck at GND due to stuck port data_in ; -; cpu:cpu|instr.op[2..31] ; Stuck at GND due to stuck port data_in ; +; cpu:cpu|instr.op[3..31] ; Stuck at GND due to stuck port data_in ; +; cpu:cpu|alu:alu|overflow ; Lost fanout ; +; cpu:cpu|alu:alu|result_int[8] ; Lost fanout ; ; cpu:cpu|wr_memory_data[0..7] ; Stuck at GND due to stuck port clock_enable ; -; cpu:cpu|draw_state.stage[1..9,11..31] ; Merged with cpu:cpu|draw_state.stage[10] ; ; cpu:cpu|state[4..9,11..31] ; Merged with cpu:cpu|state[10] ; ; cpu:cpu|instr.src[3..31] ; Merged with cpu:cpu|instr.src[0] ; +; cpu:cpu|draw_state.stage[1..9,11..31] ; Merged with cpu:cpu|draw_state.stage[10] ; ; cpu:cpu|st7920_serial_driver:gpu|command[8] ; Stuck at GND due to stuck port data_in ; ; cpu:cpu|st7920_serial_driver:gpu|commander:com|full_command_bits[0..3] ; Stuck at GND due to stuck port data_in ; ; cpu:cpu|wr_go ; Stuck at GND due to stuck port data_in ; ; cpu:cpu|draw_state.stage[10] ; Stuck at GND due to stuck port data_in ; -; cpu:cpu|instr.src[0] ; Stuck at GND due to stuck port data_in ; ; cpu:cpu|state[10] ; Stuck at GND due to stuck port data_in ; ; cpu:cpu|program_counter[12..15] ; Lost fanout ; -; Total Number of Removed Registers = 187 ; ; +; cpu:cpu|instr.src[0] ; Stuck at GND due to stuck port data_in ; +; Total Number of Removed Registers = 189 ; ; +------------------------------------------------------------------------+---------------------------------------------+ @@ -309,8 +319,12 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; cpu:cpu|st7920_serial_driver:gpu|commander:com|full_command_bits[0] ; Stuck at GND ; cpu:cpu|st7920_serial_driver:gpu|commander:com|full_command_bits[1], ; ; ; due to stuck port data_in ; cpu:cpu|st7920_serial_driver:gpu|commander:com|full_command_bits[2], ; ; ; ; cpu:cpu|st7920_serial_driver:gpu|commander:com|full_command_bits[3] ; +; cpu:cpu|compute_of ; Stuck at GND ; cpu:cpu|alu:alu|overflow, cpu:cpu|alu:alu|result_int[8] ; +; ; due to stuck port data_in ; ; ; cpu:cpu|st7920_serial_driver:gpu|d_flip_flop:dff|data_out ; Stuck at VCC ; cpu:cpu|st7920_serial_driver:gpu|command[8] ; ; ; due to stuck port data_in ; ; +; cpu:cpu|instr.op[3] ; Stuck at GND ; cpu:cpu|instr.src[0] ; +; ; due to stuck port data_in ; ; +---------------------------------------------------------------------+---------------------------+----------------------------------------------------------------------------------+ @@ -319,12 +333,12 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +----------------------------------------------+-------+ ; Statistic ; Value ; +----------------------------------------------+-------+ -; Total registers ; 8728 ; -; Number of registers using Synchronous Clear ; 118 ; -; Number of registers using Synchronous Load ; 29 ; +; Total registers ; 8836 ; +; Number of registers using Synchronous Clear ; 169 ; +; Number of registers using Synchronous Load ; 21 ; ; Number of registers using Asynchronous Clear ; 0 ; ; Number of registers using Asynchronous Load ; 0 ; -; Number of registers using Clock Enable ; 8631 ; +; Number of registers using Clock Enable ; 8673 ; ; Number of registers using Preset ; 0 ; +----------------------------------------------+-------+ @@ -334,8 +348,9 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +----------------------------------------+---------+ ; Inverted Register ; Fan out ; +----------------------------------------+---------+ +; cpu:cpu|alu_rst ; 34 ; ; cpu:cpu|program_counter[9] ; 5 ; -; Total number of inverted registers = 1 ; ; +; Total number of inverted registers = 2 ; ; +----------------------------------------+---------+ @@ -353,27 +368,28 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------------------+ ; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; +--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------------------+ -; 3:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|commander:com|full_command_bits[22] ; -; 3:1 ; 8 bits ; 16 LEs ; 0 LEs ; 16 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|commander:com|full_command_bits[17] ; -; 3:1 ; 38 bits ; 76 LEs ; 0 LEs ; 76 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|commander:com|i[9] ; -; 4:1 ; 32 bits ; 64 LEs ; 0 LEs ; 64 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|line_cnt[23] ; -; 4:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|x[5] ; +; 3:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|commander:com|full_command_bits[21] ; +; 3:1 ; 8 bits ; 16 LEs ; 0 LEs ; 16 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|commander:com|full_command_bits[5] ; +; 3:1 ; 38 bits ; 76 LEs ; 0 LEs ; 76 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|commander:com|i[15] ; +; 4:1 ; 32 bits ; 64 LEs ; 0 LEs ; 64 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|line_cnt[15] ; +; 4:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|x[4] ; ; 4:1 ; 7 bits ; 14 LEs ; 7 LEs ; 7 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|y[6] ; -; 5:1 ; 32 bits ; 96 LEs ; 32 LEs ; 64 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|i[1] ; +; 5:1 ; 32 bits ; 96 LEs ; 32 LEs ; 64 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|i[16] ; ; 1029:1 ; 2 bits ; 1372 LEs ; 1368 LEs ; 4 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|command[6] ; ; 1059:1 ; 5 bits ; 3530 LEs ; 3445 LEs ; 85 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|command[5] ; -; 3:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; Yes ; |chip8|cpu:cpu|draw_state.r[4] ; -; 4:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; Yes ; |chip8|cpu:cpu|draw_state.c[1] ; -; 16:1 ; 5 bits ; 50 LEs ; 50 LEs ; 0 LEs ; Yes ; |chip8|cpu:cpu|instr.src_sprite_y[4] ; -; 16:1 ; 6 bits ; 60 LEs ; 60 LEs ; 0 LEs ; Yes ; |chip8|cpu:cpu|instr.src_sprite_x[2] ; -; 4:1 ; 12 bits ; 24 LEs ; 0 LEs ; 24 LEs ; Yes ; |chip8|cpu:cpu|rd_memory_address[3] ; -; 5:1 ; 5 bits ; 15 LEs ; 5 LEs ; 10 LEs ; Yes ; |chip8|cpu:cpu|instr.src_sprite_idx[1] ; -; 5:1 ; 6 bits ; 18 LEs ; 6 LEs ; 12 LEs ; Yes ; |chip8|cpu:cpu|instr.src_byte[9] ; -; 5:1 ; 2 bits ; 6 LEs ; 2 LEs ; 4 LEs ; Yes ; |chip8|cpu:cpu|draw_state.stage[10] ; -; 6:1 ; 8 bits ; 32 LEs ; 0 LEs ; 32 LEs ; Yes ; |chip8|cpu:cpu|instr.src_byte[2] ; -; 6:1 ; 6 bits ; 24 LEs ; 12 LEs ; 12 LEs ; Yes ; |chip8|cpu:cpu|registers[15][5] ; -; 10:1 ; 4 bits ; 24 LEs ; 8 LEs ; 16 LEs ; Yes ; |chip8|cpu:cpu|program_counter[15] ; -; 10:1 ; 10 bits ; 60 LEs ; 20 LEs ; 40 LEs ; Yes ; |chip8|cpu:cpu|program_counter[1] ; +; 3:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; Yes ; |chip8|cpu:cpu|draw_state.r[0] ; +; 4:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; Yes ; |chip8|cpu:cpu|draw_state.c[3] ; +; 16:1 ; 8 bits ; 80 LEs ; 80 LEs ; 0 LEs ; Yes ; |chip8|cpu:cpu|instr.alu_i.operand_b[0] ; +; 16:1 ; 5 bits ; 50 LEs ; 50 LEs ; 0 LEs ; Yes ; |chip8|cpu:cpu|instr.src_sprite_y[0] ; +; 16:1 ; 6 bits ; 60 LEs ; 60 LEs ; 0 LEs ; Yes ; |chip8|cpu:cpu|instr.src_sprite_x[1] ; +; 4:1 ; 12 bits ; 24 LEs ; 0 LEs ; 24 LEs ; Yes ; |chip8|cpu:cpu|rd_memory_address[8] ; +; 5:1 ; 5 bits ; 15 LEs ; 5 LEs ; 10 LEs ; Yes ; |chip8|cpu:cpu|instr.src_sprite_idx[3] ; +; 5:1 ; 2 bits ; 6 LEs ; 2 LEs ; 4 LEs ; Yes ; |chip8|cpu:cpu|draw_state.stage[0] ; +; 7:1 ; 8 bits ; 32 LEs ; 8 LEs ; 24 LEs ; Yes ; |chip8|cpu:cpu|registers[15][5] ; +; 8:1 ; 6 bits ; 30 LEs ; 6 LEs ; 24 LEs ; Yes ; |chip8|cpu:cpu|instr.src_byte[11] ; +; 9:1 ; 4 bits ; 24 LEs ; 8 LEs ; 16 LEs ; Yes ; |chip8|cpu:cpu|program_counter[15] ; +; 9:1 ; 8 bits ; 48 LEs ; 16 LEs ; 32 LEs ; Yes ; |chip8|cpu:cpu|instr.src_byte[1] ; +; 12:1 ; 10 bits ; 80 LEs ; 20 LEs ; 60 LEs ; Yes ; |chip8|cpu:cpu|program_counter[10] ; +--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------------------+ @@ -386,6 +402,16 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +---------------------------------+--------------------+------+-------------------------+ ++-------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: downclocker:dc ; ++----------------+-------+------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+------------------------------------+ +; DC_BITS ; 10 ; Signed Integer ; ++----------------+-------+------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + +---------------------------------------------------------+ ; Parameter Settings for User Entity Instance: memory:mem ; +----------------+-------+--------------------------------+ @@ -477,13 +503,14 @@ Note: In order to hide this table in the UI and the text report file, please set +-------------------------------------------+---------------------------------+ -+--------------------------------------------------------------+ -; Port Connectivity Checks: "cpu:cpu|st7920_serial_driver:gpu" ; -+--------------+-------+----------+----------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------+-------+----------+----------------------------+ -; sys_rst_n_ms ; Input ; Info ; Stuck at VCC ; -+--------------+-------+----------+----------------------------+ ++------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "cpu:cpu|st7920_serial_driver:gpu" ; ++--------------+--------+----------+-------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++--------------+--------+----------+-------------------------------------------------------------------------------------+ +; sys_rst_n_ms ; Input ; Info ; Stuck at VCC ; +; led ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ++--------------+--------+----------+-------------------------------------------------------------------------------------+ +-------------------------------------------------------------------------------------------------------------------------+ @@ -500,38 +527,38 @@ Note: In order to hide this table in the UI and the text report file, please set +-----------------------+-----------------------------+ ; Type ; Count ; +-----------------------+-----------------------------+ -; arriav_ff ; 8728 ; -; ENA ; 8526 ; -; ENA SCLR ; 77 ; -; ENA SLD ; 28 ; -; SCLR ; 41 ; +; arriav_ff ; 8836 ; +; ENA ; 8568 ; +; ENA SCLR ; 85 ; +; ENA SLD ; 20 ; +; SCLR ; 84 ; ; SLD ; 1 ; -; plain ; 55 ; -; arriav_lcell_comb ; 17066 ; -; arith ; 257 ; +; plain ; 78 ; +; arriav_lcell_comb ; 17207 ; +; arith ; 307 ; ; 0 data inputs ; 7 ; -; 1 data inputs ; 229 ; -; 2 data inputs ; 17 ; +; 1 data inputs ; 271 ; +; 2 data inputs ; 25 ; ; 3 data inputs ; 1 ; ; 4 data inputs ; 1 ; ; 5 data inputs ; 2 ; -; extend ; 58 ; -; 7 data inputs ; 58 ; -; normal ; 16745 ; -; 0 data inputs ; 2 ; +; extend ; 56 ; +; 7 data inputs ; 56 ; +; normal ; 16838 ; +; 0 data inputs ; 1 ; ; 1 data inputs ; 1 ; -; 2 data inputs ; 176 ; -; 3 data inputs ; 5015 ; -; 4 data inputs ; 1999 ; -; 5 data inputs ; 5898 ; -; 6 data inputs ; 3654 ; +; 2 data inputs ; 198 ; +; 3 data inputs ; 4992 ; +; 4 data inputs ; 2007 ; +; 5 data inputs ; 5932 ; +; 6 data inputs ; 3707 ; ; shared ; 6 ; ; 2 data inputs ; 6 ; ; boundary_port ; 10 ; ; stratixv_ram_block ; 8 ; ; ; ; ; Max LUT depth ; 55.00 ; -; Average LUT depth ; 17.90 ; +; Average LUT depth ; 17.74 ; +-----------------------+-----------------------------+ @@ -540,7 +567,7 @@ Note: In order to hide this table in the UI and the text report file, please set +----------------+--------------+ ; Partition Name ; Elapsed Time ; +----------------+--------------+ -; Top ; 00:00:53 ; +; Top ; 00:00:44 ; +----------------+--------------+ @@ -550,7 +577,7 @@ Note: In order to hide this table in the UI and the text report file, please set Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis Info: Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition - Info: Processing started: Sun Apr 7 23:44:51 2024 + Info: Processing started: Mon Apr 8 08:46:51 2024 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off chip8 -c chip8 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (20030): Parallel compilation is enabled and will use 12 of the 12 processors detected @@ -561,27 +588,37 @@ Info (12021): Found 3 design units, including 3 entities, in source file the-bom Info (12021): Found 1 design units, including 1 entities, in source file chip8.sv Info (12023): Found entity 1: chip8 File: /home/nickorlow/programming/school/warminster/yayacemu/chip8.sv Line: 1 Info (12021): Found 1 design units, including 1 entities, in source file cpu.sv - Info (12023): Found entity 1: cpu File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 1 + Info (12023): Found entity 1: cpu File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 3 +Info (12021): Found 1 design units, including 1 entities, in source file alu.sv + Info (12023): Found entity 1: alu File: /home/nickorlow/programming/school/warminster/yayacemu/alu.sv Line: 3 +Info (12021): Found 1 design units, including 0 entities, in source file aastructs.sv + Info (12022): Found design unit 1: structs (SystemVerilog) File: /home/nickorlow/programming/school/warminster/yayacemu/aastructs.sv Line: 1 +Info (12021): Found 1 design units, including 1 entities, in source file downclocker.sv + Info (12023): Found entity 1: downclocker File: /home/nickorlow/programming/school/warminster/yayacemu/downclocker.sv Line: 1 Info (12127): Elaborating entity "chip8" for the top level hierarchy +Info (12128): Elaborating entity "downclocker" for hierarchy "downclocker:dc" File: /home/nickorlow/programming/school/warminster/yayacemu/chip8.sv Line: 14 +Warning (10230): Verilog HDL assignment warning at downclocker.sv(18): truncated value with size 32 to match size of target (10) File: /home/nickorlow/programming/school/warminster/yayacemu/downclocker.sv Line: 18 Warning (12125): Using design file memory.sv, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info (12023): Found entity 1: memory File: /home/nickorlow/programming/school/warminster/yayacemu/memory.sv Line: 1 -Info (12128): Elaborating entity "memory" for hierarchy "memory:mem" File: /home/nickorlow/programming/school/warminster/yayacemu/chip8.sv Line: 21 +Info (12128): Elaborating entity "memory" for hierarchy "memory:mem" File: /home/nickorlow/programming/school/warminster/yayacemu/chip8.sv Line: 29 Warning (10850): Verilog HDL warning at memory.sv(14): number of words (80) in memory file does not match the number of elements in the address range [0:4095] File: /home/nickorlow/programming/school/warminster/yayacemu/memory.sv Line: 14 -Warning (10850): Verilog HDL warning at memory.sv(15): number of words (260) in memory file does not match the number of elements in the address range [512:4095] File: /home/nickorlow/programming/school/warminster/yayacemu/memory.sv Line: 15 -Info (12128): Elaborating entity "cpu" for hierarchy "cpu:cpu" File: /home/nickorlow/programming/school/warminster/yayacemu/chip8.sv Line: 35 -Warning (10230): Verilog HDL assignment warning at cpu.sv(124): truncated value with size 32 to match size of target (16) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 124 -Warning (10230): Verilog HDL assignment warning at cpu.sv(130): truncated value with size 32 to match size of target (16) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 130 -Warning (10230): Verilog HDL assignment warning at cpu.sv(147): truncated value with size 32 to match size of target (16) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 147 -Warning (10230): Verilog HDL assignment warning at cpu.sv(210): truncated value with size 32 to match size of target (5) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 210 -Warning (10230): Verilog HDL assignment warning at cpu.sv(213): truncated value with size 32 to match size of target (5) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 213 -Warning (10230): Verilog HDL assignment warning at cpu.sv(242): truncated value with size 32 to match size of target (16) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 242 -Warning (10230): Verilog HDL assignment warning at cpu.sv(246): truncated value with size 32 to match size of target (5) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 246 -Warning (10230): Verilog HDL assignment warning at cpu.sv(257): truncated value with size 32 to match size of target (5) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 257 -Warning (10230): Verilog HDL assignment warning at cpu.sv(284): truncated value with size 32 to match size of target (16) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 284 -Warning (10030): Net "instr.src_reg" at cpu.sv(108) has no driver or initial value, using a default initial value '0' File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 108 -Warning (10030): Net "instr.src_addr" at cpu.sv(108) has no driver or initial value, using a default initial value '0' File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 108 -Warning (10030): Net "instr.dst_addr" at cpu.sv(108) has no driver or initial value, using a default initial value '0' File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 108 -Info (12128): Elaborating entity "st7920_serial_driver" for hierarchy "cpu:cpu|st7920_serial_driver:gpu" File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 28 +Warning (10850): Verilog HDL warning at memory.sv(15): number of words (132) in memory file does not match the number of elements in the address range [512:4095] File: /home/nickorlow/programming/school/warminster/yayacemu/memory.sv Line: 15 +Info (12128): Elaborating entity "cpu" for hierarchy "cpu:cpu" File: /home/nickorlow/programming/school/warminster/yayacemu/chip8.sv Line: 44 +Warning (10230): Verilog HDL assignment warning at cpu.sv(148): truncated value with size 32 to match size of target (16) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 148 +Warning (10230): Verilog HDL assignment warning at cpu.sv(154): truncated value with size 32 to match size of target (16) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 154 +Warning (10230): Verilog HDL assignment warning at cpu.sv(171): truncated value with size 32 to match size of target (16) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 171 +Warning (10230): Verilog HDL assignment warning at cpu.sv(249): truncated value with size 32 to match size of target (5) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 249 +Warning (10230): Verilog HDL assignment warning at cpu.sv(252): truncated value with size 32 to match size of target (5) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 252 +Warning (10230): Verilog HDL assignment warning at cpu.sv(281): truncated value with size 32 to match size of target (16) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 281 +Warning (10230): Verilog HDL assignment warning at cpu.sv(285): truncated value with size 32 to match size of target (5) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 285 +Warning (10230): Verilog HDL assignment warning at cpu.sv(296): truncated value with size 32 to match size of target (5) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 296 +Warning (10230): Verilog HDL assignment warning at cpu.sv(323): truncated value with size 32 to match size of target (16) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 323 +Warning (10230): Verilog HDL assignment warning at cpu.sv(333): truncated value with size 32 to match size of target (16) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 333 +Warning (10030): Net "instr.src_reg" at cpu.sv(131) has no driver or initial value, using a default initial value '0' File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 131 +Warning (10030): Net "instr.src_addr" at cpu.sv(131) has no driver or initial value, using a default initial value '0' File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 131 +Warning (10030): Net "instr.dst_addr" at cpu.sv(131) has no driver or initial value, using a default initial value '0' File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 131 +Info (12128): Elaborating entity "alu" for hierarchy "cpu:cpu|alu:alu" File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 33 +Info (12128): Elaborating entity "st7920_serial_driver" for hierarchy "cpu:cpu|st7920_serial_driver:gpu" File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 49 Warning (10036): Verilog HDL or VHDL warning at st7920_serial_driver.sv(23): object "line_idx" assigned a value but never read File: /home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv Line: 23 Warning (10230): Verilog HDL assignment warning at st7920_serial_driver.sv(71): truncated value with size 32 to match size of target (7) File: /home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv Line: 71 Warning (10230): Verilog HDL assignment warning at st7920_serial_driver.sv(84): truncated value with size 32 to match size of target (7) File: /home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv Line: 84 @@ -629,22 +666,30 @@ Info (12133): Instantiated megafunction "memory:mem|altsyncram:mem_rtl_0" with t Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_dsq1.tdf Info (12023): Found entity 1: altsyncram_dsq1 File: /home/nickorlow/programming/school/warminster/yayacemu/db/altsyncram_dsq1.tdf Line: 28 Warning (13024): Output pins are stuck at VCC or GND - Warning (13410): Pin "led[5]" is stuck at VCC File: /home/nickorlow/programming/school/warminster/yayacemu/chip8.sv Line: 7 + Warning (13410): Pin "led[4]" is stuck at GND File: /home/nickorlow/programming/school/warminster/yayacemu/chip8.sv Line: 7 + Warning (13410): Pin "led[5]" is stuck at GND File: /home/nickorlow/programming/school/warminster/yayacemu/chip8.sv Line: 7 Info (286030): Timing-Driven Synthesis is running -Info (17049): 4 registers lost all their fanouts during netlist optimizations. +Info (17049): 6 registers lost all their fanouts during netlist optimizations. +Info (144001): Generated suppressed messages file /home/nickorlow/programming/school/warminster/yayacemu/output_files/chip8.map.smsg Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL Warning (21074): Design contains 1 input pin(s) that do not drive logic Warning (15610): No output dependent on input pin "rst_in" File: /home/nickorlow/programming/school/warminster/yayacemu/chip8.sv Line: 3 -Info (21057): Implemented 17374 device resources after synthesis - the final resource count might be different +Info (21057): Implemented 17552 device resources after synthesis - the final resource count might be different Info (21058): Implemented 2 input pins Info (21059): Implemented 8 output pins - Info (21061): Implemented 17356 logic cells + Info (21061): Implemented 17534 logic cells Info (21064): Implemented 8 RAM segments -Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 26 warnings - Info: Peak virtual memory: 698 megabytes - Info: Processing ended: Sun Apr 7 23:45:53 2024 - Info: Elapsed time: 00:01:02 - Info: Total CPU time (on all processors): 00:01:46 +Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 29 warnings + Info: Peak virtual memory: 775 megabytes + Info: Processing ended: Mon Apr 8 08:47:47 2024 + Info: Elapsed time: 00:00:56 + Info: Total CPU time (on all processors): 00:01:34 + + ++------------------------------------------+ +; Analysis & Synthesis Suppressed Messages ; ++------------------------------------------+ +The suppressed messages can be found in /home/nickorlow/programming/school/warminster/yayacemu/output_files/chip8.map.smsg. diff --git a/output_files/chip8.map.summary b/output_files/chip8.map.summary index 456d7a5..0772e8e 100644 --- a/output_files/chip8.map.summary +++ b/output_files/chip8.map.summary @@ -1,10 +1,10 @@ -Analysis & Synthesis Status : Successful - Sun Apr 7 23:45:53 2024 +Analysis & Synthesis Status : Successful - Mon Apr 8 08:47:47 2024 Quartus Prime Version : 23.1std.0 Build 991 11/28/2023 SC Lite Edition Revision Name : chip8 Top-level Entity Name : chip8 Family : Cyclone V Logic utilization (in ALMs) : N/A -Total registers : 8728 +Total registers : 8836 Total pins : 10 Total virtual pins : 0 Total block memory bits : 32,768 diff --git a/output_files/chip8.sof b/output_files/chip8.sof index 4db08b5..4847956 100644 Binary files a/output_files/chip8.sof and b/output_files/chip8.sof differ diff --git a/output_files/chip8.sta.rpt b/output_files/chip8.sta.rpt index 61d4cdb..4bf8605 100644 --- a/output_files/chip8.sta.rpt +++ b/output_files/chip8.sta.rpt @@ -1,5 +1,5 @@ Timing Analyzer report for chip8 -Sun Apr 7 23:52:43 2024 +Mon Apr 8 08:52:45 2024 Quartus Prime Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition @@ -98,22 +98,22 @@ https://fpgasoftware.intel.com/eula. ; Number detected on machine ; 12 ; ; Maximum allowed ; 12 ; ; ; ; -; Average used ; 5.73 ; +; Average used ; 5.48 ; ; Maximum used ; 12 ; ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; -; Processor 2 ; 60.4% ; -; Processor 3 ; 57.0% ; -; Processor 4 ; 55.9% ; -; Processor 5 ; 37.5% ; -; Processor 6 ; 37.5% ; -; Processor 7 ; 37.5% ; -; Processor 8 ; 37.5% ; -; Processor 9 ; 37.5% ; -; Processor 10 ; 37.5% ; -; Processor 11 ; 37.5% ; -; Processor 12 ; 37.5% ; +; Processor 2 ; 56.2% ; +; Processor 3 ; 54.6% ; +; Processor 4 ; 54.0% ; +; Processor 5 ; 35.4% ; +; Processor 6 ; 35.4% ; +; Processor 7 ; 35.4% ; +; Processor 8 ; 35.4% ; +; Processor 9 ; 35.4% ; +; Processor 10 ; 35.4% ; +; Processor 11 ; 35.4% ; +; Processor 12 ; 35.4% ; +----------------------------+-------------+ @@ -123,18 +123,20 @@ https://fpgasoftware.intel.com/eula. ; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ; +------------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------------------------------------------+ ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { cpu:cpu|st7920_serial_driver:gpu|lcd_clk } ; +; downclocker:dc|clk_out ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { downclocker:dc|clk_out } ; ; fpga_clk ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { fpga_clk } ; +------------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------------------------------------------+ -+-------------------------------------------------------------------------------+ -; Slow 1100mV 100C Model Fmax Summary ; -+-----------+-----------------+------------------------------------------+------+ -; Fmax ; Restricted Fmax ; Clock Name ; Note ; -+-----------+-----------------+------------------------------------------+------+ -; 34.01 MHz ; 34.01 MHz ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; ; -; 82.06 MHz ; 82.06 MHz ; fpga_clk ; ; -+-----------+-----------------+------------------------------------------+------+ ++--------------------------------------------------------------------------------+ +; Slow 1100mV 100C Model Fmax Summary ; ++------------+-----------------+------------------------------------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++------------+-----------------+------------------------------------------+------+ +; 31.39 MHz ; 31.39 MHz ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; ; +; 82.93 MHz ; 82.93 MHz ; downclocker:dc|clk_out ; ; +; 189.18 MHz ; 189.18 MHz ; fpga_clk ; ; ++------------+-----------------+------------------------------------------+------+ This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. @@ -149,8 +151,9 @@ HTML report is unavailable in plain text report export. +------------------------------------------+---------+---------------+ ; Clock ; Slack ; End Point TNS ; +------------------------------------------+---------+---------------+ -; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -28.406 ; -1742.530 ; -; fpga_clk ; -11.186 ; -95769.392 ; +; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -31.412 ; -1884.356 ; +; downclocker:dc|clk_out ; -11.058 ; -87363.415 ; +; fpga_clk ; -4.953 ; -27.713 ; +------------------------------------------+---------+---------------+ @@ -159,8 +162,9 @@ HTML report is unavailable in plain text report export. +------------------------------------------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +------------------------------------------+-------+---------------+ -; fpga_clk ; 0.429 ; 0.000 ; -; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 0.476 ; 0.000 ; +; downclocker:dc|clk_out ; 0.429 ; 0.000 ; +; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 0.501 ; 0.000 ; +; fpga_clk ; 0.814 ; 0.000 ; +------------------------------------------+-------+---------------+ @@ -181,8 +185,9 @@ No paths to report. +------------------------------------------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +------------------------------------------+--------+---------------+ -; fpga_clk ; -2.636 ; -8463.323 ; -; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -0.538 ; -185.389 ; +; downclocker:dc|clk_out ; -2.636 ; -8430.055 ; +; fpga_clk ; -0.622 ; -17.105 ; +; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -0.538 ; -172.550 ; +------------------------------------------+--------+---------------+ @@ -193,14 +198,15 @@ Design MTBF is not calculated because the design doesn't meet its timing require -+-------------------------------------------------------------------------------+ -; Slow 1100mV -40C Model Fmax Summary ; -+-----------+-----------------+------------------------------------------+------+ -; Fmax ; Restricted Fmax ; Clock Name ; Note ; -+-----------+-----------------+------------------------------------------+------+ -; 35.8 MHz ; 35.8 MHz ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; ; -; 81.78 MHz ; 81.78 MHz ; fpga_clk ; ; -+-----------+-----------------+------------------------------------------+------+ ++--------------------------------------------------------------------------------+ +; Slow 1100mV -40C Model Fmax Summary ; ++------------+-----------------+------------------------------------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++------------+-----------------+------------------------------------------+------+ +; 33.23 MHz ; 33.23 MHz ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; ; +; 82.94 MHz ; 82.94 MHz ; downclocker:dc|clk_out ; ; +; 185.36 MHz ; 185.36 MHz ; fpga_clk ; ; ++------------+-----------------+------------------------------------------+------+ This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. @@ -209,8 +215,9 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +------------------------------------------+---------+---------------+ ; Clock ; Slack ; End Point TNS ; +------------------------------------------+---------+---------------+ -; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -26.933 ; -1684.576 ; -; fpga_clk ; -11.228 ; -94100.779 ; +; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -29.494 ; -1798.010 ; +; downclocker:dc|clk_out ; -11.057 ; -87142.095 ; +; fpga_clk ; -4.658 ; -29.299 ; +------------------------------------------+---------+---------------+ @@ -219,8 +226,9 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +------------------------------------------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +------------------------------------------+-------+---------------+ -; fpga_clk ; 0.484 ; 0.000 ; -; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 0.565 ; 0.000 ; +; downclocker:dc|clk_out ; 0.483 ; 0.000 ; +; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 0.546 ; 0.000 ; +; fpga_clk ; 0.786 ; 0.000 ; +------------------------------------------+-------+---------------+ @@ -241,8 +249,9 @@ No paths to report. +------------------------------------------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +------------------------------------------+--------+---------------+ -; fpga_clk ; -2.636 ; -8927.522 ; -; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -0.538 ; -184.012 ; +; downclocker:dc|clk_out ; -2.636 ; -8301.987 ; +; fpga_clk ; -0.627 ; -18.184 ; +; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -0.538 ; -170.070 ; +------------------------------------------+--------+---------------+ @@ -258,8 +267,9 @@ Design MTBF is not calculated because the design doesn't meet its timing require +------------------------------------------+---------+---------------+ ; Clock ; Slack ; End Point TNS ; +------------------------------------------+---------+---------------+ -; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -14.774 ; -901.498 ; -; fpga_clk ; -6.214 ; -50560.530 ; +; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -16.301 ; -1018.017 ; +; downclocker:dc|clk_out ; -5.608 ; -44394.911 ; +; fpga_clk ; -3.718 ; -8.178 ; +------------------------------------------+---------+---------------+ @@ -268,8 +278,9 @@ Design MTBF is not calculated because the design doesn't meet its timing require +------------------------------------------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +------------------------------------------+-------+---------------+ -; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 0.162 ; 0.000 ; -; fpga_clk ; 0.177 ; 0.000 ; +; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 0.160 ; 0.000 ; +; downclocker:dc|clk_out ; 0.177 ; 0.000 ; +; fpga_clk ; 0.303 ; 0.000 ; +------------------------------------------+-------+---------------+ @@ -290,8 +301,9 @@ No paths to report. +------------------------------------------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +------------------------------------------+--------+---------------+ -; fpga_clk ; -2.174 ; -1371.543 ; -; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -0.192 ; -9.702 ; +; downclocker:dc|clk_out ; -2.174 ; -537.344 ; +; fpga_clk ; -0.517 ; -2.901 ; +; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -0.144 ; -6.507 ; +------------------------------------------+--------+---------------+ @@ -307,8 +319,9 @@ Design MTBF is not calculated because the design doesn't meet its timing require +------------------------------------------+---------+---------------+ ; Clock ; Slack ; End Point TNS ; +------------------------------------------+---------+---------------+ -; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -12.462 ; -739.747 ; -; fpga_clk ; -4.930 ; -40871.978 ; +; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -14.004 ; -820.600 ; +; downclocker:dc|clk_out ; -4.541 ; -36337.093 ; +; fpga_clk ; -2.859 ; -5.427 ; +------------------------------------------+---------+---------------+ @@ -317,8 +330,9 @@ Design MTBF is not calculated because the design doesn't meet its timing require +------------------------------------------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +------------------------------------------+-------+---------------+ -; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 0.140 ; 0.000 ; -; fpga_clk ; 0.164 ; 0.000 ; +; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 0.138 ; 0.000 ; +; downclocker:dc|clk_out ; 0.164 ; 0.000 ; +; fpga_clk ; 0.289 ; 0.000 ; +------------------------------------------+-------+---------------+ @@ -339,8 +353,9 @@ No paths to report. +------------------------------------------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +------------------------------------------+--------+---------------+ -; fpga_clk ; -2.174 ; -1373.239 ; -; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -0.137 ; -3.355 ; +; downclocker:dc|clk_out ; -2.174 ; -534.258 ; +; fpga_clk ; -0.533 ; -2.899 ; +; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -0.057 ; -2.411 ; +------------------------------------------+--------+---------------+ @@ -356,12 +371,14 @@ Design MTBF is not calculated because the design doesn't meet its timing require +-------------------------------------------+------------+-------+----------+---------+---------------------+ ; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; +-------------------------------------------+------------+-------+----------+---------+---------------------+ -; Worst-case Slack ; -28.406 ; 0.140 ; N/A ; N/A ; -2.636 ; -; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -28.406 ; 0.140 ; N/A ; N/A ; -0.538 ; -; fpga_clk ; -11.228 ; 0.164 ; N/A ; N/A ; -2.636 ; -; Design-wide TNS ; -97511.922 ; 0.0 ; 0.0 ; 0.0 ; -9111.534 ; -; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -1742.530 ; 0.000 ; N/A ; N/A ; -185.389 ; -; fpga_clk ; -95769.392 ; 0.000 ; N/A ; N/A ; -8927.522 ; +; Worst-case Slack ; -31.412 ; 0.138 ; N/A ; N/A ; -2.636 ; +; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -31.412 ; 0.138 ; N/A ; N/A ; -0.538 ; +; downclocker:dc|clk_out ; -11.058 ; 0.164 ; N/A ; N/A ; -2.636 ; +; fpga_clk ; -4.953 ; 0.289 ; N/A ; N/A ; -0.627 ; +; Design-wide TNS ; -89275.484 ; 0.0 ; 0.0 ; 0.0 ; -8619.71 ; +; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -1884.356 ; 0.000 ; N/A ; N/A ; -172.550 ; +; downclocker:dc|clk_out ; -87363.415 ; 0.000 ; N/A ; N/A ; -8430.055 ; +; fpga_clk ; -29.299 ; 0.000 ; N/A ; N/A ; -18.184 ; +-------------------------------------------+------------+-------+----------+---------+---------------------+ @@ -460,10 +477,12 @@ Design MTBF is not calculated because the design doesn't meet its timing require +------------------------------------------+------------------------------------------+----------+----------+----------+----------+ ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; +------------------------------------------+------------------------------------------+----------+----------+----------+----------+ -; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 2667 ; 137 ; 0 ; 1681347 ; -; fpga_clk ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 0 ; 0 ; 9878 ; 0 ; +; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 2393 ; 126 ; 0 ; 1681819 ; +; downclocker:dc|clk_out ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 0 ; 0 ; 9878 ; 0 ; +; downclocker:dc|clk_out ; downclocker:dc|clk_out ; 13182899 ; 148 ; 48 ; 0 ; ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; fpga_clk ; 1 ; 1 ; 0 ; 0 ; -; fpga_clk ; fpga_clk ; 12902566 ; 152 ; 48 ; 0 ; +; downclocker:dc|clk_out ; fpga_clk ; 1 ; 1 ; 0 ; 0 ; +; fpga_clk ; fpga_clk ; 121 ; 0 ; 0 ; 0 ; +------------------------------------------+------------------------------------------+----------+----------+----------+----------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. @@ -473,10 +492,12 @@ Entries labeled "false path" only account for clock-to-clock false paths and not +------------------------------------------+------------------------------------------+----------+----------+----------+----------+ ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; +------------------------------------------+------------------------------------------+----------+----------+----------+----------+ -; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 2667 ; 137 ; 0 ; 1681347 ; -; fpga_clk ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 0 ; 0 ; 9878 ; 0 ; +; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 2393 ; 126 ; 0 ; 1681819 ; +; downclocker:dc|clk_out ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 0 ; 0 ; 9878 ; 0 ; +; downclocker:dc|clk_out ; downclocker:dc|clk_out ; 13182899 ; 148 ; 48 ; 0 ; ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; fpga_clk ; 1 ; 1 ; 0 ; 0 ; -; fpga_clk ; fpga_clk ; 12902566 ; 152 ; 48 ; 0 ; +; downclocker:dc|clk_out ; fpga_clk ; 1 ; 1 ; 0 ; 0 ; +; fpga_clk ; fpga_clk ; 121 ; 0 ; 0 ; 0 ; +------------------------------------------+------------------------------------------+----------+----------+----------+----------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. @@ -502,8 +523,8 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi ; Unconstrained Clocks ; 0 ; 0 ; ; Unconstrained Input Ports ; 0 ; 0 ; ; Unconstrained Input Port Paths ; 0 ; 0 ; -; Unconstrained Output Ports ; 7 ; 7 ; -; Unconstrained Output Port Paths ; 7 ; 7 ; +; Unconstrained Output Ports ; 6 ; 6 ; +; Unconstrained Output Port Paths ; 6 ; 6 ; +---------------------------------+-------+------+ @@ -513,6 +534,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi ; Target ; Clock ; Type ; Status ; +------------------------------------------+------------------------------------------+------+-------------+ ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; Base ; Constrained ; +; downclocker:dc|clk_out ; downclocker:dc|clk_out ; Base ; Constrained ; ; fpga_clk ; fpga_clk ; Base ; Constrained ; +------------------------------------------+------------------------------------------+------+-------------+ @@ -528,7 +550,6 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi ; led[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; led[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; led[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; led[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +-------------+---------------------------------------------------------------------------------------+ @@ -543,7 +564,6 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi ; led[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; led[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; led[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; led[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +-------------+---------------------------------------------------------------------------------------+ @@ -553,7 +573,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi Info: ******************************************************************* Info: Running Quartus Prime Timing Analyzer Info: Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition - Info: Processing started: Sun Apr 7 23:52:18 2024 + Info: Processing started: Mon Apr 8 08:52:26 2024 Info: Command: quartus_sta chip8 -c chip8 Info: qsta_default_script.tcl version: #1 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. @@ -565,29 +585,33 @@ Info (332142): No user constrained base clocks found in the design. Calling "der Info (332105): Deriving Clocks Info (332105): create_clock -period 1.000 -name fpga_clk fpga_clk Info (332105): create_clock -period 1.000 -name cpu:cpu|st7920_serial_driver:gpu|lcd_clk cpu:cpu|st7920_serial_driver:gpu|lcd_clk + Info (332105): create_clock -period 1.000 -name downclocker:dc|clk_out downclocker:dc|clk_out Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON Info: Analyzing Slow 1100mV 100C Model Critical Warning (332148): Timing requirements not met Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer. -Info (332146): Worst-case setup slack is -28.406 +Info (332146): Worst-case setup slack is -31.412 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -28.406 -1742.530 cpu:cpu|st7920_serial_driver:gpu|lcd_clk - Info (332119): -11.186 -95769.392 fpga_clk + Info (332119): -31.412 -1884.356 cpu:cpu|st7920_serial_driver:gpu|lcd_clk + Info (332119): -11.058 -87363.415 downclocker:dc|clk_out + Info (332119): -4.953 -27.713 fpga_clk Info (332146): Worst-case hold slack is 0.429 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): 0.429 0.000 fpga_clk - Info (332119): 0.476 0.000 cpu:cpu|st7920_serial_driver:gpu|lcd_clk + Info (332119): 0.429 0.000 downclocker:dc|clk_out + Info (332119): 0.501 0.000 cpu:cpu|st7920_serial_driver:gpu|lcd_clk + Info (332119): 0.814 0.000 fpga_clk Info (332140): No Recovery paths to report Info (332140): No Removal paths to report Info (332146): Worst-case minimum pulse width slack is -2.636 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -2.636 -8463.323 fpga_clk - Info (332119): -0.538 -185.389 cpu:cpu|st7920_serial_driver:gpu|lcd_clk + Info (332119): -2.636 -8430.055 downclocker:dc|clk_out + Info (332119): -0.622 -17.105 fpga_clk + Info (332119): -0.538 -172.550 cpu:cpu|st7920_serial_driver:gpu|lcd_clk Info (332114): Report Metastability: Found 8 synchronizer chains. Info (332114): Design MTBF is not calculated because the design doesn't meet its timing requirements. Info: Analyzing Slow 1100mV -40C Model @@ -596,23 +620,26 @@ Info (334004): Delay annotation completed successfully Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. Critical Warning (332148): Timing requirements not met Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer. -Info (332146): Worst-case setup slack is -26.933 +Info (332146): Worst-case setup slack is -29.494 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -26.933 -1684.576 cpu:cpu|st7920_serial_driver:gpu|lcd_clk - Info (332119): -11.228 -94100.779 fpga_clk -Info (332146): Worst-case hold slack is 0.484 + Info (332119): -29.494 -1798.010 cpu:cpu|st7920_serial_driver:gpu|lcd_clk + Info (332119): -11.057 -87142.095 downclocker:dc|clk_out + Info (332119): -4.658 -29.299 fpga_clk +Info (332146): Worst-case hold slack is 0.483 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): 0.484 0.000 fpga_clk - Info (332119): 0.565 0.000 cpu:cpu|st7920_serial_driver:gpu|lcd_clk + Info (332119): 0.483 0.000 downclocker:dc|clk_out + Info (332119): 0.546 0.000 cpu:cpu|st7920_serial_driver:gpu|lcd_clk + Info (332119): 0.786 0.000 fpga_clk Info (332140): No Recovery paths to report Info (332140): No Removal paths to report Info (332146): Worst-case minimum pulse width slack is -2.636 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -2.636 -8927.522 fpga_clk - Info (332119): -0.538 -184.012 cpu:cpu|st7920_serial_driver:gpu|lcd_clk + Info (332119): -2.636 -8301.987 downclocker:dc|clk_out + Info (332119): -0.627 -18.184 fpga_clk + Info (332119): -0.538 -170.070 cpu:cpu|st7920_serial_driver:gpu|lcd_clk Info (332114): Report Metastability: Found 8 synchronizer chains. Info (332114): Design MTBF is not calculated because the design doesn't meet its timing requirements. Info: Analyzing Fast 1100mV 100C Model @@ -621,54 +648,60 @@ Info (334004): Delay annotation completed successfully Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. Critical Warning (332148): Timing requirements not met Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer. -Info (332146): Worst-case setup slack is -14.774 +Info (332146): Worst-case setup slack is -16.301 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -14.774 -901.498 cpu:cpu|st7920_serial_driver:gpu|lcd_clk - Info (332119): -6.214 -50560.530 fpga_clk -Info (332146): Worst-case hold slack is 0.162 + Info (332119): -16.301 -1018.017 cpu:cpu|st7920_serial_driver:gpu|lcd_clk + Info (332119): -5.608 -44394.911 downclocker:dc|clk_out + Info (332119): -3.718 -8.178 fpga_clk +Info (332146): Worst-case hold slack is 0.160 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): 0.162 0.000 cpu:cpu|st7920_serial_driver:gpu|lcd_clk - Info (332119): 0.177 0.000 fpga_clk + Info (332119): 0.160 0.000 cpu:cpu|st7920_serial_driver:gpu|lcd_clk + Info (332119): 0.177 0.000 downclocker:dc|clk_out + Info (332119): 0.303 0.000 fpga_clk Info (332140): No Recovery paths to report Info (332140): No Removal paths to report Info (332146): Worst-case minimum pulse width slack is -2.174 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -2.174 -1371.543 fpga_clk - Info (332119): -0.192 -9.702 cpu:cpu|st7920_serial_driver:gpu|lcd_clk + Info (332119): -2.174 -537.344 downclocker:dc|clk_out + Info (332119): -0.517 -2.901 fpga_clk + Info (332119): -0.144 -6.507 cpu:cpu|st7920_serial_driver:gpu|lcd_clk Info (332114): Report Metastability: Found 8 synchronizer chains. Info (332114): Design MTBF is not calculated because the design doesn't meet its timing requirements. Info: Analyzing Fast 1100mV -40C Model Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. Critical Warning (332148): Timing requirements not met Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer. -Info (332146): Worst-case setup slack is -12.462 +Info (332146): Worst-case setup slack is -14.004 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -12.462 -739.747 cpu:cpu|st7920_serial_driver:gpu|lcd_clk - Info (332119): -4.930 -40871.978 fpga_clk -Info (332146): Worst-case hold slack is 0.140 + Info (332119): -14.004 -820.600 cpu:cpu|st7920_serial_driver:gpu|lcd_clk + Info (332119): -4.541 -36337.093 downclocker:dc|clk_out + Info (332119): -2.859 -5.427 fpga_clk +Info (332146): Worst-case hold slack is 0.138 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): 0.140 0.000 cpu:cpu|st7920_serial_driver:gpu|lcd_clk - Info (332119): 0.164 0.000 fpga_clk + Info (332119): 0.138 0.000 cpu:cpu|st7920_serial_driver:gpu|lcd_clk + Info (332119): 0.164 0.000 downclocker:dc|clk_out + Info (332119): 0.289 0.000 fpga_clk Info (332140): No Recovery paths to report Info (332140): No Removal paths to report Info (332146): Worst-case minimum pulse width slack is -2.174 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -2.174 -1373.239 fpga_clk - Info (332119): -0.137 -3.355 cpu:cpu|st7920_serial_driver:gpu|lcd_clk + Info (332119): -2.174 -534.258 downclocker:dc|clk_out + Info (332119): -0.533 -2.899 fpga_clk + Info (332119): -0.057 -2.411 cpu:cpu|st7920_serial_driver:gpu|lcd_clk Info (332114): Report Metastability: Found 8 synchronizer chains. Info (332114): Design MTBF is not calculated because the design doesn't meet its timing requirements. Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements Info: Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings - Info: Peak virtual memory: 1353 megabytes - Info: Processing ended: Sun Apr 7 23:52:43 2024 - Info: Elapsed time: 00:00:25 - Info: Total CPU time (on all processors): 00:01:44 + Info: Peak virtual memory: 1312 megabytes + Info: Processing ended: Mon Apr 8 08:52:45 2024 + Info: Elapsed time: 00:00:19 + Info: Total CPU time (on all processors): 00:01:25 diff --git a/output_files/chip8.sta.summary b/output_files/chip8.sta.summary index 8409d96..2aeade8 100644 --- a/output_files/chip8.sta.summary +++ b/output_files/chip8.sta.summary @@ -3,99 +3,147 @@ Timing Analyzer Summary ------------------------------------------------------------ Type : Slow 1100mV 100C Model Setup 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk' -Slack : -28.406 -TNS : -1742.530 +Slack : -31.412 +TNS : -1884.356 + +Type : Slow 1100mV 100C Model Setup 'downclocker:dc|clk_out' +Slack : -11.058 +TNS : -87363.415 Type : Slow 1100mV 100C Model Setup 'fpga_clk' -Slack : -11.186 -TNS : -95769.392 +Slack : -4.953 +TNS : -27.713 -Type : Slow 1100mV 100C Model Hold 'fpga_clk' +Type : Slow 1100mV 100C Model Hold 'downclocker:dc|clk_out' Slack : 0.429 TNS : 0.000 Type : Slow 1100mV 100C Model Hold 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk' -Slack : 0.476 +Slack : 0.501 TNS : 0.000 -Type : Slow 1100mV 100C Model Minimum Pulse Width 'fpga_clk' +Type : Slow 1100mV 100C Model Hold 'fpga_clk' +Slack : 0.814 +TNS : 0.000 + +Type : Slow 1100mV 100C Model Minimum Pulse Width 'downclocker:dc|clk_out' Slack : -2.636 -TNS : -8463.323 +TNS : -8430.055 + +Type : Slow 1100mV 100C Model Minimum Pulse Width 'fpga_clk' +Slack : -0.622 +TNS : -17.105 Type : Slow 1100mV 100C Model Minimum Pulse Width 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk' Slack : -0.538 -TNS : -185.389 +TNS : -172.550 Type : Slow 1100mV -40C Model Setup 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk' -Slack : -26.933 -TNS : -1684.576 +Slack : -29.494 +TNS : -1798.010 + +Type : Slow 1100mV -40C Model Setup 'downclocker:dc|clk_out' +Slack : -11.057 +TNS : -87142.095 Type : Slow 1100mV -40C Model Setup 'fpga_clk' -Slack : -11.228 -TNS : -94100.779 +Slack : -4.658 +TNS : -29.299 -Type : Slow 1100mV -40C Model Hold 'fpga_clk' -Slack : 0.484 +Type : Slow 1100mV -40C Model Hold 'downclocker:dc|clk_out' +Slack : 0.483 TNS : 0.000 Type : Slow 1100mV -40C Model Hold 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk' -Slack : 0.565 +Slack : 0.546 TNS : 0.000 -Type : Slow 1100mV -40C Model Minimum Pulse Width 'fpga_clk' +Type : Slow 1100mV -40C Model Hold 'fpga_clk' +Slack : 0.786 +TNS : 0.000 + +Type : Slow 1100mV -40C Model Minimum Pulse Width 'downclocker:dc|clk_out' Slack : -2.636 -TNS : -8927.522 +TNS : -8301.987 + +Type : Slow 1100mV -40C Model Minimum Pulse Width 'fpga_clk' +Slack : -0.627 +TNS : -18.184 Type : Slow 1100mV -40C Model Minimum Pulse Width 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk' Slack : -0.538 -TNS : -184.012 +TNS : -170.070 Type : Fast 1100mV 100C Model Setup 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk' -Slack : -14.774 -TNS : -901.498 +Slack : -16.301 +TNS : -1018.017 + +Type : Fast 1100mV 100C Model Setup 'downclocker:dc|clk_out' +Slack : -5.608 +TNS : -44394.911 Type : Fast 1100mV 100C Model Setup 'fpga_clk' -Slack : -6.214 -TNS : -50560.530 +Slack : -3.718 +TNS : -8.178 Type : Fast 1100mV 100C Model Hold 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk' -Slack : 0.162 +Slack : 0.160 TNS : 0.000 -Type : Fast 1100mV 100C Model Hold 'fpga_clk' +Type : Fast 1100mV 100C Model Hold 'downclocker:dc|clk_out' Slack : 0.177 TNS : 0.000 -Type : Fast 1100mV 100C Model Minimum Pulse Width 'fpga_clk' -Slack : -2.174 -TNS : -1371.543 - -Type : Fast 1100mV 100C Model Minimum Pulse Width 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk' -Slack : -0.192 -TNS : -9.702 - -Type : Fast 1100mV -40C Model Setup 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk' -Slack : -12.462 -TNS : -739.747 - -Type : Fast 1100mV -40C Model Setup 'fpga_clk' -Slack : -4.930 -TNS : -40871.978 - -Type : Fast 1100mV -40C Model Hold 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk' -Slack : 0.140 +Type : Fast 1100mV 100C Model Hold 'fpga_clk' +Slack : 0.303 TNS : 0.000 -Type : Fast 1100mV -40C Model Hold 'fpga_clk' +Type : Fast 1100mV 100C Model Minimum Pulse Width 'downclocker:dc|clk_out' +Slack : -2.174 +TNS : -537.344 + +Type : Fast 1100mV 100C Model Minimum Pulse Width 'fpga_clk' +Slack : -0.517 +TNS : -2.901 + +Type : Fast 1100mV 100C Model Minimum Pulse Width 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk' +Slack : -0.144 +TNS : -6.507 + +Type : Fast 1100mV -40C Model Setup 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk' +Slack : -14.004 +TNS : -820.600 + +Type : Fast 1100mV -40C Model Setup 'downclocker:dc|clk_out' +Slack : -4.541 +TNS : -36337.093 + +Type : Fast 1100mV -40C Model Setup 'fpga_clk' +Slack : -2.859 +TNS : -5.427 + +Type : Fast 1100mV -40C Model Hold 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk' +Slack : 0.138 +TNS : 0.000 + +Type : Fast 1100mV -40C Model Hold 'downclocker:dc|clk_out' Slack : 0.164 TNS : 0.000 -Type : Fast 1100mV -40C Model Minimum Pulse Width 'fpga_clk' +Type : Fast 1100mV -40C Model Hold 'fpga_clk' +Slack : 0.289 +TNS : 0.000 + +Type : Fast 1100mV -40C Model Minimum Pulse Width 'downclocker:dc|clk_out' Slack : -2.174 -TNS : -1373.239 +TNS : -534.258 + +Type : Fast 1100mV -40C Model Minimum Pulse Width 'fpga_clk' +Slack : -0.533 +TNS : -2.899 Type : Fast 1100mV -40C Model Minimum Pulse Width 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk' -Slack : -0.137 -TNS : -3.355 +Slack : -0.057 +TNS : -2.411 ------------------------------------------------------------