yayacemu/chip8.sv

77 lines
1.2 KiB
Systemverilog
Raw Normal View History

2024-02-01 02:57:11 +00:00
module chip8 (
2024-04-08 04:39:15 +00:00
input wire fpga_clk,
input wire rst_in,
2024-04-15 14:32:48 +00:00
output logic lcd_clk,
2024-04-08 04:39:15 +00:00
output logic lcd_data,
2024-04-11 05:47:21 +00:00
output logic [5:0] led,
input wire [3:0] row,
2024-04-15 15:32:43 +00:00
output logic [3:0] col,
output logic beep
2024-02-01 03:04:52 +00:00
);
2024-04-15 14:32:48 +00:00
logic debug_overlay;
logic slow_clk;
2024-04-15 15:32:43 +00:00
downclocker #(1) dc (
2024-04-15 14:32:48 +00:00
fpga_clk,
slow_clk
);
2024-02-01 03:04:52 +00:00
2024-04-11 05:47:21 +00:00
logic key_clk;
2024-04-15 14:32:48 +00:00
downclocker #(12) dck (
fpga_clk,
key_clk
);
2024-04-11 05:47:21 +00:00
2024-04-08 04:39:15 +00:00
logic [7:0] rd_memory_data;
logic [11:0] rd_memory_address;
logic [11:0] wr_memory_address;
logic [7:0] wr_memory_data;
logic wr_go;
memory #(4096) mem (
2024-04-15 14:32:48 +00:00
slow_clk,
wr_go,
wr_memory_address,
wr_memory_data,
rd_memory_address,
rd_memory_data
);
logic [15:0] keymap;
keypad keypad (
`ifndef DUMMY_KEYPAD
key_clk,
`endif
`ifdef DUMMY_KEYPAD
slow_clk,
`endif
row,
col,
keymap
);
assign led = { key_clk, 1'b0, slow_clk, 1'b0, fpga_clk, 1'b0};
2024-02-01 03:04:52 +00:00
int cycle_counter;
2024-04-11 05:47:21 +00:00
logic [5:0] nc;
2024-02-01 03:04:52 +00:00
cpu cpu (
2024-04-08 13:54:48 +00:00
slow_clk,
2024-04-08 04:39:15 +00:00
fpga_clk,
rd_memory_data,
2024-04-15 14:32:48 +00:00
keymap,
2024-02-01 03:04:52 +00:00
cycle_counter,
2024-04-08 04:39:15 +00:00
rd_memory_address,
wr_memory_address,
wr_memory_data,
wr_go,
lcd_clk,
lcd_data,
2024-04-15 14:32:48 +00:00
nc,
2024-04-15 15:32:43 +00:00
beep,
2024-04-15 14:32:48 +00:00
row,
col,
debug_overlay
2024-02-01 03:04:52 +00:00
);
2024-02-01 02:57:11 +00:00
endmodule
2024-04-08 04:39:15 +00:00