yayacemu/chip8.sv

61 lines
1 KiB
Systemverilog
Raw Normal View History

2024-02-01 02:57:11 +00:00
module chip8 (
2024-04-08 04:39:15 +00:00
input wire fpga_clk,
input wire rst_in,
output logic lcd_clk,
output logic lcd_data,
2024-04-11 05:47:21 +00:00
output logic [5:0] led,
input wire [3:0] row,
output logic [3:0] col
2024-02-01 03:04:52 +00:00
);
2024-04-08 13:54:48 +00:00
logic slow_clk;
`ifdef FAST_CLK
assign slow_clk = fpga_clk;
`endif
`ifndef FAST_CLK
downclocker #(10) dc(fpga_clk, slow_clk);
`endif
2024-02-01 03:04:52 +00:00
2024-04-11 05:47:21 +00:00
logic key_clk;
downclocker #(24) dck(fpga_clk, key_clk);
2024-04-08 04:39:15 +00:00
logic [7:0] rd_memory_data;
logic [11:0] rd_memory_address;
logic [11:0] wr_memory_address;
logic [7:0] wr_memory_data;
logic wr_go;
memory #(4096) mem (
2024-04-08 13:54:48 +00:00
slow_clk,
2024-04-08 04:39:15 +00:00
wr_go,
wr_memory_address,
wr_memory_data,
rd_memory_address,
rd_memory_data
);
2024-04-11 05:47:21 +00:00
keypad keypad(
key_clk,
row,
col,
led
);
2024-04-08 04:39:15 +00:00
2024-02-01 03:04:52 +00:00
int cycle_counter;
2024-04-11 05:47:21 +00:00
logic [5:0] nc;
2024-02-01 03:04:52 +00:00
cpu cpu (
2024-04-08 13:54:48 +00:00
slow_clk,
2024-04-08 04:39:15 +00:00
fpga_clk,
rd_memory_data,
2024-02-01 03:04:52 +00:00
cycle_counter,
2024-04-08 04:39:15 +00:00
rd_memory_address,
wr_memory_address,
wr_memory_data,
wr_go,
lcd_clk,
lcd_data,
2024-04-11 05:47:21 +00:00
nc
2024-02-01 03:04:52 +00:00
);
2024-02-01 02:57:11 +00:00
endmodule
2024-04-08 04:39:15 +00:00