192 lines
20 KiB
Plaintext
192 lines
20 KiB
Plaintext
Analysis & Synthesis report for chip8
|
|
Sun Apr 7 23:38:38 2024
|
|
Quartus Prime Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition
|
|
|
|
|
|
---------------------
|
|
; Table of Contents ;
|
|
---------------------
|
|
1. Legal Notice
|
|
2. Analysis & Synthesis Summary
|
|
3. Analysis & Synthesis Settings
|
|
4. Parallel Compilation
|
|
5. Analysis & Synthesis Messages
|
|
|
|
|
|
|
|
----------------
|
|
; Legal Notice ;
|
|
----------------
|
|
Copyright (C) 2023 Intel Corporation. All rights reserved.
|
|
Your use of Intel Corporation's design tools, logic functions
|
|
and other software and tools, and any partner logic
|
|
functions, and any output files from any of the foregoing
|
|
(including device programming or simulation files), and any
|
|
associated documentation or information are expressly subject
|
|
to the terms and conditions of the Intel Program License
|
|
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
|
the Intel FPGA IP License Agreement, or other applicable license
|
|
agreement, including, without limitation, that your use is for
|
|
the sole purpose of programming logic devices manufactured by
|
|
Intel and sold by Intel or its authorized distributors. Please
|
|
refer to the applicable agreement for further details, at
|
|
https://fpgasoftware.intel.com/eula.
|
|
|
|
|
|
|
|
+------------------------------------------------------------------------------+
|
|
; Analysis & Synthesis Summary ;
|
|
+-----------------------------+------------------------------------------------+
|
|
; Analysis & Synthesis Status ; Failed - Sun Apr 7 23:38:38 2024 ;
|
|
; Quartus Prime Version ; 23.1std.0 Build 991 11/28/2023 SC Lite Edition ;
|
|
; Revision Name ; chip8 ;
|
|
; Top-level Entity Name ; chip8 ;
|
|
; Family ; Cyclone V ;
|
|
; Logic utilization (in ALMs) ; N/A until Partition Merge ;
|
|
; Total registers ; N/A until Partition Merge ;
|
|
; Total pins ; N/A until Partition Merge ;
|
|
; Total virtual pins ; N/A until Partition Merge ;
|
|
; Total block memory bits ; N/A until Partition Merge ;
|
|
; Total PLLs ; N/A until Partition Merge ;
|
|
; Total DLLs ; N/A until Partition Merge ;
|
|
+-----------------------------+------------------------------------------------+
|
|
|
|
|
|
+---------------------------------------------------------------------------------------------------------------------------+
|
|
; Analysis & Synthesis Settings ;
|
|
+---------------------------------------------------------------------------------+--------------------+--------------------+
|
|
; Option ; Setting ; Default Value ;
|
|
+---------------------------------------------------------------------------------+--------------------+--------------------+
|
|
; Device ; 5CSEBA6U23I7 ; ;
|
|
; Top-level entity name ; chip8 ; chip8 ;
|
|
; Family name ; Cyclone V ; Cyclone V ;
|
|
; Use smart compilation ; Off ; Off ;
|
|
; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
|
|
; Enable compact report table ; Off ; Off ;
|
|
; Restructure Multiplexers ; Auto ; Auto ;
|
|
; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off ; Off ;
|
|
; Create Debugging Nodes for IP Cores ; Off ; Off ;
|
|
; Preserve fewer node names ; On ; On ;
|
|
; Intel FPGA IP Evaluation Mode ; Enable ; Enable ;
|
|
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
|
|
; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
|
|
; State Machine Processing ; Auto ; Auto ;
|
|
; Safe State Machine ; Off ; Off ;
|
|
; Extract Verilog State Machines ; On ; On ;
|
|
; Extract VHDL State Machines ; On ; On ;
|
|
; Ignore Verilog initial constructs ; Off ; Off ;
|
|
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
|
|
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
|
|
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
|
|
; Infer RAMs from Raw Logic ; On ; On ;
|
|
; Parallel Synthesis ; On ; On ;
|
|
; DSP Block Balancing ; Auto ; Auto ;
|
|
; NOT Gate Push-Back ; On ; On ;
|
|
; Power-Up Don't Care ; On ; On ;
|
|
; Remove Redundant Logic Cells ; Off ; Off ;
|
|
; Remove Duplicate Registers ; On ; On ;
|
|
; Ignore CARRY Buffers ; Off ; Off ;
|
|
; Ignore CASCADE Buffers ; Off ; Off ;
|
|
; Ignore GLOBAL Buffers ; Off ; Off ;
|
|
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
|
|
; Ignore LCELL Buffers ; Off ; Off ;
|
|
; Ignore SOFT Buffers ; On ; On ;
|
|
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
|
|
; Optimization Technique ; Balanced ; Balanced ;
|
|
; Carry Chain Length ; 70 ; 70 ;
|
|
; Auto Carry Chains ; On ; On ;
|
|
; Auto Open-Drain Pins ; On ; On ;
|
|
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
|
|
; Auto ROM Replacement ; On ; On ;
|
|
; Auto RAM Replacement ; On ; On ;
|
|
; Auto DSP Block Replacement ; On ; On ;
|
|
; Auto Shift Register Replacement ; Auto ; Auto ;
|
|
; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
|
|
; Auto Clock Enable Replacement ; On ; On ;
|
|
; Strict RAM Replacement ; Off ; Off ;
|
|
; Allow Synchronous Control Signals ; On ; On ;
|
|
; Force Use of Synchronous Clear Signals ; Off ; Off ;
|
|
; Auto Resource Sharing ; Off ; Off ;
|
|
; Allow Any RAM Size For Recognition ; Off ; Off ;
|
|
; Allow Any ROM Size For Recognition ; Off ; Off ;
|
|
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
|
|
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
|
|
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
|
|
; Timing-Driven Synthesis ; On ; On ;
|
|
; Report Parameter Settings ; On ; On ;
|
|
; Report Source Assignments ; On ; On ;
|
|
; Report Connectivity Checks ; On ; On ;
|
|
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
|
|
; Synchronization Register Chain Length ; 3 ; 3 ;
|
|
; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
|
|
; HDL message level ; Level2 ; Level2 ;
|
|
; Suppress Register Optimization Related Messages ; Off ; Off ;
|
|
; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
|
|
; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
|
|
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
|
|
; Clock MUX Protection ; On ; On ;
|
|
; Auto Gated Clock Conversion ; Off ; Off ;
|
|
; Block Design Naming ; Auto ; Auto ;
|
|
; SDC constraint protection ; Off ; Off ;
|
|
; Synthesis Effort ; Auto ; Auto ;
|
|
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
|
|
; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
|
|
; Analysis & Synthesis Message Level ; Medium ; Medium ;
|
|
; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
|
|
; Resource Aware Inference For Block RAM ; On ; On ;
|
|
; Automatic Parallel Synthesis ; On ; On ;
|
|
; Partial Reconfiguration Bitstream ID ; Off ; Off ;
|
|
+---------------------------------------------------------------------------------+--------------------+--------------------+
|
|
|
|
|
|
+------------------------------------------+
|
|
; Parallel Compilation ;
|
|
+----------------------------+-------------+
|
|
; Processors ; Number ;
|
|
+----------------------------+-------------+
|
|
; Number detected on machine ; 12 ;
|
|
; Maximum allowed ; 12 ;
|
|
; ; ;
|
|
; Average used ; 1.00 ;
|
|
; Maximum used ; 1 ;
|
|
; ; ;
|
|
; Usage by Processor ; % Time Used ;
|
|
; Processor 1 ; 100.0% ;
|
|
+----------------------------+-------------+
|
|
|
|
|
|
+-------------------------------+
|
|
; Analysis & Synthesis Messages ;
|
|
+-------------------------------+
|
|
Info: *******************************************************************
|
|
Info: Running Quartus Prime Analysis & Synthesis
|
|
Info: Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition
|
|
Info: Processing started: Sun Apr 7 23:38:32 2024
|
|
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off chip8 -c chip8
|
|
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
|
Info (20030): Parallel compilation is enabled and will use 12 of the 12 processors detected
|
|
Critical Warning (10191): Verilog HDL Compiler Directive warning at st7920_serial_driver.sv(12): text macro "DELAY_BITS" is undefined File: /home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv Line: 12
|
|
Error (10170): Verilog HDL syntax error at st7920_serial_driver.sv(12) near text: ":"; expecting an operand. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. File: /home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv Line: 12
|
|
Critical Warning (10191): Verilog HDL Compiler Directive warning at st7920_serial_driver.sv(64): text macro "BOOTSTRAP_INSTRS" is undefined File: /home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv Line: 64
|
|
Error (10170): Verilog HDL syntax error at st7920_serial_driver.sv(64) near text: ")"; expecting an operand. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. File: /home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv Line: 64
|
|
Error (10170): Verilog HDL syntax error at st7920_serial_driver.sv(70) near text: "else"; expecting "end". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. File: /home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv Line: 70
|
|
Error (10170): Verilog HDL syntax error at st7920_serial_driver.sv(94) near text: ")"; expecting an operand. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. File: /home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv Line: 94
|
|
Error (10170): Verilog HDL syntax error at st7920_serial_driver.sv(97) near text: ")"; expecting an operand. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. File: /home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv Line: 97
|
|
Error (10170): Verilog HDL syntax error at st7920_serial_driver.sv(124) near text: "]"; expecting an operand. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. File: /home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv Line: 124
|
|
Error (10170): Verilog HDL syntax error at st7920_serial_driver.sv(127) near text: "else"; expecting "end". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. File: /home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv Line: 127
|
|
Error (10112): Ignored design unit "st7920_serial_driver" at st7920_serial_driver.sv(1) due to previous errors File: /home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv Line: 1
|
|
Error (10112): Ignored design unit "d_flip_flop" at st7920_serial_driver.sv(134) due to previous errors File: /home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv Line: 134
|
|
Error (10112): Ignored design unit "commander" at st7920_serial_driver.sv(144) due to previous errors File: /home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv Line: 144
|
|
Info (12021): Found 0 design units, including 0 entities, in source file the-bomb/st7920_serial_driver.sv
|
|
Info (12021): Found 1 design units, including 1 entities, in source file chip8.sv
|
|
Info (12023): Found entity 1: chip8 File: /home/nickorlow/programming/school/warminster/yayacemu/chip8.sv Line: 1
|
|
Info (12021): Found 1 design units, including 1 entities, in source file cpu.sv
|
|
Info (12023): Found entity 1: cpu File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 1
|
|
Error: Quartus Prime Analysis & Synthesis was unsuccessful. 10 errors, 3 warnings
|
|
Error: Peak virtual memory: 383 megabytes
|
|
Error: Processing ended: Sun Apr 7 23:38:38 2024
|
|
Error: Elapsed time: 00:00:06
|
|
Error: Total CPU time (on all processors): 00:00:14
|
|
|
|
|