59 lines
1,012 B
Systemverilog
59 lines
1,012 B
Systemverilog
module chip8 (
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input wire clk_in,
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input wire rst_in,
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output logic lcd_clk,
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output logic lcd_data,
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output logic [5:0] led
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);
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bit [7:0] vram[0:1023];
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bit [7:0] memory[0:4095];
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bit keyboard[15:0];
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bit [7:0] sound_timer;
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bit [15:0] program_counter;
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int cycle_counter;
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bit rom_ready;
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bit font_ready;
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bit system_ready;
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bit halt;
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bit [7:0] random_number;
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and(system_ready, rom_ready, font_ready);
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cpu cpu (
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system_ready,
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memory,
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clk_in,
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keyboard,
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random_number,
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cycle_counter,
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program_counter,
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vram,
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sound_timer
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);
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st7920_serial_driver gpu (clk_in, 1'b1, vram, lcd_clk, lcd_data, led);
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rng randy (
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clk_in,
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program_counter,
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keyboard,
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cycle_counter,
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random_number
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);
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initial begin
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if (~font_ready) begin
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$readmemh("fontset.bin", memory, 0);
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$readmemb("rom.bin", memory, 'h200);
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font_ready = 1;
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rom_ready = 1;
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end
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end
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endmodule
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