22 lines
433 B
Systemverilog
22 lines
433 B
Systemverilog
module downclocker #(parameter DC_BITS = 21) (
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input wire clk_in,
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output logic clk_out
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);
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logic [DC_BITS-1:0] counter;
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initial begin
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counter = 0;
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clk_out = 0;
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end
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always_ff @(posedge clk_in) begin
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if (counter[DC_BITS-1] == 1) begin
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clk_out <= !clk_out;
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counter <= 0;
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end else begin
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counter <= counter + 1;
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end
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end
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endmodule
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