50 lines
2 KiB
Plaintext
50 lines
2 KiB
Plaintext
--lpm_abs CARRY_CHAIN="MANUAL" DEVICE_FAMILY="Cyclone V" IGNORE_CARRY_BUFFERS="OFF" LPM_WIDTH=6 data result
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--VERSION_BEGIN 23.1 cbx_cycloneii 2023:11:29:19:33:06:SC cbx_lpm_abs 2023:11:29:19:33:06:SC cbx_lpm_add_sub 2023:11:29:19:33:06:SC cbx_mgl 2023:11:29:19:43:53:SC cbx_nadder 2023:11:29:19:33:06:SC cbx_stratix 2023:11:29:19:33:06:SC cbx_stratixii 2023:11:29:19:33:05:SC cbx_util_mgl 2023:11:29:19:33:06:SC VERSION_END
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-- Copyright (C) 2023 Intel Corporation. All rights reserved.
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-- Your use of Intel Corporation's design tools, logic functions
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-- and other software and tools, and any partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Intel Program License
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-- Subscription Agreement, the Intel Quartus Prime License Agreement,
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-- the Intel FPGA IP License Agreement, or other applicable license
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-- agreement, including, without limitation, that your use is for
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-- the sole purpose of programming logic devices manufactured by
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-- Intel and sold by Intel or its authorized distributors. Please
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-- refer to the applicable agreement for further details, at
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-- https://fpgasoftware.intel.com/eula.
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--synthesis_resources = lut 6
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SUBDESIGN lpm_abs_ln9
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(
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data[5..0] : input;
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overflow : output;
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result[5..0] : output;
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)
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VARIABLE
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adder_result_int[6..0] : WIRE;
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adder_cin : WIRE;
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adder_dataa[5..0] : WIRE;
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adder_datab[5..0] : WIRE;
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adder_result[5..0] : WIRE;
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gnd_wire : WIRE;
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result_tmp[5..0] : WIRE;
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BEGIN
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adder_result_int[] = (adder_dataa[], adder_cin) + (adder_datab[], adder_cin);
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adder_result[] = adder_result_int[6..1];
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adder_cin = data[5..5];
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adder_dataa[] = (data[] $ data[5..5]);
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adder_datab[] = ( gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire);
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gnd_wire = B"0";
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overflow = (result_tmp[5..5] & data[5..5]);
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result[] = result_tmp[];
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result_tmp[] = adder_result[];
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END;
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--VALID FILE
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