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add new pic

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This commit is contained in:
Nicholas Orlowsky 2024-04-08 01:34:21 -05:00
parent 1f41f702e2
commit 7fdf4e7739
Signed by: nickorlow
GPG key ID: 838827D8C4611687
62 changed files with 9348 additions and 0 deletions
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1
README.md
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@ -43,6 +43,7 @@ yayacemu [PATH_TO_YOUR_ROM]
### Screenshots
![Chip 8 Logo Demo on an FPGA!](https://github.com/nickorlow/yayacemu/blob/main/screenshots/chip8_fpga.jpg?raw=true)
![Chip 8 Logo Demo](https://github.com/nickorlow/yayacemu/blob/main/screenshots/chip8-logo.png?raw=true)
![IBM Logo Demo](https://github.com/nickorlow/yayacemu/blob/main/screenshots/ibm-logo.png?raw=true)
![CORAX+ Test Demo](https://github.com/nickorlow/yayacemu/blob/main/screenshots/corax.png?raw=true)

11
aastructs.sv Normal file
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package structs;
typedef enum {ADD} alu_op;
typedef struct {
logic [7:0] operand_a;
logic [7:0] operand_b;
alu_op op;
} alu_input;
endpackage

46
alu.sv Normal file
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import structs::*;
module alu(
input wire rst_in,
input wire clk_in,
input alu_input in,
output logic [7:0] result,
output logic overflow,
output logic done
);
logic [8:0] result_int;
int cnt;
initial begin
overflow = 1'bx;
result = 8'hxx;
result_int = 9'bxxxxxxxxx;
done = 0;
cnt = 0;
end
always_ff @(posedge clk_in) begin
if (rst_in) begin
done <= 0;
overflow <= 1'bx;
result <= 8'hxx;
result_int <= 9'bxxxxxxxxx;
cnt <= 0;
end else begin
case(in.op)
structs::ADD: begin
result_int <= in.operand_a + in.operand_b;
result <= result_int[7:0];
overflow <= result_int[8];
if (cnt == 2) begin
$display("%b %b + %b %b ya", result, in.operand_a, in.operand_b, result_int);
done <= 1;
end
cnt <= cnt + 1;
end
endcase
end
end
endmodule

118
c5_pin_model_dump.txt Normal file
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@ -0,0 +1,118 @@
io_4iomodule_c5_index: 55gpio_index: 2
io_4iomodule_c5_index: 54gpio_index: 465
io_4iomodule_c5_index: 33gpio_index: 6
io_4iomodule_c5_index: 51gpio_index: 461
io_4iomodule_c5_index: 27gpio_index: 10
io_4iomodule_c5_index: 57gpio_index: 457
io_4iomodule_c5_index: 34gpio_index: 14
io_4iomodule_c5_index: 28gpio_index: 453
io_4iomodule_c5_index: 26gpio_index: 19
io_4iomodule_c5_index: 47gpio_index: 449
io_4iomodule_c5_index: 29gpio_index: 22
io_4iomodule_c5_index: 3gpio_index: 445
io_4iomodule_c5_index: 16gpio_index: 27
io_4iomodule_c5_index: 6gpio_index: 441
io_4iomodule_c5_index: 50gpio_index: 30
io_4iomodule_c5_index: 35gpio_index: 437
io_4iomodule_c5_index: 7gpio_index: 35
io_4iomodule_c5_index: 53gpio_index: 433
io_4iomodule_c5_index: 12gpio_index: 38
io_4iomodule_c5_index: 1gpio_index: 429
io_4iomodule_c5_index: 22gpio_index: 43
io_4iomodule_c5_index: 8gpio_index: 425
io_4iomodule_c5_index: 20gpio_index: 46
io_4iomodule_c5_index: 30gpio_index: 421
io_4iomodule_c5_index: 2gpio_index: 51
io_4iomodule_c5_index: 31gpio_index: 417
io_4iomodule_c5_index: 39gpio_index: 54
io_4iomodule_c5_index: 18gpio_index: 413
io_4iomodule_c5_index: 10gpio_index: 59
io_4iomodule_c5_index: 42gpio_index: 409
io_4iomodule_c5_index: 5gpio_index: 62
io_4iomodule_c5_index: 24gpio_index: 405
io_4iomodule_c5_index: 37gpio_index: 67
io_4iomodule_c5_index: 13gpio_index: 401
io_4iomodule_c5_index: 0gpio_index: 70
io_4iomodule_c5_index: 44gpio_index: 397
io_4iomodule_c5_index: 38gpio_index: 75
io_4iomodule_c5_index: 52gpio_index: 393
io_4iomodule_c5_index: 32gpio_index: 78
io_4iomodule_c5_index: 56gpio_index: 389
io_4iomodule_a_index: 13gpio_index: 385
io_4iomodule_c5_index: 4gpio_index: 83
io_4iomodule_c5_index: 23gpio_index: 86
io_4iomodule_a_index: 15gpio_index: 381
io_4iomodule_a_index: 8gpio_index: 377
io_4iomodule_c5_index: 46gpio_index: 91
io_4iomodule_a_index: 5gpio_index: 373
io_4iomodule_a_index: 11gpio_index: 369
io_4iomodule_c5_index: 41gpio_index: 94
io_4iomodule_a_index: 3gpio_index: 365
io_4iomodule_c5_index: 25gpio_index: 99
io_4iomodule_a_index: 7gpio_index: 361
io_4iomodule_c5_index: 9gpio_index: 102
io_4iomodule_a_index: 0gpio_index: 357
io_4iomodule_c5_index: 14gpio_index: 107
io_4iomodule_a_index: 12gpio_index: 353
io_4iomodule_c5_index: 45gpio_index: 110
io_4iomodule_c5_index: 17gpio_index: 115
io_4iomodule_a_index: 4gpio_index: 349
io_4iomodule_c5_index: 36gpio_index: 118
io_4iomodule_a_index: 10gpio_index: 345
io_4iomodule_a_index: 16gpio_index: 341
io_4iomodule_c5_index: 15gpio_index: 123
io_4iomodule_a_index: 14gpio_index: 337
io_4iomodule_c5_index: 43gpio_index: 126
io_4iomodule_c5_index: 19gpio_index: 131
io_4iomodule_a_index: 1gpio_index: 333
io_4iomodule_c5_index: 59gpio_index: 134
io_4iomodule_a_index: 2gpio_index: 329
io_4iomodule_a_index: 9gpio_index: 325
io_4iomodule_c5_index: 48gpio_index: 139
io_4iomodule_a_index: 6gpio_index: 321
io_4iomodule_a_index: 17gpio_index: 317
io_4iomodule_c5_index: 40gpio_index: 142
io_4iomodule_c5_index: 11gpio_index: 147
io_4iomodule_c5_index: 58gpio_index: 150
io_4iomodule_c5_index: 21gpio_index: 155
io_4iomodule_c5_index: 49gpio_index: 158
io_4iomodule_h_c5_index: 0gpio_index: 161
io_4iomodule_h_c5_index: 6gpio_index: 165
io_4iomodule_h_c5_index: 10gpio_index: 169
io_4iomodule_h_c5_index: 3gpio_index: 173
io_4iomodule_h_c5_index: 8gpio_index: 176
io_4iomodule_h_c5_index: 11gpio_index: 180
io_4iomodule_h_c5_index: 7gpio_index: 184
io_4iomodule_h_c5_index: 5gpio_index: 188
io_4iomodule_h_c5_index: 1gpio_index: 192
io_4iomodule_h_c5_index: 2gpio_index: 196
io_4iomodule_h_c5_index: 9gpio_index: 200
io_4iomodule_h_c5_index: 4gpio_index: 204
io_4iomodule_h_index: 15gpio_index: 208
io_4iomodule_h_index: 1gpio_index: 212
io_4iomodule_h_index: 3gpio_index: 216
io_4iomodule_h_index: 2gpio_index: 220
io_4iomodule_h_index: 11gpio_index: 224
io_4iomodule_vref_h_index: 1gpio_index: 228
io_4iomodule_h_index: 20gpio_index: 231
io_4iomodule_h_index: 8gpio_index: 235
io_4iomodule_h_index: 6gpio_index: 239
io_4iomodule_h_index: 10gpio_index: 243
io_4iomodule_h_index: 23gpio_index: 247
io_4iomodule_h_index: 7gpio_index: 251
io_4iomodule_h_index: 22gpio_index: 255
io_4iomodule_h_index: 5gpio_index: 259
io_4iomodule_h_index: 24gpio_index: 263
io_4iomodule_h_index: 0gpio_index: 267
io_4iomodule_h_index: 13gpio_index: 271
io_4iomodule_h_index: 21gpio_index: 275
io_4iomodule_h_index: 16gpio_index: 279
io_4iomodule_vref_h_index: 0gpio_index: 283
io_4iomodule_h_index: 12gpio_index: 286
io_4iomodule_h_index: 4gpio_index: 290
io_4iomodule_h_index: 19gpio_index: 294
io_4iomodule_h_index: 18gpio_index: 298
io_4iomodule_h_index: 17gpio_index: 302
io_4iomodule_h_index: 25gpio_index: 306
io_4iomodule_h_index: 14gpio_index: 310
io_4iomodule_h_index: 9gpio_index: 314

BIN
db/.cmp.kpt Normal file
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Binary file not shown.

300
db/altsyncram_dsq1.tdf Normal file
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--altsyncram ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone V" INDATA_ACLR_A="NONE" INIT_FILE="db/chip8.ram0_memory_e9e85012.hdl.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=4096 NUMWORDS_B=4096 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED" READ_DURING_WRITE_MODE_MIXED_PORTS="OLD_DATA" WIDTH_A=8 WIDTH_B=8 WIDTHAD_A=12 WIDTHAD_B=12 WRCONTROL_ACLR_A="NONE" address_a address_b clock0 data_a q_b CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
--VERSION_BEGIN 23.1 cbx_altera_syncram_nd_impl 2023:11:29:19:33:06:SC cbx_altsyncram 2023:11:29:19:33:06:SC cbx_cycloneii 2023:11:29:19:33:06:SC cbx_lpm_add_sub 2023:11:29:19:33:06:SC cbx_lpm_compare 2023:11:29:19:33:06:SC cbx_lpm_decode 2023:11:29:19:33:06:SC cbx_lpm_mux 2023:11:29:19:33:05:SC cbx_mgl 2023:11:29:19:43:53:SC cbx_nadder 2023:11:29:19:33:06:SC cbx_stratix 2023:11:29:19:33:06:SC cbx_stratixii 2023:11:29:19:33:05:SC cbx_stratixiii 2023:11:29:19:33:06:SC cbx_stratixv 2023:11:29:19:33:05:SC cbx_util_mgl 2023:11:29:19:33:06:SC VERSION_END
-- Copyright (C) 2023 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details, at
-- https://fpgasoftware.intel.com/eula.
FUNCTION cyclonev_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, ENABLE_ECC, INIT_FILE, INIT_FILE_LAYOUT, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init10, mem_init11, mem_init12, mem_init13, mem_init14, mem_init15, mem_init16, mem_init17, mem_init18, mem_init19, mem_init2, mem_init20, mem_init21, mem_init22, mem_init23, mem_init24, mem_init25, mem_init26, mem_init27, mem_init28, mem_init29, mem_init3, mem_init30, mem_init31, mem_init32, mem_init33, mem_init34, mem_init35, mem_init36, mem_init37, mem_init38, mem_init39, mem_init4, mem_init40, mem_init41, mem_init42, mem_init43, mem_init44, mem_init45, mem_init46, mem_init47, mem_init48, mem_init49, mem_init5, mem_init50, mem_init51, mem_init52, mem_init53, mem_init54, mem_init55, mem_init56, mem_init57, mem_init58, mem_init59, mem_init6, mem_init60, mem_init61, mem_init62, mem_init63, mem_init64, mem_init65, mem_init66, mem_init67, mem_init68, mem_init69, mem_init7, mem_init70, mem_init71, mem_init8, mem_init9, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, WIDTH_ECCSTATUS = 3)
RETURNS ( dftout[8..0], eccstatus[WIDTH_ECCSTATUS-1..0], portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
--synthesis_resources = M10K 4
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
SUBDESIGN altsyncram_dsq1
(
address_a[11..0] : input;
address_b[11..0] : input;
clock0 : input;
data_a[7..0] : input;
q_b[7..0] : output;
)
VARIABLE
ram_block1a0 : cyclonev_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "db/chip8.ram0_memory_e9e85012.hdl.mif",
INIT_FILE_LAYOUT = "port_b",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 4095,
PORT_A_LOGICAL_RAM_DEPTH = 4096,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 0,
PORT_B_LAST_ADDRESS = 4095,
PORT_B_LOGICAL_RAM_DEPTH = 4096,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a1 : cyclonev_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "db/chip8.ram0_memory_e9e85012.hdl.mif",
INIT_FILE_LAYOUT = "port_b",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 1,
PORT_A_LAST_ADDRESS = 4095,
PORT_A_LOGICAL_RAM_DEPTH = 4096,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 1,
PORT_B_LAST_ADDRESS = 4095,
PORT_B_LOGICAL_RAM_DEPTH = 4096,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a2 : cyclonev_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "db/chip8.ram0_memory_e9e85012.hdl.mif",
INIT_FILE_LAYOUT = "port_b",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 2,
PORT_A_LAST_ADDRESS = 4095,
PORT_A_LOGICAL_RAM_DEPTH = 4096,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 2,
PORT_B_LAST_ADDRESS = 4095,
PORT_B_LOGICAL_RAM_DEPTH = 4096,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a3 : cyclonev_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "db/chip8.ram0_memory_e9e85012.hdl.mif",
INIT_FILE_LAYOUT = "port_b",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 3,
PORT_A_LAST_ADDRESS = 4095,
PORT_A_LOGICAL_RAM_DEPTH = 4096,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 3,
PORT_B_LAST_ADDRESS = 4095,
PORT_B_LOGICAL_RAM_DEPTH = 4096,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a4 : cyclonev_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "db/chip8.ram0_memory_e9e85012.hdl.mif",
INIT_FILE_LAYOUT = "port_b",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 4,
PORT_A_LAST_ADDRESS = 4095,
PORT_A_LOGICAL_RAM_DEPTH = 4096,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 4,
PORT_B_LAST_ADDRESS = 4095,
PORT_B_LOGICAL_RAM_DEPTH = 4096,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a5 : cyclonev_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "db/chip8.ram0_memory_e9e85012.hdl.mif",
INIT_FILE_LAYOUT = "port_b",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 5,
PORT_A_LAST_ADDRESS = 4095,
PORT_A_LOGICAL_RAM_DEPTH = 4096,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 5,
PORT_B_LAST_ADDRESS = 4095,
PORT_B_LOGICAL_RAM_DEPTH = 4096,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a6 : cyclonev_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "db/chip8.ram0_memory_e9e85012.hdl.mif",
INIT_FILE_LAYOUT = "port_b",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 6,
PORT_A_LAST_ADDRESS = 4095,
PORT_A_LOGICAL_RAM_DEPTH = 4096,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 6,
PORT_B_LAST_ADDRESS = 4095,
PORT_B_LOGICAL_RAM_DEPTH = 4096,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a7 : cyclonev_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "db/chip8.ram0_memory_e9e85012.hdl.mif",
INIT_FILE_LAYOUT = "port_b",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 7,
PORT_A_LAST_ADDRESS = 4095,
PORT_A_LOGICAL_RAM_DEPTH = 4096,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 7,
PORT_B_LAST_ADDRESS = 4095,
PORT_B_LOGICAL_RAM_DEPTH = 4096,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "AUTO"
);
address_a_wire[11..0] : WIRE;
address_b_wire[11..0] : WIRE;
wren_a : NODE;
BEGIN
ram_block1a[7..0].clk0 = clock0;
ram_block1a[7..0].portaaddr[] = ( address_a_wire[11..0]);
ram_block1a[0].portadatain[] = ( data_a[0..0]);
ram_block1a[1].portadatain[] = ( data_a[1..1]);
ram_block1a[2].portadatain[] = ( data_a[2..2]);
ram_block1a[3].portadatain[] = ( data_a[3..3]);
ram_block1a[4].portadatain[] = ( data_a[4..4]);
ram_block1a[5].portadatain[] = ( data_a[5..5]);
ram_block1a[6].portadatain[] = ( data_a[6..6]);
ram_block1a[7].portadatain[] = ( data_a[7..7]);
ram_block1a[7..0].portawe = wren_a;
ram_block1a[7..0].portbaddr[] = ( address_b_wire[11..0]);
ram_block1a[7..0].portbre = B"11111111";
address_a_wire[] = address_a[];
address_b_wire[] = address_b[];
q_b[] = ( ram_block1a[7..0].portbdataout[0..0]);
wren_a = GND;
END;
--VALID FILE

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1712551930527 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition " "Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1712551930527 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 7 23:52:10 2024 " "Processing started: Sun Apr 7 23:52:10 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1712551930527 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1712551930527 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off chip8 -c chip8 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off chip8 -c chip8" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1712551930527 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1712551931223 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1712551937283 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "631 " "Peak virtual memory: 631 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1712551937598 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 7 23:52:17 2024 " "Processing ended: Sun Apr 7 23:52:17 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1712551937598 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1712551937598 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1712551937598 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1712551937598 ""}

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v1
IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,
IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 0 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000001;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000047;IO_000046;IO_000045;IO_000027;IO_000026;IO_000024;IO_000023;IO_000022;IO_000021;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000034,
IO_RULES_MATRIX,Total Pass,0;10;10;0;0;10;10;0;0;0;0;0;0;1;0;0;0;0;1;0;0;0;0;1;0;10;10;0,
IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
IO_RULES_MATRIX,Total Inapplicable,10;0;0;10;10;0;0;10;10;10;10;10;10;9;10;10;10;10;9;10;10;10;10;9;10;0;0;10,
IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
IO_RULES_MATRIX,lcd_clk,Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,lcd_data,Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,led[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,led[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,led[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,led[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,led[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,led[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,rst_in,Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_MATRIX,fpga_clk,Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
IO_RULES_SUMMARY,Total I/O Rules,28,
IO_RULES_SUMMARY,Number of I/O Rules Passed,9,
IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,19,

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1712551938749 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition " "Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1712551938749 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 7 23:52:18 2024 " "Processing started: Sun Apr 7 23:52:18 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1712551938749 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1712551938749 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta chip8 -c chip8 " "Command: quartus_sta chip8 -c chip8" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1712551938749 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1712551938772 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1712551939456 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "12 12 " "Parallel compilation is enabled and will use 12 of the 12 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1712551939456 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature -40 degrees C " "Low junction temperature is -40 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712551939481 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 100 degrees C " "High junction temperature is 100 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712551939481 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "chip8.sdc " "Synopsys Design Constraints File file not found: 'chip8.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1712551940847 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1712551940847 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name fpga_clk fpga_clk " "create_clock -period 1.000 -name fpga_clk fpga_clk" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1712551940934 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " "create_clock -period 1.000 -name cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1712551940934 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1712551940934 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1712551941197 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1712551941259 ""}
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1712551941263 ""}
{ "Info" "0" "" "Analyzing Slow 1100mV 100C Model" { } { } 0 0 "Analyzing Slow 1100mV 100C Model" 0 0 "Timing Analyzer" 0 0 1712551941268 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1712551945434 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1712551945434 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -28.406 " "Worst-case setup slack is -28.406" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551945434 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551945434 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -28.406 -1742.530 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " -28.406 -1742.530 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551945434 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -11.186 -95769.392 fpga_clk " " -11.186 -95769.392 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551945434 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712551945434 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.429 " "Worst-case hold slack is 0.429" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551945664 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551945664 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.429 0.000 fpga_clk " " 0.429 0.000 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551945664 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.476 0.000 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " 0.476 0.000 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551945664 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712551945664 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1712551945666 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1712551945667 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.636 " "Worst-case minimum pulse width slack is -2.636" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551945672 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551945672 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.636 -8463.323 fpga_clk " " -2.636 -8463.323 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551945672 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.538 -185.389 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " -0.538 -185.389 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551945672 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712551945672 ""}
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 8 synchronizer chains. " "Report Metastability: Found 8 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Design MTBF is not calculated because the design doesn't meet its timing requirements. " "Design MTBF is not calculated because the design doesn't meet its timing requirements." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1712551945720 ""} } { } 0 332114 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1712551945720 ""}
{ "Info" "0" "" "Analyzing Slow 1100mV -40C Model" { } { } 0 0 "Analyzing Slow 1100mV -40C Model" 0 0 "Timing Analyzer" 0 0 1712551945722 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1712551945782 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1712551951737 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1712551952797 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1712551953465 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1712551953465 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -26.933 " "Worst-case setup slack is -26.933" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551953465 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551953465 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -26.933 -1684.576 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " -26.933 -1684.576 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551953465 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -11.228 -94100.779 fpga_clk " " -11.228 -94100.779 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551953465 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712551953465 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.484 " "Worst-case hold slack is 0.484" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551953711 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551953711 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.484 0.000 fpga_clk " " 0.484 0.000 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551953711 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.565 0.000 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " 0.565 0.000 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551953711 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712551953711 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1712551953712 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1712551953713 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.636 " "Worst-case minimum pulse width slack is -2.636" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551953723 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551953723 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.636 -8927.522 fpga_clk " " -2.636 -8927.522 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551953723 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.538 -184.012 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " -0.538 -184.012 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551953723 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712551953723 ""}
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 8 synchronizer chains. " "Report Metastability: Found 8 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Design MTBF is not calculated because the design doesn't meet its timing requirements. " "Design MTBF is not calculated because the design doesn't meet its timing requirements." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1712551953779 ""} } { } 0 332114 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1712551953779 ""}
{ "Info" "0" "" "Analyzing Fast 1100mV 100C Model" { } { } 0 0 "Analyzing Fast 1100mV 100C Model" 0 0 "Timing Analyzer" 0 0 1712551953781 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1712551954065 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1712551959681 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1712551960616 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1712551960917 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1712551960917 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -14.774 " "Worst-case setup slack is -14.774" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551960918 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551960918 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -14.774 -901.498 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " -14.774 -901.498 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551960918 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -6.214 -50560.530 fpga_clk " " -6.214 -50560.530 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551960918 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712551960918 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.162 " "Worst-case hold slack is 0.162" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551961180 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551961180 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.162 0.000 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " 0.162 0.000 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551961180 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.177 0.000 fpga_clk " " 0.177 0.000 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551961180 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712551961180 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1712551961181 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1712551961181 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.174 " "Worst-case minimum pulse width slack is -2.174" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551961192 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551961192 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.174 -1371.543 fpga_clk " " -2.174 -1371.543 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551961192 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.192 -9.702 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " -0.192 -9.702 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551961192 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712551961192 ""}
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 8 synchronizer chains. " "Report Metastability: Found 8 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Design MTBF is not calculated because the design doesn't meet its timing requirements. " "Design MTBF is not calculated because the design doesn't meet its timing requirements." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1712551961244 ""} } { } 0 332114 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1712551961244 ""}
{ "Info" "0" "" "Analyzing Fast 1100mV -40C Model" { } { } 0 0 "Analyzing Fast 1100mV -40C Model" 0 0 "Timing Analyzer" 0 0 1712551961245 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1712551961832 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1712551962139 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1712551962139 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -12.462 " "Worst-case setup slack is -12.462" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551962139 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551962139 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -12.462 -739.747 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " -12.462 -739.747 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551962139 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.930 -40871.978 fpga_clk " " -4.930 -40871.978 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551962139 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712551962139 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.140 " "Worst-case hold slack is 0.140" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551962440 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551962440 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.140 0.000 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " 0.140 0.000 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551962440 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.164 0.000 fpga_clk " " 0.164 0.000 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551962440 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712551962440 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1712551962441 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1712551962441 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.174 " "Worst-case minimum pulse width slack is -2.174" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551962451 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551962451 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.174 -1373.239 fpga_clk " " -2.174 -1373.239 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551962451 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.137 -3.355 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " -0.137 -3.355 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551962451 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712551962451 ""}
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 8 synchronizer chains. " "Report Metastability: Found 8 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Design MTBF is not calculated because the design doesn't meet its timing requirements. " "Design MTBF is not calculated because the design doesn't meet its timing requirements." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1712551962500 ""} } { } 0 332114 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1712551962500 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1712551963345 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1712551963345 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1353 " "Peak virtual memory: 1353 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1712551963512 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 7 23:52:43 2024 " "Processing ended: Sun Apr 7 23:52:43 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1712551963512 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:25 " "Elapsed time: 00:00:25" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1712551963512 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:01:44 " "Total CPU time (on all processors): 00:01:44" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1712551963512 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1712551963512 ""}

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7aee213afbf8301ed5eefc8c827f49a3

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Assembler report for chip8
Sun Apr 7 23:52:17 2024
Quartus Prime Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Assembler Summary
3. Assembler Settings
4. Assembler Generated Files
5. Assembler Device Options: chip8.sof
6. Assembler Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2023 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Sun Apr 7 23:52:17 2024 ;
; Revision Name ; chip8 ;
; Top-level Entity Name ; chip8 ;
; Family ; Cyclone V ;
; Device ; 5CSEBA6U23I7 ;
+-----------------------+---------------------------------------+
+----------------------------------+
; Assembler Settings ;
+--------+---------+---------------+
; Option ; Setting ; Default Value ;
+--------+---------+---------------+
+-------------------------------------------------------------------------------+
; Assembler Generated Files ;
+-------------------------------------------------------------------------------+
; File Name ;
+-------------------------------------------------------------------------------+
; /home/nickorlow/programming/school/warminster/yayacemu/output_files/chip8.sof ;
+-------------------------------------------------------------------------------+
+-------------------------------------+
; Assembler Device Options: chip8.sof ;
+----------------+--------------------+
; Option ; Setting ;
+----------------+--------------------+
; JTAG usercode ; 0x02233A94 ;
; Checksum ; 0x02233A94 ;
+----------------+--------------------+
+--------------------+
; Assembler Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus Prime Assembler
Info: Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition
Info: Processing started: Sun Apr 7 23:52:10 2024
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off chip8 -c chip8
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (115030): Assembler is generating device programming files
Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
Info: Peak virtual memory: 631 megabytes
Info: Processing ended: Sun Apr 7 23:52:17 2024
Info: Elapsed time: 00:00:07
Info: Total CPU time (on all processors): 00:00:07

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/* Quartus Prime Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition */
JedecChain;
FileRevision(JESD32A);
DefaultMfr(6E);
P ActionCode(Ign)
Device PartName(SOCVHPS) MfrSpec(OpMask(0));
P ActionCode(Cfg)
Device PartName(5CSEBA6U23) Path("/home/nickorlow/programming/school/warminster/yayacemu/output_files/") File("chip8.sof") MfrSpec(OpMask(1));
ChainEnd;
AlteraBegin;
ChainType(JTAG);
AlteraEnd;

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Extra Info (176236): Started Fast Input/Output/OE register processing
Extra Info (176237): Finished Fast Input/Output/OE register processing
Extra Info (176238): Start inferring scan chains for DSP blocks
Extra Info (176239): Inferring scan chains for DSP blocks is complete
Extra Info (176246): Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density
Extra Info (176247): Finished moving registers into I/O cells, DSP blocks, and RAM blocks

20
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Fitter Status : Successful - Sun Apr 7 23:52:05 2024
Quartus Prime Version : 23.1std.0 Build 991 11/28/2023 SC Lite Edition
Revision Name : chip8
Top-level Entity Name : chip8
Family : Cyclone V
Device : 5CSEBA6U23I7
Timing Models : Final
Logic utilization (in ALMs) : 10,549 / 41,910 ( 25 % )
Total registers : 10004
Total pins : 10 / 314 ( 3 % )
Total virtual pins : 0
Total block memory bits : 32,768 / 5,662,720 ( < 1 % )
Total RAM Blocks : 4 / 553 ( < 1 % )
Total DSP Blocks : 0 / 112 ( 0 % )
Total HSSI RX PCSs : 0
Total HSSI PMA RX Deserializers : 0
Total HSSI TX PCSs : 0
Total HSSI PMA TX Serializers : 0
Total PLLs : 0 / 6 ( 0 % )
Total DLLs : 0 / 4 ( 0 % )

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<sld_project_info>
<project>
<hash md5_digest_80b="07d8c25fa74d161dca94"/>
</project>
<file_info>
<file device="5CSEBA6U23I7" path="chip8.sof" usercode="0xFFFFFFFF"/>
</file_info>
</sld_project_info>

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-- Copyright (C) 2023 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details, at
-- https://fpgasoftware.intel.com/eula.
--
-- This is a Quartus Prime output file. It is for reporting purposes only, and is
-- not intended for use as a Quartus Prime input file. This file cannot be used
-- to make Quartus Prime pin assignments - for instructions on how to make pin
-- assignments, please see Quartus Prime help.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- NC : No Connect. This pin has no internal connection to the device.
-- DNU : Do Not Use. This pin MUST NOT be connected.
-- VCCPGM : Dedicated power pin for configuration, which MUST be connected to 1.8V, 2.5V, 3.0V or 3.3V depending on the requirements of the configuration device.
-- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.1V).
-- VCCIO : Dedicated power pin, which MUST be connected to VCC
-- of its bank.
-- Bank 3A: 2.5V
-- Bank 3B: 3.3V
-- Bank 4A: 3.3V
-- Bank 5A: 3.3V
-- Bank 5B: 2.5V
-- Bank 6B: 2.5V
-- Bank 6A: 2.5V
-- Bank 7A: 2.5V
-- Bank 7B: 2.5V
-- Bank 7C: 2.5V
-- Bank 7D: 2.5V
-- Bank 8A: 2.5V
-- Bank 9A: Dedicated configuration pins only, no VCCIO required.
-- RREF : External reference resistor for the quad, MUST be connected to
-- GND via a 2k Ohm resistor.
-- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
-- It can also be used to report unused dedicated pins. The connection
-- on the board for unused dedicated pins depends on whether this will
-- be used in a future design. One example is device migration. When
-- using device migration, refer to the device pin-tables. If it is a
-- GND pin in the pin table or if it will not be used in a future design
-- for another purpose the it MUST be connected to GND. If it is an unused
-- dedicated pin, then it can be connected to a valid signal on the board
-- (low, high, or toggling) if that signal is required for a different
-- revision of the design.
-- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
-- This pin should be connected to GND. It may also be connected to a
-- valid signal on the board (low, high, or toggling) if that signal
-- is required for a different revision of the design.
-- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND
-- or leave it unconnected.
-- RESERVED : Unused I/O pin, which MUST be left unconnected.
-- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
-- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
-- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
-- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
-- GXB_NC : Unused GXB Transmitter or dedicated clock output pin. This pin
-- must not be connected.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- Pin directions (input, output or bidir) are based on device operating in user mode.
---------------------------------------------------------------------------------
Quartus Prime Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition
CHIP "chip8" ASSIGNED TO AN: 5CSEBA6U23I7
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
-------------------------------------------------------------------------------------------------------------
DNU : A2 : : : : :
GND : A3 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 7C :
RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : : : : 7C :
RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 7B :
RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 7B :
RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 7B :
RESERVED_INPUT_WITH_WEAK_PULLUP : A9 : : : : 7B :
GND : A10 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 7B :
RESERVED_INPUT_WITH_WEAK_PULLUP : A12 : : : : 7B :
RESERVED_INPUT_WITH_WEAK_PULLUP : A13 : : : : 7B :
RESERVED_INPUT_WITH_WEAK_PULLUP : A14 : : : : 7B :
RESERVED_INPUT_WITH_WEAK_PULLUP : A15 : : : : 7B :
RESERVED_INPUT_WITH_WEAK_PULLUP : A16 : : : : 7B :
RESERVED_INPUT_WITH_WEAK_PULLUP : A17 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : A18 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : A20 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : A21 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : A22 : : : : 7A :
HPS_nRST : A23 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : A24 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : A25 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : A26 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : A27 : : : : 6A :
GND : AA1 : gnd : : : :
GND : AA2 : gnd : : : :
GND : AA3 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA4 : : : : 3A :
VCCIO3A : AA5 : power : : 2.5V : 3A :
nCSO, DATA4 : AA6 : : : : 3A :
DCLK : AA8 : : : : 3A :
GND : AA9 : gnd : : : :
VCCPD3A : AA10 : power : : 2.5V : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA11 : : : : 3A :
VCCIO3B : AA12 : power : : 3.3V : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA13 : : : : 4A :
VCCPD3B4A : AA14 : power : : 3.3V : 3B, 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA15 : : : : 4A :
VCCIO4A : AA16 : power : : 3.3V : 4A :
GND : AA17 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA18 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA19 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA20 : : : : 5A :
VCCA_FPLL : AA21 : power : : 2.5V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA23 : : : : 5A :
led[1] : AA24 : output : 3.3-V LVTTL : : 5A : Y
VREFB5BN0 : AA25 : power : : : 5B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA26 : : : : 5B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA27 : : : : 6B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA28 : : : : 6B :
GND : AB1 : gnd : : : :
GND : AB2 : gnd : : : :
GND : AB3 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB4 : : : : 3A :
TCK : AB5 : input : : : 3A :
AS_DATA3, DATA3 : AB6 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB23 : : : : 5A :
GND : AB24 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB25 : : : : 5B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB26 : : : : 5B :
GND : AB27 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB28 : : : : 6B :
GND : AC1 : gnd : : : :
GND : AC2 : gnd : : : :
GND : AC3 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC4 : : : : 3A :
AS_DATA2, DATA2 : AC5 : : : : 3A :
AS_DATA1, DATA1 : AC6 : : : : 3A :
TMS : AC7 : input : : : 3A :
VCC_AUX : AC8 : power : : 2.5V : :
VCC_AUX : AC21 : power : : 2.5V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC22 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC23 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC24 : : : : 5A :
VCCIO5A : AC25 : power : : 3.3V : 5A :
VREFB5AN0 : AC26 : power : : : 5A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC27 : : : : 6B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC28 : : : : 6B :
DNU : AD1 : : : : :
DNU : AD2 : : : : :
GND : AD3 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD4 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD5 : : : : 3A :
GND : AD6 : gnd : : : :
AS_DATA0, ASDO, DATA0 : AD7 : : : : 3A :
GND : AD8 : gnd : : : :
VCCPD3B4A : AD9 : power : : 3.3V : 3B, 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD10 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD11 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD12 : : : : 3B :
VCCPD3B4A : AD13 : power : : 3.3V : 3B, 4A :
GND : AD14 : gnd : : : :
VCC_AUX : AD15 : power : : 2.5V : :
VCCPD3B4A : AD16 : power : : 3.3V : 3B, 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD17 : : : : 4A :
VCCPD3B4A : AD18 : power : : 3.3V : 3B, 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD19 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD20 : : : : 4A :
VCCPD3B4A : AD21 : power : : 3.3V : 3B, 4A :
GND : AD22 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD23 : : : : 4A :
VCCPGM : AD24 : power : : 1.8V/2.5V/3.0V/3.3V : :
GND : AD25 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD26 : : : : 5A :
VCCIO6B_HPS : AD27 : power : : 2.5V : 6B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD28 : : : : 6B :
GND : AE1 : gnd : : : :
GND : AE2 : gnd : : : :
GND : AE3 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE4 : : : : 3B :
VREFB3AN0 : AE5 : power : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE6 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE7 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE8 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE9 : : : : 3B :
VCCIO3B : AE10 : power : : 3.3V : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE11 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE12 : : : : 3B :
VCCIO3B : AE13 : power : : 3.3V : 3B :
DNU : AE14 : : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE15 : : : : 4A :
GND : AE16 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE17 : : : : 4A :
GND : AE18 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE19 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE20 : : : : 4A :
VCCIO4A : AE21 : power : : 3.3V : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE22 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE23 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE24 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE25 : : : : 5A :
led[5] : AE26 : output : 3.3-V LVTTL : : 5A : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : AE27 : : : : 6B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE28 : : : : 6B :
GND : AF1 : gnd : : : :
GND : AF2 : gnd : : : :
GND : AF3 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF4 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF5 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF6 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF7 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF8 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF9 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF10 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF11 : : : : 3B :
VREFB3BN0 : AF12 : power : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF13 : : : : 4A :
VCCIO4A : AF14 : power : : 3.3V : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF15 : : : : 4A :
VREFB4AN0 : AF16 : power : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF17 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF18 : : : : 4A :
VCCIO4A : AF19 : power : : 3.3V : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF20 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF21 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF22 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF23 : : : : 4A :
GND : AF24 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF25 : : : : 4A :
led[4] : AF26 : output : 3.3-V LVTTL : : 5A : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : AF27 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF28 : : : : 4A :
GND : AG1 : gnd : : : :
GND : AG2 : gnd : : : :
GND : AG3 : gnd : : : :
VCCIO3B : AG4 : power : : 3.3V : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AG5 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AG6 : : : : 3B :
GND : AG7 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AG8 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AG9 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AG10 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AG11 : : : : 4A :
VCCIO4A : AG12 : power : : 3.3V : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AG13 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AG14 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AG15 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AG16 : : : : 4A :
GND : AG17 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AG18 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AG19 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AG20 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AG21 : : : : 4A :
VCCIO4A : AG22 : power : : 3.3V : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AG23 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AG24 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AG25 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AG26 : : : : 4A :
GND : AG27 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AG28 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AH2 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AH3 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AH4 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AH5 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AH6 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : AH7 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AH8 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AH9 : : : : 4A :
GND : AH10 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AH11 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AH12 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AH13 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AH14 : : : : 4A :
VCCIO4A : AH15 : power : : 3.3V : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AH16 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AH17 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AH18 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AH19 : : : : 4A :
GND : AH20 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AH21 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AH22 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AH23 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AH24 : : : : 4A :
VCCIO4A : AH25 : power : : 3.3V : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AH26 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : AH27 : : : : 4A :
GND : B1 : : : : :
DNU : B2 : : : : :
GND : B3 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 7C :
GND : B5 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 7C :
GND : B7 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 7C :
RESERVED_INPUT_WITH_WEAK_PULLUP : B9 : : : : 7C :
VCCIO7C_HPS : B10 : power : : 2.5V : 7C :
RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 7C :
RESERVED_INPUT_WITH_WEAK_PULLUP : B12 : : : : 7C :
VCCIO7B_HPS : B13 : power : : 2.5V : 7B :
RESERVED_INPUT_WITH_WEAK_PULLUP : B14 : : : : 7B :
GND : B15 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : B16 : : : : 7A :
GND : B17 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : B18 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : B19 : : : : 7A :
GND : B20 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 7A :
GND : B22 : gnd : : : :
HPS_TDO : B23 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : B24 : : : : 6A :
GND : B25 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : B26 : : : : 6A :
GND : B27 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : B28 : : : : 6A :
GND : C1 : gnd : : : :
GND : C2 : gnd : : : :
GND : C3 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : : : : 7D :
RESERVED_INPUT_WITH_WEAK_PULLUP : C5 : : : : 7D :
RESERVED_INPUT_WITH_WEAK_PULLUP : C6 : : : : 7D :
RESERVED_INPUT_WITH_WEAK_PULLUP : C7 : : : : 7D :
RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 7D :
RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 7D :
RESERVED_INPUT_WITH_WEAK_PULLUP : C10 : : : : 7D :
GND : C11 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : C12 : : : : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 7C :
RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 7B :
RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 7B :
RESERVED_INPUT_WITH_WEAK_PULLUP : C16 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : C17 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : C18 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7A :
VCCIO7A_HPS : C20 : power : : 2.5V : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : C21 : : : : 7A :
HPS_TRST : C22 : : : : 7A :
HPS_TMS : C23 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : C24 : : : : 6A :
VCCIO6A_HPS : C25 : power : : 2.5V : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : C26 : : : : 6A :
VCCIO6A_HPS : C27 : power : : 2.5V : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : C28 : : : : 6A :
DNU : D1 : : : : :
DNU : D2 : : : : :
GND : D3 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : D4 : : : : 7D :
RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 7D :
VCCIO7D_HPS : D6 : power : : 2.5V : 7D :
VCCBAT : D7 : power : : 1.2V : :
lcd_clk : D8 : output : 2.5 V : : 8A : Y
VREFB8AN0 : D9 : power : : : 8A :
GND : D10 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : D11 : : : : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 8A :
GND : D13 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 7C :
RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 7B :
GND : D16 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : D17 : : : : 7B :
VCCIO7A_HPS : D18 : power : : 2.5V : 7A :
VREFB7A7B7C7DN0_HPS : D19 : power : : : 7A, 7B, 7C, 7D :
HPS_CLK2 : D20 : : : : 7A :
GND : D21 : : : : 7A :
HPS_TDI : D22 : : : : 7A :
DNU : D23 : : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : D24 : : : : 6A :
HPS_RZQ_0 : D25 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : D26 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : D27 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : D28 : : : : 6A :
GND : E1 : gnd : : : :
GND : E2 : gnd : : : :
GND : E3 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : E4 : : : : 7D :
RESERVED_INPUT_WITH_WEAK_PULLUP : E5 : : : : 7D :
nCE : E6 : : : : 9A :
VCCIO8A : E7 : power : : 2.5V : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : E8 : : : : 8A :
GND : E9 : gnd : : : :
VCCPD8A : E10 : power : : 2.5V : 8A :
RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 8A :
DNU : E12 : : : : :
VCCPD7D_HPS : E13 : power : : 2.5V : 7D :
VCCPD7C_HPS : E14 : power : : 2.5V : 7C :
VCC_AUX : E15 : power : : 2.5V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : E16 : : : : 7B :
VCCPD7B_HPS : E17 : power : : 2.5V : 7B :
HPS_PORSEL : E18 : : : : 7A :
GND : E19 : gnd : : : :
HPS_CLK1 : E20 : : : : 7A :
VCCPD7A_HPS : E21 : power : : 2.5V : 7A :
GND : E22 : gnd : : : :
GND : E23 : : : : 7A :
GND : E24 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : E25 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : E26 : : : : 6A :
GND : E27 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : E28 : : : : 6A :
GND : F1 : gnd : : : :
GND : F2 : gnd : : : :
GND : F3 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : F4 : : : : 7D :
RESERVED_INPUT_WITH_WEAK_PULLUP : F5 : : : : 7D :
GND : F6 : : : : 9A :
nCONFIG : F7 : : : : 9A :
VCC_AUX : F8 : power : : 2.5V : :
VCC_AUX_SHARED : F21 : power : : 2.5V : :
VCCRSTCLK_HPS : F22 : power : : 1.8V/2.5V/3.0V/3.3V : :
GND : F23 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : F24 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : F25 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : F26 : : : : 6A :
VCCIO6A_HPS : F27 : power : : 2.5V : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : F28 : : : : 6A :
GND : G1 : gnd : : : :
GND : G2 : gnd : : : :
GND : G3 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : G4 : : : : 7D :
VCCIO7D_HPS : G5 : power : : 2.5V : 7D :
MSEL2 : G6 : : : : 9A :
RESERVED_INPUT_WITH_WEAK_PULLUP : G23 : : : : 6A :
VCCIO6A_HPS : G24 : power : : 2.5V : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : G25 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : G26 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : G27 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : G28 : : : : 6A :
DNU : H1 : : : : :
DNU : H2 : : : : :
GND : H3 : gnd : : : :
GND : H4 : gnd : : : :
GND : H5 : gnd : : : :
GND : H6 : gnd : : : :
nSTATUS : H8 : : : : 9A :
MSEL1 : H9 : : : : 9A :
VCCPGM : H10 : power : : 1.8V/2.5V/3.0V/3.3V : :
GND : H11 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 7C :
RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 7C :
VCCIO7B_HPS : H14 : power : : 2.5V : 7B :
GND : H15 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : H16 : : : : 7B :
RESERVED_INPUT_WITH_WEAK_PULLUP : H17 : : : : 7A :
GND : H18 : gnd : : : :
HPS_nPOR : H19 : : : : 7A :
GND : H20 : gnd : : : :
VCCIO6A_HPS : H21 : power : : 2.5V : 6A :
VCCPLL_HPS : H23 : power : : 2.5V : :
GND : H24 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : H25 : : : : 6A :
VCCIO6A_HPS : H26 : power : : 2.5V : 6A :
GND : H27 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : H28 : : : : 6A :
GND : J1 : gnd : : : :
GND : J2 : gnd : : : :
GND : J3 : gnd : : : :
VCCA_FPLL : J4 : power : : 2.5V : :
GND : J5 : gnd : : : :
CONF_DONE : J8 : : : : 9A :
GND : J9 : gnd : : : :
MSEL0 : J10 : : : : 9A :
VCC : J11 : power : : 1.1V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : J12 : : : : 7B :
RESERVED_INPUT_WITH_WEAK_PULLUP : J13 : : : : 7B :
RESERVED_INPUT_WITH_WEAK_PULLUP : J14 : : : : 7B :
RESERVED_INPUT_WITH_WEAK_PULLUP : J15 : : : : 7B :
RESERVED_INPUT_WITH_WEAK_PULLUP : J16 : : : : 7B :
RESERVED_INPUT_WITH_WEAK_PULLUP : J17 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : J18 : : : : 7A :
VCCRSTCLK_HPS : J19 : : : : 7A :
RESERVED_INPUT_WITH_WEAK_PULLUP : J20 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : J21 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : J24 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : J25 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : J26 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : J27 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : J28 : : : : 6A :
GND : K1 : gnd : : : :
GND : K2 : gnd : : : :
GND : K3 : gnd : : : :
GND : K4 : gnd : : : :
VCCA_FPLL : K5 : power : : 2.5V : :
GND : K8 : gnd : : : :
MSEL4 : K9 : : : : 9A :
MSEL3 : K10 : : : : 9A :
GND : K11 : gnd : : : :
GND : K12 : gnd : : : :
VCC : K13 : power : : 1.1V : :
GND : K14 : gnd : : : :
VCC : K15 : power : : 1.1V : :
GND : K16 : gnd : : : :
VCC_HPS : K17 : power : : 1.1V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : K18 : : : : 7A :
HPS_TCK : K19 : : : : 7A :
GND : K20 : gnd : : : :
VCCPD6A6B_HPS : K21 : power : : 2.5V : 6A, 6B :
VCCPD6A6B_HPS : K24 : power : : 2.5V : 6A, 6B :
RESERVED_INPUT_WITH_WEAK_PULLUP : K25 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : K26 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : K27 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : K28 : : : : 6A :
GND : L1 : gnd : : : :
GND : L2 : gnd : : : :
GND : L3 : gnd : : : :
VCC : L4 : power : : 1.1V : :
GND : L5 : gnd : : : :
GND : L8 : gnd : : : :
GND : L9 : gnd : : : :
GND : L10 : gnd : : : :
VCC : L11 : power : : 1.1V : :
VCC : L12 : power : : 1.1V : :
GND : L13 : gnd : : : :
VCC : L14 : power : : 1.1V : :
GND : L15 : gnd : : : :
VCC_HPS : L16 : power : : 1.1V : :
GND : L17 : gnd : : : :
VCC_HPS : L18 : power : : 1.1V : :
GND : L19 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : L20 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : L21 : : : : 6A :
GND : L24 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : L25 : : : : 6A :
VCCIO6A_HPS : L26 : power : : 2.5V : 6A :
GND : L27 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : L28 : : : : 6A :
DNU : M1 : : : : :
DNU : M2 : : : : :
GND : M3 : gnd : : : :
VCCA_FPLL : M4 : power : : 2.5V : :
VCC : M5 : power : : 1.1V : :
GND : M8 : gnd : : : :
VCC : M9 : power : : 1.1V : :
GND : M10 : gnd : : : :
GND : M11 : gnd : : : :
VCC : M12 : power : : 1.1V : :
VCC : M13 : power : : 1.1V : :
GND : M14 : gnd : : : :
VCC : M15 : power : : 1.1V : :
GND : M16 : gnd : : : :
VCC_HPS : M17 : power : : 1.1V : :
VCC_HPS : M18 : power : : 1.1V : :
VCC_HPS : M19 : power : : 1.1V : :
GND : M20 : gnd : : : :
VCCIO6A_HPS : M21 : power : : 2.5V : 6A :
VCCPD6A6B_HPS : M24 : power : : 2.5V : 6A, 6B :
RESERVED_INPUT_WITH_WEAK_PULLUP : M25 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : M26 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : M27 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : M28 : : : : 6A :
GND : N1 : gnd : : : :
GND : N2 : gnd : : : :
GND : N3 : gnd : : : :
GND : N4 : gnd : : : :
VCC : N5 : power : : 1.1V : :
GND : N8 : gnd : : : :
VCC : N9 : power : : 1.1V : :
VCC : N10 : power : : 1.1V : :
VCC : N11 : power : : 1.1V : :
VCC : N12 : power : : 1.1V : :
GND : N13 : gnd : : : :
VCC : N14 : power : : 1.1V : :
GND : N15 : gnd : : : :
VCC_HPS : N16 : power : : 1.1V : :
GND : N17 : gnd : : : :
VCC_HPS : N18 : power : : 1.1V : :
GND : N19 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : N20 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : N21 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : N24 : : : : 6B :
RESERVED_INPUT_WITH_WEAK_PULLUP : N25 : : : : 6B :
RESERVED_INPUT_WITH_WEAK_PULLUP : N26 : : : : 6B :
RESERVED_INPUT_WITH_WEAK_PULLUP : N27 : : : : 6B :
RESERVED_INPUT_WITH_WEAK_PULLUP : N28 : : : : 6A :
GND : P1 : gnd : : : :
GND : P2 : gnd : : : :
GND : P3 : gnd : : : :
VCCA_FPLL : P4 : power : : 2.5V : :
GND : P5 : gnd : : : :
GND : P8 : gnd : : : :
GND : P9 : gnd : : : :
GND : P10 : gnd : : : :
VCC : P11 : power : : 1.1V : :
GND : P12 : gnd : : : :
VCC : P13 : power : : 1.1V : :
VCC : P14 : power : : 1.1V : :
VCC : P15 : power : : 1.1V : :
GND : P16 : gnd : : : :
VCC_HPS : P17 : power : : 1.1V : :
GND : P18 : gnd : : : :
VCC_HPS : P19 : power : : 1.1V : :
GND : P20 : gnd : : : :
VCCPD6A6B_HPS : P21 : power : : 2.5V : 6A, 6B :
VCCPD6A6B_HPS : P24 : power : : 2.5V : 6A, 6B :
GND : P25 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : P26 : : : : 6B :
VCCIO6B_HPS : P27 : power : : 2.5V : 6B :
RESERVED_INPUT_WITH_WEAK_PULLUP : P28 : : : : 6A :
GND : R1 : gnd : : : :
GND : R2 : gnd : : : :
GND : R3 : gnd : : : :
VCCA_FPLL : R4 : power : : 2.5V : :
VCC : R5 : power : : 1.1V : :
GND : R8 : gnd : : : :
VCC : R9 : power : : 1.1V : :
VCC : R10 : power : : 1.1V : :
GND : R11 : gnd : : : :
VCC : R12 : power : : 1.1V : :
GND : R13 : gnd : : : :
VCC : R14 : power : : 1.1V : :
GND : R15 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : R16 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : R17 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : R18 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : R19 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : R20 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : R21 : : : : 6A :
RESERVED_INPUT_WITH_WEAK_PULLUP : R24 : : : : 6B :
RESERVED_INPUT_WITH_WEAK_PULLUP : R25 : : : : 6B :
RESERVED_INPUT_WITH_WEAK_PULLUP : R26 : : : : 6B :
RESERVED_INPUT_WITH_WEAK_PULLUP : R27 : : : : 6B :
RESERVED_INPUT_WITH_WEAK_PULLUP : R28 : : : : 6B :
DNU : T1 : : : : :
DNU : T2 : : : : :
GND : T3 : gnd : : : :
VCC : T4 : power : : 1.1V : :
VCC : T5 : power : : 1.1V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : T8 : : : : 3A :
VCC : T9 : power : : 1.1V : :
GND : T10 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : T11 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : T12 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : T13 : : : : 3B :
GND : T14 : gnd : : : :
VCC : T15 : power : : 1.1V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : T16 : : : : 6B :
RESERVED_INPUT_WITH_WEAK_PULLUP : T17 : : : : 6B :
RESERVED_INPUT_WITH_WEAK_PULLUP : T18 : : : : 6B :
RESERVED_INPUT_WITH_WEAK_PULLUP : T19 : : : : 6B :
RESERVED_INPUT_WITH_WEAK_PULLUP : T20 : : : : 6B :
VCCIO6B_HPS : T21 : power : : 2.5V : 6B :
RESERVED_INPUT_WITH_WEAK_PULLUP : T24 : : : : 6B :
VCCIO6B_HPS : T25 : power : : 2.5V : 6B :
RESERVED_INPUT_WITH_WEAK_PULLUP : T26 : : : : 6B :
RESERVED_INPUT_WITH_WEAK_PULLUP : T27 : : : : 6B :
RESERVED_INPUT_WITH_WEAK_PULLUP : T28 : : : : 6B :
GND : U1 : gnd : : : :
GND : U2 : gnd : : : :
GND : U3 : gnd : : : :
VCCA_FPLL : U4 : power : : 2.5V : :
GND : U5 : gnd : : : :
DNU : U8 : : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : U9 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : U10 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : U11 : : : : 3B :
GND : U12 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : U13 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : U14 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : U15 : : : : 6B :
RESERVED_INPUT_WITH_WEAK_PULLUP : U16 : : : : 6B :
GND : U17 : gnd : : : :
VCCIO6B_HPS : U18 : power : : 2.5V : 6B :
RESERVED_INPUT_WITH_WEAK_PULLUP : U19 : : : : 6B :
GND : U20 : gnd : : : :
VCC_HPS : U21 : power : : 1.1V : :
GND : U24 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : U25 : : : : 6B :
VCC : U26 : power : : 1.1V : :
GND : U27 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : U28 : : : : 6B :
GND : V1 : gnd : : : :
GND : V2 : gnd : : : :
GND : V3 : gnd : : : :
GND : V4 : gnd : : : :
GND : V5 : gnd : : : :
GND : V8 : gnd : : : :
GND : V9 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : V10 : : : : 3A :
fpga_clk : V11 : input : 2.5 V : : 3B : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : V12 : : : : 3B :
RESERVED_INPUT_WITH_WEAK_PULLUP : V13 : : : : 4A :
GND : V14 : gnd : : : :
led[3] : V15 : output : 3.3-V LVTTL : : 5A : Y
led[2] : V16 : output : 3.3-V LVTTL : : 5A : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : V17 : : : : 6B :
RESERVED_INPUT_WITH_WEAK_PULLUP : V18 : : : : 6B :
RESERVED_INPUT_WITH_WEAK_PULLUP : V19 : : : : 6B :
RESERVED_INPUT_WITH_WEAK_PULLUP : V20 : : : : 6B :
GND : V21 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : V24 : : : : 6B :
RESERVED_INPUT_WITH_WEAK_PULLUP : V25 : : : : 6B :
GND : V26 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : V27 : : : : 6B :
RESERVED_INPUT_WITH_WEAK_PULLUP : V28 : : : : 6B :
GND : W1 : gnd : : : :
GND : W2 : gnd : : : :
GND : W3 : gnd : : : :
GND : W4 : gnd : : : :
VCCA_FPLL : W5 : power : : 2.5V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 3A :
VCCIO3A : W9 : power : : 2.5V : 3A :
TDI : W10 : input : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : W11 : : : : 3B :
lcd_data : W12 : output : 3.3-V LVTTL : : 3B : Y
VCCIO4A : W13 : power : : 3.3V : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : W14 : : : : 4A :
led[0] : W15 : output : 3.3-V LVTTL : : 5A : Y
GND : W16 : gnd : : : :
VCCIO5A : W17 : power : : 3.3V : 5A :
GND : W18 : gnd : : : :
VCCPD5B : W19 : power : : 2.5V : 5B :
rst_in : W20 : input : 2.5 V : : 5B : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : W21 : : : : 5B :
RESERVED_INPUT_WITH_WEAK_PULLUP : W24 : : : : 5B :
VCCIO5B : W25 : power : : 2.5V : 5B :
RESERVED_INPUT_WITH_WEAK_PULLUP : W26 : : : : 6B :
VCCIO6B_HPS : W27 : power : : 2.5V : 6B :
RESERVED_INPUT_WITH_WEAK_PULLUP : W28 : : : : 6B :
DNU : Y1 : : : : :
DNU : Y2 : : : : :
GND : Y3 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y4 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y5 : : : : 3A :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y8 : : : : 3A :
TDO : Y9 : output : : : 3A :
VCCPGM : Y10 : power : : 1.8V/2.5V/3.0V/3.3V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y11 : : : : 3A :
GND : Y12 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : : : 4A :
GND : Y14 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y15 : : : : 4A :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 5A :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y17 : : : : 5A :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y18 : : : : 5A :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y19 : : : : 5A :
GND : Y20 : gnd : : : :
VCCPD5A : Y21 : power : : 3.3V : 5A :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y24 : : : : 5B :
GND : Y25 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y26 : : : : 6B :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y27 : : : : 6B :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y28 : : : : 6B :

1
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Timing Analyzer report for chip8
Sun Apr 7 23:52:43 2024
Quartus Prime Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Parallel Compilation
4. Clocks
5. Slow 1100mV 100C Model Fmax Summary
6. Timing Closure Recommendations
7. Slow 1100mV 100C Model Setup Summary
8. Slow 1100mV 100C Model Hold Summary
9. Slow 1100mV 100C Model Recovery Summary
10. Slow 1100mV 100C Model Removal Summary
11. Slow 1100mV 100C Model Minimum Pulse Width Summary
12. Slow 1100mV 100C Model Metastability Summary
13. Slow 1100mV -40C Model Fmax Summary
14. Slow 1100mV -40C Model Setup Summary
15. Slow 1100mV -40C Model Hold Summary
16. Slow 1100mV -40C Model Recovery Summary
17. Slow 1100mV -40C Model Removal Summary
18. Slow 1100mV -40C Model Minimum Pulse Width Summary
19. Slow 1100mV -40C Model Metastability Summary
20. Fast 1100mV 100C Model Setup Summary
21. Fast 1100mV 100C Model Hold Summary
22. Fast 1100mV 100C Model Recovery Summary
23. Fast 1100mV 100C Model Removal Summary
24. Fast 1100mV 100C Model Minimum Pulse Width Summary
25. Fast 1100mV 100C Model Metastability Summary
26. Fast 1100mV -40C Model Setup Summary
27. Fast 1100mV -40C Model Hold Summary
28. Fast 1100mV -40C Model Recovery Summary
29. Fast 1100mV -40C Model Removal Summary
30. Fast 1100mV -40C Model Minimum Pulse Width Summary
31. Fast 1100mV -40C Model Metastability Summary
32. Multicorner Timing Analysis Summary
33. Board Trace Model Assignments
34. Input Transition Times
35. Signal Integrity Metrics (Slow 1100mv n40c Model)
36. Signal Integrity Metrics (Slow 1100mv 100c Model)
37. Signal Integrity Metrics (Fast 1100mv n40c Model)
38. Signal Integrity Metrics (Fast 1100mv 100c Model)
39. Setup Transfers
40. Hold Transfers
41. Report TCCS
42. Report RSKM
43. Unconstrained Paths Summary
44. Clock Status Summary
45. Unconstrained Output Ports
46. Unconstrained Output Ports
47. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2023 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
+--------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+-----------------------+--------------------------------------------------------+
; Quartus Prime Version ; Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition ;
; Timing Analyzer ; Legacy Timing Analyzer ;
; Revision Name ; chip8 ;
; Device Family ; Cyclone V ;
; Device Name ; 5CSEBA6U23I7 ;
; Timing Models ; Final ;
; Delay Model ; Combined ;
; Rise/Fall Delays ; Enabled ;
+-----------------------+--------------------------------------------------------+
+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 12 ;
; Maximum allowed ; 12 ;
; ; ;
; Average used ; 5.73 ;
; Maximum used ; 12 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
; Processor 2 ; 60.4% ;
; Processor 3 ; 57.0% ;
; Processor 4 ; 55.9% ;
; Processor 5 ; 37.5% ;
; Processor 6 ; 37.5% ;
; Processor 7 ; 37.5% ;
; Processor 8 ; 37.5% ;
; Processor 9 ; 37.5% ;
; Processor 10 ; 37.5% ;
; Processor 11 ; 37.5% ;
; Processor 12 ; 37.5% ;
+----------------------------+-------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks ;
+------------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------------------------------------------+
; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
+------------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------------------------------------------+
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { cpu:cpu|st7920_serial_driver:gpu|lcd_clk } ;
; fpga_clk ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { fpga_clk } ;
+------------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------------------------------------------+
+-------------------------------------------------------------------------------+
; Slow 1100mV 100C Model Fmax Summary ;
+-----------+-----------------+------------------------------------------+------+
; Fmax ; Restricted Fmax ; Clock Name ; Note ;
+-----------+-----------------+------------------------------------------+------+
; 34.01 MHz ; 34.01 MHz ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; ;
; 82.06 MHz ; 82.06 MHz ; fpga_clk ; ;
+-----------+-----------------+------------------------------------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
----------------------------------
; Timing Closure Recommendations ;
----------------------------------
HTML report is unavailable in plain text report export.
+--------------------------------------------------------------------+
; Slow 1100mV 100C Model Setup Summary ;
+------------------------------------------+---------+---------------+
; Clock ; Slack ; End Point TNS ;
+------------------------------------------+---------+---------------+
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -28.406 ; -1742.530 ;
; fpga_clk ; -11.186 ; -95769.392 ;
+------------------------------------------+---------+---------------+
+------------------------------------------------------------------+
; Slow 1100mV 100C Model Hold Summary ;
+------------------------------------------+-------+---------------+
; Clock ; Slack ; End Point TNS ;
+------------------------------------------+-------+---------------+
; fpga_clk ; 0.429 ; 0.000 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 0.476 ; 0.000 ;
+------------------------------------------+-------+---------------+
-------------------------------------------
; Slow 1100mV 100C Model Recovery Summary ;
-------------------------------------------
No paths to report.
------------------------------------------
; Slow 1100mV 100C Model Removal Summary ;
------------------------------------------
No paths to report.
+-------------------------------------------------------------------+
; Slow 1100mV 100C Model Minimum Pulse Width Summary ;
+------------------------------------------+--------+---------------+
; Clock ; Slack ; End Point TNS ;
+------------------------------------------+--------+---------------+
; fpga_clk ; -2.636 ; -8463.323 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -0.538 ; -185.389 ;
+------------------------------------------+--------+---------------+
------------------------------------------------
; Slow 1100mV 100C Model Metastability Summary ;
------------------------------------------------
Design MTBF is not calculated because the design doesn't meet its timing requirements.
+-------------------------------------------------------------------------------+
; Slow 1100mV -40C Model Fmax Summary ;
+-----------+-----------------+------------------------------------------+------+
; Fmax ; Restricted Fmax ; Clock Name ; Note ;
+-----------+-----------------+------------------------------------------+------+
; 35.8 MHz ; 35.8 MHz ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; ;
; 81.78 MHz ; 81.78 MHz ; fpga_clk ; ;
+-----------+-----------------+------------------------------------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+--------------------------------------------------------------------+
; Slow 1100mV -40C Model Setup Summary ;
+------------------------------------------+---------+---------------+
; Clock ; Slack ; End Point TNS ;
+------------------------------------------+---------+---------------+
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -26.933 ; -1684.576 ;
; fpga_clk ; -11.228 ; -94100.779 ;
+------------------------------------------+---------+---------------+
+------------------------------------------------------------------+
; Slow 1100mV -40C Model Hold Summary ;
+------------------------------------------+-------+---------------+
; Clock ; Slack ; End Point TNS ;
+------------------------------------------+-------+---------------+
; fpga_clk ; 0.484 ; 0.000 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 0.565 ; 0.000 ;
+------------------------------------------+-------+---------------+
-------------------------------------------
; Slow 1100mV -40C Model Recovery Summary ;
-------------------------------------------
No paths to report.
------------------------------------------
; Slow 1100mV -40C Model Removal Summary ;
------------------------------------------
No paths to report.
+-------------------------------------------------------------------+
; Slow 1100mV -40C Model Minimum Pulse Width Summary ;
+------------------------------------------+--------+---------------+
; Clock ; Slack ; End Point TNS ;
+------------------------------------------+--------+---------------+
; fpga_clk ; -2.636 ; -8927.522 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -0.538 ; -184.012 ;
+------------------------------------------+--------+---------------+
------------------------------------------------
; Slow 1100mV -40C Model Metastability Summary ;
------------------------------------------------
Design MTBF is not calculated because the design doesn't meet its timing requirements.
+--------------------------------------------------------------------+
; Fast 1100mV 100C Model Setup Summary ;
+------------------------------------------+---------+---------------+
; Clock ; Slack ; End Point TNS ;
+------------------------------------------+---------+---------------+
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -14.774 ; -901.498 ;
; fpga_clk ; -6.214 ; -50560.530 ;
+------------------------------------------+---------+---------------+
+------------------------------------------------------------------+
; Fast 1100mV 100C Model Hold Summary ;
+------------------------------------------+-------+---------------+
; Clock ; Slack ; End Point TNS ;
+------------------------------------------+-------+---------------+
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 0.162 ; 0.000 ;
; fpga_clk ; 0.177 ; 0.000 ;
+------------------------------------------+-------+---------------+
-------------------------------------------
; Fast 1100mV 100C Model Recovery Summary ;
-------------------------------------------
No paths to report.
------------------------------------------
; Fast 1100mV 100C Model Removal Summary ;
------------------------------------------
No paths to report.
+-------------------------------------------------------------------+
; Fast 1100mV 100C Model Minimum Pulse Width Summary ;
+------------------------------------------+--------+---------------+
; Clock ; Slack ; End Point TNS ;
+------------------------------------------+--------+---------------+
; fpga_clk ; -2.174 ; -1371.543 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -0.192 ; -9.702 ;
+------------------------------------------+--------+---------------+
------------------------------------------------
; Fast 1100mV 100C Model Metastability Summary ;
------------------------------------------------
Design MTBF is not calculated because the design doesn't meet its timing requirements.
+--------------------------------------------------------------------+
; Fast 1100mV -40C Model Setup Summary ;
+------------------------------------------+---------+---------------+
; Clock ; Slack ; End Point TNS ;
+------------------------------------------+---------+---------------+
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -12.462 ; -739.747 ;
; fpga_clk ; -4.930 ; -40871.978 ;
+------------------------------------------+---------+---------------+
+------------------------------------------------------------------+
; Fast 1100mV -40C Model Hold Summary ;
+------------------------------------------+-------+---------------+
; Clock ; Slack ; End Point TNS ;
+------------------------------------------+-------+---------------+
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 0.140 ; 0.000 ;
; fpga_clk ; 0.164 ; 0.000 ;
+------------------------------------------+-------+---------------+
-------------------------------------------
; Fast 1100mV -40C Model Recovery Summary ;
-------------------------------------------
No paths to report.
------------------------------------------
; Fast 1100mV -40C Model Removal Summary ;
------------------------------------------
No paths to report.
+-------------------------------------------------------------------+
; Fast 1100mV -40C Model Minimum Pulse Width Summary ;
+------------------------------------------+--------+---------------+
; Clock ; Slack ; End Point TNS ;
+------------------------------------------+--------+---------------+
; fpga_clk ; -2.174 ; -1373.239 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -0.137 ; -3.355 ;
+------------------------------------------+--------+---------------+
------------------------------------------------
; Fast 1100mV -40C Model Metastability Summary ;
------------------------------------------------
Design MTBF is not calculated because the design doesn't meet its timing requirements.
+-----------------------------------------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary ;
+-------------------------------------------+------------+-------+----------+---------+---------------------+
; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
+-------------------------------------------+------------+-------+----------+---------+---------------------+
; Worst-case Slack ; -28.406 ; 0.140 ; N/A ; N/A ; -2.636 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -28.406 ; 0.140 ; N/A ; N/A ; -0.538 ;
; fpga_clk ; -11.228 ; 0.164 ; N/A ; N/A ; -2.636 ;
; Design-wide TNS ; -97511.922 ; 0.0 ; 0.0 ; 0.0 ; -9111.534 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -1742.530 ; 0.000 ; N/A ; N/A ; -185.389 ;
; fpga_clk ; -95769.392 ; 0.000 ; N/A ; N/A ; -8927.522 ;
+-------------------------------------------+------------+-------+----------+---------+---------------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments ;
+----------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
+----------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; lcd_clk ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; lcd_data ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; led[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; led[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; led[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; led[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; led[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; led[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+----------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+-------------------------------------------------------------+
; Input Transition Times ;
+----------+--------------+-----------------+-----------------+
; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+----------+--------------+-----------------+-----------------+
; rst_in ; 2.5 V ; 2000 ps ; 2000 ps ;
; fpga_clk ; 2.5 V ; 2000 ps ; 2000 ps ;
+----------+--------------+-----------------+-----------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1100mv n40c Model) ;
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; lcd_clk ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.56e-08 V ; 2.43 V ; -0.0607 V ; 0.35 V ; 0.108 V ; 3.1e-10 s ; 4.28e-10 s ; No ; No ; 2.32 V ; 1.56e-08 V ; 2.43 V ; -0.0607 V ; 0.35 V ; 0.108 V ; 3.1e-10 s ; 4.28e-10 s ; No ; No ;
; lcd_data ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.47e-08 V ; 3.11 V ; -0.195 V ; 0.108 V ; 0.32 V ; 4.03e-10 s ; 1.44e-10 s ; Yes ; No ; 3.08 V ; 1.47e-08 V ; 3.11 V ; -0.195 V ; 0.108 V ; 0.32 V ; 4.03e-10 s ; 1.44e-10 s ; Yes ; No ;
; led[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.47e-08 V ; 3.11 V ; -0.195 V ; 0.108 V ; 0.32 V ; 4.03e-10 s ; 1.44e-10 s ; Yes ; No ; 3.08 V ; 1.47e-08 V ; 3.11 V ; -0.195 V ; 0.108 V ; 0.32 V ; 4.03e-10 s ; 1.44e-10 s ; Yes ; No ;
; led[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.91e-08 V ; 3.17 V ; -0.306 V ; 0.142 V ; 0.425 V ; 4.17e-10 s ; 1.36e-10 s ; Yes ; No ; 3.08 V ; 1.91e-08 V ; 3.17 V ; -0.306 V ; 0.142 V ; 0.425 V ; 4.17e-10 s ; 1.36e-10 s ; Yes ; No ;
; led[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2e-08 V ; 3.17 V ; -0.245 V ; 0.166 V ; 0.398 V ; 4.33e-10 s ; 1.46e-10 s ; Yes ; No ; 3.08 V ; 2e-08 V ; 3.17 V ; -0.245 V ; 0.166 V ; 0.398 V ; 4.33e-10 s ; 1.46e-10 s ; Yes ; No ;
; led[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.47e-08 V ; 3.11 V ; -0.195 V ; 0.108 V ; 0.32 V ; 4.03e-10 s ; 1.44e-10 s ; Yes ; No ; 3.08 V ; 1.47e-08 V ; 3.11 V ; -0.195 V ; 0.108 V ; 0.32 V ; 4.03e-10 s ; 1.44e-10 s ; Yes ; No ;
; led[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.91e-08 V ; 3.17 V ; -0.306 V ; 0.142 V ; 0.425 V ; 4.17e-10 s ; 1.36e-10 s ; Yes ; No ; 3.08 V ; 1.91e-08 V ; 3.17 V ; -0.306 V ; 0.142 V ; 0.425 V ; 4.17e-10 s ; 1.36e-10 s ; Yes ; No ;
; led[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.91e-08 V ; 3.17 V ; -0.311 V ; 0.143 V ; 0.424 V ; 4.17e-10 s ; 1.36e-10 s ; Yes ; No ; 3.08 V ; 1.91e-08 V ; 3.17 V ; -0.311 V ; 0.143 V ; 0.424 V ; 4.17e-10 s ; 1.36e-10 s ; Yes ; No ;
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1100mv 100c Model) ;
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; lcd_clk ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.73e-05 V ; 2.38 V ; -0.0297 V ; 0.21 V ; 0.199 V ; 4.77e-10 s ; 4.97e-10 s ; No ; Yes ; 2.32 V ; 4.73e-05 V ; 2.38 V ; -0.0297 V ; 0.21 V ; 0.199 V ; 4.77e-10 s ; 4.97e-10 s ; No ; Yes ;
; lcd_data ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.09e-05 V ; 3.09 V ; -0.0462 V ; 0.045 V ; 0.085 V ; 5.49e-10 s ; 3.06e-10 s ; Yes ; Yes ; 3.08 V ; 3.09e-05 V ; 3.09 V ; -0.0462 V ; 0.045 V ; 0.085 V ; 5.49e-10 s ; 3.06e-10 s ; Yes ; Yes ;
; led[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.09e-05 V ; 3.09 V ; -0.0462 V ; 0.045 V ; 0.085 V ; 5.49e-10 s ; 3.06e-10 s ; Yes ; Yes ; 3.08 V ; 3.09e-05 V ; 3.09 V ; -0.0462 V ; 0.045 V ; 0.085 V ; 5.49e-10 s ; 3.06e-10 s ; Yes ; Yes ;
; led[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.73e-05 V ; 3.11 V ; -0.104 V ; 0.101 V ; 0.139 V ; 5.54e-10 s ; 3.16e-10 s ; Yes ; Yes ; 3.08 V ; 3.73e-05 V ; 3.11 V ; -0.104 V ; 0.101 V ; 0.139 V ; 5.54e-10 s ; 3.16e-10 s ; Yes ; Yes ;
; led[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.87e-05 V ; 3.11 V ; -0.0814 V ; 0.131 V ; 0.136 V ; 5.88e-10 s ; 3.2e-10 s ; Yes ; Yes ; 3.08 V ; 3.87e-05 V ; 3.11 V ; -0.0814 V ; 0.131 V ; 0.136 V ; 5.88e-10 s ; 3.2e-10 s ; Yes ; Yes ;
; led[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.09e-05 V ; 3.09 V ; -0.0462 V ; 0.045 V ; 0.085 V ; 5.49e-10 s ; 3.06e-10 s ; Yes ; Yes ; 3.08 V ; 3.09e-05 V ; 3.09 V ; -0.0462 V ; 0.045 V ; 0.085 V ; 5.49e-10 s ; 3.06e-10 s ; Yes ; Yes ;
; led[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.73e-05 V ; 3.11 V ; -0.104 V ; 0.101 V ; 0.139 V ; 5.54e-10 s ; 3.16e-10 s ; Yes ; Yes ; 3.08 V ; 3.73e-05 V ; 3.11 V ; -0.104 V ; 0.101 V ; 0.139 V ; 5.54e-10 s ; 3.16e-10 s ; Yes ; Yes ;
; led[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.73e-05 V ; 3.11 V ; -0.105 V ; 0.101 V ; 0.142 V ; 5.54e-10 s ; 3.16e-10 s ; Yes ; Yes ; 3.08 V ; 3.73e-05 V ; 3.11 V ; -0.105 V ; 0.101 V ; 0.142 V ; 5.54e-10 s ; 3.16e-10 s ; Yes ; Yes ;
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Fast 1100mv n40c Model) ;
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; lcd_clk ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 2.38e-07 V ; 2.94 V ; -0.139 V ; 0.31 V ; 0.268 V ; 2.65e-10 s ; 2.63e-10 s ; No ; Yes ; 2.75 V ; 2.38e-07 V ; 2.94 V ; -0.139 V ; 0.31 V ; 0.268 V ; 2.65e-10 s ; 2.63e-10 s ; No ; Yes ;
; lcd_data ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.38e-07 V ; 3.67 V ; -0.403 V ; 0.084 V ; 0.542 V ; 3.5e-10 s ; 1.32e-10 s ; Yes ; No ; 3.63 V ; 3.38e-07 V ; 3.67 V ; -0.403 V ; 0.084 V ; 0.542 V ; 3.5e-10 s ; 1.32e-10 s ; Yes ; No ;
; led[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.38e-07 V ; 3.67 V ; -0.403 V ; 0.084 V ; 0.542 V ; 3.5e-10 s ; 1.32e-10 s ; Yes ; No ; 3.63 V ; 3.38e-07 V ; 3.67 V ; -0.403 V ; 0.084 V ; 0.542 V ; 3.5e-10 s ; 1.32e-10 s ; Yes ; No ;
; led[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.42e-07 V ; 3.75 V ; -0.588 V ; 0.329 V ; 0.704 V ; 2.77e-10 s ; 1.3e-10 s ; Yes ; No ; 3.63 V ; 4.42e-07 V ; 3.75 V ; -0.588 V ; 0.329 V ; 0.704 V ; 2.77e-10 s ; 1.3e-10 s ; Yes ; No ;
; led[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.64e-07 V ; 3.74 V ; -0.508 V ; 0.391 V ; 0.647 V ; 3.08e-10 s ; 1.34e-10 s ; No ; No ; 3.63 V ; 4.64e-07 V ; 3.74 V ; -0.508 V ; 0.391 V ; 0.647 V ; 3.08e-10 s ; 1.34e-10 s ; No ; No ;
; led[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.38e-07 V ; 3.67 V ; -0.403 V ; 0.084 V ; 0.542 V ; 3.5e-10 s ; 1.32e-10 s ; Yes ; No ; 3.63 V ; 3.38e-07 V ; 3.67 V ; -0.403 V ; 0.084 V ; 0.542 V ; 3.5e-10 s ; 1.32e-10 s ; Yes ; No ;
; led[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.42e-07 V ; 3.75 V ; -0.588 V ; 0.329 V ; 0.704 V ; 2.77e-10 s ; 1.3e-10 s ; Yes ; No ; 3.63 V ; 4.42e-07 V ; 3.75 V ; -0.588 V ; 0.329 V ; 0.704 V ; 2.77e-10 s ; 1.3e-10 s ; Yes ; No ;
; led[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.42e-07 V ; 3.75 V ; -0.589 V ; 0.329 V ; 0.706 V ; 2.77e-10 s ; 1.3e-10 s ; Yes ; No ; 3.63 V ; 4.42e-07 V ; 3.75 V ; -0.589 V ; 0.329 V ; 0.706 V ; 2.77e-10 s ; 1.3e-10 s ; Yes ; No ;
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Fast 1100mv 100c Model) ;
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; lcd_clk ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.00041 V ; 2.85 V ; -0.0763 V ; 0.365 V ; 0.161 V ; 3.08e-10 s ; 4.37e-10 s ; No ; No ; 2.75 V ; 0.00041 V ; 2.85 V ; -0.0763 V ; 0.365 V ; 0.161 V ; 3.08e-10 s ; 4.37e-10 s ; No ; No ;
; lcd_data ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000307 V ; 3.64 V ; -0.165 V ; 0.022 V ; 0.425 V ; 4.58e-10 s ; 2e-10 s ; Yes ; No ; 3.63 V ; 0.000307 V ; 3.64 V ; -0.165 V ; 0.022 V ; 0.425 V ; 4.58e-10 s ; 2e-10 s ; Yes ; No ;
; led[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000307 V ; 3.64 V ; -0.165 V ; 0.022 V ; 0.425 V ; 4.58e-10 s ; 2e-10 s ; Yes ; No ; 3.63 V ; 0.000307 V ; 3.64 V ; -0.165 V ; 0.022 V ; 0.425 V ; 4.58e-10 s ; 2e-10 s ; Yes ; No ;
; led[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000379 V ; 3.65 V ; -0.289 V ; 0.051 V ; 0.523 V ; 4.36e-10 s ; 1.95e-10 s ; Yes ; No ; 3.63 V ; 0.000379 V ; 3.65 V ; -0.289 V ; 0.051 V ; 0.523 V ; 4.36e-10 s ; 1.95e-10 s ; Yes ; No ;
; led[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000395 V ; 3.65 V ; -0.232 V ; 0.065 V ; 0.547 V ; 4.68e-10 s ; 2.07e-10 s ; Yes ; No ; 3.63 V ; 0.000395 V ; 3.65 V ; -0.232 V ; 0.065 V ; 0.547 V ; 4.68e-10 s ; 2.07e-10 s ; Yes ; No ;
; led[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000307 V ; 3.64 V ; -0.165 V ; 0.022 V ; 0.425 V ; 4.58e-10 s ; 2e-10 s ; Yes ; No ; 3.63 V ; 0.000307 V ; 3.64 V ; -0.165 V ; 0.022 V ; 0.425 V ; 4.58e-10 s ; 2e-10 s ; Yes ; No ;
; led[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000379 V ; 3.65 V ; -0.289 V ; 0.051 V ; 0.523 V ; 4.36e-10 s ; 1.95e-10 s ; Yes ; No ; 3.63 V ; 0.000379 V ; 3.65 V ; -0.289 V ; 0.051 V ; 0.523 V ; 4.36e-10 s ; 1.95e-10 s ; Yes ; No ;
; led[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000379 V ; 3.65 V ; -0.292 V ; 0.053 V ; 0.524 V ; 4.36e-10 s ; 1.95e-10 s ; Yes ; No ; 3.63 V ; 0.000379 V ; 3.65 V ; -0.292 V ; 0.053 V ; 0.524 V ; 4.36e-10 s ; 1.95e-10 s ; Yes ; No ;
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+---------------------------------------------------------------------------------------------------------------------------------+
; Setup Transfers ;
+------------------------------------------+------------------------------------------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------------------------------------+------------------------------------------+----------+----------+----------+----------+
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 2667 ; 137 ; 0 ; 1681347 ;
; fpga_clk ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 0 ; 0 ; 9878 ; 0 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; fpga_clk ; 1 ; 1 ; 0 ; 0 ;
; fpga_clk ; fpga_clk ; 12902566 ; 152 ; 48 ; 0 ;
+------------------------------------------+------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+---------------------------------------------------------------------------------------------------------------------------------+
; Hold Transfers ;
+------------------------------------------+------------------------------------------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------------------------------------+------------------------------------------+----------+----------+----------+----------+
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 2667 ; 137 ; 0 ; 1681347 ;
; fpga_clk ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 0 ; 0 ; 9878 ; 0 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; fpga_clk ; 1 ; 1 ; 0 ; 0 ;
; fpga_clk ; fpga_clk ; 12902566 ; 152 ; 48 ; 0 ;
+------------------------------------------+------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design
---------------
; Report RSKM ;
---------------
No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
+------------------------------------------------+
; Unconstrained Paths Summary ;
+---------------------------------+-------+------+
; Property ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks ; 0 ; 0 ;
; Unconstrained Clocks ; 0 ; 0 ;
; Unconstrained Input Ports ; 0 ; 0 ;
; Unconstrained Input Port Paths ; 0 ; 0 ;
; Unconstrained Output Ports ; 7 ; 7 ;
; Unconstrained Output Port Paths ; 7 ; 7 ;
+---------------------------------+-------+------+
+----------------------------------------------------------------------------------------------------------+
; Clock Status Summary ;
+------------------------------------------+------------------------------------------+------+-------------+
; Target ; Clock ; Type ; Status ;
+------------------------------------------+------------------------------------------+------+-------------+
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; Base ; Constrained ;
; fpga_clk ; fpga_clk ; Base ; Constrained ;
+------------------------------------------+------------------------------------------+------+-------------+
+-----------------------------------------------------------------------------------------------------+
; Unconstrained Output Ports ;
+-------------+---------------------------------------------------------------------------------------+
; Output Port ; Comment ;
+-------------+---------------------------------------------------------------------------------------+
; lcd_clk ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; lcd_data ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; led[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; led[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; led[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; led[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; led[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+-------------+---------------------------------------------------------------------------------------+
+-----------------------------------------------------------------------------------------------------+
; Unconstrained Output Ports ;
+-------------+---------------------------------------------------------------------------------------+
; Output Port ; Comment ;
+-------------+---------------------------------------------------------------------------------------+
; lcd_clk ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; lcd_data ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; led[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; led[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; led[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; led[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; led[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+-------------+---------------------------------------------------------------------------------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Timing Analyzer
Info: Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition
Info: Processing started: Sun Apr 7 23:52:18 2024
Info: Command: quartus_sta chip8 -c chip8
Info: qsta_default_script.tcl version: #1
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 12 of the 12 processors detected
Info (21077): Low junction temperature is -40 degrees C
Info (21077): High junction temperature is 100 degrees C
Critical Warning (332012): Synopsys Design Constraints File file not found: 'chip8.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332105): Deriving Clocks
Info (332105): create_clock -period 1.000 -name fpga_clk fpga_clk
Info (332105): create_clock -period 1.000 -name cpu:cpu|st7920_serial_driver:gpu|lcd_clk cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Analyzing Slow 1100mV 100C Model
Critical Warning (332148): Timing requirements not met
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer.
Info (332146): Worst-case setup slack is -28.406
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -28.406 -1742.530 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332119): -11.186 -95769.392 fpga_clk
Info (332146): Worst-case hold slack is 0.429
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 0.429 0.000 fpga_clk
Info (332119): 0.476 0.000 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is -2.636
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -2.636 -8463.323 fpga_clk
Info (332119): -0.538 -185.389 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332114): Report Metastability: Found 8 synchronizer chains.
Info (332114): Design MTBF is not calculated because the design doesn't meet its timing requirements.
Info: Analyzing Slow 1100mV -40C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer.
Info (332146): Worst-case setup slack is -26.933
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -26.933 -1684.576 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332119): -11.228 -94100.779 fpga_clk
Info (332146): Worst-case hold slack is 0.484
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 0.484 0.000 fpga_clk
Info (332119): 0.565 0.000 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is -2.636
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -2.636 -8927.522 fpga_clk
Info (332119): -0.538 -184.012 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332114): Report Metastability: Found 8 synchronizer chains.
Info (332114): Design MTBF is not calculated because the design doesn't meet its timing requirements.
Info: Analyzing Fast 1100mV 100C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer.
Info (332146): Worst-case setup slack is -14.774
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -14.774 -901.498 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332119): -6.214 -50560.530 fpga_clk
Info (332146): Worst-case hold slack is 0.162
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 0.162 0.000 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332119): 0.177 0.000 fpga_clk
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is -2.174
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -2.174 -1371.543 fpga_clk
Info (332119): -0.192 -9.702 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332114): Report Metastability: Found 8 synchronizer chains.
Info (332114): Design MTBF is not calculated because the design doesn't meet its timing requirements.
Info: Analyzing Fast 1100mV -40C Model
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer.
Info (332146): Worst-case setup slack is -12.462
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -12.462 -739.747 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332119): -4.930 -40871.978 fpga_clk
Info (332146): Worst-case hold slack is 0.140
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 0.140 0.000 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332119): 0.164 0.000 fpga_clk
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is -2.174
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -2.174 -1373.239 fpga_clk
Info (332119): -0.137 -3.355 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332114): Report Metastability: Found 8 synchronizer chains.
Info (332114): Design MTBF is not calculated because the design doesn't meet its timing requirements.
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings
Info: Peak virtual memory: 1353 megabytes
Info: Processing ended: Sun Apr 7 23:52:43 2024
Info: Elapsed time: 00:00:25
Info: Total CPU time (on all processors): 00:01:44

101
output_files/chip8.sta.summary Normal file
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@ -0,0 +1,101 @@
------------------------------------------------------------
Timing Analyzer Summary
------------------------------------------------------------
Type : Slow 1100mV 100C Model Setup 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk'
Slack : -28.406
TNS : -1742.530
Type : Slow 1100mV 100C Model Setup 'fpga_clk'
Slack : -11.186
TNS : -95769.392
Type : Slow 1100mV 100C Model Hold 'fpga_clk'
Slack : 0.429
TNS : 0.000
Type : Slow 1100mV 100C Model Hold 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk'
Slack : 0.476
TNS : 0.000
Type : Slow 1100mV 100C Model Minimum Pulse Width 'fpga_clk'
Slack : -2.636
TNS : -8463.323
Type : Slow 1100mV 100C Model Minimum Pulse Width 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk'
Slack : -0.538
TNS : -185.389
Type : Slow 1100mV -40C Model Setup 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk'
Slack : -26.933
TNS : -1684.576
Type : Slow 1100mV -40C Model Setup 'fpga_clk'
Slack : -11.228
TNS : -94100.779
Type : Slow 1100mV -40C Model Hold 'fpga_clk'
Slack : 0.484
TNS : 0.000
Type : Slow 1100mV -40C Model Hold 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk'
Slack : 0.565
TNS : 0.000
Type : Slow 1100mV -40C Model Minimum Pulse Width 'fpga_clk'
Slack : -2.636
TNS : -8927.522
Type : Slow 1100mV -40C Model Minimum Pulse Width 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk'
Slack : -0.538
TNS : -184.012
Type : Fast 1100mV 100C Model Setup 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk'
Slack : -14.774
TNS : -901.498
Type : Fast 1100mV 100C Model Setup 'fpga_clk'
Slack : -6.214
TNS : -50560.530
Type : Fast 1100mV 100C Model Hold 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk'
Slack : 0.162
TNS : 0.000
Type : Fast 1100mV 100C Model Hold 'fpga_clk'
Slack : 0.177
TNS : 0.000
Type : Fast 1100mV 100C Model Minimum Pulse Width 'fpga_clk'
Slack : -2.174
TNS : -1371.543
Type : Fast 1100mV 100C Model Minimum Pulse Width 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk'
Slack : -0.192
TNS : -9.702
Type : Fast 1100mV -40C Model Setup 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk'
Slack : -12.462
TNS : -739.747
Type : Fast 1100mV -40C Model Setup 'fpga_clk'
Slack : -4.930
TNS : -40871.978
Type : Fast 1100mV -40C Model Hold 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk'
Slack : 0.140
TNS : 0.000
Type : Fast 1100mV -40C Model Hold 'fpga_clk'
Slack : 0.164
TNS : 0.000
Type : Fast 1100mV -40C Model Minimum Pulse Width 'fpga_clk'
Slack : -2.174
TNS : -1373.239
Type : Fast 1100mV -40C Model Minimum Pulse Width 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk'
Slack : -0.137
TNS : -3.355
------------------------------------------------------------

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