diff --git a/README.md b/README.md index 6993cfa..ff0f71f 100644 --- a/README.md +++ b/README.md @@ -43,6 +43,7 @@ yayacemu [PATH_TO_YOUR_ROM] ### Screenshots +![Chip 8 Logo Demo on an FPGA!](https://github.com/nickorlow/yayacemu/blob/main/screenshots/chip8_fpga.jpg?raw=true) ![Chip 8 Logo Demo](https://github.com/nickorlow/yayacemu/blob/main/screenshots/chip8-logo.png?raw=true) ![IBM Logo Demo](https://github.com/nickorlow/yayacemu/blob/main/screenshots/ibm-logo.png?raw=true) ![CORAX+ Test Demo](https://github.com/nickorlow/yayacemu/blob/main/screenshots/corax.png?raw=true) diff --git a/aastructs.sv b/aastructs.sv new file mode 100644 index 0000000..9f6b459 --- /dev/null +++ b/aastructs.sv @@ -0,0 +1,11 @@ +package structs; + + typedef enum {ADD} alu_op; + + typedef struct { + logic [7:0] operand_a; + logic [7:0] operand_b; + alu_op op; + } alu_input; + +endpackage diff --git a/alu.sv b/alu.sv new file mode 100644 index 0000000..26d4c0f --- /dev/null +++ b/alu.sv @@ -0,0 +1,46 @@ +import structs::*; + +module alu( + input wire rst_in, + input wire clk_in, + input alu_input in, + output logic [7:0] result, + output logic overflow, + output logic done + ); + + logic [8:0] result_int; + int cnt; + + initial begin + overflow = 1'bx; + result = 8'hxx; + result_int = 9'bxxxxxxxxx; + done = 0; + cnt = 0; + end + + always_ff @(posedge clk_in) begin + if (rst_in) begin + done <= 0; + overflow <= 1'bx; + result <= 8'hxx; + result_int <= 9'bxxxxxxxxx; + cnt <= 0; + end else begin + case(in.op) + structs::ADD: begin + result_int <= in.operand_a + in.operand_b; + result <= result_int[7:0]; + overflow <= result_int[8]; + if (cnt == 2) begin + $display("%b %b + %b %b ya", result, in.operand_a, in.operand_b, result_int); + done <= 1; + end + cnt <= cnt + 1; + end + endcase + end + end + +endmodule diff --git a/c5_pin_model_dump.txt b/c5_pin_model_dump.txt new file mode 100644 index 0000000..31bb72c --- /dev/null +++ b/c5_pin_model_dump.txt @@ -0,0 +1,118 @@ +io_4iomodule_c5_index: 55gpio_index: 2 +io_4iomodule_c5_index: 54gpio_index: 465 +io_4iomodule_c5_index: 33gpio_index: 6 +io_4iomodule_c5_index: 51gpio_index: 461 +io_4iomodule_c5_index: 27gpio_index: 10 +io_4iomodule_c5_index: 57gpio_index: 457 +io_4iomodule_c5_index: 34gpio_index: 14 +io_4iomodule_c5_index: 28gpio_index: 453 +io_4iomodule_c5_index: 26gpio_index: 19 +io_4iomodule_c5_index: 47gpio_index: 449 +io_4iomodule_c5_index: 29gpio_index: 22 +io_4iomodule_c5_index: 3gpio_index: 445 +io_4iomodule_c5_index: 16gpio_index: 27 +io_4iomodule_c5_index: 6gpio_index: 441 +io_4iomodule_c5_index: 50gpio_index: 30 +io_4iomodule_c5_index: 35gpio_index: 437 +io_4iomodule_c5_index: 7gpio_index: 35 +io_4iomodule_c5_index: 53gpio_index: 433 +io_4iomodule_c5_index: 12gpio_index: 38 +io_4iomodule_c5_index: 1gpio_index: 429 +io_4iomodule_c5_index: 22gpio_index: 43 +io_4iomodule_c5_index: 8gpio_index: 425 +io_4iomodule_c5_index: 20gpio_index: 46 +io_4iomodule_c5_index: 30gpio_index: 421 +io_4iomodule_c5_index: 2gpio_index: 51 +io_4iomodule_c5_index: 31gpio_index: 417 +io_4iomodule_c5_index: 39gpio_index: 54 +io_4iomodule_c5_index: 18gpio_index: 413 +io_4iomodule_c5_index: 10gpio_index: 59 +io_4iomodule_c5_index: 42gpio_index: 409 +io_4iomodule_c5_index: 5gpio_index: 62 +io_4iomodule_c5_index: 24gpio_index: 405 +io_4iomodule_c5_index: 37gpio_index: 67 +io_4iomodule_c5_index: 13gpio_index: 401 +io_4iomodule_c5_index: 0gpio_index: 70 +io_4iomodule_c5_index: 44gpio_index: 397 +io_4iomodule_c5_index: 38gpio_index: 75 +io_4iomodule_c5_index: 52gpio_index: 393 +io_4iomodule_c5_index: 32gpio_index: 78 +io_4iomodule_c5_index: 56gpio_index: 389 +io_4iomodule_a_index: 13gpio_index: 385 +io_4iomodule_c5_index: 4gpio_index: 83 +io_4iomodule_c5_index: 23gpio_index: 86 +io_4iomodule_a_index: 15gpio_index: 381 +io_4iomodule_a_index: 8gpio_index: 377 +io_4iomodule_c5_index: 46gpio_index: 91 +io_4iomodule_a_index: 5gpio_index: 373 +io_4iomodule_a_index: 11gpio_index: 369 +io_4iomodule_c5_index: 41gpio_index: 94 +io_4iomodule_a_index: 3gpio_index: 365 +io_4iomodule_c5_index: 25gpio_index: 99 +io_4iomodule_a_index: 7gpio_index: 361 +io_4iomodule_c5_index: 9gpio_index: 102 +io_4iomodule_a_index: 0gpio_index: 357 +io_4iomodule_c5_index: 14gpio_index: 107 +io_4iomodule_a_index: 12gpio_index: 353 +io_4iomodule_c5_index: 45gpio_index: 110 +io_4iomodule_c5_index: 17gpio_index: 115 +io_4iomodule_a_index: 4gpio_index: 349 +io_4iomodule_c5_index: 36gpio_index: 118 +io_4iomodule_a_index: 10gpio_index: 345 +io_4iomodule_a_index: 16gpio_index: 341 +io_4iomodule_c5_index: 15gpio_index: 123 +io_4iomodule_a_index: 14gpio_index: 337 +io_4iomodule_c5_index: 43gpio_index: 126 +io_4iomodule_c5_index: 19gpio_index: 131 +io_4iomodule_a_index: 1gpio_index: 333 +io_4iomodule_c5_index: 59gpio_index: 134 +io_4iomodule_a_index: 2gpio_index: 329 +io_4iomodule_a_index: 9gpio_index: 325 +io_4iomodule_c5_index: 48gpio_index: 139 +io_4iomodule_a_index: 6gpio_index: 321 +io_4iomodule_a_index: 17gpio_index: 317 +io_4iomodule_c5_index: 40gpio_index: 142 +io_4iomodule_c5_index: 11gpio_index: 147 +io_4iomodule_c5_index: 58gpio_index: 150 +io_4iomodule_c5_index: 21gpio_index: 155 +io_4iomodule_c5_index: 49gpio_index: 158 +io_4iomodule_h_c5_index: 0gpio_index: 161 +io_4iomodule_h_c5_index: 6gpio_index: 165 +io_4iomodule_h_c5_index: 10gpio_index: 169 +io_4iomodule_h_c5_index: 3gpio_index: 173 +io_4iomodule_h_c5_index: 8gpio_index: 176 +io_4iomodule_h_c5_index: 11gpio_index: 180 +io_4iomodule_h_c5_index: 7gpio_index: 184 +io_4iomodule_h_c5_index: 5gpio_index: 188 +io_4iomodule_h_c5_index: 1gpio_index: 192 +io_4iomodule_h_c5_index: 2gpio_index: 196 +io_4iomodule_h_c5_index: 9gpio_index: 200 +io_4iomodule_h_c5_index: 4gpio_index: 204 +io_4iomodule_h_index: 15gpio_index: 208 +io_4iomodule_h_index: 1gpio_index: 212 +io_4iomodule_h_index: 3gpio_index: 216 +io_4iomodule_h_index: 2gpio_index: 220 +io_4iomodule_h_index: 11gpio_index: 224 +io_4iomodule_vref_h_index: 1gpio_index: 228 +io_4iomodule_h_index: 20gpio_index: 231 +io_4iomodule_h_index: 8gpio_index: 235 +io_4iomodule_h_index: 6gpio_index: 239 +io_4iomodule_h_index: 10gpio_index: 243 +io_4iomodule_h_index: 23gpio_index: 247 +io_4iomodule_h_index: 7gpio_index: 251 +io_4iomodule_h_index: 22gpio_index: 255 +io_4iomodule_h_index: 5gpio_index: 259 +io_4iomodule_h_index: 24gpio_index: 263 +io_4iomodule_h_index: 0gpio_index: 267 +io_4iomodule_h_index: 13gpio_index: 271 +io_4iomodule_h_index: 21gpio_index: 275 +io_4iomodule_h_index: 16gpio_index: 279 +io_4iomodule_vref_h_index: 0gpio_index: 283 +io_4iomodule_h_index: 12gpio_index: 286 +io_4iomodule_h_index: 4gpio_index: 290 +io_4iomodule_h_index: 19gpio_index: 294 +io_4iomodule_h_index: 18gpio_index: 298 +io_4iomodule_h_index: 17gpio_index: 302 +io_4iomodule_h_index: 25gpio_index: 306 +io_4iomodule_h_index: 14gpio_index: 310 +io_4iomodule_h_index: 9gpio_index: 314 diff --git a/db/.cmp.kpt b/db/.cmp.kpt new file mode 100644 index 0000000..9c21138 Binary files /dev/null and b/db/.cmp.kpt differ diff --git a/db/altsyncram_dsq1.tdf b/db/altsyncram_dsq1.tdf new file mode 100644 index 0000000..72df83f --- /dev/null +++ b/db/altsyncram_dsq1.tdf @@ -0,0 +1,300 @@ +--altsyncram ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone V" INDATA_ACLR_A="NONE" INIT_FILE="db/chip8.ram0_memory_e9e85012.hdl.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=4096 NUMWORDS_B=4096 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED" READ_DURING_WRITE_MODE_MIXED_PORTS="OLD_DATA" WIDTH_A=8 WIDTH_B=8 WIDTHAD_A=12 WIDTHAD_B=12 WRCONTROL_ACLR_A="NONE" address_a address_b clock0 data_a q_b CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 23.1 cbx_altera_syncram_nd_impl 2023:11:29:19:33:06:SC cbx_altsyncram 2023:11:29:19:33:06:SC cbx_cycloneii 2023:11:29:19:33:06:SC cbx_lpm_add_sub 2023:11:29:19:33:06:SC cbx_lpm_compare 2023:11:29:19:33:06:SC cbx_lpm_decode 2023:11:29:19:33:06:SC cbx_lpm_mux 2023:11:29:19:33:05:SC cbx_mgl 2023:11:29:19:43:53:SC cbx_nadder 2023:11:29:19:33:06:SC cbx_stratix 2023:11:29:19:33:06:SC cbx_stratixii 2023:11:29:19:33:05:SC cbx_stratixiii 2023:11:29:19:33:06:SC cbx_stratixv 2023:11:29:19:33:05:SC cbx_util_mgl 2023:11:29:19:33:06:SC VERSION_END + + +-- Copyright (C) 2023 Intel Corporation. All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions +-- and other software and tools, and any partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Intel Program License +-- Subscription Agreement, the Intel Quartus Prime License Agreement, +-- the Intel FPGA IP License Agreement, or other applicable license +-- agreement, including, without limitation, that your use is for +-- the sole purpose of programming logic devices manufactured by +-- Intel and sold by Intel or its authorized distributors. Please +-- refer to the applicable agreement for further details, at +-- https://fpgasoftware.intel.com/eula. + + +FUNCTION cyclonev_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) +WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, ENABLE_ECC, INIT_FILE, INIT_FILE_LAYOUT, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init10, mem_init11, mem_init12, mem_init13, mem_init14, mem_init15, mem_init16, mem_init17, mem_init18, mem_init19, mem_init2, mem_init20, mem_init21, mem_init22, mem_init23, mem_init24, mem_init25, mem_init26, mem_init27, mem_init28, mem_init29, mem_init3, mem_init30, mem_init31, mem_init32, mem_init33, mem_init34, mem_init35, mem_init36, mem_init37, mem_init38, mem_init39, mem_init4, mem_init40, mem_init41, mem_init42, mem_init43, mem_init44, mem_init45, mem_init46, mem_init47, mem_init48, mem_init49, mem_init5, mem_init50, mem_init51, mem_init52, mem_init53, mem_init54, mem_init55, mem_init56, mem_init57, mem_init58, mem_init59, mem_init6, mem_init60, mem_init61, mem_init62, mem_init63, mem_init64, mem_init65, mem_init66, mem_init67, mem_init68, mem_init69, mem_init7, mem_init70, mem_init71, mem_init8, mem_init9, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, WIDTH_ECCSTATUS = 3) +RETURNS ( dftout[8..0], eccstatus[WIDTH_ECCSTATUS-1..0], portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); + +--synthesis_resources = M10K 4 +OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; + +SUBDESIGN altsyncram_dsq1 +( + address_a[11..0] : input; + address_b[11..0] : input; + clock0 : input; + data_a[7..0] : input; + q_b[7..0] : output; +) +VARIABLE + ram_block1a0 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/chip8.ram0_memory_e9e85012.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 12, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 4095, + PORT_B_LOGICAL_RAM_DEPTH = 4096, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/chip8.ram0_memory_e9e85012.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 12, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 4095, + PORT_B_LOGICAL_RAM_DEPTH = 4096, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/chip8.ram0_memory_e9e85012.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 12, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 4095, + PORT_B_LOGICAL_RAM_DEPTH = 4096, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a3 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/chip8.ram0_memory_e9e85012.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 12, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 4095, + PORT_B_LOGICAL_RAM_DEPTH = 4096, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a4 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/chip8.ram0_memory_e9e85012.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 12, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 4095, + PORT_B_LOGICAL_RAM_DEPTH = 4096, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a5 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/chip8.ram0_memory_e9e85012.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 12, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 4095, + PORT_B_LOGICAL_RAM_DEPTH = 4096, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a6 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/chip8.ram0_memory_e9e85012.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 12, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 4095, + PORT_B_LOGICAL_RAM_DEPTH = 4096, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a7 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "db/chip8.ram0_memory_e9e85012.hdl.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 12, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 4095, + PORT_B_LOGICAL_RAM_DEPTH = 4096, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + address_a_wire[11..0] : WIRE; + address_b_wire[11..0] : WIRE; + wren_a : NODE; + +BEGIN + ram_block1a[7..0].clk0 = clock0; + ram_block1a[7..0].portaaddr[] = ( address_a_wire[11..0]); + ram_block1a[0].portadatain[] = ( data_a[0..0]); + ram_block1a[1].portadatain[] = ( data_a[1..1]); + ram_block1a[2].portadatain[] = ( data_a[2..2]); + ram_block1a[3].portadatain[] = ( data_a[3..3]); + ram_block1a[4].portadatain[] = ( data_a[4..4]); + ram_block1a[5].portadatain[] = ( data_a[5..5]); + ram_block1a[6].portadatain[] = ( data_a[6..6]); + ram_block1a[7].portadatain[] = ( data_a[7..7]); + ram_block1a[7..0].portawe = wren_a; + ram_block1a[7..0].portbaddr[] = ( address_b_wire[11..0]); + ram_block1a[7..0].portbre = B"11111111"; + address_a_wire[] = address_a[]; + address_b_wire[] = address_b[]; + q_b[] = ( ram_block1a[7..0].portbdataout[0..0]); + wren_a = GND; +END; +--VALID FILE diff --git a/db/chip8.(25).cnf.cdb b/db/chip8.(25).cnf.cdb new file mode 100644 index 0000000..c0a2fb9 Binary files /dev/null and b/db/chip8.(25).cnf.cdb differ diff --git a/db/chip8.(25).cnf.hdb b/db/chip8.(25).cnf.hdb new file mode 100644 index 0000000..e58e2ed Binary files /dev/null and b/db/chip8.(25).cnf.hdb differ diff --git a/db/chip8.ace_cmp.bpm b/db/chip8.ace_cmp.bpm new file mode 100644 index 0000000..7906c4c Binary files /dev/null and b/db/chip8.ace_cmp.bpm differ diff --git a/db/chip8.ace_cmp.cdb b/db/chip8.ace_cmp.cdb new file mode 100644 index 0000000..631d3a8 Binary files /dev/null and b/db/chip8.ace_cmp.cdb differ diff --git a/db/chip8.ace_cmp.hdb b/db/chip8.ace_cmp.hdb new file mode 100644 index 0000000..a7c3b6a Binary files /dev/null and b/db/chip8.ace_cmp.hdb differ diff --git a/db/chip8.asm.qmsg b/db/chip8.asm.qmsg new file mode 100644 index 0000000..dbf09a5 --- /dev/null +++ b/db/chip8.asm.qmsg @@ -0,0 +1,6 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1712551930527 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition " "Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1712551930527 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 7 23:52:10 2024 " "Processing started: Sun Apr 7 23:52:10 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1712551930527 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1712551930527 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off chip8 -c chip8 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off chip8 -c chip8" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1712551930527 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1712551931223 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1712551937283 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "631 " "Peak virtual memory: 631 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1712551937598 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 7 23:52:17 2024 " "Processing ended: Sun Apr 7 23:52:17 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1712551937598 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1712551937598 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1712551937598 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1712551937598 ""} diff --git a/db/chip8.asm.rdb b/db/chip8.asm.rdb new file mode 100644 index 0000000..64b8e19 Binary files /dev/null and b/db/chip8.asm.rdb differ diff --git a/db/chip8.cmp.bpm b/db/chip8.cmp.bpm new file mode 100644 index 0000000..7906c4c Binary files /dev/null and b/db/chip8.cmp.bpm differ diff --git a/db/chip8.cmp.cdb b/db/chip8.cmp.cdb new file mode 100644 index 0000000..631d3a8 Binary files /dev/null and b/db/chip8.cmp.cdb differ diff --git a/db/chip8.cmp.hdb b/db/chip8.cmp.hdb new file mode 100644 index 0000000..a7c3b6a Binary files /dev/null and b/db/chip8.cmp.hdb differ diff --git a/db/chip8.cmp.idb b/db/chip8.cmp.idb new file mode 100644 index 0000000..b2d2924 Binary files /dev/null and b/db/chip8.cmp.idb differ diff --git a/db/chip8.cmp.logdb b/db/chip8.cmp.logdb new file mode 100644 index 0000000..24dafab --- /dev/null +++ b/db/chip8.cmp.logdb @@ -0,0 +1,50 @@ +v1 +IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,, +IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,, +IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,, +IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,, +IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,, +IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,, +IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 0 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,, +IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,, +IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000001;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000047;IO_000046;IO_000045;IO_000027;IO_000026;IO_000024;IO_000023;IO_000022;IO_000021;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000034, +IO_RULES_MATRIX,Total Pass,0;10;10;0;0;10;10;0;0;0;0;0;0;1;0;0;0;0;1;0;0;0;0;1;0;10;10;0, +IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,Total Inapplicable,10;0;0;10;10;0;0;10;10;10;10;10;10;9;10;10;10;10;9;10;10;10;10;9;10;0;0;10, +IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,lcd_clk,Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,lcd_data,Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,led[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,led[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,led[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,led[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,led[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,led[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,rst_in,Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_MATRIX,fpga_clk,Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, +IO_RULES_SUMMARY,Total I/O Rules,28, +IO_RULES_SUMMARY,Number of I/O Rules Passed,9, +IO_RULES_SUMMARY,Number of I/O Rules Failed,0, +IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0, +IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,19, diff --git a/db/chip8.cyclonev_io_sim_cache.ff_100c_fast.hsd b/db/chip8.cyclonev_io_sim_cache.ff_100c_fast.hsd new file mode 100644 index 0000000..4037e7e Binary files /dev/null and b/db/chip8.cyclonev_io_sim_cache.ff_100c_fast.hsd differ diff --git a/db/chip8.cyclonev_io_sim_cache.ff_n40c_fast.hsd b/db/chip8.cyclonev_io_sim_cache.ff_n40c_fast.hsd new file mode 100644 index 0000000..fdb72d5 Binary files /dev/null and b/db/chip8.cyclonev_io_sim_cache.ff_n40c_fast.hsd differ diff --git a/db/chip8.cyclonev_io_sim_cache.ii_100c_slow.hsd b/db/chip8.cyclonev_io_sim_cache.ii_100c_slow.hsd new file mode 100644 index 0000000..8f2fb43 Binary files /dev/null and b/db/chip8.cyclonev_io_sim_cache.ii_100c_slow.hsd differ diff --git a/db/chip8.cyclonev_io_sim_cache.ii_85c_slow.hsd b/db/chip8.cyclonev_io_sim_cache.ii_85c_slow.hsd new file mode 100644 index 0000000..4d4c749 Binary files /dev/null and b/db/chip8.cyclonev_io_sim_cache.ii_85c_slow.hsd differ diff --git a/db/chip8.cyclonev_io_sim_cache.ii_n40c_slow.hsd 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: 01110000; + 8 : 00100000; + 7 : 00100000; + 6 : 01100000; + 5 : 00100000; + 4 : 11110000; + 3 : 10010000; + 2 : 10010000; + 1 : 10010000; + 0 : 11110000; +END; diff --git a/db/chip8.routing.rdb b/db/chip8.routing.rdb new file mode 100644 index 0000000..bba26b9 Binary files /dev/null and b/db/chip8.routing.rdb differ diff --git a/db/chip8.sta.qmsg b/db/chip8.sta.qmsg new file mode 100644 index 0000000..df15159 --- /dev/null +++ b/db/chip8.sta.qmsg @@ -0,0 +1,56 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1712551938749 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition " "Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1712551938749 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 7 23:52:18 2024 " "Processing started: Sun Apr 7 23:52:18 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1712551938749 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1712551938749 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta chip8 -c chip8 " "Command: quartus_sta chip8 -c chip8" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1712551938749 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1712551938772 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1712551939456 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "12 12 " "Parallel compilation is enabled and will use 12 of the 12 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1712551939456 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature -40 degrees C " "Low junction temperature is -40 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712551939481 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 100 degrees C " "High junction temperature is 100 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712551939481 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "chip8.sdc " "Synopsys Design Constraints File file not found: 'chip8.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1712551940847 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1712551940847 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name fpga_clk fpga_clk " "create_clock -period 1.000 -name fpga_clk fpga_clk" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1712551940934 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " "create_clock -period 1.000 -name cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1712551940934 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1712551940934 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1712551941197 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1712551941259 ""} +{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1712551941263 ""} +{ "Info" "0" "" "Analyzing Slow 1100mV 100C Model" { } { } 0 0 "Analyzing Slow 1100mV 100C Model" 0 0 "Timing Analyzer" 0 0 1712551941268 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1712551945434 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1712551945434 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -28.406 " "Worst-case setup slack is -28.406" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551945434 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551945434 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -28.406 -1742.530 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " -28.406 -1742.530 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551945434 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -11.186 -95769.392 fpga_clk " " -11.186 -95769.392 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551945434 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712551945434 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.429 " "Worst-case hold slack is 0.429" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551945664 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551945664 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.429 0.000 fpga_clk " " 0.429 0.000 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551945664 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.476 0.000 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " 0.476 0.000 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551945664 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712551945664 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1712551945666 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1712551945667 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.636 " "Worst-case minimum pulse width slack is -2.636" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551945672 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551945672 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.636 -8463.323 fpga_clk " " -2.636 -8463.323 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551945672 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.538 -185.389 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " -0.538 -185.389 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551945672 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712551945672 ""} +{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 8 synchronizer chains. " "Report Metastability: Found 8 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Design MTBF is not calculated because the design doesn't meet its timing requirements. " "Design MTBF is not calculated because the design doesn't meet its timing requirements." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1712551945720 ""} } { } 0 332114 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1712551945720 ""} +{ "Info" "0" "" "Analyzing Slow 1100mV -40C Model" { } { } 0 0 "Analyzing Slow 1100mV -40C Model" 0 0 "Timing Analyzer" 0 0 1712551945722 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1712551945782 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1712551951737 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1712551952797 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1712551953465 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1712551953465 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -26.933 " "Worst-case setup slack is -26.933" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551953465 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551953465 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -26.933 -1684.576 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " -26.933 -1684.576 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551953465 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -11.228 -94100.779 fpga_clk " " -11.228 -94100.779 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551953465 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712551953465 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.484 " "Worst-case hold slack is 0.484" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551953711 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551953711 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.484 0.000 fpga_clk " " 0.484 0.000 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551953711 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.565 0.000 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " 0.565 0.000 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551953711 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712551953711 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1712551953712 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1712551953713 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.636 " "Worst-case minimum pulse width slack is -2.636" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551953723 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551953723 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.636 -8927.522 fpga_clk " " -2.636 -8927.522 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551953723 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.538 -184.012 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " -0.538 -184.012 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551953723 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712551953723 ""} +{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 8 synchronizer chains. " "Report Metastability: Found 8 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Design MTBF is not calculated because the design doesn't meet its timing requirements. " "Design MTBF is not calculated because the design doesn't meet its timing requirements." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1712551953779 ""} } { } 0 332114 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1712551953779 ""} +{ "Info" "0" "" "Analyzing Fast 1100mV 100C Model" { } { } 0 0 "Analyzing Fast 1100mV 100C Model" 0 0 "Timing Analyzer" 0 0 1712551953781 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1712551954065 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1712551959681 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1712551960616 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1712551960917 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1712551960917 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -14.774 " "Worst-case setup slack is -14.774" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551960918 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551960918 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -14.774 -901.498 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " -14.774 -901.498 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551960918 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -6.214 -50560.530 fpga_clk " " -6.214 -50560.530 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551960918 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712551960918 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.162 " "Worst-case hold slack is 0.162" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551961180 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551961180 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.162 0.000 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " 0.162 0.000 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551961180 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.177 0.000 fpga_clk " " 0.177 0.000 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551961180 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712551961180 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1712551961181 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1712551961181 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.174 " "Worst-case minimum pulse width slack is -2.174" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551961192 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551961192 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.174 -1371.543 fpga_clk " " -2.174 -1371.543 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551961192 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.192 -9.702 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " -0.192 -9.702 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551961192 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712551961192 ""} +{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 8 synchronizer chains. " "Report Metastability: Found 8 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Design MTBF is not calculated because the design doesn't meet its timing requirements. " "Design MTBF is not calculated because the design doesn't meet its timing requirements." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1712551961244 ""} } { } 0 332114 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1712551961244 ""} +{ "Info" "0" "" "Analyzing Fast 1100mV -40C Model" { } { } 0 0 "Analyzing Fast 1100mV -40C Model" 0 0 "Timing Analyzer" 0 0 1712551961245 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1712551961832 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1712551962139 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1712551962139 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -12.462 " "Worst-case setup slack is -12.462" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551962139 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551962139 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -12.462 -739.747 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " -12.462 -739.747 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551962139 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.930 -40871.978 fpga_clk " " -4.930 -40871.978 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551962139 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712551962139 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.140 " "Worst-case hold slack is 0.140" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551962440 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551962440 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.140 0.000 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " 0.140 0.000 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551962440 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.164 0.000 fpga_clk " " 0.164 0.000 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551962440 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712551962440 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1712551962441 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1712551962441 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.174 " "Worst-case minimum pulse width slack is -2.174" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551962451 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551962451 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.174 -1373.239 fpga_clk " " -2.174 -1373.239 fpga_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551962451 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.137 -3.355 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " " -0.137 -3.355 cpu:cpu\|st7920_serial_driver:gpu\|lcd_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1712551962451 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1712551962451 ""} +{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 8 synchronizer chains. " "Report Metastability: Found 8 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Design MTBF is not calculated because the design doesn't meet its timing requirements. " "Design MTBF is not calculated because the design doesn't meet its timing requirements." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1712551962500 ""} } { } 0 332114 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1712551962500 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1712551963345 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1712551963345 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1353 " "Peak virtual memory: 1353 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1712551963512 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 7 23:52:43 2024 " "Processing ended: Sun Apr 7 23:52:43 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1712551963512 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:25 " "Elapsed time: 00:00:25" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1712551963512 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:01:44 " "Total CPU time (on all processors): 00:01:44" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1712551963512 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1712551963512 ""} diff --git a/db/chip8.sta.rdb b/db/chip8.sta.rdb new file mode 100644 index 0000000..403eaee Binary files /dev/null and b/db/chip8.sta.rdb differ diff --git a/db/chip8.sta_cmp.7_slow_1100mv_100c.tdb b/db/chip8.sta_cmp.7_slow_1100mv_100c.tdb new file mode 100644 index 0000000..7c19512 Binary files /dev/null and b/db/chip8.sta_cmp.7_slow_1100mv_100c.tdb differ diff --git a/db/chip8.tiscmp.fast_1100mv_100c.ddb b/db/chip8.tiscmp.fast_1100mv_100c.ddb new file mode 100644 index 0000000..7b0f644 Binary files /dev/null and b/db/chip8.tiscmp.fast_1100mv_100c.ddb differ diff --git a/db/chip8.tiscmp.fast_1100mv_n40c.ddb b/db/chip8.tiscmp.fast_1100mv_n40c.ddb new file mode 100644 index 0000000..5516421 Binary files /dev/null and b/db/chip8.tiscmp.fast_1100mv_n40c.ddb differ diff --git a/db/chip8.tiscmp.fastest_slow_1100mv_85c.ddb b/db/chip8.tiscmp.fastest_slow_1100mv_85c.ddb new file mode 100644 index 0000000..bd7eb78 Binary files /dev/null and b/db/chip8.tiscmp.fastest_slow_1100mv_85c.ddb differ diff --git a/db/chip8.tiscmp.fastest_slow_1100mv_n40c.ddb b/db/chip8.tiscmp.fastest_slow_1100mv_n40c.ddb new file mode 100644 index 0000000..248c52a Binary files /dev/null and b/db/chip8.tiscmp.fastest_slow_1100mv_n40c.ddb differ diff --git a/db/chip8.tiscmp.slow_1100mv_100c.ddb b/db/chip8.tiscmp.slow_1100mv_100c.ddb new file mode 100644 index 0000000..90b065f Binary files /dev/null and b/db/chip8.tiscmp.slow_1100mv_100c.ddb differ diff --git a/db/chip8.tiscmp.slow_1100mv_n40c.ddb b/db/chip8.tiscmp.slow_1100mv_n40c.ddb new file mode 100644 index 0000000..5220654 Binary files /dev/null and b/db/chip8.tiscmp.slow_1100mv_n40c.ddb differ diff --git a/incremental_db/compiled_partitions/chip8.root_partition.cmp.ammdb b/incremental_db/compiled_partitions/chip8.root_partition.cmp.ammdb new file mode 100644 index 0000000..db46419 Binary files /dev/null and b/incremental_db/compiled_partitions/chip8.root_partition.cmp.ammdb differ diff --git a/incremental_db/compiled_partitions/chip8.root_partition.cmp.cdb b/incremental_db/compiled_partitions/chip8.root_partition.cmp.cdb new file mode 100644 index 0000000..2544e0d Binary files /dev/null and b/incremental_db/compiled_partitions/chip8.root_partition.cmp.cdb differ diff --git a/incremental_db/compiled_partitions/chip8.root_partition.cmp.dfp b/incremental_db/compiled_partitions/chip8.root_partition.cmp.dfp new file mode 100644 index 0000000..b1c67d6 Binary files /dev/null and b/incremental_db/compiled_partitions/chip8.root_partition.cmp.dfp differ diff --git a/incremental_db/compiled_partitions/chip8.root_partition.cmp.hbdb.cdb b/incremental_db/compiled_partitions/chip8.root_partition.cmp.hbdb.cdb new file mode 100644 index 0000000..5be6049 Binary files /dev/null and b/incremental_db/compiled_partitions/chip8.root_partition.cmp.hbdb.cdb differ diff --git a/incremental_db/compiled_partitions/chip8.root_partition.cmp.hbdb.hdb b/incremental_db/compiled_partitions/chip8.root_partition.cmp.hbdb.hdb new file mode 100644 index 0000000..6c77492 Binary files /dev/null and b/incremental_db/compiled_partitions/chip8.root_partition.cmp.hbdb.hdb differ diff --git a/incremental_db/compiled_partitions/chip8.root_partition.cmp.hbdb.sig b/incremental_db/compiled_partitions/chip8.root_partition.cmp.hbdb.sig new file mode 100644 index 0000000..af9b8e9 --- /dev/null +++ b/incremental_db/compiled_partitions/chip8.root_partition.cmp.hbdb.sig @@ -0,0 +1 @@ +7aee213afbf8301ed5eefc8c827f49a3 \ No newline at end of file diff --git a/incremental_db/compiled_partitions/chip8.root_partition.cmp.hdb b/incremental_db/compiled_partitions/chip8.root_partition.cmp.hdb new file mode 100644 index 0000000..eda732a Binary files /dev/null and b/incremental_db/compiled_partitions/chip8.root_partition.cmp.hdb differ diff --git a/incremental_db/compiled_partitions/chip8.root_partition.cmp.logdb b/incremental_db/compiled_partitions/chip8.root_partition.cmp.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/incremental_db/compiled_partitions/chip8.root_partition.cmp.logdb @@ -0,0 +1 @@ +v1 diff --git a/incremental_db/compiled_partitions/chip8.root_partition.cmp.rcfdb b/incremental_db/compiled_partitions/chip8.root_partition.cmp.rcfdb new file mode 100644 index 0000000..39adc53 Binary files /dev/null and b/incremental_db/compiled_partitions/chip8.root_partition.cmp.rcfdb differ diff --git a/incremental_db/compiled_partitions/chip8.rrp.hdb b/incremental_db/compiled_partitions/chip8.rrp.hdb new file mode 100644 index 0000000..2c2963d Binary files /dev/null and b/incremental_db/compiled_partitions/chip8.rrp.hdb differ diff --git a/incremental_db/compiled_partitions/chip8.rrs.cdb b/incremental_db/compiled_partitions/chip8.rrs.cdb new file mode 100644 index 0000000..881e967 Binary files /dev/null and b/incremental_db/compiled_partitions/chip8.rrs.cdb differ diff --git a/output_files/chip8.asm.rpt b/output_files/chip8.asm.rpt new file mode 100644 index 0000000..851cabd --- /dev/null +++ b/output_files/chip8.asm.rpt @@ -0,0 +1,91 @@ +Assembler report for chip8 +Sun Apr 7 23:52:17 2024 +Quartus Prime Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Generated Files + 5. Assembler Device Options: chip8.sof + 6. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2023 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Sun Apr 7 23:52:17 2024 ; +; Revision Name ; chip8 ; +; Top-level Entity Name ; chip8 ; +; Family ; Cyclone V ; +; Device ; 5CSEBA6U23I7 ; ++-----------------------+---------------------------------------+ + + ++----------------------------------+ +; Assembler Settings ; ++--------+---------+---------------+ +; Option ; Setting ; Default Value ; ++--------+---------+---------------+ + + ++-------------------------------------------------------------------------------+ +; Assembler Generated Files ; ++-------------------------------------------------------------------------------+ +; File Name ; ++-------------------------------------------------------------------------------+ +; /home/nickorlow/programming/school/warminster/yayacemu/output_files/chip8.sof ; ++-------------------------------------------------------------------------------+ + + ++-------------------------------------+ +; Assembler Device Options: chip8.sof ; ++----------------+--------------------+ +; Option ; Setting ; ++----------------+--------------------+ +; JTAG usercode ; 0x02233A94 ; +; Checksum ; 0x02233A94 ; ++----------------+--------------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Assembler + Info: Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition + Info: Processing started: Sun Apr 7 23:52:10 2024 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off chip8 -c chip8 +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (115030): Assembler is generating device programming files +Info: Quartus Prime Assembler was successful. 0 errors, 1 warning + Info: Peak virtual memory: 631 megabytes + Info: Processing ended: Sun Apr 7 23:52:17 2024 + Info: Elapsed time: 00:00:07 + Info: Total CPU time (on all processors): 00:00:07 + + diff --git a/output_files/chip8.cdf b/output_files/chip8.cdf new file mode 100644 index 0000000..0b007b1 --- /dev/null +++ b/output_files/chip8.cdf @@ -0,0 +1,15 @@ + /* Quartus Prime Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition */ + JedecChain; + FileRevision(JESD32A); + DefaultMfr(6E); + + P ActionCode(Ign) + Device PartName(SOCVHPS) MfrSpec(OpMask(0)); + P ActionCode(Cfg) + Device PartName(5CSEBA6U23) Path("/home/nickorlow/programming/school/warminster/yayacemu/output_files/") File("chip8.sof") MfrSpec(OpMask(1)); + + ChainEnd; + + AlteraBegin; + ChainType(JTAG); + AlteraEnd; diff --git a/output_files/chip8.fit.rpt b/output_files/chip8.fit.rpt new file mode 100644 index 0000000..73b2250 --- /dev/null +++ b/output_files/chip8.fit.rpt @@ -0,0 +1,2981 @@ +Fitter report for chip8 +Sun Apr 7 23:52:05 2024 +Quartus Prime Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Parallel Compilation + 5. Fitter Netlist Optimizations + 6. Ignored Assignments + 7. Incremental Compilation Preservation Summary + 8. Incremental Compilation Partition Settings + 9. Incremental Compilation Placement Preservation + 10. Pin-Out File + 11. Fitter Resource Usage Summary + 12. Fitter Partition Statistics + 13. Input Pins + 14. Output Pins + 15. I/O Bank Usage + 16. All Package Pins + 17. I/O Assignment Warnings + 18. Fitter Resource Utilization by Entity + 19. Delay Chain Summary + 20. Pad To Core Delay Chain Fanout + 21. Control Signals + 22. Global & Other Fast Signals + 23. Non-Global High Fan-Out Signals + 24. Fitter RAM Summary + 25. Routing Usage Summary + 26. I/O Rules Summary + 27. I/O Rules Details + 28. I/O Rules Matrix + 29. Fitter Device Options + 30. Operating Settings and Conditions + 31. Estimated Delay Added for Hold Timing Summary + 32. Estimated Delay Added for Hold Timing Details + 33. Fitter Messages + 34. Fitter Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2023 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++----------------------------------------------------------------------------------+ +; Fitter Summary ; ++---------------------------------+------------------------------------------------+ +; Fitter Status ; Successful - Sun Apr 7 23:52:05 2024 ; +; Quartus Prime Version ; 23.1std.0 Build 991 11/28/2023 SC Lite Edition ; +; Revision Name ; chip8 ; +; Top-level Entity Name ; chip8 ; +; Family ; Cyclone V ; +; Device ; 5CSEBA6U23I7 ; +; Timing Models ; Final ; +; Logic utilization (in ALMs) ; 10,549 / 41,910 ( 25 % ) ; +; Total registers ; 10004 ; +; Total pins ; 10 / 314 ( 3 % ) ; +; Total virtual pins ; 0 ; +; Total block memory bits ; 32,768 / 5,662,720 ( < 1 % ) ; +; Total RAM Blocks ; 4 / 553 ( < 1 % ) ; +; Total DSP Blocks ; 0 / 112 ( 0 % ) ; +; Total HSSI RX PCSs ; 0 ; +; Total HSSI PMA RX Deserializers ; 0 ; +; Total HSSI TX PCSs ; 0 ; +; Total HSSI PMA TX Serializers ; 0 ; +; Total PLLs ; 0 / 6 ( 0 % ) ; +; Total DLLs ; 0 / 4 ( 0 % ) ; ++---------------------------------+------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Option ; Setting ; Default Value ; ++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Device ; 5CSEBA6U23I7 ; ; +; Minimum Core Junction Temperature ; -40 ; ; +; Maximum Core Junction Temperature ; 100 ; ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Perform Clocking Topology Analysis During Routing ; Off ; Off ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Device initialization clock source ; INIT_INTOSC ; INIT_INTOSC ; +; Optimize Hold Timing ; All Paths ; All Paths ; +; Optimize Multi-Corner Timing ; On ; On ; +; Auto RAM to MLAB Conversion ; On ; On ; +; Equivalent RAM and MLAB Power Up ; Auto ; Auto ; +; Equivalent RAM and MLAB Paused Read Capabilities ; Care ; Care ; +; Power Optimization During Fitting ; Normal compilation ; Normal compilation ; +; SSN Optimization ; Off ; Off ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; Normal ; Normal ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; Periphery to Core Placement and Routing Optimization ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Packed Registers ; Auto ; Auto ; +; Auto Delay Chains ; On ; On ; +; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ; +; Treat Bidirectional Pin as Output Pin ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; +; Perform Register Duplication for Performance ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Physical Synthesis Effort Level ; Normal ; Normal ; +; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ; +; Auto Register Duplication ; Auto ; Auto ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ; +; Synchronizer Identification ; Auto ; Auto ; +; Enable Beneficial Skew Optimization ; On ; On ; +; Optimize Design for Metastability ; On ; On ; +; Active Serial clock source ; FREQ_100MHz ; FREQ_100MHz ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; +; Clamping Diode ; Off ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; Off ; +; Advanced Physical Optimization ; On ; On ; ++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 12 ; +; Maximum allowed ; 12 ; +; ; ; +; Average used ; 1.61 ; +; Maximum used ; 12 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processor 2 ; 10.6% ; +; Processor 3 ; 8.3% ; +; Processor 4 ; 7.9% ; +; Processor 5 ; 4.6% ; +; Processor 6 ; 4.5% ; +; Processor 7 ; 4.5% ; +; Processor 8 ; 4.4% ; +; Processor 9 ; 4.1% ; +; Processor 10 ; 4.1% ; +; Processor 11 ; 4.1% ; +; Processor 12 ; 4.1% ; ++----------------------------+-------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Netlist Optimizations ; ++------------------------------------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+----------------------------------------------------------------+------------------+-----------------------+ +; Node ; Action ; Operation ; Reason ; Node Port ; Node Port Name ; Destination Node ; Destination Port ; Destination Port Name ; ++------------------------------------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+----------------------------------------------------------------+------------------+-----------------------+ +; fpga_clk~inputCLKENA0 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; +; cpu:cpu|draw_state.c[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|draw_state.c[0]~DUPLICATE ; ; ; +; cpu:cpu|draw_state.c[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|draw_state.c[1]~DUPLICATE ; ; ; +; cpu:cpu|draw_state.c[3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|draw_state.c[3]~DUPLICATE ; ; ; +; cpu:cpu|draw_state.r[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|draw_state.r[0]~DUPLICATE ; ; ; +; cpu:cpu|draw_state.r[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|draw_state.r[1]~DUPLICATE ; ; ; +; cpu:cpu|draw_state.r[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|draw_state.r[2]~DUPLICATE ; ; ; +; cpu:cpu|draw_state.r[3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|draw_state.r[3]~DUPLICATE ; ; ; +; cpu:cpu|draw_state.r[4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|draw_state.r[4]~DUPLICATE ; ; ; +; cpu:cpu|instr.dst_reg[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|instr.dst_reg[1]~DUPLICATE ; ; ; +; cpu:cpu|instr.dst_reg[3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|instr.dst_reg[3]~DUPLICATE ; ; ; +; cpu:cpu|instr.op[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|instr.op[1]~DUPLICATE ; ; ; +; cpu:cpu|instr.src_byte[7] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|instr.src_byte[7]~DUPLICATE ; ; ; +; cpu:cpu|instr.src_byte[8] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|instr.src_byte[8]~DUPLICATE ; ; ; +; cpu:cpu|instr.src_byte[10] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|instr.src_byte[10]~DUPLICATE ; ; ; +; cpu:cpu|instr.src_byte[11] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|instr.src_byte[11]~DUPLICATE ; ; ; +; cpu:cpu|instr.src_sprite_idx[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|instr.src_sprite_idx[0]~DUPLICATE ; ; ; +; cpu:cpu|instr.src_sprite_idx[3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|instr.src_sprite_idx[3]~DUPLICATE ; ; ; +; cpu:cpu|instr.src_sprite_idx[4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|instr.src_sprite_idx[4]~DUPLICATE ; ; ; +; cpu:cpu|instr.src_sprite_vx[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|instr.src_sprite_vx[1]~DUPLICATE ; ; ; +; cpu:cpu|opcode[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|opcode[0]~DUPLICATE ; ; ; +; cpu:cpu|opcode[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|opcode[1]~DUPLICATE ; ; ; +; cpu:cpu|opcode[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|opcode[2]~DUPLICATE ; ; ; +; cpu:cpu|opcode[4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|opcode[4]~DUPLICATE ; ; ; +; cpu:cpu|opcode[5] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|opcode[5]~DUPLICATE ; ; ; +; cpu:cpu|opcode[9] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|opcode[9]~DUPLICATE ; ; ; +; cpu:cpu|opcode[10] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|opcode[10]~DUPLICATE ; ; ; +; cpu:cpu|opcode[15] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|opcode[15]~DUPLICATE ; ; ; +; cpu:cpu|program_counter[9] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|program_counter[9]~DUPLICATE ; ; ; +; cpu:cpu|registers[0][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|registers[0][0]~DUPLICATE ; ; ; +; cpu:cpu|registers[0][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|registers[0][2]~DUPLICATE ; ; ; +; cpu:cpu|registers[0][3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|registers[0][3]~DUPLICATE ; ; ; +; cpu:cpu|registers[0][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|registers[0][4]~DUPLICATE ; ; ; +; cpu:cpu|registers[8][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|registers[8][2]~DUPLICATE ; ; ; +; cpu:cpu|registers[8][3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|registers[8][3]~DUPLICATE ; ; ; +; cpu:cpu|registers[8][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|registers[8][4]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|c[12] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|c[12]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|commander:com|i[3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|commander:com|i[3]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|commander:com|i[6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|commander:com|i[6]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|commander:com|i[10] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|commander:com|i[10]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|commander:com|i[13] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|commander:com|i[13]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|commander:com|i[14] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|commander:com|i[14]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|commander:com|i[21] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|commander:com|i[21]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|commander:com|i[22] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|commander:com|i[22]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|commander:com|i[23] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|commander:com|i[23]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|commander:com|i[25] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|commander:com|i[25]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|commander:com|i[26] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|commander:com|i[26]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|commander:com|i[28] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|commander:com|i[28]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|commander:com|i[29] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|commander:com|i[29]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|i[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|i[0]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|i[10] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|i[10]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|i[13] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|i[13]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|i[16] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|i[16]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|i[22] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|i[22]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|i[29] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|i[29]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|i[30] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|i[30]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|i[31] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|i[31]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|line_cnt[4]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[5] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|line_cnt[5]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|line_cnt[6]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[7] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|line_cnt[7]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[8] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|line_cnt[8]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[9] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|line_cnt[9]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[10] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|line_cnt[10]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[11] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|line_cnt[11]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[13] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|line_cnt[13]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[14] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|line_cnt[14]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[16] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|line_cnt[16]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[18] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|line_cnt[18]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[19] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|line_cnt[19]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[20] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|line_cnt[20]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[21] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|line_cnt[21]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[22] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|line_cnt[22]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[24] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|line_cnt[24]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[31] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|line_cnt[31]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|x[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|x[0]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|x[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|x[2]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|y[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|y[0]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|y[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|y[1]~DUPLICATE ; ; ; +; cpu:cpu|st7920_serial_driver:gpu|y[3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|st7920_serial_driver:gpu|y[3]~DUPLICATE ; ; ; +; cpu:cpu|state[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|state[2]~DUPLICATE ; ; ; +; cpu:cpu|vram[0][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[0][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[1][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[1][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[2][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[2][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[5][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[5][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[5][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[5][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[5][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[5][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[7][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[7][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[7][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[7][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[8][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[8][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[9][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[9][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[9][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[9][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[11][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[11][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[11][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[11][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[12][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[12][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[14][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[14][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[15][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[15][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[17][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[17][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[17][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[17][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[18][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[18][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[18][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[18][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[18][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[18][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[19][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[19][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[19][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[19][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[22][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[22][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[22][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[22][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[26][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[26][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[27][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[27][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[27][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[27][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[28][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[28][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[28][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[28][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[29][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[29][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[30][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[30][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[30][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[30][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[31][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[31][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[32][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[32][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[33][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[33][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[36][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[36][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[37][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[37][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[39][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[39][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[39][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[39][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[39][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[39][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[40][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[40][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[41][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[41][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[41][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[41][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[43][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[43][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[43][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[43][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[44][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[44][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[46][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[46][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[47][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[47][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[47][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[47][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[48][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[48][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[49][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[49][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[49][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[49][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[50][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[50][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[52][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[52][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[53][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[53][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[54][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[54][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[55][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[55][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[56][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[56][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[57][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[57][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[57][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[57][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[58][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[58][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[59][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[59][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[60][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[60][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[62][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[62][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[63][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[63][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[63][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[63][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[63][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[63][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[64][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[64][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[65][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[65][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[65][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[65][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[66][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[66][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[66][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[66][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[66][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[66][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[67][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[67][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[67][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[67][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[70][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[70][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[71][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[71][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[72][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[72][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[73][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[73][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[75][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[75][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[76][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[76][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[76][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[76][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[78][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[78][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[79][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[79][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[79][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[79][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[80][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[80][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[80][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[80][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[82][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[82][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[83][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[83][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[88][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[88][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[88][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[88][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[88][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[88][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[89][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[89][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[90][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[90][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[90][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[90][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[92][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[92][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[93][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[93][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[97][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[97][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[99][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[99][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[101][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[101][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[102][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[102][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[103][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[103][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[104][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[104][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[106][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[106][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[107][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[107][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[110][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[110][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[110][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[110][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[111][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[111][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[112][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[112][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[115][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[115][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[116][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[116][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[117][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[117][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[118][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[118][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[120][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[120][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[122][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[122][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[122][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[122][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[122][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[122][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[122][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[122][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[124][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[124][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[126][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[126][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[128][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[128][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[132][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[132][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[133][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[133][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[134][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[134][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[135][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[135][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[136][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[136][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[137][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[137][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[139][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[139][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[140][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[140][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[141][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[141][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[141][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[141][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[145][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[145][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[146][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[146][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[147][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[147][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[147][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[147][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[148][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[148][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[149][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[149][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[150][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[150][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[150][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[150][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[155][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[155][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[156][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[156][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[157][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[157][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[157][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[157][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[161][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[161][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[161][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[161][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[161][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[161][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[166][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[166][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[168][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[168][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[168][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[168][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[174][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[174][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[174][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[174][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[174][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[174][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[175][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[175][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[175][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[175][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[176][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[176][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[176][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[176][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[177][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[177][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[178][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[178][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[180][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[180][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[181][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[181][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[182][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[182][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[185][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[185][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[186][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[186][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[187][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[187][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[187][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[187][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[190][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[190][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[192][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[192][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[193][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[193][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[197][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[197][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[197][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[197][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[198][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[198][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[200][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[200][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[203][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[203][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[204][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[204][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[205][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[205][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[205][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[205][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[205][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[205][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[206][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[206][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[213][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[213][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[216][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[216][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[217][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[217][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[217][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[217][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[217][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[217][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[218][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[218][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[219][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[219][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[219][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[219][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[220][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[220][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[223][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[223][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[224][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[224][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[225][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[225][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[226][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[226][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[226][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[226][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[227][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[227][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[228][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[228][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[229][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[229][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[230][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[230][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[231][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[231][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[231][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[231][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[231][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[231][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[232][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[232][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[234][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[234][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[235][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[235][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[236][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[236][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[237][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[237][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[237][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[237][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[238][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[238][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[239][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[239][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[241][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[241][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[241][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[241][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[241][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[241][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[244][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[244][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[244][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[244][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[245][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[245][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[245][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[245][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[245][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[245][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[246][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[246][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[247][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[247][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[248][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[248][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[249][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[249][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[249][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[249][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[250][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[250][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[250][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[250][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[257][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[257][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[258][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[258][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[260][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[260][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[261][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[261][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[262][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[262][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[264][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[264][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[264][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[264][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[265][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[265][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[266][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[266][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[266][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[266][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[267][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[267][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[267][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[267][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[267][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[267][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[268][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[268][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[269][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[269][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[270][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[270][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[270][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[270][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[272][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[272][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[272][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[272][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[273][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[273][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[273][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[273][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[274][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[274][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[275][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[275][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[275][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[275][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[276][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[276][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[277][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[277][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[278][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[278][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[279][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[279][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[279][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[279][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[280][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[280][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[280][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[280][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[281][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[281][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[281][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[281][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[282][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[282][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[282][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[282][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[282][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[282][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[283][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[283][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[284][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[284][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[284][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[284][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[286][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[286][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[288][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[288][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[288][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[288][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[289][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[289][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[289][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[289][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[292][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[292][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[292][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[292][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[293][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[293][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[293][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[293][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[294][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[294][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[294][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[294][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[295][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[295][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[295][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[295][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[295][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[295][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[297][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[297][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[297][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[297][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[298][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[298][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[298][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[298][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[298][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[298][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[299][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[299][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[301][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[301][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[302][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[302][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[302][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[302][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[303][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[303][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[304][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[304][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[305][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[305][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[305][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[305][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[305][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[305][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[306][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[306][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[307][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[307][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[309][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[309][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[309][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[309][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[310][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[310][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[312][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[312][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[313][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[313][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[315][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[315][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[315][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[315][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[316][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[316][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[316][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[316][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[317][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[317][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[318][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[318][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[318][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[318][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[319][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[319][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[319][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[319][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[320][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[320][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[321][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[321][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[321][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[321][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[322][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[322][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[323][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[323][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[324][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[324][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[325][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[325][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[326][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[326][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[329][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[329][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[330][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[330][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[331][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[331][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[331][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[331][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[331][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[331][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[332][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[332][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[334][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[334][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[334][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[334][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[335][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[335][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[336][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[336][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[336][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[336][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[337][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[337][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[337][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[337][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[340][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[340][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[340][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[340][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[341][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[341][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[342][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[342][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[342][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[342][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[342][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[342][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[343][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[343][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[343][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[343][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[344][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[344][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[347][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[347][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[349][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[349][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[351][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[351][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[351][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[351][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[352][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[352][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[354][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[354][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[354][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[354][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[355][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[355][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[356][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[356][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[356][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[356][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[356][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[356][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[360][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[360][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[361][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[361][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[362][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[362][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[362][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[362][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[364][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[364][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[365][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[365][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[367][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[367][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[368][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[368][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[369][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[369][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[370][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[370][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[372][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[372][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[372][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[372][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[373][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[373][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[373][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[373][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[373][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[373][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[374][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[374][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[374][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[374][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[374][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[374][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[375][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[375][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[375][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[375][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[375][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[375][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[376][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[376][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[377][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[377][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[378][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[378][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[378][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[378][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[379][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[379][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[379][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[379][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[380][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[380][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[380][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[380][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[381][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[381][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[381][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[381][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[383][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[383][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[384][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[384][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[385][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[385][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[386][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[386][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[387][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[387][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[388][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[388][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[388][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[388][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[390][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[390][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[392][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[392][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[393][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[393][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[394][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[394][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[394][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[394][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[394][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[394][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[395][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[395][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[395][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[395][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[397][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[397][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[397][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[397][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[401][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[401][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[403][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[403][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[403][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[403][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[405][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[405][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[405][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[405][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[406][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[406][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[407][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[407][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[407][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[407][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[408][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[408][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[408][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[408][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[409][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[409][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[409][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[409][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[411][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[411][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[411][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[411][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[412][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[412][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[414][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[414][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[418][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[418][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[418][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[418][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[418][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[418][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[421][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[421][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[422][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[422][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[423][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[423][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[424][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[424][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[425][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[425][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[425][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[425][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[426][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[426][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[426][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[426][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[429][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[429][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[429][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[429][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[430][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[430][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[431][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[431][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[432][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[432][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[432][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[432][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[433][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[433][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[433][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[433][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[433][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[433][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[434][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[434][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[434][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[434][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[435][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[435][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[437][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[437][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[438][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[438][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[438][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[438][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[439][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[439][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[443][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[443][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[443][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[443][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[444][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[444][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[444][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[444][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[445][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[445][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[445][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[445][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[447][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[447][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[448][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[448][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[448][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[448][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[449][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[449][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[449][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[449][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[451][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[451][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[454][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[454][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[455][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[455][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[457][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[457][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[458][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[458][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[458][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[458][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[458][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[458][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[460][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[460][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[460][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[460][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[461][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[461][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[462][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[462][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[463][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[463][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[466][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[466][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[466][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[466][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[466][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[466][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[467][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[467][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[467][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[467][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[467][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[467][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[470][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[470][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[471][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[471][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[474][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[474][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[477][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[477][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[477][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[477][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[477][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[477][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[480][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[480][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[481][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[481][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[482][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[482][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[482][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[482][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[485][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[485][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[486][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[486][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[487][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[487][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[488][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[488][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[488][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[488][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[490][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[490][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[490][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[490][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[493][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[493][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[493][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[493][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[494][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[494][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[495][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[495][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[496][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[496][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[498][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[498][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[499][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[499][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[500][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[500][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[502][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[502][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[502][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[502][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[502][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[502][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[503][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[503][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[503][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[503][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[504][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[504][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[505][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[505][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[505][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[505][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[506][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[506][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[507][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[507][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[507][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[507][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[510][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[510][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[511][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[511][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[512][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[512][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[514][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[514][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[515][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[515][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[516][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[516][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[516][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[516][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[518][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[518][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[518][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[518][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[519][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[519][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[519][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[519][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[520][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[520][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[520][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[520][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[521][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[521][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[521][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[521][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[522][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[522][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[522][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[522][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[522][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[522][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[523][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[523][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[524][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[524][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[525][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[525][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[527][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[527][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[528][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[528][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[529][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[529][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[529][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[529][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[529][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[529][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[531][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[531][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[533][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[533][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[533][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[533][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[534][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[534][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[535][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[535][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[536][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[536][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[536][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[536][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[537][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[537][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[537][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[537][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[539][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[539][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[539][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[539][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[539][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[539][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[540][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[540][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[540][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[540][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[541][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[541][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[545][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[545][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[547][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[547][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[547][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[547][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[549][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[549][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[550][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[550][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[552][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[552][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[552][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[552][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[553][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[553][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[554][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[554][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[554][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[554][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[555][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[555][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[556][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[556][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[557][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[557][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[557][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[557][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[557][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[557][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[557][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[557][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[558][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[558][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[559][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[559][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[560][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[560][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[561][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[561][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[561][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[561][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[563][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[563][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[563][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[563][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[564][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[564][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[565][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[565][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[565][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[565][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[565][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[565][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[567][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[567][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[571][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[571][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[571][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[571][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[572][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[572][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[574][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[574][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[575][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[575][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[575][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[575][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[580][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[580][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[581][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[581][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[581][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[581][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[582][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[582][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[583][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[583][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[584][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[584][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[584][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[584][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[584][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[584][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[584][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[584][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[585][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[585][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[587][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[587][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[588][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[588][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[589][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[589][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[590][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[590][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[592][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[592][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[592][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[592][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[594][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[594][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[596][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[596][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[596][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[596][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[598][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[598][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[598][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[598][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[598][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[598][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[599][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[599][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[600][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[600][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[601][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[601][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[601][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[601][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[602][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[602][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[603][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[603][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[608][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[608][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[608][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[608][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[609][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[609][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[609][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[609][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[610][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[610][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[610][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[610][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[611][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[611][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[612][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[612][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[612][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[612][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[613][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[613][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[613][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[613][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[614][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[614][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[614][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[614][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[617][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[617][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[617][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[617][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[618][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[618][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[620][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[620][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[620][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[620][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[621][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[621][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[621][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[621][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[623][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[623][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[624][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[624][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[624][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[624][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[626][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[626][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[627][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[627][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[627][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[627][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[627][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[627][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[628][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[628][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[628][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[628][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[628][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[628][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[629][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[629][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[629][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[629][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[631][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[631][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[632][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[632][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[632][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[632][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[632][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[632][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[636][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[636][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[639][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[639][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[640][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[640][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[640][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[640][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[641][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[641][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[641][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[641][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[641][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[641][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[642][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[642][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[642][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[642][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[643][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[643][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[643][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[643][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[644][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[644][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[646][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[646][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[647][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[647][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[648][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[648][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[649][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[649][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[650][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[650][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[650][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[650][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[650][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[650][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[651][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[651][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[652][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[652][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[652][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[652][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[652][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[652][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[653][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[653][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[653][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[653][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[654][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[654][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[656][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[656][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[659][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[659][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[659][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[659][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[660][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[660][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[660][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[660][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[662][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[662][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[662][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[662][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[664][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[664][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[664][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[664][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[665][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[665][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[665][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[665][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[665][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[665][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[666][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[666][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[668][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[668][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[668][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[668][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[670][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[670][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[670][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[670][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[671][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[671][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[672][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[672][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[673][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[673][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[673][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[673][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[673][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[673][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[674][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[674][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[676][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[676][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[678][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[678][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[679][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[679][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[679][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[679][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[680][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[680][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[680][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[680][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[680][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[680][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[683][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[683][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[685][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[685][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[685][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[685][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[685][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[685][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[687][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[687][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[687][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[687][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[687][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[687][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[688][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[688][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[688][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[688][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[690][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[690][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[691][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[691][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[691][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[691][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[692][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[692][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[695][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[695][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[696][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[696][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[698][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[698][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[698][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[698][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[701][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[701][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[702][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[702][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[703][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[703][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[704][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[704][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[704][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[704][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[704][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[704][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[705][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[705][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[707][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[707][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[707][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[707][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[707][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[707][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[708][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[708][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[708][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[708][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[708][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[708][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[711][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[711][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[711][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[711][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[712][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[712][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[712][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[712][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[712][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[712][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[713][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[713][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[713][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[713][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[714][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[714][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[714][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[714][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[715][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[715][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[715][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[715][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[715][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[715][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[717][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[717][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[718][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[718][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[719][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[719][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[720][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[720][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[720][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[720][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[720][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[720][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[721][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[721][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[722][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[722][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[723][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[723][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[724][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[724][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[725][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[725][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[725][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[725][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[726][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[726][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[727][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[727][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[727][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[727][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[728][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[728][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[729][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[729][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[730][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[730][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[730][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[730][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[730][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[730][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[731][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[731][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[731][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[731][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[736][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[736][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[737][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[737][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[738][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[738][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[738][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[738][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[740][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[740][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[741][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[741][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[744][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[744][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[744][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[744][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[745][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[745][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[746][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[746][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[748][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[748][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[748][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[748][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[752][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[752][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[752][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[752][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[753][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[753][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[753][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[753][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[754][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[754][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[754][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[754][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[755][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[755][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[755][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[755][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[756][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[756][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[757][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[757][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[758][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[758][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[758][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[758][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[759][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[759][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[759][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[759][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[759][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[759][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[761][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[761][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[762][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[762][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[762][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[762][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[762][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[762][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[763][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[763][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[763][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[763][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[765][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[765][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[765][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[765][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[766][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[766][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[766][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[766][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[767][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[767][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[768][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[768][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[769][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[769][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[770][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[770][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[770][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[770][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[770][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[770][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[771][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[771][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[771][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[771][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[773][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[773][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[773][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[773][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[774][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[774][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[774][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[774][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[774][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[774][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[775][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[775][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[775][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[775][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[775][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[775][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[775][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[775][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[776][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[776][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[778][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[778][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[778][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[778][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[778][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[778][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[779][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[779][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[779][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[779][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[780][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[780][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[780][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[780][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[781][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[781][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[782][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[782][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[783][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[783][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[784][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[784][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[785][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[785][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[787][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[787][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[788][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[788][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[788][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[788][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[788][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[788][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[789][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[789][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[789][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[789][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[790][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[790][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[791][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[791][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[791][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[791][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[792][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[792][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[792][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[792][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[794][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[794][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[795][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[795][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[795][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[795][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[796][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[796][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[796][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[796][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[797][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[797][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[797][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[797][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[799][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[799][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[801][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[801][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[801][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[801][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[802][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[802][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[802][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[802][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[803][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[803][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[803][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[803][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[804][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[804][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[804][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[804][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[805][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[805][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[805][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[805][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[806][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[806][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[807][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[807][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[808][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[808][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[808][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[808][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[808][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[808][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[809][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[809][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[810][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[810][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[810][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[810][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[810][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[810][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[811][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[811][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[812][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[812][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[812][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[812][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[812][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[812][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[813][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[813][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[813][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[813][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[815][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[815][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[818][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[818][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[820][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[820][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[821][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[821][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[821][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[821][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[822][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[822][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[822][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[822][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[823][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[823][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[823][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[823][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[824][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[824][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[825][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[825][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[825][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[825][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[825][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[825][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[827][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[827][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[828][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[828][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[830][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[830][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[831][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[831][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[831][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[831][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[832][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[832][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[832][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[832][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[833][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[833][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[834][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[834][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[835][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[835][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[836][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[836][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[836][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[836][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[838][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[838][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[840][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[840][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[841][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[841][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[841][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[841][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[842][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[842][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[842][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[842][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[843][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[843][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[843][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[843][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[844][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[844][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[845][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[845][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[846][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[846][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[846][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[846][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[847][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[847][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[848][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[848][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[849][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[849][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[849][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[849][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[849][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[849][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[850][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[850][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[850][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[850][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[852][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[852][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[852][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[852][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[853][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[853][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[853][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[853][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[855][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[855][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[855][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[855][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[856][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[856][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[856][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[856][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[857][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[857][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[858][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[858][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[858][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[858][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[860][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[860][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[861][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[861][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[861][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[861][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[861][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[861][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[862][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[862][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[864][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[864][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[864][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[864][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[864][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[864][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[866][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[866][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[867][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[867][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[868][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[868][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[869][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[869][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[870][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[870][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[871][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[871][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[873][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[873][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[874][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[874][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[875][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[875][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[876][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[876][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[877][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[877][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[877][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[877][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[878][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[878][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[880][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[880][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[880][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[880][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[881][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[881][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[882][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[882][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[882][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[882][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[882][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[882][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[883][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[883][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[883][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[883][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[884][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[884][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[884][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[884][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[884][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[884][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[884][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[884][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[885][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[885][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[885][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[885][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[885][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[885][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[885][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[885][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[886][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[886][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[886][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[886][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[889][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[889][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[890][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[890][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[891][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[891][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[891][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[891][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[892][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[892][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[892][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[892][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[893][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[893][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[894][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[894][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[894][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[894][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[895][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[895][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[895][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[895][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[896][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[896][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[897][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[897][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[897][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[897][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[898][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[898][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[898][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[898][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[899][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[899][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[899][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[899][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[900][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[900][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[900][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[900][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[901][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[901][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[901][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[901][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[903][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[903][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[904][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[904][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[905][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[905][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[905][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[905][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[906][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[906][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[906][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[906][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[906][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[906][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[907][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[907][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[907][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[907][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[908][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[908][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[908][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[908][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[910][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[910][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[910][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[910][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[910][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[910][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[911][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[911][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[912][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[912][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[912][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[912][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[913][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[913][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[913][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[913][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[914][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[914][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[914][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[914][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[914][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[914][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[915][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[915][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[915][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[915][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[915][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[915][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[916][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[916][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[917][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[917][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[917][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[917][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[918][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[918][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[918][3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[918][3]~DUPLICATE ; ; ; +; cpu:cpu|vram[919][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[919][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[919][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[919][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[919][5] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[919][5]~DUPLICATE ; ; ; +; cpu:cpu|vram[919][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[919][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[920][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[920][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[921][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[921][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[922][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[922][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[922][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[922][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[923][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[923][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[924][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[924][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[925][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[925][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[927][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[927][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[928][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[928][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[928][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[928][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[929][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[929][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[929][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[929][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[929][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[929][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[930][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[930][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[930][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[930][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[931][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[931][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[932][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[932][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[932][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[932][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[933][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[933][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[935][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[935][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[935][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[935][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[936][3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[936][3]~DUPLICATE ; ; ; +; cpu:cpu|vram[937][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[937][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[938][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[938][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[938][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[938][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[939][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[939][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[940][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[940][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[940][3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[940][3]~DUPLICATE ; ; ; +; cpu:cpu|vram[940][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[940][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[940][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[940][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[941][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[941][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[941][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[941][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[942][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[942][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[942][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[942][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[943][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[943][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[944][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[944][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[944][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[944][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[945][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[945][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[945][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[945][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[946][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[946][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[946][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[946][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[946][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[946][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[947][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[947][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[947][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[947][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[947][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[947][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[948][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[948][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[948][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[948][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[949][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[949][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[949][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[949][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[950][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[950][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[950][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[950][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[950][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[950][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[951][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[951][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[951][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[951][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[952][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[952][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[955][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[955][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[955][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[955][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[956][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[956][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[957][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[957][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[957][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[957][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[958][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[958][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[959][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[959][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[959][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[959][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[959][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[959][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[960][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[960][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[960][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[960][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[961][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[961][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[962][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[962][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[962][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[962][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[963][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[963][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[963][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[963][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[964][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[964][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[965][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[965][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[965][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[965][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[965][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[965][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[966][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[966][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[966][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[966][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[967][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[967][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[968][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[968][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[968][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[968][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[969][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[969][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[969][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[969][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[969][5] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[969][5]~DUPLICATE ; ; ; +; cpu:cpu|vram[970][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[970][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[970][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[970][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[971][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[971][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[971][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[971][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[971][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[971][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[972][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[972][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[973][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[973][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[973][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[973][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[973][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[973][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[974][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[974][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[974][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[974][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[974][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[974][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[975][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[975][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[977][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[977][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[978][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[978][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[979][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[979][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[980][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[980][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[980][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[980][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[980][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[980][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[980][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[980][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[981][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[981][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[981][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[981][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[981][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[981][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[982][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[982][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[982][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[982][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[982][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[982][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[983][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[983][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[983][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[983][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[984][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[984][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[984][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[984][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[984][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[984][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[984][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[984][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[986][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[986][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[987][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[987][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[988][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[988][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[988][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[988][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[989][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[989][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[989][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[989][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[989][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[989][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[990][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[990][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[990][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[990][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[991][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[991][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[992][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[992][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[992][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[992][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[993][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[993][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[994][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[994][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[995][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[995][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[995][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[995][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[995][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[995][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[996][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[996][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[999][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[999][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[1001][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1001][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[1002][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1002][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[1003][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1003][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[1004][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1004][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[1004][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1004][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[1007][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1007][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[1007][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1007][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[1007][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1007][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[1008][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1008][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[1008][3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1008][3]~DUPLICATE ; ; ; +; cpu:cpu|vram[1008][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1008][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[1009][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1009][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[1009][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1009][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[1009][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1009][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[1010][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1010][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[1011][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1011][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[1011][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1011][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[1012][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1012][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[1012][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1012][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[1012][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1012][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[1012][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1012][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[1013][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1013][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[1014][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1014][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[1015][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1015][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[1015][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1015][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[1015][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1015][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[1016][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1016][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[1016][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1016][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[1016][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1016][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[1017][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1017][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[1018][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1018][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[1019][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1019][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[1019][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1019][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[1019][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1019][6]~DUPLICATE ; ; ; +; cpu:cpu|vram[1021][4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1021][4]~DUPLICATE ; ; ; +; cpu:cpu|vram[1022][2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1022][2]~DUPLICATE ; ; ; +; cpu:cpu|vram[1023][0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1023][0]~DUPLICATE ; ; ; +; cpu:cpu|vram[1023][6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; cpu:cpu|vram[1023][6]~DUPLICATE ; ; ; ++------------------------------------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+----------------------------------------------------------------+------------------+-----------------------+ + + ++--------------------------------------------------------------------------------------------+ +; Ignored Assignments ; ++--------------+----------------+--------------+------------+---------------+----------------+ +; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ; ++--------------+----------------+--------------+------------+---------------+----------------+ +; Location ; ; ; lcd_cs ; PIN_V12 ; QSF Assignment ; +; I/O Standard ; chip8 ; ; lcd_clock ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; chip8 ; ; lcd_cs ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; chip8 ; ; led ; 3.3-V LVTTL ; QSF Assignment ; ++--------------+----------------+--------------+------------+---------------+----------------+ + + ++----------------------------------------------------------------------------------------------------+ +; Incremental Compilation Preservation Summary ; ++---------------------+----------------------+----------------------------+--------------------------+ +; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ; ++---------------------+----------------------+----------------------------+--------------------------+ +; Placement (by node) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 25822 ) ; 0.00 % ( 0 / 25822 ) ; 0.00 % ( 0 / 25822 ) ; +; -- Achieved ; 0.00 % ( 0 / 25822 ) ; 0.00 % ( 0 / 25822 ) ; 0.00 % ( 0 / 25822 ) ; +; ; ; ; ; +; Routing (by net) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; +; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; ++---------------------+----------------------+----------------------------+--------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Partition Settings ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Placement Preservation ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Top ; 0.00 % ( 0 / 25822 ) ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; 0.00 % ( 0 / 0 ) ; N/A ; Source File ; N/A ; ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in /home/nickorlow/programming/school/warminster/yayacemu/output_files/chip8.pin. + + ++---------------------------------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++-------------------------------------------------------------+-----------------------+-------+ +; Resource ; Usage ; % ; ++-------------------------------------------------------------+-----------------------+-------+ +; Logic utilization (ALMs needed / total ALMs on device) ; 10,549 / 41,910 ; 25 % ; +; ALMs needed [=A-B+C] ; 10,549 ; ; +; [A] ALMs used in final placement [=a+b+c+d] ; 11,599 / 41,910 ; 28 % ; +; [a] ALMs used for LUT logic and registers ; 4,235 ; ; +; [b] ALMs used for LUT logic ; 7,235 ; ; +; [c] ALMs used for registers ; 129 ; ; +; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; ; +; [B] Estimate of ALMs recoverable by dense packing ; 1,192 / 41,910 ; 3 % ; +; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 142 / 41,910 ; < 1 % ; +; [a] Due to location constrained logic ; 0 ; ; +; [b] Due to LAB-wide signal conflicts ; 0 ; ; +; [c] Due to LAB input limits ; 142 ; ; +; [d] Due to virtual I/Os ; 0 ; ; +; ; ; ; +; Difficulty packing design ; Low ; ; +; ; ; ; +; Total LABs: partially or completely used ; 1,382 / 4,191 ; 33 % ; +; -- Logic LABs ; 1,382 ; ; +; -- Memory LABs (up to half of total LABs) ; 0 ; ; +; ; ; ; +; Combinational ALUT usage for logic ; 17,065 ; ; +; -- 7 input functions ; 58 ; ; +; -- 6 input functions ; 3,654 ; ; +; -- 5 input functions ; 5,900 ; ; +; -- 4 input functions ; 2,000 ; ; +; -- <=3 input functions ; 5,453 ; ; +; Combinational ALUT usage for route-throughs ; 106 ; ; +; ; ; ; +; Dedicated logic registers ; 10,004 ; ; +; -- By type: ; ; ; +; -- Primary logic registers ; 8,728 / 83,820 ; 10 % ; +; -- Secondary logic registers ; 1,276 / 83,820 ; 2 % ; +; -- By function: ; ; ; +; -- Design implementation registers ; 8,728 ; ; +; -- Routing optimization registers ; 1,276 ; ; +; ; ; ; +; Virtual pins ; 0 ; ; +; I/O pins ; 10 / 314 ; 3 % ; +; -- Clock pins ; 3 / 8 ; 38 % ; +; -- Dedicated input pins ; 0 / 21 ; 0 % ; +; ; ; ; +; Hard processor system peripheral utilization ; ; ; +; -- Boot from FPGA ; 0 / 1 ( 0 % ) ; ; +; -- Clock resets ; 0 / 1 ( 0 % ) ; ; +; -- Cross trigger ; 0 / 1 ( 0 % ) ; ; +; -- S2F AXI ; 0 / 1 ( 0 % ) ; ; +; -- F2S AXI ; 0 / 1 ( 0 % ) ; ; +; -- AXI Lightweight ; 0 / 1 ( 0 % ) ; ; +; -- SDRAM ; 0 / 1 ( 0 % ) ; ; +; -- Interrupts ; 0 / 1 ( 0 % ) ; ; +; -- JTAG ; 0 / 1 ( 0 % ) ; ; +; -- Loan I/O ; 0 / 1 ( 0 % ) ; ; +; -- MPU event standby ; 0 / 1 ( 0 % ) ; ; +; -- MPU general purpose ; 0 / 1 ( 0 % ) ; ; +; -- STM event ; 0 / 1 ( 0 % ) ; ; +; -- TPIU trace ; 0 / 1 ( 0 % ) ; ; +; -- DMA ; 0 / 1 ( 0 % ) ; ; +; -- CAN ; 0 / 2 ( 0 % ) ; ; +; -- EMAC ; 0 / 2 ( 0 % ) ; ; +; -- I2C ; 0 / 4 ( 0 % ) ; ; +; -- NAND Flash ; 0 / 1 ( 0 % ) ; ; +; -- QSPI ; 0 / 1 ( 0 % ) ; ; +; -- SDMMC ; 0 / 1 ( 0 % ) ; ; +; -- SPI Master ; 0 / 2 ( 0 % ) ; ; +; -- SPI Slave ; 0 / 2 ( 0 % ) ; ; +; -- UART ; 0 / 2 ( 0 % ) ; ; +; -- USB ; 0 / 2 ( 0 % ) ; ; +; ; ; ; +; M10K blocks ; 4 / 553 ; < 1 % ; +; Total MLAB memory bits ; 0 ; ; +; Total block memory bits ; 32,768 / 5,662,720 ; < 1 % ; +; Total block memory implementation bits ; 40,960 / 5,662,720 ; < 1 % ; +; ; ; ; +; Total DSP Blocks ; 0 / 112 ; 0 % ; +; ; ; ; +; Fractional PLLs ; 0 / 6 ; 0 % ; +; Global signals ; 1 ; ; +; -- Global clocks ; 1 / 16 ; 6 % ; +; -- Quadrant clocks ; 0 / 66 ; 0 % ; +; -- Horizontal periphery clocks ; 0 / 18 ; 0 % ; +; SERDES Transmitters ; 0 / 100 ; 0 % ; +; SERDES Receivers ; 0 / 100 ; 0 % ; +; JTAGs ; 0 / 1 ; 0 % ; +; ASMI blocks ; 0 / 1 ; 0 % ; +; CRC blocks ; 0 / 1 ; 0 % ; +; Remote update blocks ; 0 / 1 ; 0 % ; +; Oscillator blocks ; 0 / 1 ; 0 % ; +; Impedance control blocks ; 0 / 4 ; 0 % ; +; Hard Memory Controllers ; 0 / 1 ; 0 % ; +; Average interconnect usage (total/H/V) ; 14.5% / 14.3% / 14.9% ; ; +; Peak interconnect usage (total/H/V) ; 63.5% / 63.1% / 64.9% ; ; +; Maximum fan-out ; 9791 ; ; +; Highest non-global fan-out ; 9095 ; ; +; Total fan-out ; 106041 ; ; +; Average fan-out ; 3.90 ; ; ++-------------------------------------------------------------+-----------------------+-------+ + + ++-----------------------------------------------------------------------------------------------------------------------+ +; Fitter Partition Statistics ; ++-------------------------------------------------------------+------------------------+--------------------------------+ +; Statistic ; Top ; hard_block:auto_generated_inst ; ++-------------------------------------------------------------+------------------------+--------------------------------+ +; Logic utilization (ALMs needed / total ALMs on device) ; 10549 / 41910 ( 25 % ) ; 0 / 41910 ( 0 % ) ; +; ALMs needed [=A-B+C] ; 10549 ; 0 ; +; [A] ALMs used in final placement [=a+b+c+d] ; 11599 / 41910 ( 28 % ) ; 0 / 41910 ( 0 % ) ; +; [a] ALMs used for LUT logic and registers ; 4235 ; 0 ; +; [b] ALMs used for LUT logic ; 7235 ; 0 ; +; [c] ALMs used for registers ; 129 ; 0 ; +; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; 0 ; +; [B] Estimate of ALMs recoverable by dense packing ; 1192 / 41910 ( 3 % ) ; 0 / 41910 ( 0 % ) ; +; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 142 / 41910 ( < 1 % ) ; 0 / 41910 ( 0 % ) ; +; [a] Due to location constrained logic ; 0 ; 0 ; +; [b] Due to LAB-wide signal conflicts ; 0 ; 0 ; +; [c] Due to LAB input limits ; 142 ; 0 ; +; [d] Due to virtual I/Os ; 0 ; 0 ; +; ; ; ; +; Difficulty packing design ; Low ; Low ; +; ; ; ; +; Total LABs: partially or completely used ; 1382 / 4191 ( 33 % ) ; 0 / 4191 ( 0 % ) ; +; -- Logic LABs ; 1382 ; 0 ; +; -- Memory LABs (up to half of total LABs) ; 0 ; 0 ; +; ; ; ; +; Combinational ALUT usage for logic ; 17065 ; 0 ; +; -- 7 input functions ; 58 ; 0 ; +; -- 6 input functions ; 3654 ; 0 ; +; -- 5 input functions ; 5900 ; 0 ; +; -- 4 input functions ; 2000 ; 0 ; +; -- <=3 input functions ; 5453 ; 0 ; +; Combinational ALUT usage for route-throughs ; 106 ; 0 ; +; Memory ALUT usage ; 0 ; 0 ; +; -- 64-address deep ; 0 ; 0 ; +; -- 32-address deep ; 0 ; 0 ; +; ; ; ; +; Dedicated logic registers ; 0 ; 0 ; +; -- By type: ; ; ; +; -- Primary logic registers ; 8728 / 83820 ( 10 % ) ; 0 / 83820 ( 0 % ) ; +; -- Secondary logic registers ; 1276 / 83820 ( 2 % ) ; 0 / 83820 ( 0 % ) ; +; -- By function: ; ; ; +; -- Design implementation registers ; 8728 ; 0 ; +; -- Routing optimization registers ; 1276 ; 0 ; +; ; ; ; +; ; ; ; +; Virtual pins ; 0 ; 0 ; +; I/O pins ; 10 ; 0 ; +; I/O registers ; 0 ; 0 ; +; Total block memory bits ; 32768 ; 0 ; +; Total block memory implementation bits ; 40960 ; 0 ; +; M10K block ; 4 / 553 ( < 1 % ) ; 0 / 553 ( 0 % ) ; +; Clock enable block ; 1 / 116 ( < 1 % ) ; 0 / 116 ( 0 % ) ; +; ; ; ; +; Connections ; ; ; +; -- Input Connections ; 0 ; 0 ; +; -- Registered Input Connections ; 0 ; 0 ; +; -- Output Connections ; 0 ; 0 ; +; -- Registered Output Connections ; 0 ; 0 ; +; ; ; ; +; Internal Connections ; ; ; +; -- Total Connections ; 106154 ; 0 ; +; -- Registered Connections ; 24291 ; 0 ; +; ; ; ; +; External Connections ; ; ; +; -- Top ; 0 ; 0 ; +; -- hard_block:auto_generated_inst ; 0 ; 0 ; +; ; ; ; +; Partition Interface ; ; ; +; -- Input Ports ; 2 ; 0 ; +; -- Output Ports ; 8 ; 0 ; +; -- Bidir Ports ; 0 ; 0 ; +; ; ; ; +; Registered Ports ; ; ; +; -- Registered Input Ports ; 0 ; 0 ; +; -- Registered Output Ports ; 0 ; 0 ; +; ; ; ; +; Port Connectivity ; ; ; +; -- Input Ports driven by GND ; 0 ; 0 ; +; -- Output Ports driven by GND ; 0 ; 0 ; +; -- Input Ports driven by VCC ; 0 ; 0 ; +; -- Output Ports driven by VCC ; 0 ; 0 ; +; -- Input Ports with no Source ; 0 ; 0 ; +; -- Output Ports with no Source ; 0 ; 0 ; +; -- Input Ports with no Fanout ; 0 ; 0 ; +; -- Output Ports with no Fanout ; 0 ; 0 ; ++-------------------------------------------------------------+------------------------+--------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ; ++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+ +; fpga_clk ; V11 ; 3B ; 32 ; 0 ; 0 ; 9792 ; 0 ; yes ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; User ; no ; +; rst_in ; W20 ; 5B ; 89 ; 23 ; 20 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; User ; no ; ++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ; ++----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+ +; lcd_clk ; D8 ; 8A ; 38 ; 81 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; lcd_data ; W12 ; 3B ; 40 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; led[0] ; W15 ; 5A ; 89 ; 8 ; 20 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; led[1] ; AA24 ; 5A ; 89 ; 9 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; led[2] ; V16 ; 5A ; 89 ; 9 ; 3 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; led[3] ; V15 ; 5A ; 89 ; 9 ; 20 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; led[4] ; AF26 ; 5A ; 89 ; 4 ; 77 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; +; led[5] ; AE26 ; 5A ; 89 ; 4 ; 94 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; ++----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+ + + ++---------------------------------------------------------------------------+ +; I/O Bank Usage ; ++----------+-----------------+---------------+--------------+---------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ; ++----------+-----------------+---------------+--------------+---------------+ +; B2L ; 0 / 0 ( -- ) ; -- ; -- ; -- ; +; B1L ; 0 / 0 ( -- ) ; -- ; -- ; -- ; +; 3A ; 0 / 16 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 3B ; 2 / 32 ( 6 % ) ; 3.3V ; -- ; 3.3V ; +; 4A ; 0 / 68 ( 0 % ) ; 3.3V ; -- ; 3.3V ; +; 5A ; 6 / 16 ( 38 % ) ; 3.3V ; -- ; 3.3V ; +; 5B ; 1 / 7 ( 14 % ) ; 2.5V ; -- ; 2.5V ; +; 6B ; 0 / 44 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 6A ; 0 / 56 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 7A ; 0 / 19 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 7B ; 0 / 22 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 7C ; 0 / 12 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 7D ; 0 / 14 ( 0 % ) ; 2.5V ; -- ; 2.5V ; +; 8A ; 1 / 6 ( 17 % ) ; 2.5V ; -- ; 2.5V ; ++----------+-----------------+---------------+--------------+---------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+ +; A2 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; A3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A4 ; 435 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A5 ; 431 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A6 ; 425 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A7 ; 423 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A8 ; 421 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A9 ; 419 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A11 ; 417 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A12 ; 415 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A13 ; 413 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A14 ; 411 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A15 ; 409 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A16 ; 407 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A17 ; 399 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A18 ; 395 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A19 ; 393 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A20 ; 391 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A21 ; 389 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A22 ; 387 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A23 ; 374 ; 7A ; ^HPS_nRST ; ; ; ; -- ; ; -- ; -- ; +; A24 ; 361 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; A25 ; 359 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; A26 ; 357 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; A27 ; 353 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA4 ; 59 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA5 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AA6 ; 43 ; 3A ; ^nCSO, DATA4 ; ; ; ; Weak Pull Up ; ; -- ; On ; +; AA8 ; 50 ; 3A ; ^DCLK ; ; ; ; Weak Pull Up ; ; -- ; On ; +; AA9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA10 ; ; 3A ; VCCPD3A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AA11 ; 64 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA12 ; ; 3B ; VCCIO3B ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AA13 ; 144 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA14 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AA15 ; 160 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA16 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AA17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA18 ; 168 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA19 ; 170 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA20 ; 213 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA21 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AA23 ; 226 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA24 ; 224 ; 5A ; led[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AA25 ; ; 5B ; VREFB5BN0 ; power ; ; ; -- ; ; -- ; -- ; +; AA26 ; 255 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA27 ; 279 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA28 ; 289 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB4 ; 57 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB5 ; 46 ; 3A ; #TCK ; input ; ; ; -- ; ; -- ; -- ; +; AB6 ; 45 ; 3A ; ^AS_DATA3, DATA3 ; ; ; ; Weak Pull Up ; ; -- ; On ; +; AB23 ; 222 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB25 ; 259 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB26 ; 253 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB28 ; 277 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AC1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC4 ; 63 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC5 ; 47 ; 3A ; ^AS_DATA2, DATA2 ; ; ; ; Weak Pull Up ; ; -- ; On ; +; AC6 ; 49 ; 3A ; ^AS_DATA1, DATA1 ; ; ; ; Weak Pull Up ; ; -- ; On ; +; AC7 ; 44 ; 3A ; #TMS ; input ; ; ; -- ; ; -- ; -- ; +; AC8 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AC21 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AC22 ; 202 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC23 ; 200 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC24 ; 220 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AC25 ; ; 5A ; VCCIO5A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AC26 ; ; 5A ; VREFB5AN0 ; power ; ; ; -- ; ; -- ; -- ; +; AC27 ; 275 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AC28 ; 273 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AD1 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; AD2 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; AD3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AD4 ; 61 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD5 ; 67 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AD7 ; 51 ; 3A ; ^AS_DATA0, ASDO, DATA0 ; ; ; ; Weak Pull Up ; ; -- ; On ; +; AD8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AD9 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AD10 ; 103 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD11 ; 111 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD12 ; 125 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD13 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AD14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AD15 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AD16 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AD17 ; 159 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD18 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AD19 ; 165 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD20 ; 173 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD21 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AD22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AD23 ; 186 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD24 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ; +; AD25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AD26 ; 218 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AD27 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AD28 ; 263 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AE1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AE2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AE3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AE4 ; 102 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE5 ; ; 3A ; VREFB3AN0 ; power ; ; ; -- ; ; -- ; -- ; +; AE6 ; 65 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE7 ; 107 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE8 ; 110 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE9 ; 101 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE10 ; ; 3B ; VCCIO3B ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AE11 ; 109 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE12 ; 127 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE13 ; ; 3B ; VCCIO3B ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AE14 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; AE15 ; 141 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AE17 ; 157 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AE19 ; 167 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE20 ; 175 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE21 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AE22 ; 184 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE23 ; 197 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE24 ; 199 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE25 ; 216 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AE26 ; 214 ; 5A ; led[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AE27 ; 265 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AE28 ; 261 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AF1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AF2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AF3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AF4 ; 100 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF5 ; 115 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF6 ; 113 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF7 ; 118 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF8 ; 105 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF9 ; 108 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF10 ; 117 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF11 ; 119 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF12 ; ; 3B ; VREFB3BN0 ; power ; ; ; -- ; ; -- ; -- ; +; AF13 ; 133 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF14 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AF15 ; 143 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF16 ; ; 4A ; VREFB4AN0 ; power ; ; ; -- ; ; -- ; -- ; +; AF17 ; 151 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF18 ; 166 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF19 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AF20 ; 179 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF21 ; 181 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF22 ; 183 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF23 ; 189 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AF25 ; 207 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF26 ; 212 ; 5A ; led[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AF27 ; 211 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF28 ; 209 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AG2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AG3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AG4 ; ; 3B ; VCCIO3B ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AG5 ; 126 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG6 ; 116 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AG8 ; 134 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG9 ; 139 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG10 ; 142 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG11 ; 147 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG12 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AG13 ; 135 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG14 ; 155 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG15 ; 158 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG16 ; 149 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AG18 ; 171 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG19 ; 174 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG20 ; 177 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG21 ; 182 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG22 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AG23 ; 191 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG24 ; 195 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG25 ; 205 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG26 ; 198 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AG28 ; 206 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH2 ; 121 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH3 ; 123 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH4 ; 124 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH5 ; 129 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH6 ; 131 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH7 ; 132 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH8 ; 137 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH9 ; 140 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AH11 ; 145 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH12 ; 150 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH13 ; 153 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH14 ; 156 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH15 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AH16 ; 161 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH17 ; 163 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH18 ; 169 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH19 ; 172 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AH21 ; 185 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH22 ; 188 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH23 ; 190 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH24 ; 193 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH25 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AH26 ; 201 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH27 ; 204 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B1 ; ; ; GND ; ; ; ; -- ; ; -- ; -- ; +; B2 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; B3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B4 ; 437 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B6 ; 433 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B8 ; 439 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B9 ; 441 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B10 ; ; 7C ; VCCIO7C_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; B11 ; 440 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B12 ; 438 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B13 ; ; 7B ; VCCIO7B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; B14 ; 427 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B16 ; 402 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B18 ; 397 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B19 ; 403 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B21 ; 388 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B23 ; 376 ; 7A ; ^HPS_TDO ; ; ; ; -- ; ; -- ; -- ; +; B24 ; 363 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; B25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B26 ; 351 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; B27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B28 ; 343 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C4 ; 446 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C5 ; 453 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C6 ; 451 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C7 ; 449 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C8 ; 447 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C9 ; 445 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C10 ; 443 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C12 ; 460 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C13 ; 432 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C14 ; 426 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C15 ; 418 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C16 ; 404 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C17 ; 396 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C18 ; 394 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C19 ; 401 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C20 ; ; 7A ; VCCIO7A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; C21 ; 386 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C22 ; 380 ; 7A ; ^HPS_TRST ; ; ; ; -- ; ; -- ; -- ; +; C23 ; 378 ; 7A ; ^HPS_TMS ; ; ; ; -- ; ; -- ; -- ; +; C24 ; 367 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C25 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; C26 ; 349 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C27 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; C28 ; 341 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D1 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; D2 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; D3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D4 ; 448 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D5 ; 455 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D6 ; ; 7D ; VCCIO7D_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; D7 ; ; -- ; VCCBAT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; D8 ; 465 ; 8A ; lcd_clk ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; D9 ; ; 8A ; VREFB8AN0 ; power ; ; ; -- ; ; -- ; -- ; +; D10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D11 ; 476 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D12 ; 458 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D14 ; 430 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D15 ; 420 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D17 ; 410 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D18 ; ; 7A ; VCCIO7A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; D19 ; ; 7A, 7B, 7C, 7D ; VREFB7A7B7C7DN0_HPS ; power ; ; ; -- ; ; -- ; -- ; +; D20 ; 385 ; 7A ; ^HPS_CLK2 ; ; ; ; -- ; ; -- ; -- ; +; D21 ; 382 ; 7A ; ^GND ; ; ; ; -- ; ; -- ; -- ; +; D22 ; 381 ; 7A ; ^HPS_TDI ; ; ; ; -- ; ; -- ; -- ; +; D23 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; D24 ; 365 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D25 ; 371 ; 6A ; HPS_RZQ_0 ; ; ; ; -- ; ; no ; On ; +; D26 ; 347 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D27 ; 335 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D28 ; 333 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E4 ; 442 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E5 ; 454 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E6 ; 542 ; 9A ; ^nCE ; ; ; ; -- ; ; -- ; -- ; +; E7 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; E8 ; 463 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E10 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; E11 ; 474 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E12 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; E13 ; ; 7D ; VCCPD7D_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; E14 ; ; 7C ; VCCPD7C_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; E15 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; E16 ; 412 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E17 ; ; 7B ; VCCPD7B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; E18 ; 383 ; 7A ; ^HPS_PORSEL ; ; ; ; -- ; ; -- ; -- ; +; E19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E20 ; 384 ; 7A ; ^HPS_CLK1 ; ; ; ; -- ; ; -- ; -- ; +; E21 ; ; 7A ; VCCPD7A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; E22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E23 ; 373 ; 7A ; ^GND ; ; ; ; -- ; ; -- ; -- ; +; E24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E25 ; 369 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E26 ; 345 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E28 ; 337 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F4 ; 450 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F5 ; 444 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F6 ; 547 ; 9A ; ^GND ; ; ; ; -- ; ; -- ; -- ; +; F7 ; 545 ; 9A ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ; +; F8 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F21 ; ; -- ; VCC_AUX_SHARED ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F22 ; ; -- ; VCCRSTCLK_HPS ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ; +; F23 ; 372 ; 7A ; ^GND ; ; ; ; -- ; ; -- ; -- ; +; F24 ; 370 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F25 ; 362 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F26 ; 360 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F27 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F28 ; 327 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G4 ; 452 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G5 ; ; 7D ; VCCIO7D_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G6 ; 543 ; 9A ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ; +; G23 ; 368 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G24 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G25 ; 354 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G26 ; 331 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G27 ; 329 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G28 ; 325 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H1 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; H2 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; H3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H8 ; 541 ; 9A ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ; +; H9 ; 540 ; 9A ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ; +; H10 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ; +; H11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H12 ; 436 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H13 ; 434 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H14 ; ; 7B ; VCCIO7B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H16 ; 422 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H17 ; 400 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H19 ; 375 ; 7A ; ^HPS_nPOR ; ; ; ; -- ; ; -- ; -- ; +; H20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H21 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H23 ; ; -- ; VCCPLL_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H25 ; 352 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H26 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H28 ; 339 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; J1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J4 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; J5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J8 ; 539 ; 9A ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ; +; J9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J10 ; 538 ; 9A ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ; +; J11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; J12 ; 416 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J13 ; 414 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J14 ; 408 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J15 ; 406 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J16 ; 424 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J17 ; 398 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J18 ; 392 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J19 ; 377 ; 7A ; ^VCCRSTCLK_HPS ; ; ; ; -- ; ; -- ; -- ; +; J20 ; 346 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J21 ; 344 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J24 ; 336 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J25 ; 338 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J26 ; 330 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J27 ; 321 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J28 ; 319 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K5 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K9 ; 546 ; 9A ; ^MSEL4 ; ; ; ; -- ; ; -- ; -- ; +; K10 ; 544 ; 9A ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ; +; K11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; K14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K15 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; K16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K17 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; K18 ; 390 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; K19 ; 379 ; 7A ; ^HPS_TCK ; ; ; ; -- ; ; -- ; -- ; +; K20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K21 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K24 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K25 ; 322 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K26 ; 328 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K27 ; 323 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K28 ; 317 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L4 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; L5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; L12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; L15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L16 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; L17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L18 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; L19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L20 ; 366 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L21 ; 364 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L25 ; 320 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L26 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L28 ; 315 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M1 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; M2 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; M3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M4 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; M5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; M8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M9 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; M13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; M14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M15 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; M16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M17 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; M18 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; M19 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; M20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M21 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; M24 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; M25 ; 324 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M26 ; 312 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M27 ; 314 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M28 ; 313 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; N8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N9 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; N10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; N11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; N12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; N15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N16 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; N17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N18 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; N19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N20 ; 350 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N21 ; 348 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N24 ; 306 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N25 ; 304 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N26 ; 298 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N27 ; 296 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N28 ; 311 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P4 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; P12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; P14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; P15 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; P16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P17 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; P18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P19 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; P20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P21 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P24 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P26 ; 299 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P27 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P28 ; 309 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R4 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; R5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; R8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R9 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; R10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; R11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; R13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; R15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R16 ; 334 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R17 ; 332 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R18 ; 318 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R19 ; 316 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R20 ; 310 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R21 ; 308 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R24 ; 282 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R25 ; 288 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R26 ; 290 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R27 ; 297 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R28 ; 307 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T1 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; T2 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; T3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T4 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; T5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; T8 ; 56 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T9 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; T10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T11 ; 106 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T12 ; 120 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T13 ; 122 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T15 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; T16 ; 292 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T17 ; 294 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T18 ; 302 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T19 ; 300 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T20 ; 286 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T21 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T24 ; 280 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T25 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T26 ; 274 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T27 ; 283 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; T28 ; 305 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U4 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U8 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; U9 ; 58 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U10 ; 62 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U11 ; 104 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U13 ; 136 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U14 ; 138 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U15 ; 278 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U16 ; 276 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U18 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U19 ; 284 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U21 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; U24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U25 ; 272 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U26 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ; +; U27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U28 ; 303 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V10 ; 60 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V11 ; 114 ; 3B ; fpga_clk ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; V12 ; 130 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V13 ; 152 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V15 ; 227 ; 5A ; led[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; V16 ; 225 ; 5A ; led[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; V17 ; 270 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V18 ; 268 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V19 ; 266 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V20 ; 264 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V24 ; 269 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V25 ; 271 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V27 ; 295 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V28 ; 301 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W5 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; W8 ; 54 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W9 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; W10 ; 48 ; 3A ; #TDI ; input ; ; ; -- ; ; -- ; -- ; +; W11 ; 112 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W12 ; 128 ; 3B ; lcd_data ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; W13 ; ; 4A ; VCCIO4A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; W14 ; 154 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; W15 ; 223 ; 5A ; led[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; W16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W17 ; ; 5A ; VCCIO5A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; W18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W19 ; ; 5B ; VCCPD5B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; W20 ; 254 ; 5B ; rst_in ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; W21 ; 252 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W24 ; 258 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W25 ; ; 5B ; VCCIO5B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; W26 ; 287 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W27 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; W28 ; 293 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y1 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; Y2 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ; +; Y3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y4 ; 53 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y5 ; 55 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y8 ; 52 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y9 ; 42 ; 3A ; #TDO ; output ; ; ; -- ; ; -- ; -- ; +; Y10 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ; +; Y11 ; 66 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y13 ; 146 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y15 ; 162 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y16 ; 221 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y17 ; 217 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y18 ; 219 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y19 ; 215 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y21 ; ; 5A ; VCCPD5A ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; Y24 ; 256 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y26 ; 285 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y27 ; 281 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y28 ; 291 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; ++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++-------------------------------------------------+ +; I/O Assignment Warnings ; ++----------+--------------------------------------+ +; Pin Name ; Reason ; ++----------+--------------------------------------+ +; lcd_clk ; Incomplete set of assignments ; +; lcd_data ; Missing drive strength and slew rate ; +; led[0] ; Missing drive strength and slew rate ; +; led[1] ; Missing drive strength and slew rate ; +; led[2] ; Missing drive strength and slew rate ; +; led[3] ; Missing drive strength and slew rate ; +; led[4] ; Missing drive strength and slew rate ; +; led[5] ; Missing drive strength and slew rate ; +; rst_in ; Incomplete set of assignments ; +; fpga_clk ; Incomplete set of assignments ; ++----------+--------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++-------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-----------------------------------------------------------------------+----------------------+--------------+ +; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ; ++-------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-----------------------------------------------------------------------+----------------------+--------------+ +; |chip8 ; 10548.6 (0.5) ; 11599.5 (0.5) ; 1192.4 (0.0) ; 141.5 (0.0) ; 0.0 (0.0) ; 17065 (1) ; 10004 (0) ; 0 (0) ; 32768 ; 4 ; 0 ; 10 ; 0 ; |chip8 ; chip8 ; work ; +; |cpu:cpu| ; 10548.1 (6640.6) ; 11599.0 (7583.7) ; 1192.4 (997.1) ; 141.5 (54.0) ; 0.0 (0.0) ; 17064 (11448) ; 10004 (9778) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |chip8|cpu:cpu ; cpu ; work ; +; |st7920_serial_driver:gpu| ; 3907.5 (3877.7) ; 4015.3 (3982.5) ; 195.4 (192.4) ; 87.5 (87.5) ; 0.0 (0.0) ; 5616 (5570) ; 226 (161) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |chip8|cpu:cpu|st7920_serial_driver:gpu ; st7920_serial_driver ; work ; +; |commander:com| ; 29.8 (29.8) ; 32.8 (32.8) ; 3.0 (3.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 46 (46) ; 65 (65) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |chip8|cpu:cpu|st7920_serial_driver:gpu|commander:com ; commander ; work ; +; |memory:mem| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 32768 ; 4 ; 0 ; 0 ; 0 ; |chip8|memory:mem ; memory ; work ; +; |altsyncram:mem_rtl_0| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 32768 ; 4 ; 0 ; 0 ; 0 ; |chip8|memory:mem|altsyncram:mem_rtl_0 ; altsyncram ; work ; +; |altsyncram_dsq1:auto_generated| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 32768 ; 4 ; 0 ; 0 ; 0 ; |chip8|memory:mem|altsyncram:mem_rtl_0|altsyncram_dsq1:auto_generated ; altsyncram_dsq1 ; work ; ++-------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-----------------------------------------------------------------------+----------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++-------------------------------------------------------------------------------------------------------------------------+ +; Delay Chain Summary ; ++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+ +; Name ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5 ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ; ++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+ +; lcd_clk ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; lcd_data ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; led[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; led[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; led[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; led[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; led[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; led[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; +; rst_in ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; +; fpga_clk ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; ++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+ + + ++-------------------------------------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++-------------------------------------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++-------------------------------------------------+-------------------+---------+ +; rst_in ; ; ; +; fpga_clk ; ; ; +; - cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 0 ; 0 ; ++-------------------------------------------------+-------------------+---------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Control Signals ; ++------------------------------------------------------------------------+----------------------+---------+---------------------------+--------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++------------------------------------------------------------------------+----------------------+---------+---------------------------+--------+----------------------+------------------+---------------------------+ +; cpu:cpu|Decoder0~10 ; MLABCELL_X72_Y24_N39 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|Decoder0~11 ; LABCELL_X73_Y25_N57 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|Decoder0~12 ; LABCELL_X68_Y22_N30 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|Decoder0~13 ; MLABCELL_X72_Y24_N27 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|Decoder0~15 ; MLABCELL_X72_Y24_N6 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|Decoder0~17 ; MLABCELL_X72_Y24_N33 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|Decoder0~18 ; MLABCELL_X72_Y24_N3 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|Decoder0~19 ; MLABCELL_X72_Y24_N18 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|Decoder0~20 ; MLABCELL_X72_Y24_N15 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|Decoder0~21 ; MLABCELL_X72_Y24_N21 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|Decoder0~22 ; MLABCELL_X72_Y24_N54 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|Decoder0~23 ; MLABCELL_X72_Y24_N51 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|Decoder0~3 ; LABCELL_X66_Y22_N42 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|Decoder0~5 ; MLABCELL_X72_Y26_N57 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|Decoder0~7 ; LABCELL_X66_Y22_N33 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|Decoder0~9 ; MLABCELL_X72_Y24_N45 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|Equal17~1 ; LABCELL_X75_Y26_N51 ; 13 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|Equal19~0 ; LABCELL_X74_Y26_N48 ; 14 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|Equal20~0 ; LABCELL_X74_Y26_N45 ; 23 ; Sync. load ; no ; -- ; -- ; -- ; +; cpu:cpu|Equal23~0 ; LABCELL_X74_Y26_N51 ; 23 ; Sync. load ; no ; -- ; -- ; -- ; +; cpu:cpu|draw_state.r[4]~0 ; LABCELL_X51_Y22_N33 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|index_reg[11]~0 ; MLABCELL_X78_Y26_N3 ; 12 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|instr.dst_reg[3]~0 ; LABCELL_X77_Y28_N21 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|instr.src_byte[2]~2 ; MLABCELL_X72_Y25_N51 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|instr.src_byte[9]~1 ; MLABCELL_X72_Y25_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|instr.src_sprite_addr[0]~0 ; MLABCELL_X72_Y25_N45 ; 26 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|instr.src_sprite_idx[1]~0 ; MLABCELL_X72_Y26_N0 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|instr.src_sprite_y[0]~0 ; MLABCELL_X72_Y26_N45 ; 11 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|program_counter[1]~1 ; LABCELL_X75_Y26_N30 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|rd_memory_address[3]~1 ; MLABCELL_X72_Y26_N3 ; 12 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|registers[0][0]~3 ; MLABCELL_X78_Y28_N54 ; 12 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|registers[10][0]~15 ; MLABCELL_X78_Y28_N48 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|registers[11][0]~19 ; LABCELL_X81_Y28_N12 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|registers[12][0]~6 ; MLABCELL_X78_Y28_N24 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|registers[13][0]~12 ; MLABCELL_X78_Y28_N18 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|registers[14][0]~16 ; MLABCELL_X78_Y28_N0 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|registers[15][5]~0 ; LABCELL_X77_Y26_N45 ; 12 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|registers[15][5]~20 ; LABCELL_X29_Y27_N12 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|registers[1][0]~9 ; LABCELL_X81_Y28_N42 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|registers[2][0]~13 ; MLABCELL_X78_Y28_N30 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|registers[3][0]~17 ; LABCELL_X81_Y28_N9 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|registers[4][0]~4 ; MLABCELL_X78_Y28_N27 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|registers[5][0]~10 ; MLABCELL_X78_Y28_N3 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|registers[6][0]~14 ; MLABCELL_X78_Y28_N9 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|registers[7][0]~18 ; MLABCELL_X78_Y28_N33 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|registers[8][0]~5 ; MLABCELL_X78_Y28_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|registers[9][0]~11 ; LABCELL_X81_Y28_N36 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|st7920_serial_driver:gpu|always0~0 ; LABCELL_X77_Y27_N3 ; 44 ; Clock enable, Sync. clear ; no ; -- ; -- ; -- ; +; cpu:cpu|st7920_serial_driver:gpu|commander:com|full_command_bits[22]~1 ; LABCELL_X73_Y31_N36 ; 63 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|st7920_serial_driver:gpu|counter[8] ; FF_X75_Y27_N26 ; 11 ; Sync. clear ; no ; -- ; -- ; -- ; +; cpu:cpu|st7920_serial_driver:gpu|i[1]~2 ; LABCELL_X67_Y27_N48 ; 33 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; FF_X74_Y30_N59 ; 218 ; Clock ; no ; -- ; -- ; -- ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[23]~0 ; LABCELL_X70_Y26_N48 ; 57 ; Sync. clear ; no ; -- ; -- ; -- ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[23]~2 ; LABCELL_X67_Y27_N36 ; 50 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|st7920_serial_driver:gpu|start ; FF_X74_Y28_N14 ; 66 ; Sync. clear, Sync. load ; no ; -- ; -- ; -- ; +; cpu:cpu|st7920_serial_driver:gpu|y[0]~2 ; LABCELL_X70_Y27_N54 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|st7920_serial_driver:gpu|y[6]~0 ; LABCELL_X67_Y27_N45 ; 11 ; Sync. clear ; no ; -- ; -- ; -- ; +; cpu:cpu|vram[188][7]~2 ; LABCELL_X51_Y22_N48 ; 9095 ; Clock enable ; no ; -- ; -- ; -- ; +; cpu:cpu|vram[890][6]~1184 ; LABCELL_X61_Y22_N39 ; 293 ; Clock enable ; no ; -- ; -- ; -- ; +; fpga_clk ; PIN_V11 ; 2 ; Clock ; no ; -- ; -- ; -- ; +; fpga_clk ; PIN_V11 ; 9791 ; Clock ; yes ; Global Clock ; GCLK5 ; -- ; ++------------------------------------------------------------------------+----------------------+---------+---------------------------+--------+----------------------+------------------+---------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Global & Other Fast Signals ; ++----------+----------+---------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++----------+----------+---------+----------------------+------------------+---------------------------+ +; fpga_clk ; PIN_V11 ; 9791 ; Global Clock ; GCLK5 ; -- ; ++----------+----------+---------+----------------------+------------------+---------------------------+ + + ++-----------------------------------------------------------+ +; Non-Global High Fan-Out Signals ; ++-------------------------------------------------+---------+ +; Name ; Fan-Out ; ++-------------------------------------------------+---------+ +; cpu:cpu|vram[188][7]~2 ; 9095 ; +; cpu:cpu|Decoder11~0 ; 1024 ; +; cpu:cpu|Decoder11~1 ; 1024 ; +; cpu:cpu|Decoder11~2 ; 1024 ; +; cpu:cpu|Decoder11~3 ; 1024 ; +; cpu:cpu|st7920_serial_driver:gpu|i[0] ; 823 ; +; cpu:cpu|st7920_serial_driver:gpu|i[0]~DUPLICATE ; 636 ; +; cpu:cpu|Add11~1 ; 570 ; +; cpu:cpu|Add11~5 ; 570 ; ++-------------------------------------------------+---------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter RAM Summary ; ++---------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------------+-------+---------------------------------------+--------------------------------------------------------------------+----------------------+-----------------+-----------------+----------+------------------------+-----------------------+ +; Name ; Type ; Mode ; Clock Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M10K blocks ; MLABs ; MIF ; Location ; Mixed Width RDW Mode ; Port A RDW Mode ; Port B RDW Mode ; ECC Mode ; ECC Pipeline Registers ; Fits in MLABs ; ++---------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------------+-------+---------------------------------------+--------------------------------------------------------------------+----------------------+-----------------+-----------------+----------+------------------------+-----------------------+ +; memory:mem|altsyncram:mem_rtl_0|altsyncram_dsq1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 4096 ; 8 ; 4096 ; 8 ; yes ; no ; yes ; no ; 32768 ; 4096 ; 8 ; 4096 ; 8 ; 32768 ; 4 ; 0 ; db/chip8.ram0_memory_e9e85012.hdl.mif ; M10K_X69_Y24_N0, M10K_X69_Y25_N0, M10K_X69_Y23_N0, M10K_X69_Y22_N0 ; Old data ; New data ; New data ; Off ; No ; No - Address Too Wide ; ++---------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------------+-------+---------------------------------------+--------------------------------------------------------------------+----------------------+-----------------+-----------------+----------+------------------------+-----------------------+ +Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section. + + ++-------------------------------------------------------------------------+ +; Routing Usage Summary ; ++---------------------------------------------+---------------------------+ +; Routing Resource Type ; Usage ; ++---------------------------------------------+---------------------------+ +; Block interconnects ; 38,285 / 289,320 ( 13 % ) ; +; C12 interconnects ; 1,962 / 13,420 ( 15 % ) ; +; C2 interconnects ; 14,750 / 119,108 ( 12 % ) ; +; C4 interconnects ; 8,316 / 56,300 ( 15 % ) ; +; DQS bus muxes ; 0 / 25 ( 0 % ) ; +; DQS-18 I/O buses ; 0 / 25 ( 0 % ) ; +; DQS-9 I/O buses ; 0 / 25 ( 0 % ) ; +; Direct links ; 2,082 / 289,320 ( < 1 % ) ; +; Global clocks ; 1 / 16 ( 6 % ) ; +; HPS SDRAM PLL inputs ; 0 / 1 ( 0 % ) ; +; HPS SDRAM PLL outputs ; 0 / 1 ( 0 % ) ; +; HPS_INTERFACE_BOOT_FROM_FPGA_INPUTs ; 0 / 9 ( 0 % ) ; +; HPS_INTERFACE_CLOCKS_RESETS_INPUTs ; 0 / 7 ( 0 % ) ; +; HPS_INTERFACE_CLOCKS_RESETS_OUTPUTs ; 0 / 6 ( 0 % ) ; +; HPS_INTERFACE_CROSS_TRIGGER_INPUTs ; 0 / 18 ( 0 % ) ; +; HPS_INTERFACE_CROSS_TRIGGER_OUTPUTs ; 0 / 24 ( 0 % ) ; +; HPS_INTERFACE_DBG_APB_INPUTs ; 0 / 37 ( 0 % ) ; +; HPS_INTERFACE_DBG_APB_OUTPUTs ; 0 / 55 ( 0 % ) ; +; HPS_INTERFACE_DMA_INPUTs ; 0 / 16 ( 0 % ) ; +; HPS_INTERFACE_DMA_OUTPUTs ; 0 / 8 ( 0 % ) ; +; HPS_INTERFACE_FPGA2HPS_INPUTs ; 0 / 287 ( 0 % ) ; +; HPS_INTERFACE_FPGA2HPS_OUTPUTs ; 0 / 154 ( 0 % ) ; +; HPS_INTERFACE_FPGA2SDRAM_INPUTs ; 0 / 852 ( 0 % ) ; +; HPS_INTERFACE_FPGA2SDRAM_OUTPUTs ; 0 / 408 ( 0 % ) ; +; HPS_INTERFACE_HPS2FPGA_INPUTs ; 0 / 165 ( 0 % ) ; +; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_INPUTs ; 0 / 67 ( 0 % ) ; +; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_OUTPUTs ; 0 / 156 ( 0 % ) ; +; HPS_INTERFACE_HPS2FPGA_OUTPUTs ; 0 / 282 ( 0 % ) ; +; HPS_INTERFACE_INTERRUPTS_INPUTs ; 0 / 64 ( 0 % ) ; +; HPS_INTERFACE_INTERRUPTS_OUTPUTs ; 0 / 42 ( 0 % ) ; +; HPS_INTERFACE_JTAG_OUTPUTs ; 0 / 5 ( 0 % ) ; +; HPS_INTERFACE_LOAN_IO_INPUTs ; 0 / 142 ( 0 % ) ; +; HPS_INTERFACE_LOAN_IO_OUTPUTs ; 0 / 85 ( 0 % ) ; +; HPS_INTERFACE_MPU_EVENT_STANDBY_INPUTs ; 0 / 1 ( 0 % ) ; +; HPS_INTERFACE_MPU_EVENT_STANDBY_OUTPUTs ; 0 / 5 ( 0 % ) ; +; HPS_INTERFACE_MPU_GENERAL_PURPOSE_INPUTs ; 0 / 32 ( 0 % ) ; +; HPS_INTERFACE_MPU_GENERAL_PURPOSE_OUTPUTs ; 0 / 32 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_CAN_INPUTs ; 0 / 2 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_CAN_OUTPUTs ; 0 / 2 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_EMAC_INPUTs ; 0 / 32 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_EMAC_OUTPUTs ; 0 / 34 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_I2C_INPUTs ; 0 / 8 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_I2C_OUTPUTs ; 0 / 8 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_NAND_INPUTs ; 0 / 12 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_NAND_OUTPUTs ; 0 / 18 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_QSPI_INPUTs ; 0 / 4 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_QSPI_OUTPUTs ; 0 / 13 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_SDMMC_INPUTs ; 0 / 13 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_SDMMC_OUTPUTs ; 0 / 22 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_INPUTs ; 0 / 4 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_OUTPUTs ; 0 / 14 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_INPUTs ; 0 / 6 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_OUTPUTs ; 0 / 4 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_UART_INPUTs ; 0 / 10 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_UART_OUTPUTs ; 0 / 10 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_USB_INPUTs ; 0 / 22 ( 0 % ) ; +; HPS_INTERFACE_PERIPHERAL_USB_OUTPUTs ; 0 / 34 ( 0 % ) ; +; HPS_INTERFACE_STM_EVENT_INPUTs ; 0 / 28 ( 0 % ) ; +; HPS_INTERFACE_TEST_INPUTs ; 0 / 610 ( 0 % ) ; +; HPS_INTERFACE_TEST_OUTPUTs ; 0 / 513 ( 0 % ) ; +; HPS_INTERFACE_TPIU_TRACE_INPUTs ; 0 / 2 ( 0 % ) ; +; HPS_INTERFACE_TPIU_TRACE_OUTPUTs ; 0 / 33 ( 0 % ) ; +; Horizontal periphery clocks ; 0 / 72 ( 0 % ) ; +; Local interconnects ; 8,860 / 84,580 ( 10 % ) ; +; Quadrant clocks ; 0 / 66 ( 0 % ) ; +; R14 interconnects ; 2,626 / 12,676 ( 21 % ) ; +; R14/C12 interconnect drivers ; 4,060 / 20,720 ( 20 % ) ; +; R3 interconnects ; 17,868 / 130,992 ( 14 % ) ; +; R6 interconnects ; 32,054 / 266,960 ( 12 % ) ; +; Spine clocks ; 9 / 360 ( 3 % ) ; +; Wire stub REs ; 0 / 15,858 ( 0 % ) ; ++---------------------------------------------+---------------------------+ + + ++------------------------------------------+ +; I/O Rules Summary ; ++----------------------------------+-------+ +; I/O Rules Statistic ; Total ; ++----------------------------------+-------+ +; Total I/O Rules ; 28 ; +; Number of I/O Rules Passed ; 9 ; +; Number of I/O Rules Failed ; 0 ; +; Number of I/O Rules Unchecked ; 0 ; +; Number of I/O Rules Inapplicable ; 19 ; ++----------------------------------+-------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Details ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ; +; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ; +; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ; +; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ; +; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ; +; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; No Clamping Diode assignments found. ; I/O ; ; +; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Inapplicable ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; No Clamping Diode assignments found. ; I/O ; ; +; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 0 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ; +; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Matrix ; ++--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+ +; Pin/Rules ; IO_000002 ; IO_000001 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000047 ; IO_000046 ; IO_000045 ; IO_000027 ; IO_000026 ; IO_000024 ; IO_000023 ; IO_000022 ; IO_000021 ; IO_000020 ; IO_000019 ; IO_000018 ; IO_000015 ; IO_000014 ; IO_000013 ; IO_000012 ; IO_000011 ; IO_000010 ; IO_000009 ; IO_000034 ; ++--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+ +; Total Pass ; 0 ; 10 ; 10 ; 0 ; 0 ; 10 ; 10 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 10 ; 10 ; 0 ; +; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; Total Inapplicable ; 10 ; 0 ; 0 ; 10 ; 10 ; 0 ; 0 ; 10 ; 10 ; 10 ; 10 ; 10 ; 10 ; 9 ; 10 ; 10 ; 10 ; 10 ; 9 ; 10 ; 10 ; 10 ; 10 ; 9 ; 10 ; 0 ; 0 ; 10 ; +; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; lcd_clk ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; lcd_data ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; led[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; led[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; led[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; led[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; led[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; led[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; rst_in ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; +; fpga_clk ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; ++--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+ + + ++------------------------------------------------------------------------------------------------+ +; Fitter Device Options ; ++------------------------------------------------------------------+-----------------------------+ +; Option ; Setting ; ++------------------------------------------------------------------+-----------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Passive Serial ; +; Enable Error Detection CRC_ERROR pin ; Off ; +; Enable CvP_CONFDONE pin ; Off ; +; Enable open drain on CRC_ERROR pin ; On ; +; Enable open drain on CvP_CONFDONE pin ; On ; +; Enable open drain on INIT_DONE pin ; On ; +; Enable open drain on Partial Reconfiguration pins ; Off ; +; Enable open drain on nCEO pin ; On ; +; Enable Partial Reconfiguration pins ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; +; Enable internal scrubbing ; Off ; +; Active Serial clock source ; 100 MHz Internal Oscillator ; +; Device initialization clock source ; Internal Oscillator ; +; Configuration via Protocol ; Off ; +; Configuration Voltage Level ; Auto ; +; Force Configuration Voltage Level ; Off ; +; Enable nCEO output ; Off ; +; Data[15..8] ; Unreserved ; +; Data[7..5] ; Unreserved ; +; Base pin-out file on sameframe device ; Off ; ++------------------------------------------------------------------+-----------------------------+ + + ++------------------------------------+ +; Operating Settings and Conditions ; ++---------------------------+--------+ +; Setting ; Value ; ++---------------------------+--------+ +; Nominal Core Voltage ; 1.10 V ; +; Low Junction Temperature ; -40 °C ; +; High Junction Temperature ; 100 °C ; ++---------------------------+--------+ + + ++---------------------------------------------------------------------------------------------------------+ +; Estimated Delay Added for Hold Timing Summary ; ++------------------------------------------+------------------------------------------+-------------------+ +; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ; ++------------------------------------------+------------------------------------------+-------------------+ +; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 124.3 ; +; fpga_clk ; fpga_clk ; 57.4 ; +; fpga_clk ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 29.5 ; ++------------------------------------------+------------------------------------------+-------------------+ +Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off. +This will disable optimization of problematic paths and expose them for further analysis using the Timing Analyzer. + + ++--------------------------------------------------------------------------------------------------------------+ +; Estimated Delay Added for Hold Timing Details ; ++-----------------------------------------------+------------------------------------------+-------------------+ +; Source Register ; Destination Register ; Delay Added in ns ; ++-----------------------------------------------+------------------------------------------+-------------------+ +; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 7.432 ; +; cpu:cpu|st7920_serial_driver:gpu|counter[8] ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 3.716 ; +; cpu:cpu|st7920_serial_driver:gpu|x[3] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.655 ; +; cpu:cpu|st7920_serial_driver:gpu|x[2] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.653 ; +; cpu:cpu|st7920_serial_driver:gpu|i[2] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.622 ; +; cpu:cpu|st7920_serial_driver:gpu|x[4] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.584 ; +; cpu:cpu|st7920_serial_driver:gpu|x[0] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.504 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[30] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.374 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[29] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.374 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[27] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.374 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[23] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.374 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[6] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.374 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[4] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.374 ; +; cpu:cpu|st7920_serial_driver:gpu|i[31] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.363 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[12] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.343 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[11] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.343 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[10] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.343 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[9] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.343 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[8] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.343 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[7] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.343 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[28] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.323 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[26] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.323 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[25] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.323 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[24] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.323 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[14] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.323 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[13] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.323 ; +; cpu:cpu|st7920_serial_driver:gpu|c[31] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.280 ; +; cpu:cpu|st7920_serial_driver:gpu|i[20] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.241 ; +; cpu:cpu|st7920_serial_driver:gpu|i[17] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.213 ; +; cpu:cpu|st7920_serial_driver:gpu|i[18] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.213 ; +; cpu:cpu|st7920_serial_driver:gpu|i[19] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.213 ; +; cpu:cpu|st7920_serial_driver:gpu|i[21] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.213 ; +; cpu:cpu|st7920_serial_driver:gpu|i[22] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.213 ; +; cpu:cpu|st7920_serial_driver:gpu|i[23] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.185 ; +; cpu:cpu|st7920_serial_driver:gpu|i[24] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.185 ; +; cpu:cpu|st7920_serial_driver:gpu|i[25] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.185 ; +; cpu:cpu|st7920_serial_driver:gpu|i[26] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.185 ; +; cpu:cpu|st7920_serial_driver:gpu|i[27] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.185 ; +; cpu:cpu|st7920_serial_driver:gpu|i[28] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.185 ; +; cpu:cpu|st7920_serial_driver:gpu|c[29] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.160 ; +; cpu:cpu|st7920_serial_driver:gpu|c[28] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.160 ; +; cpu:cpu|st7920_serial_driver:gpu|c[27] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.160 ; +; cpu:cpu|st7920_serial_driver:gpu|c[30] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.160 ; +; cpu:cpu|st7920_serial_driver:gpu|c[25] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.160 ; +; cpu:cpu|st7920_serial_driver:gpu|c[24] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.160 ; +; cpu:cpu|st7920_serial_driver:gpu|c[23] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.160 ; +; cpu:cpu|st7920_serial_driver:gpu|c[22] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.160 ; +; cpu:cpu|st7920_serial_driver:gpu|c[21] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.160 ; +; cpu:cpu|st7920_serial_driver:gpu|c[20] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.160 ; +; cpu:cpu|st7920_serial_driver:gpu|c[19] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.160 ; +; cpu:cpu|st7920_serial_driver:gpu|c[18] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.160 ; +; cpu:cpu|st7920_serial_driver:gpu|c[17] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.160 ; +; cpu:cpu|st7920_serial_driver:gpu|c[16] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.160 ; +; cpu:cpu|st7920_serial_driver:gpu|c[15] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.160 ; +; cpu:cpu|st7920_serial_driver:gpu|c[14] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.160 ; +; cpu:cpu|st7920_serial_driver:gpu|c[13] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.160 ; +; cpu:cpu|st7920_serial_driver:gpu|c[12] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.160 ; +; cpu:cpu|st7920_serial_driver:gpu|c[11] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.160 ; +; cpu:cpu|st7920_serial_driver:gpu|c[10] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.160 ; +; cpu:cpu|st7920_serial_driver:gpu|c[9] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.160 ; +; cpu:cpu|st7920_serial_driver:gpu|c[8] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.160 ; +; cpu:cpu|st7920_serial_driver:gpu|c[7] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.160 ; +; cpu:cpu|st7920_serial_driver:gpu|c[6] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.160 ; +; cpu:cpu|st7920_serial_driver:gpu|c[5] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.160 ; +; cpu:cpu|st7920_serial_driver:gpu|c[4] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.160 ; +; cpu:cpu|st7920_serial_driver:gpu|c[3] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.160 ; +; cpu:cpu|st7920_serial_driver:gpu|c[26] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.160 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[16] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.153 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[15] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.153 ; +; cpu:cpu|st7920_serial_driver:gpu|i[1] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.089 ; +; cpu:cpu|st7920_serial_driver:gpu|i[11] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.089 ; +; cpu:cpu|st7920_serial_driver:gpu|i[12] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.089 ; +; cpu:cpu|st7920_serial_driver:gpu|i[13] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.089 ; +; cpu:cpu|st7920_serial_driver:gpu|i[14] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.089 ; +; cpu:cpu|st7920_serial_driver:gpu|i[15] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.089 ; +; cpu:cpu|st7920_serial_driver:gpu|i[16] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.089 ; +; cpu:cpu|st7920_serial_driver:gpu|i[5] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.089 ; +; cpu:cpu|st7920_serial_driver:gpu|i[6] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.089 ; +; cpu:cpu|st7920_serial_driver:gpu|i[7] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.089 ; +; cpu:cpu|st7920_serial_driver:gpu|i[8] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.089 ; +; cpu:cpu|st7920_serial_driver:gpu|i[9] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.089 ; +; cpu:cpu|st7920_serial_driver:gpu|i[10] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.089 ; +; cpu:cpu|st7920_serial_driver:gpu|i[3] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.089 ; +; cpu:cpu|st7920_serial_driver:gpu|i[4] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.089 ; +; cpu:cpu|st7920_serial_driver:gpu|i[29] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.089 ; +; cpu:cpu|st7920_serial_driver:gpu|i[30] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.089 ; +; cpu:cpu|st7920_serial_driver:gpu|i[0] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 2.089 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[22] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 1.999 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[21] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 1.999 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[20] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 1.999 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[19] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 1.999 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[18] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 1.999 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[17] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 1.999 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[31] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 1.999 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[5] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 1.999 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[3] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 1.999 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[2] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 1.999 ; +; cpu:cpu|st7920_serial_driver:gpu|line_cnt[1] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 1.999 ; +; cpu:cpu|st7920_serial_driver:gpu|x[1] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 1.999 ; +; cpu:cpu|st7920_serial_driver:gpu|y[5] ; cpu:cpu|st7920_serial_driver:gpu|x[3] ; 1.999 ; ++-----------------------------------------------+------------------------------------------+-------------------+ +Note: This table only shows the top 100 path(s) that have the largest delay added for hold. + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 12 of the 12 processors detected +Info (119006): Selected device 5CSEBA6U23I7 for design "chip8" +Info (21077): Low junction temperature is -40 degrees C +Info (21077): High junction temperature is 100 degrees C +Warning (18550): Found RAM instances implemented as ROM because the write logic is disabled. One instance is listed below as an example. + Info (119043): Atom "memory:mem|altsyncram:mem_rtl_0|altsyncram_dsq1:auto_generated|ram_block1a4" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled +Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. +Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details +Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements. +Info (184020): Starting Fitter periphery placement operations +Info (11191): Automatically promoted 1 clock (1 global) + Info (11162): fpga_clk~inputCLKENA0 with 8563 fanout uses global clock CLKCTRL_G5 +Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00 +Info (176233): Starting register packing +Critical Warning (332012): Synopsys Design Constraints File file not found: 'chip8.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332144): No user constrained base clocks found in the design +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. +Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time. +Info (176235): Finished register packing + Extra Info (176219): No registers were packed into other blocks +Warning (15705): Ignored locations or region assignments to the following nodes + Warning (15706): Node "lcd_cs" is assigned to location or region, but does not exist in design +Info (11798): Fitter preparation operations ending: elapsed time is 00:00:13 +Info (170189): Fitter placement preparation operations beginning +Info (14951): The Fitter is using Advanced Physical Optimization. +Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:52 +Info (170191): Fitter placement operations beginning +Info (170137): Fitter placement was successful +Info (170192): Fitter placement operations ending: elapsed time is 00:00:24 +Info (170193): Fitter routing operations beginning +Info (170195): Router estimated average interconnect usage is 12% of the available device resources + Info (170196): Router estimated peak interconnect usage is 57% of the available device resources in the region that extends from location X22_Y23 to location X32_Y34 +Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info (170201): Optimizations that may affect the design's routability were skipped +Info (170194): Fitter routing operations ending: elapsed time is 00:03:08 +Info (11888): Total time spent on timing analysis during the Fitter is 49.90 seconds. +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:29 +Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. +Info (144001): Generated suppressed messages file /home/nickorlow/programming/school/warminster/yayacemu/output_files/chip8.fit.smsg +Info: Quartus Prime Fitter was successful. 0 errors, 8 warnings + Info: Peak virtual memory: 2797 megabytes + Info: Processing ended: Sun Apr 7 23:52:09 2024 + Info: Elapsed time: 00:06:15 + Info: Total CPU time (on all processors): 00:14:19 + + ++----------------------------+ +; Fitter Suppressed Messages ; ++----------------------------+ +The suppressed messages can be found in /home/nickorlow/programming/school/warminster/yayacemu/output_files/chip8.fit.smsg. + + diff --git a/output_files/chip8.fit.smsg b/output_files/chip8.fit.smsg new file mode 100644 index 0000000..9302919 --- /dev/null +++ b/output_files/chip8.fit.smsg @@ -0,0 +1,6 @@ +Extra Info (176236): Started Fast Input/Output/OE register processing +Extra Info (176237): Finished Fast Input/Output/OE register processing +Extra Info (176238): Start inferring scan chains for DSP blocks +Extra Info (176239): Inferring scan chains for DSP blocks is complete +Extra Info (176246): Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density +Extra Info (176247): Finished moving registers into I/O cells, DSP blocks, and RAM blocks diff --git a/output_files/chip8.fit.summary b/output_files/chip8.fit.summary new file mode 100644 index 0000000..2da5d4b --- /dev/null +++ b/output_files/chip8.fit.summary @@ -0,0 +1,20 @@ +Fitter Status : Successful - Sun Apr 7 23:52:05 2024 +Quartus Prime Version : 23.1std.0 Build 991 11/28/2023 SC Lite Edition +Revision Name : chip8 +Top-level Entity Name : chip8 +Family : Cyclone V +Device : 5CSEBA6U23I7 +Timing Models : Final +Logic utilization (in ALMs) : 10,549 / 41,910 ( 25 % ) +Total registers : 10004 +Total pins : 10 / 314 ( 3 % ) +Total virtual pins : 0 +Total block memory bits : 32,768 / 5,662,720 ( < 1 % ) +Total RAM Blocks : 4 / 553 ( < 1 % ) +Total DSP Blocks : 0 / 112 ( 0 % ) +Total HSSI RX PCSs : 0 +Total HSSI PMA RX Deserializers : 0 +Total HSSI TX PCSs : 0 +Total HSSI PMA TX Serializers : 0 +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 4 ( 0 % ) diff --git a/output_files/chip8.jdi b/output_files/chip8.jdi new file mode 100644 index 0000000..afc91b2 --- /dev/null +++ b/output_files/chip8.jdi @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/output_files/chip8.pin b/output_files/chip8.pin new file mode 100644 index 0000000..7104ee7 --- /dev/null +++ b/output_files/chip8.pin @@ -0,0 +1,753 @@ + -- Copyright (C) 2023 Intel Corporation. All rights reserved. + -- Your use of Intel Corporation's design tools, logic functions + -- and other software and tools, and any partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Intel Program License + -- Subscription Agreement, the Intel Quartus Prime License Agreement, + -- the Intel FPGA IP License Agreement, or other applicable license + -- agreement, including, without limitation, that your use is for + -- the sole purpose of programming logic devices manufactured by + -- Intel and sold by Intel or its authorized distributors. Please + -- refer to the applicable agreement for further details, at + -- https://fpgasoftware.intel.com/eula. + -- + -- This is a Quartus Prime output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus Prime input file. This file cannot be used + -- to make Quartus Prime pin assignments - for instructions on how to make pin + -- assignments, please see Quartus Prime help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCPGM : Dedicated power pin for configuration, which MUST be connected to 1.8V, 2.5V, 3.0V or 3.3V depending on the requirements of the configuration device. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.1V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 3A: 2.5V + -- Bank 3B: 3.3V + -- Bank 4A: 3.3V + -- Bank 5A: 3.3V + -- Bank 5B: 2.5V + -- Bank 6B: 2.5V + -- Bank 6A: 2.5V + -- Bank 7A: 2.5V + -- Bank 7B: 2.5V + -- Bank 7C: 2.5V + -- Bank 7D: 2.5V + -- Bank 8A: 2.5V + -- Bank 9A: Dedicated configuration pins only, no VCCIO required. + -- RREF : External reference resistor for the quad, MUST be connected to + -- GND via a 2k Ohm resistor. + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + -- GXB_NC : Unused GXB Transmitter or dedicated clock output pin. This pin + -- must not be connected. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus Prime Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition +CHIP "chip8" ASSIGNED TO AN: 5CSEBA6U23I7 + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +DNU : A2 : : : : : +GND : A3 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 7C : +RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : : : : 7C : +RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 7B : +RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 7B : +RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 7B : +RESERVED_INPUT_WITH_WEAK_PULLUP : A9 : : : : 7B : +GND : A10 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 7B : +RESERVED_INPUT_WITH_WEAK_PULLUP : A12 : : : : 7B : +RESERVED_INPUT_WITH_WEAK_PULLUP : A13 : : : : 7B : +RESERVED_INPUT_WITH_WEAK_PULLUP : A14 : : : : 7B : +RESERVED_INPUT_WITH_WEAK_PULLUP : A15 : : : : 7B : +RESERVED_INPUT_WITH_WEAK_PULLUP : A16 : : : : 7B : +RESERVED_INPUT_WITH_WEAK_PULLUP : A17 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : A18 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : A20 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : A21 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : A22 : : : : 7A : +HPS_nRST : A23 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : A24 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : A25 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : A26 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : A27 : : : : 6A : +GND : AA1 : gnd : : : : +GND : AA2 : gnd : : : : +GND : AA3 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA4 : : : : 3A : +VCCIO3A : AA5 : power : : 2.5V : 3A : +nCSO, DATA4 : AA6 : : : : 3A : +DCLK : AA8 : : : : 3A : +GND : AA9 : gnd : : : : +VCCPD3A : AA10 : power : : 2.5V : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA11 : : : : 3A : +VCCIO3B : AA12 : power : : 3.3V : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA13 : : : : 4A : +VCCPD3B4A : AA14 : power : : 3.3V : 3B, 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA15 : : : : 4A : +VCCIO4A : AA16 : power : : 3.3V : 4A : +GND : AA17 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA18 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA19 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA20 : : : : 5A : +VCCA_FPLL : AA21 : power : : 2.5V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA23 : : : : 5A : +led[1] : AA24 : output : 3.3-V LVTTL : : 5A : Y +VREFB5BN0 : AA25 : power : : : 5B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA26 : : : : 5B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA27 : : : : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA28 : : : : 6B : +GND : AB1 : gnd : : : : +GND : AB2 : gnd : : : : +GND : AB3 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB4 : : : : 3A : +TCK : AB5 : input : : : 3A : +AS_DATA3, DATA3 : AB6 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB23 : : : : 5A : +GND : AB24 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB25 : : : : 5B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB26 : : : : 5B : +GND : AB27 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB28 : : : : 6B : +GND : AC1 : gnd : : : : +GND : AC2 : gnd : : : : +GND : AC3 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC4 : : : : 3A : +AS_DATA2, DATA2 : AC5 : : : : 3A : +AS_DATA1, DATA1 : AC6 : : : : 3A : +TMS : AC7 : input : : : 3A : +VCC_AUX : AC8 : power : : 2.5V : : +VCC_AUX : AC21 : power : : 2.5V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC22 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC23 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC24 : : : : 5A : +VCCIO5A : AC25 : power : : 3.3V : 5A : +VREFB5AN0 : AC26 : power : : : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC27 : : : : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC28 : : : : 6B : +DNU : AD1 : : : : : +DNU : AD2 : : : : : +GND : AD3 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD4 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD5 : : : : 3A : +GND : AD6 : gnd : : : : +AS_DATA0, ASDO, DATA0 : AD7 : : : : 3A : +GND : AD8 : gnd : : : : +VCCPD3B4A : AD9 : power : : 3.3V : 3B, 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD10 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD11 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD12 : : : : 3B : +VCCPD3B4A : AD13 : power : : 3.3V : 3B, 4A : +GND : AD14 : gnd : : : : +VCC_AUX : AD15 : power : : 2.5V : : +VCCPD3B4A : AD16 : power : : 3.3V : 3B, 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD17 : : : : 4A : +VCCPD3B4A : AD18 : power : : 3.3V : 3B, 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD19 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD20 : : : : 4A : +VCCPD3B4A : AD21 : power : : 3.3V : 3B, 4A : +GND : AD22 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD23 : : : : 4A : +VCCPGM : AD24 : power : : 1.8V/2.5V/3.0V/3.3V : : +GND : AD25 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD26 : : : : 5A : +VCCIO6B_HPS : AD27 : power : : 2.5V : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD28 : : : : 6B : +GND : AE1 : gnd : : : : +GND : AE2 : gnd : : : : +GND : AE3 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE4 : : : : 3B : +VREFB3AN0 : AE5 : power : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE6 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE7 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE8 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE9 : : : : 3B : +VCCIO3B : AE10 : power : : 3.3V : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE11 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE12 : : : : 3B : +VCCIO3B : AE13 : power : : 3.3V : 3B : +DNU : AE14 : : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE15 : : : : 4A : +GND : AE16 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE17 : : : : 4A : +GND : AE18 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE19 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE20 : : : : 4A : +VCCIO4A : AE21 : power : : 3.3V : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE22 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE23 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE24 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE25 : : : : 5A : +led[5] : AE26 : output : 3.3-V LVTTL : : 5A : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : AE27 : : : : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE28 : : : : 6B : +GND : AF1 : gnd : : : : +GND : AF2 : gnd : : : : +GND : AF3 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF4 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF5 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF6 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF7 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF8 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF9 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF10 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF11 : : : : 3B : +VREFB3BN0 : AF12 : power : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF13 : : : : 4A : +VCCIO4A : AF14 : power : : 3.3V : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF15 : : : : 4A : +VREFB4AN0 : AF16 : power : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF17 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF18 : : : : 4A : +VCCIO4A : AF19 : power : : 3.3V : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF20 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF21 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF22 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF23 : : : : 4A : +GND : AF24 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF25 : : : : 4A : +led[4] : AF26 : output : 3.3-V LVTTL : : 5A : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : AF27 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF28 : : : : 4A : +GND : AG1 : gnd : : : : +GND : AG2 : gnd : : : : +GND : AG3 : gnd : : : : +VCCIO3B : AG4 : power : : 3.3V : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AG5 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AG6 : : : : 3B : +GND : AG7 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AG8 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AG9 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AG10 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AG11 : : : : 4A : +VCCIO4A : AG12 : power : : 3.3V : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AG13 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AG14 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AG15 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AG16 : : : : 4A : +GND : AG17 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AG18 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AG19 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AG20 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AG21 : : : : 4A : +VCCIO4A : AG22 : power : : 3.3V : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AG23 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AG24 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AG25 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AG26 : : : : 4A : +GND : AG27 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AG28 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AH2 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AH3 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AH4 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AH5 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AH6 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : AH7 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AH8 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AH9 : : : : 4A : +GND : AH10 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AH11 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AH12 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AH13 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AH14 : : : : 4A : +VCCIO4A : AH15 : power : : 3.3V : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AH16 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AH17 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AH18 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AH19 : : : : 4A : +GND : AH20 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AH21 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AH22 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AH23 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AH24 : : : : 4A : +VCCIO4A : AH25 : power : : 3.3V : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AH26 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : AH27 : : : : 4A : +GND : B1 : : : : : +DNU : B2 : : : : : +GND : B3 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 7C : +GND : B5 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 7C : +GND : B7 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 7C : +RESERVED_INPUT_WITH_WEAK_PULLUP : B9 : : : : 7C : +VCCIO7C_HPS : B10 : power : : 2.5V : 7C : +RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 7C : +RESERVED_INPUT_WITH_WEAK_PULLUP : B12 : : : : 7C : +VCCIO7B_HPS : B13 : power : : 2.5V : 7B : +RESERVED_INPUT_WITH_WEAK_PULLUP : B14 : : : : 7B : +GND : B15 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B16 : : : : 7A : +GND : B17 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B18 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : B19 : : : : 7A : +GND : B20 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 7A : +GND : B22 : gnd : : : : +HPS_TDO : B23 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : B24 : : : : 6A : +GND : B25 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B26 : : : : 6A : +GND : B27 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B28 : : : : 6A : +GND : C1 : gnd : : : : +GND : C2 : gnd : : : : +GND : C3 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : : : : 7D : +RESERVED_INPUT_WITH_WEAK_PULLUP : C5 : : : : 7D : +RESERVED_INPUT_WITH_WEAK_PULLUP : C6 : : : : 7D : +RESERVED_INPUT_WITH_WEAK_PULLUP : C7 : : : : 7D : +RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 7D : +RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 7D : +RESERVED_INPUT_WITH_WEAK_PULLUP : C10 : : : : 7D : +GND : C11 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : C12 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 7C : +RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 7B : +RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 7B : +RESERVED_INPUT_WITH_WEAK_PULLUP : C16 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : C17 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : C18 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7A : +VCCIO7A_HPS : C20 : power : : 2.5V : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : C21 : : : : 7A : +HPS_TRST : C22 : : : : 7A : +HPS_TMS : C23 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : C24 : : : : 6A : +VCCIO6A_HPS : C25 : power : : 2.5V : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : C26 : : : : 6A : +VCCIO6A_HPS : C27 : power : : 2.5V : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : C28 : : : : 6A : +DNU : D1 : : : : : +DNU : D2 : : : : : +GND : D3 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D4 : : : : 7D : +RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 7D : +VCCIO7D_HPS : D6 : power : : 2.5V : 7D : +VCCBAT : D7 : power : : 1.2V : : +lcd_clk : D8 : output : 2.5 V : : 8A : Y +VREFB8AN0 : D9 : power : : : 8A : +GND : D10 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D11 : : : : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 8A : +GND : D13 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 7C : +RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 7B : +GND : D16 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D17 : : : : 7B : +VCCIO7A_HPS : D18 : power : : 2.5V : 7A : +VREFB7A7B7C7DN0_HPS : D19 : power : : : 7A, 7B, 7C, 7D : +HPS_CLK2 : D20 : : : : 7A : +GND : D21 : : : : 7A : +HPS_TDI : D22 : : : : 7A : +DNU : D23 : : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D24 : : : : 6A : +HPS_RZQ_0 : D25 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : D26 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : D27 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : D28 : : : : 6A : +GND : E1 : gnd : : : : +GND : E2 : gnd : : : : +GND : E3 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E4 : : : : 7D : +RESERVED_INPUT_WITH_WEAK_PULLUP : E5 : : : : 7D : +nCE : E6 : : : : 9A : +VCCIO8A : E7 : power : : 2.5V : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : E8 : : : : 8A : +GND : E9 : gnd : : : : +VCCPD8A : E10 : power : : 2.5V : 8A : +RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 8A : +DNU : E12 : : : : : +VCCPD7D_HPS : E13 : power : : 2.5V : 7D : +VCCPD7C_HPS : E14 : power : : 2.5V : 7C : +VCC_AUX : E15 : power : : 2.5V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E16 : : : : 7B : +VCCPD7B_HPS : E17 : power : : 2.5V : 7B : +HPS_PORSEL : E18 : : : : 7A : +GND : E19 : gnd : : : : +HPS_CLK1 : E20 : : : : 7A : +VCCPD7A_HPS : E21 : power : : 2.5V : 7A : +GND : E22 : gnd : : : : +GND : E23 : : : : 7A : +GND : E24 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E25 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : E26 : : : : 6A : +GND : E27 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E28 : : : : 6A : +GND : F1 : gnd : : : : +GND : F2 : gnd : : : : +GND : F3 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : F4 : : : : 7D : +RESERVED_INPUT_WITH_WEAK_PULLUP : F5 : : : : 7D : +GND : F6 : : : : 9A : +nCONFIG : F7 : : : : 9A : +VCC_AUX : F8 : power : : 2.5V : : +VCC_AUX_SHARED : F21 : power : : 2.5V : : +VCCRSTCLK_HPS : F22 : power : : 1.8V/2.5V/3.0V/3.3V : : +GND : F23 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : F24 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : F25 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : F26 : : : : 6A : +VCCIO6A_HPS : F27 : power : : 2.5V : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : F28 : : : : 6A : +GND : G1 : gnd : : : : +GND : G2 : gnd : : : : +GND : G3 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G4 : : : : 7D : +VCCIO7D_HPS : G5 : power : : 2.5V : 7D : +MSEL2 : G6 : : : : 9A : +RESERVED_INPUT_WITH_WEAK_PULLUP : G23 : : : : 6A : +VCCIO6A_HPS : G24 : power : : 2.5V : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : G25 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : G26 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : G27 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : G28 : : : : 6A : +DNU : H1 : : : : : +DNU : H2 : : : : : +GND : H3 : gnd : : : : +GND : H4 : gnd : : : : +GND : H5 : gnd : : : : +GND : H6 : gnd : : : : +nSTATUS : H8 : : : : 9A : +MSEL1 : H9 : : : : 9A : +VCCPGM : H10 : power : : 1.8V/2.5V/3.0V/3.3V : : +GND : H11 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 7C : +RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 7C : +VCCIO7B_HPS : H14 : power : : 2.5V : 7B : +GND : H15 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : H16 : : : : 7B : +RESERVED_INPUT_WITH_WEAK_PULLUP : H17 : : : : 7A : +GND : H18 : gnd : : : : +HPS_nPOR : H19 : : : : 7A : +GND : H20 : gnd : : : : +VCCIO6A_HPS : H21 : power : : 2.5V : 6A : +VCCPLL_HPS : H23 : power : : 2.5V : : +GND : H24 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : H25 : : : : 6A : +VCCIO6A_HPS : H26 : power : : 2.5V : 6A : +GND : H27 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : H28 : : : : 6A : +GND : J1 : gnd : : : : +GND : J2 : gnd : : : : +GND : J3 : gnd : : : : +VCCA_FPLL : J4 : power : : 2.5V : : +GND : J5 : gnd : : : : +CONF_DONE : J8 : : : : 9A : +GND : J9 : gnd : : : : +MSEL0 : J10 : : : : 9A : +VCC : J11 : power : : 1.1V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J12 : : : : 7B : +RESERVED_INPUT_WITH_WEAK_PULLUP : J13 : : : : 7B : +RESERVED_INPUT_WITH_WEAK_PULLUP : J14 : : : : 7B : +RESERVED_INPUT_WITH_WEAK_PULLUP : J15 : : : : 7B : +RESERVED_INPUT_WITH_WEAK_PULLUP : J16 : : : : 7B : +RESERVED_INPUT_WITH_WEAK_PULLUP : J17 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J18 : : : : 7A : +VCCRSTCLK_HPS : J19 : : : : 7A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J20 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J21 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J24 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J25 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J26 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J27 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : J28 : : : : 6A : +GND : K1 : gnd : : : : +GND : K2 : gnd : : : : +GND : K3 : gnd : : : : +GND : K4 : gnd : : : : +VCCA_FPLL : K5 : power : : 2.5V : : +GND : K8 : gnd : : : : +MSEL4 : K9 : : : : 9A : +MSEL3 : K10 : : : : 9A : +GND : K11 : gnd : : : : +GND : K12 : gnd : : : : +VCC : K13 : power : : 1.1V : : +GND : K14 : gnd : : : : +VCC : K15 : power : : 1.1V : : +GND : K16 : gnd : : : : +VCC_HPS : K17 : power : : 1.1V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : K18 : : : : 7A : +HPS_TCK : K19 : : : : 7A : +GND : K20 : gnd : : : : +VCCPD6A6B_HPS : K21 : power : : 2.5V : 6A, 6B : +VCCPD6A6B_HPS : K24 : power : : 2.5V : 6A, 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : K25 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K26 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K27 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : K28 : : : : 6A : +GND : L1 : gnd : : : : +GND : L2 : gnd : : : : +GND : L3 : gnd : : : : +VCC : L4 : power : : 1.1V : : +GND : L5 : gnd : : : : +GND : L8 : gnd : : : : +GND : L9 : gnd : : : : +GND : L10 : gnd : : : : +VCC : L11 : power : : 1.1V : : +VCC : L12 : power : : 1.1V : : +GND : L13 : gnd : : : : +VCC : L14 : power : : 1.1V : : +GND : L15 : gnd : : : : +VCC_HPS : L16 : power : : 1.1V : : +GND : L17 : gnd : : : : +VCC_HPS : L18 : power : : 1.1V : : +GND : L19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : L20 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : L21 : : : : 6A : +GND : L24 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : L25 : : : : 6A : +VCCIO6A_HPS : L26 : power : : 2.5V : 6A : +GND : L27 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : L28 : : : : 6A : +DNU : M1 : : : : : +DNU : M2 : : : : : +GND : M3 : gnd : : : : +VCCA_FPLL : M4 : power : : 2.5V : : +VCC : M5 : power : : 1.1V : : +GND : M8 : gnd : : : : +VCC : M9 : power : : 1.1V : : +GND : M10 : gnd : : : : +GND : M11 : gnd : : : : +VCC : M12 : power : : 1.1V : : +VCC : M13 : power : : 1.1V : : +GND : M14 : gnd : : : : +VCC : M15 : power : : 1.1V : : +GND : M16 : gnd : : : : +VCC_HPS : M17 : power : : 1.1V : : +VCC_HPS : M18 : power : : 1.1V : : +VCC_HPS : M19 : power : : 1.1V : : +GND : M20 : gnd : : : : +VCCIO6A_HPS : M21 : power : : 2.5V : 6A : +VCCPD6A6B_HPS : M24 : power : : 2.5V : 6A, 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : M25 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : M26 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : M27 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : M28 : : : : 6A : +GND : N1 : gnd : : : : +GND : N2 : gnd : : : : +GND : N3 : gnd : : : : +GND : N4 : gnd : : : : +VCC : N5 : power : : 1.1V : : +GND : N8 : gnd : : : : +VCC : N9 : power : : 1.1V : : +VCC : N10 : power : : 1.1V : : +VCC : N11 : power : : 1.1V : : +VCC : N12 : power : : 1.1V : : +GND : N13 : gnd : : : : +VCC : N14 : power : : 1.1V : : +GND : N15 : gnd : : : : +VCC_HPS : N16 : power : : 1.1V : : +GND : N17 : gnd : : : : +VCC_HPS : N18 : power : : 1.1V : : +GND : N19 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : N20 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : N21 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : N24 : : : : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : N25 : : : : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : N26 : : : : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : N27 : : : : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : N28 : : : : 6A : +GND : P1 : gnd : : : : +GND : P2 : gnd : : : : +GND : P3 : gnd : : : : +VCCA_FPLL : P4 : power : : 2.5V : : +GND : P5 : gnd : : : : +GND : P8 : gnd : : : : +GND : P9 : gnd : : : : +GND : P10 : gnd : : : : +VCC : P11 : power : : 1.1V : : +GND : P12 : gnd : : : : +VCC : P13 : power : : 1.1V : : +VCC : P14 : power : : 1.1V : : +VCC : P15 : power : : 1.1V : : +GND : P16 : gnd : : : : +VCC_HPS : P17 : power : : 1.1V : : +GND : P18 : gnd : : : : +VCC_HPS : P19 : power : : 1.1V : : +GND : P20 : gnd : : : : +VCCPD6A6B_HPS : P21 : power : : 2.5V : 6A, 6B : +VCCPD6A6B_HPS : P24 : power : : 2.5V : 6A, 6B : +GND : P25 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : P26 : : : : 6B : +VCCIO6B_HPS : P27 : power : : 2.5V : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : P28 : : : : 6A : +GND : R1 : gnd : : : : +GND : R2 : gnd : : : : +GND : R3 : gnd : : : : +VCCA_FPLL : R4 : power : : 2.5V : : +VCC : R5 : power : : 1.1V : : +GND : R8 : gnd : : : : +VCC : R9 : power : : 1.1V : : +VCC : R10 : power : : 1.1V : : +GND : R11 : gnd : : : : +VCC : R12 : power : : 1.1V : : +GND : R13 : gnd : : : : +VCC : R14 : power : : 1.1V : : +GND : R15 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : R16 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : R17 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : R18 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : R19 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : R20 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : R21 : : : : 6A : +RESERVED_INPUT_WITH_WEAK_PULLUP : R24 : : : : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : R25 : : : : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : R26 : : : : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : R27 : : : : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : R28 : : : : 6B : +DNU : T1 : : : : : +DNU : T2 : : : : : +GND : T3 : gnd : : : : +VCC : T4 : power : : 1.1V : : +VCC : T5 : power : : 1.1V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : T8 : : : : 3A : +VCC : T9 : power : : 1.1V : : +GND : T10 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : T11 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : T12 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : T13 : : : : 3B : +GND : T14 : gnd : : : : +VCC : T15 : power : : 1.1V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : T16 : : : : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : T17 : : : : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : T18 : : : : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : T19 : : : : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : T20 : : : : 6B : +VCCIO6B_HPS : T21 : power : : 2.5V : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : T24 : : : : 6B : +VCCIO6B_HPS : T25 : power : : 2.5V : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : T26 : : : : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : T27 : : : : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : T28 : : : : 6B : +GND : U1 : gnd : : : : +GND : U2 : gnd : : : : +GND : U3 : gnd : : : : +VCCA_FPLL : U4 : power : : 2.5V : : +GND : U5 : gnd : : : : +DNU : U8 : : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : U9 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : U10 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : U11 : : : : 3B : +GND : U12 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : U13 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : U14 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : U15 : : : : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : U16 : : : : 6B : +GND : U17 : gnd : : : : +VCCIO6B_HPS : U18 : power : : 2.5V : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : U19 : : : : 6B : +GND : U20 : gnd : : : : +VCC_HPS : U21 : power : : 1.1V : : +GND : U24 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : U25 : : : : 6B : +VCC : U26 : power : : 1.1V : : +GND : U27 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : U28 : : : : 6B : +GND : V1 : gnd : : : : +GND : V2 : gnd : : : : +GND : V3 : gnd : : : : +GND : V4 : gnd : : : : +GND : V5 : gnd : : : : +GND : V8 : gnd : : : : +GND : V9 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : V10 : : : : 3A : +fpga_clk : V11 : input : 2.5 V : : 3B : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : V12 : : : : 3B : +RESERVED_INPUT_WITH_WEAK_PULLUP : V13 : : : : 4A : +GND : V14 : gnd : : : : +led[3] : V15 : output : 3.3-V LVTTL : : 5A : Y +led[2] : V16 : output : 3.3-V LVTTL : : 5A : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : V17 : : : : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : V18 : : : : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : V19 : : : : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : V20 : : : : 6B : +GND : V21 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : V24 : : : : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : V25 : : : : 6B : +GND : V26 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : V27 : : : : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : V28 : : : : 6B : +GND : W1 : gnd : : : : +GND : W2 : gnd : : : : +GND : W3 : gnd : : : : +GND : W4 : gnd : : : : +VCCA_FPLL : W5 : power : : 2.5V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 3A : +VCCIO3A : W9 : power : : 2.5V : 3A : +TDI : W10 : input : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : W11 : : : : 3B : +lcd_data : W12 : output : 3.3-V LVTTL : : 3B : Y +VCCIO4A : W13 : power : : 3.3V : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : W14 : : : : 4A : +led[0] : W15 : output : 3.3-V LVTTL : : 5A : Y +GND : W16 : gnd : : : : +VCCIO5A : W17 : power : : 3.3V : 5A : +GND : W18 : gnd : : : : +VCCPD5B : W19 : power : : 2.5V : 5B : +rst_in : W20 : input : 2.5 V : : 5B : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : W21 : : : : 5B : +RESERVED_INPUT_WITH_WEAK_PULLUP : W24 : : : : 5B : +VCCIO5B : W25 : power : : 2.5V : 5B : +RESERVED_INPUT_WITH_WEAK_PULLUP : W26 : : : : 6B : +VCCIO6B_HPS : W27 : power : : 2.5V : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : W28 : : : : 6B : +DNU : Y1 : : : : : +DNU : Y2 : : : : : +GND : Y3 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y4 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y5 : : : : 3A : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y8 : : : : 3A : +TDO : Y9 : output : : : 3A : +VCCPGM : Y10 : power : : 1.8V/2.5V/3.0V/3.3V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y11 : : : : 3A : +GND : Y12 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : : : 4A : +GND : Y14 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y15 : : : : 4A : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y17 : : : : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y18 : : : : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y19 : : : : 5A : +GND : Y20 : gnd : : : : +VCCPD5A : Y21 : power : : 3.3V : 5A : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y24 : : : : 5B : +GND : Y25 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y26 : : : : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y27 : : : : 6B : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y28 : : : : 6B : diff --git a/output_files/chip8.sld b/output_files/chip8.sld new file mode 100644 index 0000000..f7d3ed7 --- /dev/null +++ b/output_files/chip8.sld @@ -0,0 +1 @@ + diff --git a/output_files/chip8.sof b/output_files/chip8.sof new file mode 100644 index 0000000..4db08b5 Binary files /dev/null and b/output_files/chip8.sof differ diff --git a/output_files/chip8.sta.rpt b/output_files/chip8.sta.rpt new file mode 100644 index 0000000..61d4cdb --- /dev/null +++ b/output_files/chip8.sta.rpt @@ -0,0 +1,674 @@ +Timing Analyzer report for chip8 +Sun Apr 7 23:52:43 2024 +Quartus Prime Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Timing Analyzer Summary + 3. Parallel Compilation + 4. Clocks + 5. Slow 1100mV 100C Model Fmax Summary + 6. Timing Closure Recommendations + 7. Slow 1100mV 100C Model Setup Summary + 8. Slow 1100mV 100C Model Hold Summary + 9. Slow 1100mV 100C Model Recovery Summary + 10. Slow 1100mV 100C Model Removal Summary + 11. Slow 1100mV 100C Model Minimum Pulse Width Summary + 12. Slow 1100mV 100C Model Metastability Summary + 13. Slow 1100mV -40C Model Fmax Summary + 14. Slow 1100mV -40C Model Setup Summary + 15. Slow 1100mV -40C Model Hold Summary + 16. Slow 1100mV -40C Model Recovery Summary + 17. Slow 1100mV -40C Model Removal Summary + 18. Slow 1100mV -40C Model Minimum Pulse Width Summary + 19. Slow 1100mV -40C Model Metastability Summary + 20. Fast 1100mV 100C Model Setup Summary + 21. Fast 1100mV 100C Model Hold Summary + 22. Fast 1100mV 100C Model Recovery Summary + 23. Fast 1100mV 100C Model Removal Summary + 24. Fast 1100mV 100C Model Minimum Pulse Width Summary + 25. Fast 1100mV 100C Model Metastability Summary + 26. Fast 1100mV -40C Model Setup Summary + 27. Fast 1100mV -40C Model Hold Summary + 28. Fast 1100mV -40C Model Recovery Summary + 29. Fast 1100mV -40C Model Removal Summary + 30. Fast 1100mV -40C Model Minimum Pulse Width Summary + 31. Fast 1100mV -40C Model Metastability Summary + 32. Multicorner Timing Analysis Summary + 33. Board Trace Model Assignments + 34. Input Transition Times + 35. Signal Integrity Metrics (Slow 1100mv n40c Model) + 36. Signal Integrity Metrics (Slow 1100mv 100c Model) + 37. Signal Integrity Metrics (Fast 1100mv n40c Model) + 38. Signal Integrity Metrics (Fast 1100mv 100c Model) + 39. Setup Transfers + 40. Hold Transfers + 41. Report TCCS + 42. Report RSKM + 43. Unconstrained Paths Summary + 44. Clock Status Summary + 45. Unconstrained Output Ports + 46. Unconstrained Output Ports + 47. Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2023 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++--------------------------------------------------------------------------------+ +; Timing Analyzer Summary ; ++-----------------------+--------------------------------------------------------+ +; Quartus Prime Version ; Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition ; +; Timing Analyzer ; Legacy Timing Analyzer ; +; Revision Name ; chip8 ; +; Device Family ; Cyclone V ; +; Device Name ; 5CSEBA6U23I7 ; +; Timing Models ; Final ; +; Delay Model ; Combined ; +; Rise/Fall Delays ; Enabled ; ++-----------------------+--------------------------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 12 ; +; Maximum allowed ; 12 ; +; ; ; +; Average used ; 5.73 ; +; Maximum used ; 12 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processor 2 ; 60.4% ; +; Processor 3 ; 57.0% ; +; Processor 4 ; 55.9% ; +; Processor 5 ; 37.5% ; +; Processor 6 ; 37.5% ; +; Processor 7 ; 37.5% ; +; Processor 8 ; 37.5% ; +; Processor 9 ; 37.5% ; +; Processor 10 ; 37.5% ; +; Processor 11 ; 37.5% ; +; Processor 12 ; 37.5% ; ++----------------------------+-------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clocks ; ++------------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------------------------------------------+ +; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ; ++------------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------------------------------------------+ +; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { cpu:cpu|st7920_serial_driver:gpu|lcd_clk } ; +; fpga_clk ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { fpga_clk } ; ++------------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------------------------------------------+ + + ++-------------------------------------------------------------------------------+ +; Slow 1100mV 100C Model Fmax Summary ; ++-----------+-----------------+------------------------------------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------------------------------------+------+ +; 34.01 MHz ; 34.01 MHz ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; ; +; 82.06 MHz ; 82.06 MHz ; fpga_clk ; ; ++-----------+-----------------+------------------------------------------+------+ +This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. + + +---------------------------------- +; Timing Closure Recommendations ; +---------------------------------- +HTML report is unavailable in plain text report export. + + ++--------------------------------------------------------------------+ +; Slow 1100mV 100C Model Setup Summary ; ++------------------------------------------+---------+---------------+ +; Clock ; Slack ; End Point TNS ; ++------------------------------------------+---------+---------------+ +; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -28.406 ; -1742.530 ; +; fpga_clk ; -11.186 ; -95769.392 ; ++------------------------------------------+---------+---------------+ + + ++------------------------------------------------------------------+ +; Slow 1100mV 100C Model Hold Summary ; ++------------------------------------------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++------------------------------------------+-------+---------------+ +; fpga_clk ; 0.429 ; 0.000 ; +; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 0.476 ; 0.000 ; ++------------------------------------------+-------+---------------+ + + +------------------------------------------- +; Slow 1100mV 100C Model Recovery Summary ; +------------------------------------------- +No paths to report. + + +------------------------------------------ +; Slow 1100mV 100C Model Removal Summary ; +------------------------------------------ +No paths to report. + + ++-------------------------------------------------------------------+ +; Slow 1100mV 100C Model Minimum Pulse Width Summary ; ++------------------------------------------+--------+---------------+ +; Clock ; Slack ; End Point TNS ; ++------------------------------------------+--------+---------------+ +; fpga_clk ; -2.636 ; -8463.323 ; +; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -0.538 ; -185.389 ; ++------------------------------------------+--------+---------------+ + + +------------------------------------------------ +; Slow 1100mV 100C Model Metastability Summary ; +------------------------------------------------ +Design MTBF is not calculated because the design doesn't meet its timing requirements. + + + ++-------------------------------------------------------------------------------+ +; Slow 1100mV -40C Model Fmax Summary ; ++-----------+-----------------+------------------------------------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------------------------------------+------+ +; 35.8 MHz ; 35.8 MHz ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; ; +; 81.78 MHz ; 81.78 MHz ; fpga_clk ; ; ++-----------+-----------------+------------------------------------------+------+ +This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. + + ++--------------------------------------------------------------------+ +; Slow 1100mV -40C Model Setup Summary ; ++------------------------------------------+---------+---------------+ +; Clock ; Slack ; End Point TNS ; ++------------------------------------------+---------+---------------+ +; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -26.933 ; -1684.576 ; +; fpga_clk ; -11.228 ; -94100.779 ; ++------------------------------------------+---------+---------------+ + + ++------------------------------------------------------------------+ +; Slow 1100mV -40C Model Hold Summary ; ++------------------------------------------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++------------------------------------------+-------+---------------+ +; fpga_clk ; 0.484 ; 0.000 ; +; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 0.565 ; 0.000 ; ++------------------------------------------+-------+---------------+ + + +------------------------------------------- +; Slow 1100mV -40C Model Recovery Summary ; +------------------------------------------- +No paths to report. + + +------------------------------------------ +; Slow 1100mV -40C Model Removal Summary ; +------------------------------------------ +No paths to report. + + ++-------------------------------------------------------------------+ +; Slow 1100mV -40C Model Minimum Pulse Width Summary ; ++------------------------------------------+--------+---------------+ +; Clock ; Slack ; End Point TNS ; ++------------------------------------------+--------+---------------+ +; fpga_clk ; -2.636 ; -8927.522 ; +; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -0.538 ; -184.012 ; ++------------------------------------------+--------+---------------+ + + +------------------------------------------------ +; Slow 1100mV -40C Model Metastability Summary ; +------------------------------------------------ +Design MTBF is not calculated because the design doesn't meet its timing requirements. + + + ++--------------------------------------------------------------------+ +; Fast 1100mV 100C Model Setup Summary ; ++------------------------------------------+---------+---------------+ +; Clock ; Slack ; End Point TNS ; ++------------------------------------------+---------+---------------+ +; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -14.774 ; -901.498 ; +; fpga_clk ; -6.214 ; -50560.530 ; ++------------------------------------------+---------+---------------+ + + ++------------------------------------------------------------------+ +; Fast 1100mV 100C Model Hold Summary ; ++------------------------------------------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++------------------------------------------+-------+---------------+ +; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 0.162 ; 0.000 ; +; fpga_clk ; 0.177 ; 0.000 ; ++------------------------------------------+-------+---------------+ + + +------------------------------------------- +; Fast 1100mV 100C Model Recovery Summary ; +------------------------------------------- +No paths to report. + + +------------------------------------------ +; Fast 1100mV 100C Model Removal Summary ; +------------------------------------------ +No paths to report. + + ++-------------------------------------------------------------------+ +; Fast 1100mV 100C Model Minimum Pulse Width Summary ; ++------------------------------------------+--------+---------------+ +; Clock ; Slack ; End Point TNS ; ++------------------------------------------+--------+---------------+ +; fpga_clk ; -2.174 ; -1371.543 ; +; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -0.192 ; -9.702 ; ++------------------------------------------+--------+---------------+ + + +------------------------------------------------ +; Fast 1100mV 100C Model Metastability Summary ; +------------------------------------------------ +Design MTBF is not calculated because the design doesn't meet its timing requirements. + + + ++--------------------------------------------------------------------+ +; Fast 1100mV -40C Model Setup Summary ; ++------------------------------------------+---------+---------------+ +; Clock ; Slack ; End Point TNS ; ++------------------------------------------+---------+---------------+ +; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -12.462 ; -739.747 ; +; fpga_clk ; -4.930 ; -40871.978 ; ++------------------------------------------+---------+---------------+ + + ++------------------------------------------------------------------+ +; Fast 1100mV -40C Model Hold Summary ; ++------------------------------------------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++------------------------------------------+-------+---------------+ +; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 0.140 ; 0.000 ; +; fpga_clk ; 0.164 ; 0.000 ; ++------------------------------------------+-------+---------------+ + + +------------------------------------------- +; Fast 1100mV -40C Model Recovery Summary ; +------------------------------------------- +No paths to report. + + +------------------------------------------ +; Fast 1100mV -40C Model Removal Summary ; +------------------------------------------ +No paths to report. + + ++-------------------------------------------------------------------+ +; Fast 1100mV -40C Model Minimum Pulse Width Summary ; ++------------------------------------------+--------+---------------+ +; Clock ; Slack ; End Point TNS ; ++------------------------------------------+--------+---------------+ +; fpga_clk ; -2.174 ; -1373.239 ; +; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -0.137 ; -3.355 ; ++------------------------------------------+--------+---------------+ + + +------------------------------------------------ +; Fast 1100mV -40C Model Metastability Summary ; +------------------------------------------------ +Design MTBF is not calculated because the design doesn't meet its timing requirements. + + + ++-----------------------------------------------------------------------------------------------------------+ +; Multicorner Timing Analysis Summary ; ++-------------------------------------------+------------+-------+----------+---------+---------------------+ +; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; ++-------------------------------------------+------------+-------+----------+---------+---------------------+ +; Worst-case Slack ; -28.406 ; 0.140 ; N/A ; N/A ; -2.636 ; +; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -28.406 ; 0.140 ; N/A ; N/A ; -0.538 ; +; fpga_clk ; -11.228 ; 0.164 ; N/A ; N/A ; -2.636 ; +; Design-wide TNS ; -97511.922 ; 0.0 ; 0.0 ; 0.0 ; -9111.534 ; +; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -1742.530 ; 0.000 ; N/A ; N/A ; -185.389 ; +; fpga_clk ; -95769.392 ; 0.000 ; N/A ; N/A ; -8927.522 ; ++-------------------------------------------+------------+-------+----------+---------+---------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Board Trace Model Assignments ; ++----------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ; ++----------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; lcd_clk ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; lcd_data ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; led[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; led[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; led[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; led[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; led[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; led[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ++----------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ + + ++-------------------------------------------------------------+ +; Input Transition Times ; ++----------+--------------+-----------------+-----------------+ +; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; ++----------+--------------+-----------------+-----------------+ +; rst_in ; 2.5 V ; 2000 ps ; 2000 ps ; +; fpga_clk ; 2.5 V ; 2000 ps ; 2000 ps ; ++----------+--------------+-----------------+-----------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1100mv n40c Model) ; ++----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; lcd_clk ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.56e-08 V ; 2.43 V ; -0.0607 V ; 0.35 V ; 0.108 V ; 3.1e-10 s ; 4.28e-10 s ; No ; No ; 2.32 V ; 1.56e-08 V ; 2.43 V ; -0.0607 V ; 0.35 V ; 0.108 V ; 3.1e-10 s ; 4.28e-10 s ; No ; No ; +; lcd_data ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.47e-08 V ; 3.11 V ; -0.195 V ; 0.108 V ; 0.32 V ; 4.03e-10 s ; 1.44e-10 s ; Yes ; No ; 3.08 V ; 1.47e-08 V ; 3.11 V ; -0.195 V ; 0.108 V ; 0.32 V ; 4.03e-10 s ; 1.44e-10 s ; Yes ; No ; +; led[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.47e-08 V ; 3.11 V ; -0.195 V ; 0.108 V ; 0.32 V ; 4.03e-10 s ; 1.44e-10 s ; Yes ; No ; 3.08 V ; 1.47e-08 V ; 3.11 V ; -0.195 V ; 0.108 V ; 0.32 V ; 4.03e-10 s ; 1.44e-10 s ; Yes ; No ; +; led[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.91e-08 V ; 3.17 V ; -0.306 V ; 0.142 V ; 0.425 V ; 4.17e-10 s ; 1.36e-10 s ; Yes ; No ; 3.08 V ; 1.91e-08 V ; 3.17 V ; -0.306 V ; 0.142 V ; 0.425 V ; 4.17e-10 s ; 1.36e-10 s ; Yes ; No ; +; led[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2e-08 V ; 3.17 V ; -0.245 V ; 0.166 V ; 0.398 V ; 4.33e-10 s ; 1.46e-10 s ; Yes ; No ; 3.08 V ; 2e-08 V ; 3.17 V ; -0.245 V ; 0.166 V ; 0.398 V ; 4.33e-10 s ; 1.46e-10 s ; Yes ; No ; +; led[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.47e-08 V ; 3.11 V ; -0.195 V ; 0.108 V ; 0.32 V ; 4.03e-10 s ; 1.44e-10 s ; Yes ; No ; 3.08 V ; 1.47e-08 V ; 3.11 V ; -0.195 V ; 0.108 V ; 0.32 V ; 4.03e-10 s ; 1.44e-10 s ; Yes ; No ; +; led[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.91e-08 V ; 3.17 V ; -0.306 V ; 0.142 V ; 0.425 V ; 4.17e-10 s ; 1.36e-10 s ; Yes ; No ; 3.08 V ; 1.91e-08 V ; 3.17 V ; -0.306 V ; 0.142 V ; 0.425 V ; 4.17e-10 s ; 1.36e-10 s ; Yes ; No ; +; led[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.91e-08 V ; 3.17 V ; -0.311 V ; 0.143 V ; 0.424 V ; 4.17e-10 s ; 1.36e-10 s ; Yes ; No ; 3.08 V ; 1.91e-08 V ; 3.17 V ; -0.311 V ; 0.143 V ; 0.424 V ; 4.17e-10 s ; 1.36e-10 s ; Yes ; No ; ++----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1100mv 100c Model) ; ++----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; lcd_clk ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.73e-05 V ; 2.38 V ; -0.0297 V ; 0.21 V ; 0.199 V ; 4.77e-10 s ; 4.97e-10 s ; No ; Yes ; 2.32 V ; 4.73e-05 V ; 2.38 V ; -0.0297 V ; 0.21 V ; 0.199 V ; 4.77e-10 s ; 4.97e-10 s ; No ; Yes ; +; lcd_data ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.09e-05 V ; 3.09 V ; -0.0462 V ; 0.045 V ; 0.085 V ; 5.49e-10 s ; 3.06e-10 s ; Yes ; Yes ; 3.08 V ; 3.09e-05 V ; 3.09 V ; -0.0462 V ; 0.045 V ; 0.085 V ; 5.49e-10 s ; 3.06e-10 s ; Yes ; Yes ; +; led[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.09e-05 V ; 3.09 V ; -0.0462 V ; 0.045 V ; 0.085 V ; 5.49e-10 s ; 3.06e-10 s ; Yes ; Yes ; 3.08 V ; 3.09e-05 V ; 3.09 V ; -0.0462 V ; 0.045 V ; 0.085 V ; 5.49e-10 s ; 3.06e-10 s ; Yes ; Yes ; +; led[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.73e-05 V ; 3.11 V ; -0.104 V ; 0.101 V ; 0.139 V ; 5.54e-10 s ; 3.16e-10 s ; Yes ; Yes ; 3.08 V ; 3.73e-05 V ; 3.11 V ; -0.104 V ; 0.101 V ; 0.139 V ; 5.54e-10 s ; 3.16e-10 s ; Yes ; Yes ; +; led[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.87e-05 V ; 3.11 V ; -0.0814 V ; 0.131 V ; 0.136 V ; 5.88e-10 s ; 3.2e-10 s ; Yes ; Yes ; 3.08 V ; 3.87e-05 V ; 3.11 V ; -0.0814 V ; 0.131 V ; 0.136 V ; 5.88e-10 s ; 3.2e-10 s ; Yes ; Yes ; +; led[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.09e-05 V ; 3.09 V ; -0.0462 V ; 0.045 V ; 0.085 V ; 5.49e-10 s ; 3.06e-10 s ; Yes ; Yes ; 3.08 V ; 3.09e-05 V ; 3.09 V ; -0.0462 V ; 0.045 V ; 0.085 V ; 5.49e-10 s ; 3.06e-10 s ; Yes ; Yes ; +; led[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.73e-05 V ; 3.11 V ; -0.104 V ; 0.101 V ; 0.139 V ; 5.54e-10 s ; 3.16e-10 s ; Yes ; Yes ; 3.08 V ; 3.73e-05 V ; 3.11 V ; -0.104 V ; 0.101 V ; 0.139 V ; 5.54e-10 s ; 3.16e-10 s ; Yes ; Yes ; +; led[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.73e-05 V ; 3.11 V ; -0.105 V ; 0.101 V ; 0.142 V ; 5.54e-10 s ; 3.16e-10 s ; Yes ; Yes ; 3.08 V ; 3.73e-05 V ; 3.11 V ; -0.105 V ; 0.101 V ; 0.142 V ; 5.54e-10 s ; 3.16e-10 s ; Yes ; Yes ; ++----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Fast 1100mv n40c Model) ; ++----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; lcd_clk ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 2.38e-07 V ; 2.94 V ; -0.139 V ; 0.31 V ; 0.268 V ; 2.65e-10 s ; 2.63e-10 s ; No ; Yes ; 2.75 V ; 2.38e-07 V ; 2.94 V ; -0.139 V ; 0.31 V ; 0.268 V ; 2.65e-10 s ; 2.63e-10 s ; No ; Yes ; +; lcd_data ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.38e-07 V ; 3.67 V ; -0.403 V ; 0.084 V ; 0.542 V ; 3.5e-10 s ; 1.32e-10 s ; Yes ; No ; 3.63 V ; 3.38e-07 V ; 3.67 V ; -0.403 V ; 0.084 V ; 0.542 V ; 3.5e-10 s ; 1.32e-10 s ; Yes ; No ; +; led[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.38e-07 V ; 3.67 V ; -0.403 V ; 0.084 V ; 0.542 V ; 3.5e-10 s ; 1.32e-10 s ; Yes ; No ; 3.63 V ; 3.38e-07 V ; 3.67 V ; -0.403 V ; 0.084 V ; 0.542 V ; 3.5e-10 s ; 1.32e-10 s ; Yes ; No ; +; led[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.42e-07 V ; 3.75 V ; -0.588 V ; 0.329 V ; 0.704 V ; 2.77e-10 s ; 1.3e-10 s ; Yes ; No ; 3.63 V ; 4.42e-07 V ; 3.75 V ; -0.588 V ; 0.329 V ; 0.704 V ; 2.77e-10 s ; 1.3e-10 s ; Yes ; No ; +; led[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.64e-07 V ; 3.74 V ; -0.508 V ; 0.391 V ; 0.647 V ; 3.08e-10 s ; 1.34e-10 s ; No ; No ; 3.63 V ; 4.64e-07 V ; 3.74 V ; -0.508 V ; 0.391 V ; 0.647 V ; 3.08e-10 s ; 1.34e-10 s ; No ; No ; +; led[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.38e-07 V ; 3.67 V ; -0.403 V ; 0.084 V ; 0.542 V ; 3.5e-10 s ; 1.32e-10 s ; Yes ; No ; 3.63 V ; 3.38e-07 V ; 3.67 V ; -0.403 V ; 0.084 V ; 0.542 V ; 3.5e-10 s ; 1.32e-10 s ; Yes ; No ; +; led[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.42e-07 V ; 3.75 V ; -0.588 V ; 0.329 V ; 0.704 V ; 2.77e-10 s ; 1.3e-10 s ; Yes ; No ; 3.63 V ; 4.42e-07 V ; 3.75 V ; -0.588 V ; 0.329 V ; 0.704 V ; 2.77e-10 s ; 1.3e-10 s ; Yes ; No ; +; led[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.42e-07 V ; 3.75 V ; -0.589 V ; 0.329 V ; 0.706 V ; 2.77e-10 s ; 1.3e-10 s ; Yes ; No ; 3.63 V ; 4.42e-07 V ; 3.75 V ; -0.589 V ; 0.329 V ; 0.706 V ; 2.77e-10 s ; 1.3e-10 s ; Yes ; No ; ++----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Fast 1100mv 100c Model) ; ++----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; lcd_clk ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.00041 V ; 2.85 V ; -0.0763 V ; 0.365 V ; 0.161 V ; 3.08e-10 s ; 4.37e-10 s ; No ; No ; 2.75 V ; 0.00041 V ; 2.85 V ; -0.0763 V ; 0.365 V ; 0.161 V ; 3.08e-10 s ; 4.37e-10 s ; No ; No ; +; lcd_data ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000307 V ; 3.64 V ; -0.165 V ; 0.022 V ; 0.425 V ; 4.58e-10 s ; 2e-10 s ; Yes ; No ; 3.63 V ; 0.000307 V ; 3.64 V ; -0.165 V ; 0.022 V ; 0.425 V ; 4.58e-10 s ; 2e-10 s ; Yes ; No ; +; led[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000307 V ; 3.64 V ; -0.165 V ; 0.022 V ; 0.425 V ; 4.58e-10 s ; 2e-10 s ; Yes ; No ; 3.63 V ; 0.000307 V ; 3.64 V ; -0.165 V ; 0.022 V ; 0.425 V ; 4.58e-10 s ; 2e-10 s ; Yes ; No ; +; led[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000379 V ; 3.65 V ; -0.289 V ; 0.051 V ; 0.523 V ; 4.36e-10 s ; 1.95e-10 s ; Yes ; No ; 3.63 V ; 0.000379 V ; 3.65 V ; -0.289 V ; 0.051 V ; 0.523 V ; 4.36e-10 s ; 1.95e-10 s ; Yes ; No ; +; led[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000395 V ; 3.65 V ; -0.232 V ; 0.065 V ; 0.547 V ; 4.68e-10 s ; 2.07e-10 s ; Yes ; No ; 3.63 V ; 0.000395 V ; 3.65 V ; -0.232 V ; 0.065 V ; 0.547 V ; 4.68e-10 s ; 2.07e-10 s ; Yes ; No ; +; led[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000307 V ; 3.64 V ; -0.165 V ; 0.022 V ; 0.425 V ; 4.58e-10 s ; 2e-10 s ; Yes ; No ; 3.63 V ; 0.000307 V ; 3.64 V ; -0.165 V ; 0.022 V ; 0.425 V ; 4.58e-10 s ; 2e-10 s ; Yes ; No ; +; led[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000379 V ; 3.65 V ; -0.289 V ; 0.051 V ; 0.523 V ; 4.36e-10 s ; 1.95e-10 s ; Yes ; No ; 3.63 V ; 0.000379 V ; 3.65 V ; -0.289 V ; 0.051 V ; 0.523 V ; 4.36e-10 s ; 1.95e-10 s ; Yes ; No ; +; led[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000379 V ; 3.65 V ; -0.292 V ; 0.053 V ; 0.524 V ; 4.36e-10 s ; 1.95e-10 s ; Yes ; No ; 3.63 V ; 0.000379 V ; 3.65 V ; -0.292 V ; 0.053 V ; 0.524 V ; 4.36e-10 s ; 1.95e-10 s ; Yes ; No ; ++----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Setup Transfers ; ++------------------------------------------+------------------------------------------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++------------------------------------------+------------------------------------------+----------+----------+----------+----------+ +; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 2667 ; 137 ; 0 ; 1681347 ; +; fpga_clk ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 0 ; 0 ; 9878 ; 0 ; +; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; fpga_clk ; 1 ; 1 ; 0 ; 0 ; +; fpga_clk ; fpga_clk ; 12902566 ; 152 ; 48 ; 0 ; ++------------------------------------------+------------------------------------------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Hold Transfers ; ++------------------------------------------+------------------------------------------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++------------------------------------------+------------------------------------------+----------+----------+----------+----------+ +; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 2667 ; 137 ; 0 ; 1681347 ; +; fpga_clk ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 0 ; 0 ; 9878 ; 0 ; +; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; fpga_clk ; 1 ; 1 ; 0 ; 0 ; +; fpga_clk ; fpga_clk ; 12902566 ; 152 ; 48 ; 0 ; ++------------------------------------------+------------------------------------------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + +--------------- +; Report TCCS ; +--------------- +No dedicated SERDES Transmitter circuitry present in device or used in design + + +--------------- +; Report RSKM ; +--------------- +No non-DPA dedicated SERDES Receiver circuitry present in device or used in design + + ++------------------------------------------------+ +; Unconstrained Paths Summary ; ++---------------------------------+-------+------+ +; Property ; Setup ; Hold ; ++---------------------------------+-------+------+ +; Illegal Clocks ; 0 ; 0 ; +; Unconstrained Clocks ; 0 ; 0 ; +; Unconstrained Input Ports ; 0 ; 0 ; +; Unconstrained Input Port Paths ; 0 ; 0 ; +; Unconstrained Output Ports ; 7 ; 7 ; +; Unconstrained Output Port Paths ; 7 ; 7 ; ++---------------------------------+-------+------+ + + ++----------------------------------------------------------------------------------------------------------+ +; Clock Status Summary ; ++------------------------------------------+------------------------------------------+------+-------------+ +; Target ; Clock ; Type ; Status ; ++------------------------------------------+------------------------------------------+------+-------------+ +; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; Base ; Constrained ; +; fpga_clk ; fpga_clk ; Base ; Constrained ; ++------------------------------------------+------------------------------------------+------+-------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; lcd_clk ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; lcd_data ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; led[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; led[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; led[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; led[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; led[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; lcd_clk ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; lcd_data ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; led[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; led[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; led[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; led[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; led[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++--------------------------+ +; Timing Analyzer Messages ; ++--------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Timing Analyzer + Info: Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition + Info: Processing started: Sun Apr 7 23:52:18 2024 +Info: Command: quartus_sta chip8 -c chip8 +Info: qsta_default_script.tcl version: #1 +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 12 of the 12 processors detected +Info (21077): Low junction temperature is -40 degrees C +Info (21077): High junction temperature is 100 degrees C +Critical Warning (332012): Synopsys Design Constraints File file not found: 'chip8.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332105): Deriving Clocks + Info (332105): create_clock -period 1.000 -name fpga_clk fpga_clk + Info (332105): create_clock -period 1.000 -name cpu:cpu|st7920_serial_driver:gpu|lcd_clk cpu:cpu|st7920_serial_driver:gpu|lcd_clk +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. +Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON +Info: Analyzing Slow 1100mV 100C Model +Critical Warning (332148): Timing requirements not met + Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer. +Info (332146): Worst-case setup slack is -28.406 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -28.406 -1742.530 cpu:cpu|st7920_serial_driver:gpu|lcd_clk + Info (332119): -11.186 -95769.392 fpga_clk +Info (332146): Worst-case hold slack is 0.429 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.429 0.000 fpga_clk + Info (332119): 0.476 0.000 cpu:cpu|st7920_serial_driver:gpu|lcd_clk +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332146): Worst-case minimum pulse width slack is -2.636 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -2.636 -8463.323 fpga_clk + Info (332119): -0.538 -185.389 cpu:cpu|st7920_serial_driver:gpu|lcd_clk +Info (332114): Report Metastability: Found 8 synchronizer chains. + Info (332114): Design MTBF is not calculated because the design doesn't meet its timing requirements. +Info: Analyzing Slow 1100mV -40C Model +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. +Critical Warning (332148): Timing requirements not met + Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer. +Info (332146): Worst-case setup slack is -26.933 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -26.933 -1684.576 cpu:cpu|st7920_serial_driver:gpu|lcd_clk + Info (332119): -11.228 -94100.779 fpga_clk +Info (332146): Worst-case hold slack is 0.484 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.484 0.000 fpga_clk + Info (332119): 0.565 0.000 cpu:cpu|st7920_serial_driver:gpu|lcd_clk +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332146): Worst-case minimum pulse width slack is -2.636 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -2.636 -8927.522 fpga_clk + Info (332119): -0.538 -184.012 cpu:cpu|st7920_serial_driver:gpu|lcd_clk +Info (332114): Report Metastability: Found 8 synchronizer chains. + Info (332114): Design MTBF is not calculated because the design doesn't meet its timing requirements. +Info: Analyzing Fast 1100mV 100C Model +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. +Critical Warning (332148): Timing requirements not met + Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer. +Info (332146): Worst-case setup slack is -14.774 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -14.774 -901.498 cpu:cpu|st7920_serial_driver:gpu|lcd_clk + Info (332119): -6.214 -50560.530 fpga_clk +Info (332146): Worst-case hold slack is 0.162 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.162 0.000 cpu:cpu|st7920_serial_driver:gpu|lcd_clk + Info (332119): 0.177 0.000 fpga_clk +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332146): Worst-case minimum pulse width slack is -2.174 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -2.174 -1371.543 fpga_clk + Info (332119): -0.192 -9.702 cpu:cpu|st7920_serial_driver:gpu|lcd_clk +Info (332114): Report Metastability: Found 8 synchronizer chains. + Info (332114): Design MTBF is not calculated because the design doesn't meet its timing requirements. +Info: Analyzing Fast 1100mV -40C Model +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. +Critical Warning (332148): Timing requirements not met + Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer. +Info (332146): Worst-case setup slack is -12.462 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -12.462 -739.747 cpu:cpu|st7920_serial_driver:gpu|lcd_clk + Info (332119): -4.930 -40871.978 fpga_clk +Info (332146): Worst-case hold slack is 0.140 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.140 0.000 cpu:cpu|st7920_serial_driver:gpu|lcd_clk + Info (332119): 0.164 0.000 fpga_clk +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332146): Worst-case minimum pulse width slack is -2.174 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -2.174 -1373.239 fpga_clk + Info (332119): -0.137 -3.355 cpu:cpu|st7920_serial_driver:gpu|lcd_clk +Info (332114): Report Metastability: Found 8 synchronizer chains. + Info (332114): Design MTBF is not calculated because the design doesn't meet its timing requirements. +Info (332102): Design is not fully constrained for setup requirements +Info (332102): Design is not fully constrained for hold requirements +Info: Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings + Info: Peak virtual memory: 1353 megabytes + Info: Processing ended: Sun Apr 7 23:52:43 2024 + Info: Elapsed time: 00:00:25 + Info: Total CPU time (on all processors): 00:01:44 + + diff --git a/output_files/chip8.sta.summary b/output_files/chip8.sta.summary new file mode 100644 index 0000000..8409d96 --- /dev/null +++ b/output_files/chip8.sta.summary @@ -0,0 +1,101 @@ +------------------------------------------------------------ +Timing Analyzer Summary +------------------------------------------------------------ + +Type : Slow 1100mV 100C Model Setup 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk' +Slack : -28.406 +TNS : -1742.530 + +Type : Slow 1100mV 100C Model Setup 'fpga_clk' +Slack : -11.186 +TNS : -95769.392 + +Type : Slow 1100mV 100C Model Hold 'fpga_clk' +Slack : 0.429 +TNS : 0.000 + +Type : Slow 1100mV 100C Model Hold 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk' +Slack : 0.476 +TNS : 0.000 + +Type : Slow 1100mV 100C Model Minimum Pulse Width 'fpga_clk' +Slack : -2.636 +TNS : -8463.323 + +Type : Slow 1100mV 100C Model Minimum Pulse Width 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk' +Slack : -0.538 +TNS : -185.389 + +Type : Slow 1100mV -40C Model Setup 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk' +Slack : -26.933 +TNS : -1684.576 + +Type : Slow 1100mV -40C Model Setup 'fpga_clk' +Slack : -11.228 +TNS : -94100.779 + +Type : Slow 1100mV -40C Model Hold 'fpga_clk' +Slack : 0.484 +TNS : 0.000 + +Type : Slow 1100mV -40C Model Hold 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk' +Slack : 0.565 +TNS : 0.000 + +Type : Slow 1100mV -40C Model Minimum Pulse Width 'fpga_clk' +Slack : -2.636 +TNS : -8927.522 + +Type : Slow 1100mV -40C Model Minimum Pulse Width 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk' +Slack : -0.538 +TNS : -184.012 + +Type : Fast 1100mV 100C Model Setup 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk' +Slack : -14.774 +TNS : -901.498 + +Type : Fast 1100mV 100C Model Setup 'fpga_clk' +Slack : -6.214 +TNS : -50560.530 + +Type : Fast 1100mV 100C Model Hold 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk' +Slack : 0.162 +TNS : 0.000 + +Type : Fast 1100mV 100C Model Hold 'fpga_clk' +Slack : 0.177 +TNS : 0.000 + +Type : Fast 1100mV 100C Model Minimum Pulse Width 'fpga_clk' +Slack : -2.174 +TNS : -1371.543 + +Type : Fast 1100mV 100C Model Minimum Pulse Width 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk' +Slack : -0.192 +TNS : -9.702 + +Type : Fast 1100mV -40C Model Setup 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk' +Slack : -12.462 +TNS : -739.747 + +Type : Fast 1100mV -40C Model Setup 'fpga_clk' +Slack : -4.930 +TNS : -40871.978 + +Type : Fast 1100mV -40C Model Hold 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk' +Slack : 0.140 +TNS : 0.000 + +Type : Fast 1100mV -40C Model Hold 'fpga_clk' +Slack : 0.164 +TNS : 0.000 + +Type : Fast 1100mV -40C Model Minimum Pulse Width 'fpga_clk' +Slack : -2.174 +TNS : -1373.239 + +Type : Fast 1100mV -40C Model Minimum Pulse Width 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk' +Slack : -0.137 +TNS : -3.355 + +------------------------------------------------------------ diff --git a/screenshots/chip8_fpga.jpg b/screenshots/chip8_fpga.jpg new file mode 100644 index 0000000..f5dbf1a Binary files /dev/null and b/screenshots/chip8_fpga.jpg differ