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alu works on fpga

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This commit is contained in:
Nicholas Orlowsky 2024-04-08 08:54:48 -05:00
parent 7fdf4e7739
commit 0ba56bc41e
Signed by: nickorlow
GPG key ID: 838827D8C4611687
75 changed files with 2771 additions and 2316 deletions
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16
output_files/chip8.asm.rpt
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@ -1,5 +1,5 @@
Assembler report for chip8
Sun Apr 7 23:52:17 2024
Mon Apr 8 08:52:25 2024
Quartus Prime Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition
@ -38,7 +38,7 @@ https://fpgasoftware.intel.com/eula.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Sun Apr 7 23:52:17 2024 ;
; Assembler Status ; Successful - Mon Apr 8 08:52:25 2024 ;
; Revision Name ; chip8 ;
; Top-level Entity Name ; chip8 ;
; Family ; Cyclone V ;
@ -67,8 +67,8 @@ https://fpgasoftware.intel.com/eula.
+----------------+--------------------+
; Option ; Setting ;
+----------------+--------------------+
; JTAG usercode ; 0x02233A94 ;
; Checksum ; 0x02233A94 ;
; JTAG usercode ; 0x0223939A ;
; Checksum ; 0x0223939A ;
+----------------+--------------------+
@ -78,14 +78,14 @@ https://fpgasoftware.intel.com/eula.
Info: *******************************************************************
Info: Running Quartus Prime Assembler
Info: Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition
Info: Processing started: Sun Apr 7 23:52:10 2024
Info: Processing started: Mon Apr 8 08:52:19 2024
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off chip8 -c chip8
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (115030): Assembler is generating device programming files
Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
Info: Peak virtual memory: 631 megabytes
Info: Processing ended: Sun Apr 7 23:52:17 2024
Info: Elapsed time: 00:00:07
Info: Peak virtual memory: 628 megabytes
Info: Processing ended: Mon Apr 8 08:52:25 2024
Info: Elapsed time: 00:00:06
Info: Total CPU time (on all processors): 00:00:07

2
output_files/chip8.done
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@ -1 +1 @@
Sun Apr 7 23:52:44 2024
Mon Apr 8 08:52:46 2024

3193
output_files/chip8.fit.rpt
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File diff suppressed because it is too large Load diff

6
output_files/chip8.fit.summary
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@ -1,12 +1,12 @@
Fitter Status : Successful - Sun Apr 7 23:52:05 2024
Fitter Status : Successful - Mon Apr 8 08:52:14 2024
Quartus Prime Version : 23.1std.0 Build 991 11/28/2023 SC Lite Edition
Revision Name : chip8
Top-level Entity Name : chip8
Family : Cyclone V
Device : 5CSEBA6U23I7
Timing Models : Final
Logic utilization (in ALMs) : 10,549 / 41,910 ( 25 % )
Total registers : 10004
Logic utilization (in ALMs) : 10,693 / 41,910 ( 26 % )
Total registers : 10165
Total pins : 10 / 314 ( 3 % )
Total virtual pins : 0
Total block memory bits : 32,768 / 5,662,720 ( < 1 % )

22
output_files/chip8.flow.rpt
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@ -1,5 +1,5 @@
Flow report for chip8
Sun Apr 7 23:52:43 2024
Mon Apr 8 08:52:45 2024
Quartus Prime Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition
@ -41,15 +41,15 @@ https://fpgasoftware.intel.com/eula.
+----------------------------------------------------------------------------------+
; Flow Summary ;
+---------------------------------+------------------------------------------------+
; Flow Status ; Successful - Sun Apr 7 23:52:17 2024 ;
; Flow Status ; Successful - Mon Apr 8 08:52:25 2024 ;
; Quartus Prime Version ; 23.1std.0 Build 991 11/28/2023 SC Lite Edition ;
; Revision Name ; chip8 ;
; Top-level Entity Name ; chip8 ;
; Family ; Cyclone V ;
; Device ; 5CSEBA6U23I7 ;
; Timing Models ; Final ;
; Logic utilization (in ALMs) ; 10,549 / 41,910 ( 25 % ) ;
; Total registers ; 10004 ;
; Logic utilization (in ALMs) ; 10,693 / 41,910 ( 26 % ) ;
; Total registers ; 10165 ;
; Total pins ; 10 / 314 ( 3 % ) ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 32,768 / 5,662,720 ( < 1 % ) ;
@ -68,7 +68,7 @@ https://fpgasoftware.intel.com/eula.
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 04/07/2024 23:44:51 ;
; Start date & time ; 04/08/2024 08:46:51 ;
; Main task ; Compilation ;
; Revision Name ; chip8 ;
+-------------------+---------------------+
@ -79,7 +79,7 @@ https://fpgasoftware.intel.com/eula.
+-------------------------------------+----------------------------------------+---------------+-------------+----------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+----------------------------------------+---------------+-------------+----------------+
; COMPILER_SIGNATURE_ID ; 346662554261.171255149111146 ; -- ; -- ; -- ;
; COMPILER_SIGNATURE_ID ; 346662554261.171258401122441 ; -- ; -- ; -- ;
; EDA_OUTPUT_DATA_FORMAT ; None ; -- ; -- ; eda_simulation ;
; MAX_CORE_JUNCTION_TEMP ; 100 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; -40 ; -- ; -- ; -- ;
@ -97,11 +97,11 @@ https://fpgasoftware.intel.com/eula.
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:01:01 ; 3.7 ; 698 MB ; 00:01:45 ;
; Fitter ; 00:06:11 ; 1.6 ; 2797 MB ; 00:14:15 ;
; Assembler ; 00:00:07 ; 1.0 ; 631 MB ; 00:00:07 ;
; Timing Analyzer ; 00:00:25 ; 5.7 ; 1353 MB ; 00:01:44 ;
; Total ; 00:07:44 ; -- ; -- ; 00:17:51 ;
; Analysis & Synthesis ; 00:00:54 ; 3.7 ; 775 MB ; 00:01:32 ;
; Fitter ; 00:04:26 ; 1.6 ; 2824 MB ; 00:11:35 ;
; Assembler ; 00:00:06 ; 1.0 ; 628 MB ; 00:00:06 ;
; Timing Analyzer ; 00:00:19 ; 5.5 ; 1312 MB ; 00:01:25 ;
; Total ; 00:05:45 ; -- ; -- ; 00:14:38 ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+

315
output_files/chip8.map.rpt
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@ -1,5 +1,5 @@
Analysis & Synthesis report for chip8
Sun Apr 7 23:45:53 2024
Mon Apr 8 08:47:47 2024
Quartus Prime Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition
@ -21,14 +21,16 @@ Quartus Prime Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition
13. Registers Packed Into Inferred Megafunctions
14. Multiplexer Restructuring Statistics (Restructuring Performed)
15. Source assignments for memory:mem|altsyncram:mem_rtl_0|altsyncram_dsq1:auto_generated
16. Parameter Settings for User Entity Instance: memory:mem
17. Parameter Settings for Inferred Entity Instance: memory:mem|altsyncram:mem_rtl_0
18. altsyncram Parameter Settings by Entity Instance
19. Port Connectivity Checks: "cpu:cpu|st7920_serial_driver:gpu"
20. Port Connectivity Checks: "cpu:cpu"
21. Post-Synthesis Netlist Statistics for Top Partition
22. Elapsed Time Per Partition
23. Analysis & Synthesis Messages
16. Parameter Settings for User Entity Instance: downclocker:dc
17. Parameter Settings for User Entity Instance: memory:mem
18. Parameter Settings for Inferred Entity Instance: memory:mem|altsyncram:mem_rtl_0
19. altsyncram Parameter Settings by Entity Instance
20. Port Connectivity Checks: "cpu:cpu|st7920_serial_driver:gpu"
21. Port Connectivity Checks: "cpu:cpu"
22. Post-Synthesis Netlist Statistics for Top Partition
23. Elapsed Time Per Partition
24. Analysis & Synthesis Messages
25. Analysis & Synthesis Suppressed Messages
@ -55,13 +57,13 @@ https://fpgasoftware.intel.com/eula.
+----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+---------------------------------+------------------------------------------------+
; Analysis & Synthesis Status ; Successful - Sun Apr 7 23:45:53 2024 ;
; Analysis & Synthesis Status ; Successful - Mon Apr 8 08:47:47 2024 ;
; Quartus Prime Version ; 23.1std.0 Build 991 11/28/2023 SC Lite Edition ;
; Revision Name ; chip8 ;
; Top-level Entity Name ; chip8 ;
; Family ; Cyclone V ;
; Logic utilization (in ALMs) ; N/A ;
; Total registers ; 8728 ;
; Total registers ; 8836 ;
; Total pins ; 10 ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 32,768 ;
@ -170,22 +172,22 @@ https://fpgasoftware.intel.com/eula.
; Number detected on machine ; 12 ;
; Maximum allowed ; 12 ;
; ; ;
; Average used ; 3.71 ;
; Average used ; 3.67 ;
; Maximum used ; 12 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
; Processor 2 ; 48.5% ;
; Processor 3 ; 48.3% ;
; Processor 4 ; 24.0% ;
; Processor 5 ; 24.0% ;
; Processor 6 ; 24.0% ;
; Processor 7 ; 19.2% ;
; Processor 8 ; 19.2% ;
; Processor 9 ; 19.2% ;
; Processor 10 ; 18.8% ;
; Processor 11 ; 18.8% ;
; Processor 12 ; 7.5% ;
; Processor 2 ; 40.2% ;
; Processor 3 ; 40.2% ;
; Processor 4 ; 35.9% ;
; Processor 5 ; 35.8% ;
; Processor 6 ; 35.8% ;
; Processor 7 ; 25.7% ;
; Processor 8 ; 25.7% ;
; Processor 9 ; 6.9% ;
; Processor 10 ; 6.9% ;
; Processor 11 ; 6.9% ;
; Processor 12 ; 6.8% ;
+----------------------------+-------------+
@ -197,6 +199,9 @@ https://fpgasoftware.intel.com/eula.
; the-bomb/st7920_serial_driver.sv ; yes ; User SystemVerilog HDL File ; /home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv ; ;
; chip8.sv ; yes ; User SystemVerilog HDL File ; /home/nickorlow/programming/school/warminster/yayacemu/chip8.sv ; ;
; cpu.sv ; yes ; User SystemVerilog HDL File ; /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv ; ;
; alu.sv ; yes ; User SystemVerilog HDL File ; /home/nickorlow/programming/school/warminster/yayacemu/alu.sv ; ;
; aastructs.sv ; yes ; User SystemVerilog HDL File ; /home/nickorlow/programming/school/warminster/yayacemu/aastructs.sv ; ;
; downclocker.sv ; yes ; User SystemVerilog HDL File ; /home/nickorlow/programming/school/warminster/yayacemu/downclocker.sv ; ;
; memory.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/nickorlow/programming/school/warminster/yayacemu/memory.sv ; ;
; rom.bin ; yes ; Auto-Found Unspecified File ; /home/nickorlow/programming/school/warminster/yayacemu/rom.bin ; ;
; fontset.bin ; yes ; Auto-Found Unspecified File ; /home/nickorlow/programming/school/warminster/yayacemu/fontset.bin ; ;
@ -214,33 +219,33 @@ https://fpgasoftware.intel.com/eula.
+---------------------------------------+-----------------+-------------------------------------------------------+----------------------------------------------------------------------------------------------+---------+
+--------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+----------------+
; Resource ; Usage ;
+---------------------------------------------+----------------+
; Estimate of Logic utilization (ALMs needed) ; 10412 ;
; ; ;
; Combinational ALUT usage for logic ; 17065 ;
; -- 7 input functions ; 58 ;
; -- 6 input functions ; 3654 ;
; -- 5 input functions ; 5900 ;
; -- 4 input functions ; 2000 ;
; -- <=3 input functions ; 5453 ;
; ; ;
; Dedicated logic registers ; 8728 ;
; ; ;
; I/O pins ; 10 ;
; Total MLAB memory bits ; 0 ;
; Total block memory bits ; 32768 ;
; ; ;
; Total DSP Blocks ; 0 ;
; ; ;
; Maximum fan-out node ; fpga_clk~input ;
; Maximum fan-out ; 8564 ;
; Total fan-out ; 102143 ;
; Average fan-out ; 3.96 ;
+---------------------------------------------+----------------+
+----------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+------------------------+
; Resource ; Usage ;
+---------------------------------------------+------------------------+
; Estimate of Logic utilization (ALMs needed) ; 10507 ;
; ; ;
; Combinational ALUT usage for logic ; 17207 ;
; -- 7 input functions ; 56 ;
; -- 6 input functions ; 3707 ;
; -- 5 input functions ; 5934 ;
; -- 4 input functions ; 2008 ;
; -- <=3 input functions ; 5502 ;
; ; ;
; Dedicated logic registers ; 8836 ;
; ; ;
; I/O pins ; 10 ;
; Total MLAB memory bits ; 0 ;
; Total block memory bits ; 32768 ;
; ; ;
; Total DSP Blocks ; 0 ;
; ; ;
; Maximum fan-out node ; downclocker:dc|clk_out ;
; Maximum fan-out ; 8652 ;
; Total fan-out ; 103021 ;
; Average fan-out ; 3.95 ;
+---------------------------------------------+------------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
@ -248,10 +253,12 @@ https://fpgasoftware.intel.com/eula.
+-------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+-----------------------------------------------------------------------+----------------------+--------------+
; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
+-------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+-----------------------------------------------------------------------+----------------------+--------------+
; |chip8 ; 17065 (1) ; 8728 (0) ; 32768 ; 0 ; 10 ; 0 ; |chip8 ; chip8 ; work ;
; |cpu:cpu| ; 17064 (11448) ; 8728 (8546) ; 0 ; 0 ; 0 ; 0 ; |chip8|cpu:cpu ; cpu ; work ;
; |st7920_serial_driver:gpu| ; 5616 (5570) ; 182 (129) ; 0 ; 0 ; 0 ; 0 ; |chip8|cpu:cpu|st7920_serial_driver:gpu ; st7920_serial_driver ; work ;
; |chip8 ; 17207 (1) ; 8836 (0) ; 32768 ; 0 ; 10 ; 0 ; |chip8 ; chip8 ; work ;
; |cpu:cpu| ; 17195 (11517) ; 8825 (8594) ; 0 ; 0 ; 0 ; 0 ; |chip8|cpu:cpu ; cpu ; work ;
; |alu:alu| ; 47 (47) ; 49 (49) ; 0 ; 0 ; 0 ; 0 ; |chip8|cpu:cpu|alu:alu ; alu ; work ;
; |st7920_serial_driver:gpu| ; 5631 (5585) ; 182 (129) ; 0 ; 0 ; 0 ; 0 ; |chip8|cpu:cpu|st7920_serial_driver:gpu ; st7920_serial_driver ; work ;
; |commander:com| ; 46 (46) ; 53 (53) ; 0 ; 0 ; 0 ; 0 ; |chip8|cpu:cpu|st7920_serial_driver:gpu|commander:com ; commander ; work ;
; |downclocker:dc| ; 11 (11) ; 11 (11) ; 0 ; 0 ; 0 ; 0 ; |chip8|downclocker:dc ; downclocker ; work ;
; |memory:mem| ; 0 (0) ; 0 (0) ; 32768 ; 0 ; 0 ; 0 ; |chip8|memory:mem ; memory ; work ;
; |altsyncram:mem_rtl_0| ; 0 (0) ; 0 (0) ; 32768 ; 0 ; 0 ; 0 ; |chip8|memory:mem|altsyncram:mem_rtl_0 ; altsyncram ; work ;
; |altsyncram_dsq1:auto_generated| ; 0 (0) ; 0 (0) ; 32768 ; 0 ; 0 ; 0 ; |chip8|memory:mem|altsyncram:mem_rtl_0|altsyncram_dsq1:auto_generated ; altsyncram_dsq1 ; work ;
@ -275,23 +282,26 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+------------------------------------------------------------------------+---------------------------------------------+
; cpu:cpu|st7920_serial_driver:gpu|d_flip_flop:dff|data_out ; Stuck at VCC due to stuck port data_in ;
; cpu:cpu|wr_memory_address[0..11] ; Stuck at GND due to stuck port data_in ;
; cpu:cpu|compute_of ; Stuck at GND due to stuck port data_in ;
; cpu:cpu|instr.src_sprite_sz[4] ; Stuck at GND due to stuck port data_in ;
; cpu:cpu|instr.src_sprite_y[5..7] ; Stuck at GND due to stuck port data_in ;
; cpu:cpu|instr.src_sprite_x[6,7] ; Stuck at GND due to stuck port data_in ;
; cpu:cpu|instr.dst[1..31] ; Stuck at GND due to stuck port data_in ;
; cpu:cpu|instr.op[2..31] ; Stuck at GND due to stuck port data_in ;
; cpu:cpu|instr.op[3..31] ; Stuck at GND due to stuck port data_in ;
; cpu:cpu|alu:alu|overflow ; Lost fanout ;
; cpu:cpu|alu:alu|result_int[8] ; Lost fanout ;
; cpu:cpu|wr_memory_data[0..7] ; Stuck at GND due to stuck port clock_enable ;
; cpu:cpu|draw_state.stage[1..9,11..31] ; Merged with cpu:cpu|draw_state.stage[10] ;
; cpu:cpu|state[4..9,11..31] ; Merged with cpu:cpu|state[10] ;
; cpu:cpu|instr.src[3..31] ; Merged with cpu:cpu|instr.src[0] ;
; cpu:cpu|draw_state.stage[1..9,11..31] ; Merged with cpu:cpu|draw_state.stage[10] ;
; cpu:cpu|st7920_serial_driver:gpu|command[8] ; Stuck at GND due to stuck port data_in ;
; cpu:cpu|st7920_serial_driver:gpu|commander:com|full_command_bits[0..3] ; Stuck at GND due to stuck port data_in ;
; cpu:cpu|wr_go ; Stuck at GND due to stuck port data_in ;
; cpu:cpu|draw_state.stage[10] ; Stuck at GND due to stuck port data_in ;
; cpu:cpu|instr.src[0] ; Stuck at GND due to stuck port data_in ;
; cpu:cpu|state[10] ; Stuck at GND due to stuck port data_in ;
; cpu:cpu|program_counter[12..15] ; Lost fanout ;
; Total Number of Removed Registers = 187 ; ;
; cpu:cpu|instr.src[0] ; Stuck at GND due to stuck port data_in ;
; Total Number of Removed Registers = 189 ; ;
+------------------------------------------------------------------------+---------------------------------------------+
@ -309,8 +319,12 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; cpu:cpu|st7920_serial_driver:gpu|commander:com|full_command_bits[0] ; Stuck at GND ; cpu:cpu|st7920_serial_driver:gpu|commander:com|full_command_bits[1], ;
; ; due to stuck port data_in ; cpu:cpu|st7920_serial_driver:gpu|commander:com|full_command_bits[2], ;
; ; ; cpu:cpu|st7920_serial_driver:gpu|commander:com|full_command_bits[3] ;
; cpu:cpu|compute_of ; Stuck at GND ; cpu:cpu|alu:alu|overflow, cpu:cpu|alu:alu|result_int[8] ;
; ; due to stuck port data_in ; ;
; cpu:cpu|st7920_serial_driver:gpu|d_flip_flop:dff|data_out ; Stuck at VCC ; cpu:cpu|st7920_serial_driver:gpu|command[8] ;
; ; due to stuck port data_in ; ;
; cpu:cpu|instr.op[3] ; Stuck at GND ; cpu:cpu|instr.src[0] ;
; ; due to stuck port data_in ; ;
+---------------------------------------------------------------------+---------------------------+----------------------------------------------------------------------------------+
@ -319,12 +333,12 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 8728 ;
; Number of registers using Synchronous Clear ; 118 ;
; Number of registers using Synchronous Load ; 29 ;
; Total registers ; 8836 ;
; Number of registers using Synchronous Clear ; 169 ;
; Number of registers using Synchronous Load ; 21 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 8631 ;
; Number of registers using Clock Enable ; 8673 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
@ -334,8 +348,9 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+----------------------------------------+---------+
; Inverted Register ; Fan out ;
+----------------------------------------+---------+
; cpu:cpu|alu_rst ; 34 ;
; cpu:cpu|program_counter[9] ; 5 ;
; Total number of inverted registers = 1 ; ;
; Total number of inverted registers = 2 ; ;
+----------------------------------------+---------+
@ -353,27 +368,28 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------------------+
; 3:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|commander:com|full_command_bits[22] ;
; 3:1 ; 8 bits ; 16 LEs ; 0 LEs ; 16 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|commander:com|full_command_bits[17] ;
; 3:1 ; 38 bits ; 76 LEs ; 0 LEs ; 76 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|commander:com|i[9] ;
; 4:1 ; 32 bits ; 64 LEs ; 0 LEs ; 64 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|line_cnt[23] ;
; 4:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|x[5] ;
; 3:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|commander:com|full_command_bits[21] ;
; 3:1 ; 8 bits ; 16 LEs ; 0 LEs ; 16 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|commander:com|full_command_bits[5] ;
; 3:1 ; 38 bits ; 76 LEs ; 0 LEs ; 76 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|commander:com|i[15] ;
; 4:1 ; 32 bits ; 64 LEs ; 0 LEs ; 64 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|line_cnt[15] ;
; 4:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|x[4] ;
; 4:1 ; 7 bits ; 14 LEs ; 7 LEs ; 7 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|y[6] ;
; 5:1 ; 32 bits ; 96 LEs ; 32 LEs ; 64 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|i[1] ;
; 5:1 ; 32 bits ; 96 LEs ; 32 LEs ; 64 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|i[16] ;
; 1029:1 ; 2 bits ; 1372 LEs ; 1368 LEs ; 4 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|command[6] ;
; 1059:1 ; 5 bits ; 3530 LEs ; 3445 LEs ; 85 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|command[5] ;
; 3:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; Yes ; |chip8|cpu:cpu|draw_state.r[4] ;
; 4:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; Yes ; |chip8|cpu:cpu|draw_state.c[1] ;
; 16:1 ; 5 bits ; 50 LEs ; 50 LEs ; 0 LEs ; Yes ; |chip8|cpu:cpu|instr.src_sprite_y[4] ;
; 16:1 ; 6 bits ; 60 LEs ; 60 LEs ; 0 LEs ; Yes ; |chip8|cpu:cpu|instr.src_sprite_x[2] ;
; 4:1 ; 12 bits ; 24 LEs ; 0 LEs ; 24 LEs ; Yes ; |chip8|cpu:cpu|rd_memory_address[3] ;
; 5:1 ; 5 bits ; 15 LEs ; 5 LEs ; 10 LEs ; Yes ; |chip8|cpu:cpu|instr.src_sprite_idx[1] ;
; 5:1 ; 6 bits ; 18 LEs ; 6 LEs ; 12 LEs ; Yes ; |chip8|cpu:cpu|instr.src_byte[9] ;
; 5:1 ; 2 bits ; 6 LEs ; 2 LEs ; 4 LEs ; Yes ; |chip8|cpu:cpu|draw_state.stage[10] ;
; 6:1 ; 8 bits ; 32 LEs ; 0 LEs ; 32 LEs ; Yes ; |chip8|cpu:cpu|instr.src_byte[2] ;
; 6:1 ; 6 bits ; 24 LEs ; 12 LEs ; 12 LEs ; Yes ; |chip8|cpu:cpu|registers[15][5] ;
; 10:1 ; 4 bits ; 24 LEs ; 8 LEs ; 16 LEs ; Yes ; |chip8|cpu:cpu|program_counter[15] ;
; 10:1 ; 10 bits ; 60 LEs ; 20 LEs ; 40 LEs ; Yes ; |chip8|cpu:cpu|program_counter[1] ;
; 3:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; Yes ; |chip8|cpu:cpu|draw_state.r[0] ;
; 4:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; Yes ; |chip8|cpu:cpu|draw_state.c[3] ;
; 16:1 ; 8 bits ; 80 LEs ; 80 LEs ; 0 LEs ; Yes ; |chip8|cpu:cpu|instr.alu_i.operand_b[0] ;
; 16:1 ; 5 bits ; 50 LEs ; 50 LEs ; 0 LEs ; Yes ; |chip8|cpu:cpu|instr.src_sprite_y[0] ;
; 16:1 ; 6 bits ; 60 LEs ; 60 LEs ; 0 LEs ; Yes ; |chip8|cpu:cpu|instr.src_sprite_x[1] ;
; 4:1 ; 12 bits ; 24 LEs ; 0 LEs ; 24 LEs ; Yes ; |chip8|cpu:cpu|rd_memory_address[8] ;
; 5:1 ; 5 bits ; 15 LEs ; 5 LEs ; 10 LEs ; Yes ; |chip8|cpu:cpu|instr.src_sprite_idx[3] ;
; 5:1 ; 2 bits ; 6 LEs ; 2 LEs ; 4 LEs ; Yes ; |chip8|cpu:cpu|draw_state.stage[0] ;
; 7:1 ; 8 bits ; 32 LEs ; 8 LEs ; 24 LEs ; Yes ; |chip8|cpu:cpu|registers[15][5] ;
; 8:1 ; 6 bits ; 30 LEs ; 6 LEs ; 24 LEs ; Yes ; |chip8|cpu:cpu|instr.src_byte[11] ;
; 9:1 ; 4 bits ; 24 LEs ; 8 LEs ; 16 LEs ; Yes ; |chip8|cpu:cpu|program_counter[15] ;
; 9:1 ; 8 bits ; 48 LEs ; 16 LEs ; 32 LEs ; Yes ; |chip8|cpu:cpu|instr.src_byte[1] ;
; 12:1 ; 10 bits ; 80 LEs ; 20 LEs ; 60 LEs ; Yes ; |chip8|cpu:cpu|program_counter[10] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------------------+
@ -386,6 +402,16 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+---------------------------------+--------------------+------+-------------------------+
+-------------------------------------------------------------+
; Parameter Settings for User Entity Instance: downclocker:dc ;
+----------------+-------+------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+------------------------------------+
; DC_BITS ; 10 ; Signed Integer ;
+----------------+-------+------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+---------------------------------------------------------+
; Parameter Settings for User Entity Instance: memory:mem ;
+----------------+-------+--------------------------------+
@ -477,13 +503,14 @@ Note: In order to hide this table in the UI and the text report file, please set
+-------------------------------------------+---------------------------------+
+--------------------------------------------------------------+
; Port Connectivity Checks: "cpu:cpu|st7920_serial_driver:gpu" ;
+--------------+-------+----------+----------------------------+
; Port ; Type ; Severity ; Details ;
+--------------+-------+----------+----------------------------+
; sys_rst_n_ms ; Input ; Info ; Stuck at VCC ;
+--------------+-------+----------+----------------------------+
+------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "cpu:cpu|st7920_serial_driver:gpu" ;
+--------------+--------+----------+-------------------------------------------------------------------------------------+
; Port ; Type ; Severity ; Details ;
+--------------+--------+----------+-------------------------------------------------------------------------------------+
; sys_rst_n_ms ; Input ; Info ; Stuck at VCC ;
; led ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+--------------+--------+----------+-------------------------------------------------------------------------------------+
+-------------------------------------------------------------------------------------------------------------------------+
@ -500,38 +527,38 @@ Note: In order to hide this table in the UI and the text report file, please set
+-----------------------+-----------------------------+
; Type ; Count ;
+-----------------------+-----------------------------+
; arriav_ff ; 8728 ;
; ENA ; 8526 ;
; ENA SCLR ; 77 ;
; ENA SLD ; 28 ;
; SCLR ; 41 ;
; arriav_ff ; 8836 ;
; ENA ; 8568 ;
; ENA SCLR ; 85 ;
; ENA SLD ; 20 ;
; SCLR ; 84 ;
; SLD ; 1 ;
; plain ; 55 ;
; arriav_lcell_comb ; 17066 ;
; arith ; 257 ;
; plain ; 78 ;
; arriav_lcell_comb ; 17207 ;
; arith ; 307 ;
; 0 data inputs ; 7 ;
; 1 data inputs ; 229 ;
; 2 data inputs ; 17 ;
; 1 data inputs ; 271 ;
; 2 data inputs ; 25 ;
; 3 data inputs ; 1 ;
; 4 data inputs ; 1 ;
; 5 data inputs ; 2 ;
; extend ; 58 ;
; 7 data inputs ; 58 ;
; normal ; 16745 ;
; 0 data inputs ; 2 ;
; extend ; 56 ;
; 7 data inputs ; 56 ;
; normal ; 16838 ;
; 0 data inputs ; 1 ;
; 1 data inputs ; 1 ;
; 2 data inputs ; 176 ;
; 3 data inputs ; 5015 ;
; 4 data inputs ; 1999 ;
; 5 data inputs ; 5898 ;
; 6 data inputs ; 3654 ;
; 2 data inputs ; 198 ;
; 3 data inputs ; 4992 ;
; 4 data inputs ; 2007 ;
; 5 data inputs ; 5932 ;
; 6 data inputs ; 3707 ;
; shared ; 6 ;
; 2 data inputs ; 6 ;
; boundary_port ; 10 ;
; stratixv_ram_block ; 8 ;
; ; ;
; Max LUT depth ; 55.00 ;
; Average LUT depth ; 17.90 ;
; Average LUT depth ; 17.74 ;
+-----------------------+-----------------------------+
@ -540,7 +567,7 @@ Note: In order to hide this table in the UI and the text report file, please set
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top ; 00:00:53 ;
; Top ; 00:00:44 ;
+----------------+--------------+
@ -550,7 +577,7 @@ Note: In order to hide this table in the UI and the text report file, please set
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
Info: Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition
Info: Processing started: Sun Apr 7 23:44:51 2024
Info: Processing started: Mon Apr 8 08:46:51 2024
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off chip8 -c chip8
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 12 of the 12 processors detected
@ -561,27 +588,37 @@ Info (12021): Found 3 design units, including 3 entities, in source file the-bom
Info (12021): Found 1 design units, including 1 entities, in source file chip8.sv
Info (12023): Found entity 1: chip8 File: /home/nickorlow/programming/school/warminster/yayacemu/chip8.sv Line: 1
Info (12021): Found 1 design units, including 1 entities, in source file cpu.sv
Info (12023): Found entity 1: cpu File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 1
Info (12023): Found entity 1: cpu File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 3
Info (12021): Found 1 design units, including 1 entities, in source file alu.sv
Info (12023): Found entity 1: alu File: /home/nickorlow/programming/school/warminster/yayacemu/alu.sv Line: 3
Info (12021): Found 1 design units, including 0 entities, in source file aastructs.sv
Info (12022): Found design unit 1: structs (SystemVerilog) File: /home/nickorlow/programming/school/warminster/yayacemu/aastructs.sv Line: 1
Info (12021): Found 1 design units, including 1 entities, in source file downclocker.sv
Info (12023): Found entity 1: downclocker File: /home/nickorlow/programming/school/warminster/yayacemu/downclocker.sv Line: 1
Info (12127): Elaborating entity "chip8" for the top level hierarchy
Info (12128): Elaborating entity "downclocker" for hierarchy "downclocker:dc" File: /home/nickorlow/programming/school/warminster/yayacemu/chip8.sv Line: 14
Warning (10230): Verilog HDL assignment warning at downclocker.sv(18): truncated value with size 32 to match size of target (10) File: /home/nickorlow/programming/school/warminster/yayacemu/downclocker.sv Line: 18
Warning (12125): Using design file memory.sv, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info (12023): Found entity 1: memory File: /home/nickorlow/programming/school/warminster/yayacemu/memory.sv Line: 1
Info (12128): Elaborating entity "memory" for hierarchy "memory:mem" File: /home/nickorlow/programming/school/warminster/yayacemu/chip8.sv Line: 21
Info (12128): Elaborating entity "memory" for hierarchy "memory:mem" File: /home/nickorlow/programming/school/warminster/yayacemu/chip8.sv Line: 29
Warning (10850): Verilog HDL warning at memory.sv(14): number of words (80) in memory file does not match the number of elements in the address range [0:4095] File: /home/nickorlow/programming/school/warminster/yayacemu/memory.sv Line: 14
Warning (10850): Verilog HDL warning at memory.sv(15): number of words (260) in memory file does not match the number of elements in the address range [512:4095] File: /home/nickorlow/programming/school/warminster/yayacemu/memory.sv Line: 15
Info (12128): Elaborating entity "cpu" for hierarchy "cpu:cpu" File: /home/nickorlow/programming/school/warminster/yayacemu/chip8.sv Line: 35
Warning (10230): Verilog HDL assignment warning at cpu.sv(124): truncated value with size 32 to match size of target (16) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 124
Warning (10230): Verilog HDL assignment warning at cpu.sv(130): truncated value with size 32 to match size of target (16) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 130
Warning (10230): Verilog HDL assignment warning at cpu.sv(147): truncated value with size 32 to match size of target (16) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 147
Warning (10230): Verilog HDL assignment warning at cpu.sv(210): truncated value with size 32 to match size of target (5) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 210
Warning (10230): Verilog HDL assignment warning at cpu.sv(213): truncated value with size 32 to match size of target (5) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 213
Warning (10230): Verilog HDL assignment warning at cpu.sv(242): truncated value with size 32 to match size of target (16) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 242
Warning (10230): Verilog HDL assignment warning at cpu.sv(246): truncated value with size 32 to match size of target (5) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 246
Warning (10230): Verilog HDL assignment warning at cpu.sv(257): truncated value with size 32 to match size of target (5) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 257
Warning (10230): Verilog HDL assignment warning at cpu.sv(284): truncated value with size 32 to match size of target (16) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 284
Warning (10030): Net "instr.src_reg" at cpu.sv(108) has no driver or initial value, using a default initial value '0' File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 108
Warning (10030): Net "instr.src_addr" at cpu.sv(108) has no driver or initial value, using a default initial value '0' File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 108
Warning (10030): Net "instr.dst_addr" at cpu.sv(108) has no driver or initial value, using a default initial value '0' File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 108
Info (12128): Elaborating entity "st7920_serial_driver" for hierarchy "cpu:cpu|st7920_serial_driver:gpu" File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 28
Warning (10850): Verilog HDL warning at memory.sv(15): number of words (132) in memory file does not match the number of elements in the address range [512:4095] File: /home/nickorlow/programming/school/warminster/yayacemu/memory.sv Line: 15
Info (12128): Elaborating entity "cpu" for hierarchy "cpu:cpu" File: /home/nickorlow/programming/school/warminster/yayacemu/chip8.sv Line: 44
Warning (10230): Verilog HDL assignment warning at cpu.sv(148): truncated value with size 32 to match size of target (16) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 148
Warning (10230): Verilog HDL assignment warning at cpu.sv(154): truncated value with size 32 to match size of target (16) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 154
Warning (10230): Verilog HDL assignment warning at cpu.sv(171): truncated value with size 32 to match size of target (16) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 171
Warning (10230): Verilog HDL assignment warning at cpu.sv(249): truncated value with size 32 to match size of target (5) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 249
Warning (10230): Verilog HDL assignment warning at cpu.sv(252): truncated value with size 32 to match size of target (5) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 252
Warning (10230): Verilog HDL assignment warning at cpu.sv(281): truncated value with size 32 to match size of target (16) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 281
Warning (10230): Verilog HDL assignment warning at cpu.sv(285): truncated value with size 32 to match size of target (5) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 285
Warning (10230): Verilog HDL assignment warning at cpu.sv(296): truncated value with size 32 to match size of target (5) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 296
Warning (10230): Verilog HDL assignment warning at cpu.sv(323): truncated value with size 32 to match size of target (16) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 323
Warning (10230): Verilog HDL assignment warning at cpu.sv(333): truncated value with size 32 to match size of target (16) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 333
Warning (10030): Net "instr.src_reg" at cpu.sv(131) has no driver or initial value, using a default initial value '0' File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 131
Warning (10030): Net "instr.src_addr" at cpu.sv(131) has no driver or initial value, using a default initial value '0' File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 131
Warning (10030): Net "instr.dst_addr" at cpu.sv(131) has no driver or initial value, using a default initial value '0' File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 131
Info (12128): Elaborating entity "alu" for hierarchy "cpu:cpu|alu:alu" File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 33
Info (12128): Elaborating entity "st7920_serial_driver" for hierarchy "cpu:cpu|st7920_serial_driver:gpu" File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 49
Warning (10036): Verilog HDL or VHDL warning at st7920_serial_driver.sv(23): object "line_idx" assigned a value but never read File: /home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv Line: 23
Warning (10230): Verilog HDL assignment warning at st7920_serial_driver.sv(71): truncated value with size 32 to match size of target (7) File: /home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv Line: 71
Warning (10230): Verilog HDL assignment warning at st7920_serial_driver.sv(84): truncated value with size 32 to match size of target (7) File: /home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv Line: 84
@ -629,22 +666,30 @@ Info (12133): Instantiated megafunction "memory:mem|altsyncram:mem_rtl_0" with t
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_dsq1.tdf
Info (12023): Found entity 1: altsyncram_dsq1 File: /home/nickorlow/programming/school/warminster/yayacemu/db/altsyncram_dsq1.tdf Line: 28
Warning (13024): Output pins are stuck at VCC or GND
Warning (13410): Pin "led[5]" is stuck at VCC File: /home/nickorlow/programming/school/warminster/yayacemu/chip8.sv Line: 7
Warning (13410): Pin "led[4]" is stuck at GND File: /home/nickorlow/programming/school/warminster/yayacemu/chip8.sv Line: 7
Warning (13410): Pin "led[5]" is stuck at GND File: /home/nickorlow/programming/school/warminster/yayacemu/chip8.sv Line: 7
Info (286030): Timing-Driven Synthesis is running
Info (17049): 4 registers lost all their fanouts during netlist optimizations.
Info (17049): 6 registers lost all their fanouts during netlist optimizations.
Info (144001): Generated suppressed messages file /home/nickorlow/programming/school/warminster/yayacemu/output_files/chip8.map.smsg
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
Warning (21074): Design contains 1 input pin(s) that do not drive logic
Warning (15610): No output dependent on input pin "rst_in" File: /home/nickorlow/programming/school/warminster/yayacemu/chip8.sv Line: 3
Info (21057): Implemented 17374 device resources after synthesis - the final resource count might be different
Info (21057): Implemented 17552 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 2 input pins
Info (21059): Implemented 8 output pins
Info (21061): Implemented 17356 logic cells
Info (21061): Implemented 17534 logic cells
Info (21064): Implemented 8 RAM segments
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 26 warnings
Info: Peak virtual memory: 698 megabytes
Info: Processing ended: Sun Apr 7 23:45:53 2024
Info: Elapsed time: 00:01:02
Info: Total CPU time (on all processors): 00:01:46
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 29 warnings
Info: Peak virtual memory: 775 megabytes
Info: Processing ended: Mon Apr 8 08:47:47 2024
Info: Elapsed time: 00:00:56
Info: Total CPU time (on all processors): 00:01:34
+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in /home/nickorlow/programming/school/warminster/yayacemu/output_files/chip8.map.smsg.

4
output_files/chip8.map.summary
View file

@ -1,10 +1,10 @@
Analysis & Synthesis Status : Successful - Sun Apr 7 23:45:53 2024
Analysis & Synthesis Status : Successful - Mon Apr 8 08:47:47 2024
Quartus Prime Version : 23.1std.0 Build 991 11/28/2023 SC Lite Edition
Revision Name : chip8
Top-level Entity Name : chip8
Family : Cyclone V
Logic utilization (in ALMs) : N/A
Total registers : 8728
Total registers : 8836
Total pins : 10
Total virtual pins : 0
Total block memory bits : 32,768

BIN
output_files/chip8.sof
View file

Binary file not shown.

243
output_files/chip8.sta.rpt
View file

@ -1,5 +1,5 @@
Timing Analyzer report for chip8
Sun Apr 7 23:52:43 2024
Mon Apr 8 08:52:45 2024
Quartus Prime Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition
@ -98,22 +98,22 @@ https://fpgasoftware.intel.com/eula.
; Number detected on machine ; 12 ;
; Maximum allowed ; 12 ;
; ; ;
; Average used ; 5.73 ;
; Average used ; 5.48 ;
; Maximum used ; 12 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
; Processor 2 ; 60.4% ;
; Processor 3 ; 57.0% ;
; Processor 4 ; 55.9% ;
; Processor 5 ; 37.5% ;
; Processor 6 ; 37.5% ;
; Processor 7 ; 37.5% ;
; Processor 8 ; 37.5% ;
; Processor 9 ; 37.5% ;
; Processor 10 ; 37.5% ;
; Processor 11 ; 37.5% ;
; Processor 12 ; 37.5% ;
; Processor 2 ; 56.2% ;
; Processor 3 ; 54.6% ;
; Processor 4 ; 54.0% ;
; Processor 5 ; 35.4% ;
; Processor 6 ; 35.4% ;
; Processor 7 ; 35.4% ;
; Processor 8 ; 35.4% ;
; Processor 9 ; 35.4% ;
; Processor 10 ; 35.4% ;
; Processor 11 ; 35.4% ;
; Processor 12 ; 35.4% ;
+----------------------------+-------------+
@ -123,18 +123,20 @@ https://fpgasoftware.intel.com/eula.
; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
+------------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------------------------------------------+
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { cpu:cpu|st7920_serial_driver:gpu|lcd_clk } ;
; downclocker:dc|clk_out ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { downclocker:dc|clk_out } ;
; fpga_clk ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { fpga_clk } ;
+------------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------------------------------------------+
+-------------------------------------------------------------------------------+
; Slow 1100mV 100C Model Fmax Summary ;
+-----------+-----------------+------------------------------------------+------+
; Fmax ; Restricted Fmax ; Clock Name ; Note ;
+-----------+-----------------+------------------------------------------+------+
; 34.01 MHz ; 34.01 MHz ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; ;
; 82.06 MHz ; 82.06 MHz ; fpga_clk ; ;
+-----------+-----------------+------------------------------------------+------+
+--------------------------------------------------------------------------------+
; Slow 1100mV 100C Model Fmax Summary ;
+------------+-----------------+------------------------------------------+------+
; Fmax ; Restricted Fmax ; Clock Name ; Note ;
+------------+-----------------+------------------------------------------+------+
; 31.39 MHz ; 31.39 MHz ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; ;
; 82.93 MHz ; 82.93 MHz ; downclocker:dc|clk_out ; ;
; 189.18 MHz ; 189.18 MHz ; fpga_clk ; ;
+------------+-----------------+------------------------------------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
@ -149,8 +151,9 @@ HTML report is unavailable in plain text report export.
+------------------------------------------+---------+---------------+
; Clock ; Slack ; End Point TNS ;
+------------------------------------------+---------+---------------+
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -28.406 ; -1742.530 ;
; fpga_clk ; -11.186 ; -95769.392 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -31.412 ; -1884.356 ;
; downclocker:dc|clk_out ; -11.058 ; -87363.415 ;
; fpga_clk ; -4.953 ; -27.713 ;
+------------------------------------------+---------+---------------+
@ -159,8 +162,9 @@ HTML report is unavailable in plain text report export.
+------------------------------------------+-------+---------------+
; Clock ; Slack ; End Point TNS ;
+------------------------------------------+-------+---------------+
; fpga_clk ; 0.429 ; 0.000 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 0.476 ; 0.000 ;
; downclocker:dc|clk_out ; 0.429 ; 0.000 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 0.501 ; 0.000 ;
; fpga_clk ; 0.814 ; 0.000 ;
+------------------------------------------+-------+---------------+
@ -181,8 +185,9 @@ No paths to report.
+------------------------------------------+--------+---------------+
; Clock ; Slack ; End Point TNS ;
+------------------------------------------+--------+---------------+
; fpga_clk ; -2.636 ; -8463.323 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -0.538 ; -185.389 ;
; downclocker:dc|clk_out ; -2.636 ; -8430.055 ;
; fpga_clk ; -0.622 ; -17.105 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -0.538 ; -172.550 ;
+------------------------------------------+--------+---------------+
@ -193,14 +198,15 @@ Design MTBF is not calculated because the design doesn't meet its timing require
+-------------------------------------------------------------------------------+
; Slow 1100mV -40C Model Fmax Summary ;
+-----------+-----------------+------------------------------------------+------+
; Fmax ; Restricted Fmax ; Clock Name ; Note ;
+-----------+-----------------+------------------------------------------+------+
; 35.8 MHz ; 35.8 MHz ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; ;
; 81.78 MHz ; 81.78 MHz ; fpga_clk ; ;
+-----------+-----------------+------------------------------------------+------+
+--------------------------------------------------------------------------------+
; Slow 1100mV -40C Model Fmax Summary ;
+------------+-----------------+------------------------------------------+------+
; Fmax ; Restricted Fmax ; Clock Name ; Note ;
+------------+-----------------+------------------------------------------+------+
; 33.23 MHz ; 33.23 MHz ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; ;
; 82.94 MHz ; 82.94 MHz ; downclocker:dc|clk_out ; ;
; 185.36 MHz ; 185.36 MHz ; fpga_clk ; ;
+------------+-----------------+------------------------------------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
@ -209,8 +215,9 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
+------------------------------------------+---------+---------------+
; Clock ; Slack ; End Point TNS ;
+------------------------------------------+---------+---------------+
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -26.933 ; -1684.576 ;
; fpga_clk ; -11.228 ; -94100.779 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -29.494 ; -1798.010 ;
; downclocker:dc|clk_out ; -11.057 ; -87142.095 ;
; fpga_clk ; -4.658 ; -29.299 ;
+------------------------------------------+---------+---------------+
@ -219,8 +226,9 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
+------------------------------------------+-------+---------------+
; Clock ; Slack ; End Point TNS ;
+------------------------------------------+-------+---------------+
; fpga_clk ; 0.484 ; 0.000 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 0.565 ; 0.000 ;
; downclocker:dc|clk_out ; 0.483 ; 0.000 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 0.546 ; 0.000 ;
; fpga_clk ; 0.786 ; 0.000 ;
+------------------------------------------+-------+---------------+
@ -241,8 +249,9 @@ No paths to report.
+------------------------------------------+--------+---------------+
; Clock ; Slack ; End Point TNS ;
+------------------------------------------+--------+---------------+
; fpga_clk ; -2.636 ; -8927.522 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -0.538 ; -184.012 ;
; downclocker:dc|clk_out ; -2.636 ; -8301.987 ;
; fpga_clk ; -0.627 ; -18.184 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -0.538 ; -170.070 ;
+------------------------------------------+--------+---------------+
@ -258,8 +267,9 @@ Design MTBF is not calculated because the design doesn't meet its timing require
+------------------------------------------+---------+---------------+
; Clock ; Slack ; End Point TNS ;
+------------------------------------------+---------+---------------+
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -14.774 ; -901.498 ;
; fpga_clk ; -6.214 ; -50560.530 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -16.301 ; -1018.017 ;
; downclocker:dc|clk_out ; -5.608 ; -44394.911 ;
; fpga_clk ; -3.718 ; -8.178 ;
+------------------------------------------+---------+---------------+
@ -268,8 +278,9 @@ Design MTBF is not calculated because the design doesn't meet its timing require
+------------------------------------------+-------+---------------+
; Clock ; Slack ; End Point TNS ;
+------------------------------------------+-------+---------------+
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 0.162 ; 0.000 ;
; fpga_clk ; 0.177 ; 0.000 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 0.160 ; 0.000 ;
; downclocker:dc|clk_out ; 0.177 ; 0.000 ;
; fpga_clk ; 0.303 ; 0.000 ;
+------------------------------------------+-------+---------------+
@ -290,8 +301,9 @@ No paths to report.
+------------------------------------------+--------+---------------+
; Clock ; Slack ; End Point TNS ;
+------------------------------------------+--------+---------------+
; fpga_clk ; -2.174 ; -1371.543 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -0.192 ; -9.702 ;
; downclocker:dc|clk_out ; -2.174 ; -537.344 ;
; fpga_clk ; -0.517 ; -2.901 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -0.144 ; -6.507 ;
+------------------------------------------+--------+---------------+
@ -307,8 +319,9 @@ Design MTBF is not calculated because the design doesn't meet its timing require
+------------------------------------------+---------+---------------+
; Clock ; Slack ; End Point TNS ;
+------------------------------------------+---------+---------------+
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -12.462 ; -739.747 ;
; fpga_clk ; -4.930 ; -40871.978 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -14.004 ; -820.600 ;
; downclocker:dc|clk_out ; -4.541 ; -36337.093 ;
; fpga_clk ; -2.859 ; -5.427 ;
+------------------------------------------+---------+---------------+
@ -317,8 +330,9 @@ Design MTBF is not calculated because the design doesn't meet its timing require
+------------------------------------------+-------+---------------+
; Clock ; Slack ; End Point TNS ;
+------------------------------------------+-------+---------------+
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 0.140 ; 0.000 ;
; fpga_clk ; 0.164 ; 0.000 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 0.138 ; 0.000 ;
; downclocker:dc|clk_out ; 0.164 ; 0.000 ;
; fpga_clk ; 0.289 ; 0.000 ;
+------------------------------------------+-------+---------------+
@ -339,8 +353,9 @@ No paths to report.
+------------------------------------------+--------+---------------+
; Clock ; Slack ; End Point TNS ;
+------------------------------------------+--------+---------------+
; fpga_clk ; -2.174 ; -1373.239 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -0.137 ; -3.355 ;
; downclocker:dc|clk_out ; -2.174 ; -534.258 ;
; fpga_clk ; -0.533 ; -2.899 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -0.057 ; -2.411 ;
+------------------------------------------+--------+---------------+
@ -356,12 +371,14 @@ Design MTBF is not calculated because the design doesn't meet its timing require
+-------------------------------------------+------------+-------+----------+---------+---------------------+
; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
+-------------------------------------------+------------+-------+----------+---------+---------------------+
; Worst-case Slack ; -28.406 ; 0.140 ; N/A ; N/A ; -2.636 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -28.406 ; 0.140 ; N/A ; N/A ; -0.538 ;
; fpga_clk ; -11.228 ; 0.164 ; N/A ; N/A ; -2.636 ;
; Design-wide TNS ; -97511.922 ; 0.0 ; 0.0 ; 0.0 ; -9111.534 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -1742.530 ; 0.000 ; N/A ; N/A ; -185.389 ;
; fpga_clk ; -95769.392 ; 0.000 ; N/A ; N/A ; -8927.522 ;
; Worst-case Slack ; -31.412 ; 0.138 ; N/A ; N/A ; -2.636 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -31.412 ; 0.138 ; N/A ; N/A ; -0.538 ;
; downclocker:dc|clk_out ; -11.058 ; 0.164 ; N/A ; N/A ; -2.636 ;
; fpga_clk ; -4.953 ; 0.289 ; N/A ; N/A ; -0.627 ;
; Design-wide TNS ; -89275.484 ; 0.0 ; 0.0 ; 0.0 ; -8619.71 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -1884.356 ; 0.000 ; N/A ; N/A ; -172.550 ;
; downclocker:dc|clk_out ; -87363.415 ; 0.000 ; N/A ; N/A ; -8430.055 ;
; fpga_clk ; -29.299 ; 0.000 ; N/A ; N/A ; -18.184 ;
+-------------------------------------------+------------+-------+----------+---------+---------------------+
@ -460,10 +477,12 @@ Design MTBF is not calculated because the design doesn't meet its timing require
+------------------------------------------+------------------------------------------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------------------------------------+------------------------------------------+----------+----------+----------+----------+
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 2667 ; 137 ; 0 ; 1681347 ;
; fpga_clk ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 0 ; 0 ; 9878 ; 0 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 2393 ; 126 ; 0 ; 1681819 ;
; downclocker:dc|clk_out ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 0 ; 0 ; 9878 ; 0 ;
; downclocker:dc|clk_out ; downclocker:dc|clk_out ; 13182899 ; 148 ; 48 ; 0 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; fpga_clk ; 1 ; 1 ; 0 ; 0 ;
; fpga_clk ; fpga_clk ; 12902566 ; 152 ; 48 ; 0 ;
; downclocker:dc|clk_out ; fpga_clk ; 1 ; 1 ; 0 ; 0 ;
; fpga_clk ; fpga_clk ; 121 ; 0 ; 0 ; 0 ;
+------------------------------------------+------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
@ -473,10 +492,12 @@ Entries labeled "false path" only account for clock-to-clock false paths and not
+------------------------------------------+------------------------------------------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------------------------------------+------------------------------------------+----------+----------+----------+----------+
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 2667 ; 137 ; 0 ; 1681347 ;
; fpga_clk ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 0 ; 0 ; 9878 ; 0 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 2393 ; 126 ; 0 ; 1681819 ;
; downclocker:dc|clk_out ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 0 ; 0 ; 9878 ; 0 ;
; downclocker:dc|clk_out ; downclocker:dc|clk_out ; 13182899 ; 148 ; 48 ; 0 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; fpga_clk ; 1 ; 1 ; 0 ; 0 ;
; fpga_clk ; fpga_clk ; 12902566 ; 152 ; 48 ; 0 ;
; downclocker:dc|clk_out ; fpga_clk ; 1 ; 1 ; 0 ; 0 ;
; fpga_clk ; fpga_clk ; 121 ; 0 ; 0 ; 0 ;
+------------------------------------------+------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
@ -502,8 +523,8 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
; Unconstrained Clocks ; 0 ; 0 ;
; Unconstrained Input Ports ; 0 ; 0 ;
; Unconstrained Input Port Paths ; 0 ; 0 ;
; Unconstrained Output Ports ; 7 ; 7 ;
; Unconstrained Output Port Paths ; 7 ; 7 ;
; Unconstrained Output Ports ; 6 ; 6 ;
; Unconstrained Output Port Paths ; 6 ; 6 ;
+---------------------------------+-------+------+
@ -513,6 +534,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
; Target ; Clock ; Type ; Status ;
+------------------------------------------+------------------------------------------+------+-------------+
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; Base ; Constrained ;
; downclocker:dc|clk_out ; downclocker:dc|clk_out ; Base ; Constrained ;
; fpga_clk ; fpga_clk ; Base ; Constrained ;
+------------------------------------------+------------------------------------------+------+-------------+
@ -528,7 +550,6 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
; led[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; led[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; led[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; led[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+-------------+---------------------------------------------------------------------------------------+
@ -543,7 +564,6 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
; led[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; led[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; led[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; led[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+-------------+---------------------------------------------------------------------------------------+
@ -553,7 +573,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
Info: *******************************************************************
Info: Running Quartus Prime Timing Analyzer
Info: Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition
Info: Processing started: Sun Apr 7 23:52:18 2024
Info: Processing started: Mon Apr 8 08:52:26 2024
Info: Command: quartus_sta chip8 -c chip8
Info: qsta_default_script.tcl version: #1
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
@ -565,29 +585,33 @@ Info (332142): No user constrained base clocks found in the design. Calling "der
Info (332105): Deriving Clocks
Info (332105): create_clock -period 1.000 -name fpga_clk fpga_clk
Info (332105): create_clock -period 1.000 -name cpu:cpu|st7920_serial_driver:gpu|lcd_clk cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332105): create_clock -period 1.000 -name downclocker:dc|clk_out downclocker:dc|clk_out
Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Analyzing Slow 1100mV 100C Model
Critical Warning (332148): Timing requirements not met
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer.
Info (332146): Worst-case setup slack is -28.406
Info (332146): Worst-case setup slack is -31.412
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -28.406 -1742.530 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332119): -11.186 -95769.392 fpga_clk
Info (332119): -31.412 -1884.356 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332119): -11.058 -87363.415 downclocker:dc|clk_out
Info (332119): -4.953 -27.713 fpga_clk
Info (332146): Worst-case hold slack is 0.429
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 0.429 0.000 fpga_clk
Info (332119): 0.476 0.000 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332119): 0.429 0.000 downclocker:dc|clk_out
Info (332119): 0.501 0.000 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332119): 0.814 0.000 fpga_clk
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is -2.636
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -2.636 -8463.323 fpga_clk
Info (332119): -0.538 -185.389 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332119): -2.636 -8430.055 downclocker:dc|clk_out
Info (332119): -0.622 -17.105 fpga_clk
Info (332119): -0.538 -172.550 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332114): Report Metastability: Found 8 synchronizer chains.
Info (332114): Design MTBF is not calculated because the design doesn't meet its timing requirements.
Info: Analyzing Slow 1100mV -40C Model
@ -596,23 +620,26 @@ Info (334004): Delay annotation completed successfully
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer.
Info (332146): Worst-case setup slack is -26.933
Info (332146): Worst-case setup slack is -29.494
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -26.933 -1684.576 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332119): -11.228 -94100.779 fpga_clk
Info (332146): Worst-case hold slack is 0.484
Info (332119): -29.494 -1798.010 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332119): -11.057 -87142.095 downclocker:dc|clk_out
Info (332119): -4.658 -29.299 fpga_clk
Info (332146): Worst-case hold slack is 0.483
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 0.484 0.000 fpga_clk
Info (332119): 0.565 0.000 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332119): 0.483 0.000 downclocker:dc|clk_out
Info (332119): 0.546 0.000 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332119): 0.786 0.000 fpga_clk
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is -2.636
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -2.636 -8927.522 fpga_clk
Info (332119): -0.538 -184.012 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332119): -2.636 -8301.987 downclocker:dc|clk_out
Info (332119): -0.627 -18.184 fpga_clk
Info (332119): -0.538 -170.070 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332114): Report Metastability: Found 8 synchronizer chains.
Info (332114): Design MTBF is not calculated because the design doesn't meet its timing requirements.
Info: Analyzing Fast 1100mV 100C Model
@ -621,54 +648,60 @@ Info (334004): Delay annotation completed successfully
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer.
Info (332146): Worst-case setup slack is -14.774
Info (332146): Worst-case setup slack is -16.301
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -14.774 -901.498 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332119): -6.214 -50560.530 fpga_clk
Info (332146): Worst-case hold slack is 0.162
Info (332119): -16.301 -1018.017 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332119): -5.608 -44394.911 downclocker:dc|clk_out
Info (332119): -3.718 -8.178 fpga_clk
Info (332146): Worst-case hold slack is 0.160
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 0.162 0.000 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332119): 0.177 0.000 fpga_clk
Info (332119): 0.160 0.000 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332119): 0.177 0.000 downclocker:dc|clk_out
Info (332119): 0.303 0.000 fpga_clk
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is -2.174
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -2.174 -1371.543 fpga_clk
Info (332119): -0.192 -9.702 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332119): -2.174 -537.344 downclocker:dc|clk_out
Info (332119): -0.517 -2.901 fpga_clk
Info (332119): -0.144 -6.507 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332114): Report Metastability: Found 8 synchronizer chains.
Info (332114): Design MTBF is not calculated because the design doesn't meet its timing requirements.
Info: Analyzing Fast 1100mV -40C Model
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer.
Info (332146): Worst-case setup slack is -12.462
Info (332146): Worst-case setup slack is -14.004
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -12.462 -739.747 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332119): -4.930 -40871.978 fpga_clk
Info (332146): Worst-case hold slack is 0.140
Info (332119): -14.004 -820.600 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332119): -4.541 -36337.093 downclocker:dc|clk_out
Info (332119): -2.859 -5.427 fpga_clk
Info (332146): Worst-case hold slack is 0.138
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 0.140 0.000 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332119): 0.164 0.000 fpga_clk
Info (332119): 0.138 0.000 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332119): 0.164 0.000 downclocker:dc|clk_out
Info (332119): 0.289 0.000 fpga_clk
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is -2.174
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -2.174 -1373.239 fpga_clk
Info (332119): -0.137 -3.355 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332119): -2.174 -534.258 downclocker:dc|clk_out
Info (332119): -0.533 -2.899 fpga_clk
Info (332119): -0.057 -2.411 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332114): Report Metastability: Found 8 synchronizer chains.
Info (332114): Design MTBF is not calculated because the design doesn't meet its timing requirements.
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings
Info: Peak virtual memory: 1353 megabytes
Info: Processing ended: Sun Apr 7 23:52:43 2024
Info: Elapsed time: 00:00:25
Info: Total CPU time (on all processors): 00:01:44
Info: Peak virtual memory: 1312 megabytes
Info: Processing ended: Mon Apr 8 08:52:45 2024
Info: Elapsed time: 00:00:19
Info: Total CPU time (on all processors): 00:01:25

144
output_files/chip8.sta.summary
View file

@ -3,99 +3,147 @@ Timing Analyzer Summary
------------------------------------------------------------
Type : Slow 1100mV 100C Model Setup 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk'
Slack : -28.406
TNS : -1742.530
Slack : -31.412
TNS : -1884.356
Type : Slow 1100mV 100C Model Setup 'downclocker:dc|clk_out'
Slack : -11.058
TNS : -87363.415
Type : Slow 1100mV 100C Model Setup 'fpga_clk'
Slack : -11.186
TNS : -95769.392
Slack : -4.953
TNS : -27.713
Type : Slow 1100mV 100C Model Hold 'fpga_clk'
Type : Slow 1100mV 100C Model Hold 'downclocker:dc|clk_out'
Slack : 0.429
TNS : 0.000
Type : Slow 1100mV 100C Model Hold 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk'
Slack : 0.476
Slack : 0.501
TNS : 0.000
Type : Slow 1100mV 100C Model Minimum Pulse Width 'fpga_clk'
Type : Slow 1100mV 100C Model Hold 'fpga_clk'
Slack : 0.814
TNS : 0.000
Type : Slow 1100mV 100C Model Minimum Pulse Width 'downclocker:dc|clk_out'
Slack : -2.636
TNS : -8463.323
TNS : -8430.055
Type : Slow 1100mV 100C Model Minimum Pulse Width 'fpga_clk'
Slack : -0.622
TNS : -17.105
Type : Slow 1100mV 100C Model Minimum Pulse Width 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk'
Slack : -0.538
TNS : -185.389
TNS : -172.550
Type : Slow 1100mV -40C Model Setup 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk'
Slack : -26.933
TNS : -1684.576
Slack : -29.494
TNS : -1798.010
Type : Slow 1100mV -40C Model Setup 'downclocker:dc|clk_out'
Slack : -11.057
TNS : -87142.095
Type : Slow 1100mV -40C Model Setup 'fpga_clk'
Slack : -11.228
TNS : -94100.779
Slack : -4.658
TNS : -29.299
Type : Slow 1100mV -40C Model Hold 'fpga_clk'
Slack : 0.484
Type : Slow 1100mV -40C Model Hold 'downclocker:dc|clk_out'
Slack : 0.483
TNS : 0.000
Type : Slow 1100mV -40C Model Hold 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk'
Slack : 0.565
Slack : 0.546
TNS : 0.000
Type : Slow 1100mV -40C Model Minimum Pulse Width 'fpga_clk'
Type : Slow 1100mV -40C Model Hold 'fpga_clk'
Slack : 0.786
TNS : 0.000
Type : Slow 1100mV -40C Model Minimum Pulse Width 'downclocker:dc|clk_out'
Slack : -2.636
TNS : -8927.522
TNS : -8301.987
Type : Slow 1100mV -40C Model Minimum Pulse Width 'fpga_clk'
Slack : -0.627
TNS : -18.184
Type : Slow 1100mV -40C Model Minimum Pulse Width 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk'
Slack : -0.538
TNS : -184.012
TNS : -170.070
Type : Fast 1100mV 100C Model Setup 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk'
Slack : -14.774
TNS : -901.498
Slack : -16.301
TNS : -1018.017
Type : Fast 1100mV 100C Model Setup 'downclocker:dc|clk_out'
Slack : -5.608
TNS : -44394.911
Type : Fast 1100mV 100C Model Setup 'fpga_clk'
Slack : -6.214
TNS : -50560.530
Slack : -3.718
TNS : -8.178
Type : Fast 1100mV 100C Model Hold 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk'
Slack : 0.162
Slack : 0.160
TNS : 0.000
Type : Fast 1100mV 100C Model Hold 'fpga_clk'
Type : Fast 1100mV 100C Model Hold 'downclocker:dc|clk_out'
Slack : 0.177
TNS : 0.000
Type : Fast 1100mV 100C Model Minimum Pulse Width 'fpga_clk'
Slack : -2.174
TNS : -1371.543
Type : Fast 1100mV 100C Model Minimum Pulse Width 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk'
Slack : -0.192
TNS : -9.702
Type : Fast 1100mV -40C Model Setup 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk'
Slack : -12.462
TNS : -739.747
Type : Fast 1100mV -40C Model Setup 'fpga_clk'
Slack : -4.930
TNS : -40871.978
Type : Fast 1100mV -40C Model Hold 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk'
Slack : 0.140
Type : Fast 1100mV 100C Model Hold 'fpga_clk'
Slack : 0.303
TNS : 0.000
Type : Fast 1100mV -40C Model Hold 'fpga_clk'
Type : Fast 1100mV 100C Model Minimum Pulse Width 'downclocker:dc|clk_out'
Slack : -2.174
TNS : -537.344
Type : Fast 1100mV 100C Model Minimum Pulse Width 'fpga_clk'
Slack : -0.517
TNS : -2.901
Type : Fast 1100mV 100C Model Minimum Pulse Width 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk'
Slack : -0.144
TNS : -6.507
Type : Fast 1100mV -40C Model Setup 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk'
Slack : -14.004
TNS : -820.600
Type : Fast 1100mV -40C Model Setup 'downclocker:dc|clk_out'
Slack : -4.541
TNS : -36337.093
Type : Fast 1100mV -40C Model Setup 'fpga_clk'
Slack : -2.859
TNS : -5.427
Type : Fast 1100mV -40C Model Hold 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk'
Slack : 0.138
TNS : 0.000
Type : Fast 1100mV -40C Model Hold 'downclocker:dc|clk_out'
Slack : 0.164
TNS : 0.000
Type : Fast 1100mV -40C Model Minimum Pulse Width 'fpga_clk'
Type : Fast 1100mV -40C Model Hold 'fpga_clk'
Slack : 0.289
TNS : 0.000
Type : Fast 1100mV -40C Model Minimum Pulse Width 'downclocker:dc|clk_out'
Slack : -2.174
TNS : -1373.239
TNS : -534.258
Type : Fast 1100mV -40C Model Minimum Pulse Width 'fpga_clk'
Slack : -0.533
TNS : -2.899
Type : Fast 1100mV -40C Model Minimum Pulse Width 'cpu:cpu|st7920_serial_driver:gpu|lcd_clk'
Slack : -0.137
TNS : -3.355
Slack : -0.057
TNS : -2.411
------------------------------------------------------------