alu works on fpga
This commit is contained in:
parent
7fdf4e7739
commit
0ba56bc41e
GPG key ID:
838827D8C4611687
75 changed files with 2771 additions and 2316 deletions
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@ -1,14 +1,29 @@
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|chip8
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fpga_clk => fpga_clk.IN2
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rst_in => ~NO_FANOUT~
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lcd_clk << cpu:cpu.port7
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lcd_data << cpu:cpu.port8
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led[0] << cpu:cpu.port9
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led[1] << cpu:cpu.port9
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led[2] << cpu:cpu.port9
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led[3] << cpu:cpu.port9
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led[4] << cpu:cpu.port9
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led[5] << cpu:cpu.port9
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lcd_clk << cpu:cpu.port8
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lcd_data << cpu:cpu.port9
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led[0] << cpu:cpu.port10
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led[1] << cpu:cpu.port10
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led[2] << cpu:cpu.port10
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led[3] << cpu:cpu.port10
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led[4] << cpu:cpu.port10
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led[5] << cpu:cpu.port10
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|chip8|downclocker:dc
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clk_in => counter[0].CLK
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clk_in => counter[1].CLK
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clk_in => counter[2].CLK
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clk_in => counter[3].CLK
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clk_in => counter[4].CLK
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clk_in => counter[5].CLK
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clk_in => counter[6].CLK
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clk_in => counter[7].CLK
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clk_in => counter[8].CLK
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clk_in => counter[9].CLK
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clk_in => clk_out~reg0.CLK
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clk_out <= clk_out~reg0.DB_MAX_OUTPUT_PORT_TYPE
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|chip8|memory:mem
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@ -107,7 +122,7 @@ data_out[7] <= data_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
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|chip8|cpu:cpu
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clk_in => st7920_serial_driver:gpu.sys_clk
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clk_in => alu:alu.clk_in
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clk_in => cycle_counter[0]~reg0.CLK
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clk_in => cycle_counter[1]~reg0.CLK
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clk_in => cycle_counter[2]~reg0.CLK
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@ -173,6 +188,7 @@ clk_in => wr_memory_address[8]~reg0.CLK
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clk_in => wr_memory_address[9]~reg0.CLK
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clk_in => wr_memory_address[10]~reg0.CLK
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clk_in => wr_memory_address[11]~reg0.CLK
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clk_in => alu_rst.CLK
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clk_in => vram[1023][0].CLK
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clk_in => vram[1023][1].CLK
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clk_in => vram[1023][2].CLK
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@ -8535,6 +8551,7 @@ clk_in => draw_state.stage[28].CLK
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clk_in => draw_state.stage[29].CLK
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clk_in => draw_state.stage[30].CLK
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clk_in => draw_state.stage[31].CLK
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clk_in => compute_of.CLK
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clk_in => instr.src_sprite_idx[0].CLK
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clk_in => instr.src_sprite_idx[1].CLK
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clk_in => instr.src_sprite_idx[2].CLK
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@ -8721,6 +8738,54 @@ clk_in => instr.src_byte[8].CLK
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clk_in => instr.src_byte[9].CLK
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clk_in => instr.src_byte[10].CLK
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clk_in => instr.src_byte[11].CLK
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clk_in => instr.alu_i.op[0].CLK
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clk_in => instr.alu_i.op[1].CLK
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clk_in => instr.alu_i.op[2].CLK
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clk_in => instr.alu_i.op[3].CLK
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clk_in => instr.alu_i.op[4].CLK
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clk_in => instr.alu_i.op[5].CLK
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clk_in => instr.alu_i.op[6].CLK
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clk_in => instr.alu_i.op[7].CLK
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clk_in => instr.alu_i.op[8].CLK
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clk_in => instr.alu_i.op[9].CLK
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clk_in => instr.alu_i.op[10].CLK
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clk_in => instr.alu_i.op[11].CLK
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clk_in => instr.alu_i.op[12].CLK
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clk_in => instr.alu_i.op[13].CLK
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clk_in => instr.alu_i.op[14].CLK
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clk_in => instr.alu_i.op[15].CLK
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clk_in => instr.alu_i.op[16].CLK
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clk_in => instr.alu_i.op[17].CLK
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clk_in => instr.alu_i.op[18].CLK
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clk_in => instr.alu_i.op[19].CLK
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clk_in => instr.alu_i.op[20].CLK
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clk_in => instr.alu_i.op[21].CLK
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clk_in => instr.alu_i.op[22].CLK
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clk_in => instr.alu_i.op[23].CLK
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clk_in => instr.alu_i.op[24].CLK
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clk_in => instr.alu_i.op[25].CLK
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clk_in => instr.alu_i.op[26].CLK
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clk_in => instr.alu_i.op[27].CLK
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clk_in => instr.alu_i.op[28].CLK
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clk_in => instr.alu_i.op[29].CLK
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clk_in => instr.alu_i.op[30].CLK
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clk_in => instr.alu_i.op[31].CLK
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clk_in => instr.alu_i.operand_b[0].CLK
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clk_in => instr.alu_i.operand_b[1].CLK
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clk_in => instr.alu_i.operand_b[2].CLK
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clk_in => instr.alu_i.operand_b[3].CLK
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clk_in => instr.alu_i.operand_b[4].CLK
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clk_in => instr.alu_i.operand_b[5].CLK
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clk_in => instr.alu_i.operand_b[6].CLK
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clk_in => instr.alu_i.operand_b[7].CLK
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clk_in => instr.alu_i.operand_a[0].CLK
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clk_in => instr.alu_i.operand_a[1].CLK
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clk_in => instr.alu_i.operand_a[2].CLK
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clk_in => instr.alu_i.operand_a[3].CLK
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clk_in => instr.alu_i.operand_a[4].CLK
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clk_in => instr.alu_i.operand_a[5].CLK
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clk_in => instr.alu_i.operand_a[6].CLK
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clk_in => instr.alu_i.operand_a[7].CLK
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clk_in => instr.dst_reg[0].CLK
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clk_in => instr.dst_reg[1].CLK
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clk_in => instr.dst_reg[2].CLK
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@ -8897,6 +8962,7 @@ clk_in => rd_memory_address[8]~reg0.CLK
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clk_in => rd_memory_address[9]~reg0.CLK
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clk_in => rd_memory_address[10]~reg0.CLK
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clk_in => rd_memory_address[11]~reg0.CLK
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fpga_clk => st7920_serial_driver:gpu.sys_clk
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rd_memory_data[0] => instr.DATAB
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rd_memory_data[0] => src_sprite.DATAB
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rd_memory_data[0] => src_sprite.DATAB
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@ -8914,7 +8980,7 @@ rd_memory_data[0] => src_sprite.DATAB
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rd_memory_data[0] => src_sprite.DATAB
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rd_memory_data[0] => src_sprite.DATAB
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rd_memory_data[0] => src_sprite.DATAB
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rd_memory_data[0] => Selector79.IN4
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rd_memory_data[0] => Selector171.IN4
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rd_memory_data[0] => opcode[8].DATAIN
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rd_memory_data[1] => instr.DATAB
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rd_memory_data[1] => src_sprite.DATAB
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@ -8933,7 +8999,7 @@ rd_memory_data[1] => src_sprite.DATAB
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rd_memory_data[1] => src_sprite.DATAB
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rd_memory_data[1] => src_sprite.DATAB
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rd_memory_data[1] => src_sprite.DATAB
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rd_memory_data[1] => Selector78.IN4
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rd_memory_data[1] => Selector170.IN4
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rd_memory_data[1] => opcode[9].DATAIN
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rd_memory_data[2] => instr.DATAB
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rd_memory_data[2] => src_sprite.DATAB
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@ -8952,7 +9018,7 @@ rd_memory_data[2] => src_sprite.DATAB
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rd_memory_data[2] => src_sprite.DATAB
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rd_memory_data[2] => src_sprite.DATAB
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rd_memory_data[2] => src_sprite.DATAB
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rd_memory_data[2] => Selector77.IN4
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rd_memory_data[2] => Selector169.IN4
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rd_memory_data[2] => opcode[10].DATAIN
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rd_memory_data[3] => instr.DATAB
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rd_memory_data[3] => src_sprite.DATAB
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@ -8971,7 +9037,7 @@ rd_memory_data[3] => src_sprite.DATAB
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rd_memory_data[3] => src_sprite.DATAB
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rd_memory_data[3] => src_sprite.DATAB
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rd_memory_data[3] => src_sprite.DATAB
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rd_memory_data[3] => Selector76.IN4
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rd_memory_data[3] => Selector168.IN4
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rd_memory_data[3] => opcode[11].DATAIN
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rd_memory_data[4] => instr.DATAB
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rd_memory_data[4] => src_sprite.DATAB
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@ -8990,7 +9056,7 @@ rd_memory_data[4] => src_sprite.DATAB
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rd_memory_data[4] => src_sprite.DATAB
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rd_memory_data[4] => src_sprite.DATAB
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rd_memory_data[4] => src_sprite.DATAB
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rd_memory_data[4] => Selector75.IN4
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rd_memory_data[4] => Selector167.IN4
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rd_memory_data[4] => opcode[12].DATAIN
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rd_memory_data[5] => instr.DATAB
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rd_memory_data[5] => src_sprite.DATAB
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@ -9009,7 +9075,7 @@ rd_memory_data[5] => src_sprite.DATAB
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rd_memory_data[5] => src_sprite.DATAB
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rd_memory_data[5] => src_sprite.DATAB
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rd_memory_data[5] => src_sprite.DATAB
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rd_memory_data[5] => Selector74.IN4
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rd_memory_data[5] => Selector166.IN4
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rd_memory_data[5] => opcode[13].DATAIN
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rd_memory_data[6] => instr.DATAB
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rd_memory_data[6] => src_sprite.DATAB
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@ -9028,7 +9094,7 @@ rd_memory_data[6] => src_sprite.DATAB
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rd_memory_data[6] => src_sprite.DATAB
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rd_memory_data[6] => src_sprite.DATAB
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rd_memory_data[6] => src_sprite.DATAB
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rd_memory_data[6] => Selector73.IN4
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rd_memory_data[6] => Selector165.IN4
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rd_memory_data[6] => opcode[14].DATAIN
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rd_memory_data[7] => instr.DATAB
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rd_memory_data[7] => src_sprite.DATAB
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@ -9047,7 +9113,7 @@ rd_memory_data[7] => src_sprite.DATAB
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rd_memory_data[7] => src_sprite.DATAB
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rd_memory_data[7] => src_sprite.DATAB
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rd_memory_data[7] => src_sprite.DATAB
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rd_memory_data[7] => Selector72.IN4
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rd_memory_data[7] => Selector164.IN4
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rd_memory_data[7] => opcode[15].DATAIN
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cycle_counter[0] <= cycle_counter[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
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cycle_counter[1] <= cycle_counter[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
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@ -9116,12 +9182,157 @@ wr_memory_data[7] <= wr_memory_data[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
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wr_go <= wr_go~reg0.DB_MAX_OUTPUT_PORT_TYPE
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lcd_clk <= st7920_serial_driver:gpu.lcd_clk
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lcd_data <= st7920_serial_driver:gpu.lcd_data
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led[0] <= st7920_serial_driver:gpu.led[0]
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led[1] <= st7920_serial_driver:gpu.led[1]
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led[2] <= st7920_serial_driver:gpu.led[2]
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led[3] <= st7920_serial_driver:gpu.led[3]
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led[4] <= st7920_serial_driver:gpu.led[4]
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led[5] <= st7920_serial_driver:gpu.led[5]
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led[0] <= state[0].DB_MAX_OUTPUT_PORT_TYPE
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led[1] <= state[1].DB_MAX_OUTPUT_PORT_TYPE
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led[2] <= state[2].DB_MAX_OUTPUT_PORT_TYPE
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led[3] <= state[3].DB_MAX_OUTPUT_PORT_TYPE
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led[4] <= state[4].DB_MAX_OUTPUT_PORT_TYPE
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led[5] <= state[5].DB_MAX_OUTPUT_PORT_TYPE
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|chip8|cpu:cpu|alu:alu
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rst_in => done.OUTPUTSELECT
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rst_in => cnt.OUTPUTSELECT
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rst_in => cnt.OUTPUTSELECT
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rst_in => cnt.OUTPUTSELECT
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rst_in => cnt.OUTPUTSELECT
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rst_in => cnt.OUTPUTSELECT
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rst_in => cnt.OUTPUTSELECT
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rst_in => cnt.OUTPUTSELECT
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rst_in => cnt.OUTPUTSELECT
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rst_in => cnt.OUTPUTSELECT
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rst_in => cnt.OUTPUTSELECT
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rst_in => cnt.OUTPUTSELECT
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rst_in => cnt.OUTPUTSELECT
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rst_in => cnt.OUTPUTSELECT
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rst_in => cnt.OUTPUTSELECT
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rst_in => cnt.OUTPUTSELECT
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rst_in => cnt.OUTPUTSELECT
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rst_in => cnt.OUTPUTSELECT
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rst_in => cnt.OUTPUTSELECT
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rst_in => cnt.OUTPUTSELECT
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rst_in => cnt.OUTPUTSELECT
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rst_in => cnt.OUTPUTSELECT
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rst_in => cnt.OUTPUTSELECT
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rst_in => cnt.OUTPUTSELECT
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rst_in => cnt.OUTPUTSELECT
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rst_in => cnt.OUTPUTSELECT
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rst_in => cnt.OUTPUTSELECT
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rst_in => cnt.OUTPUTSELECT
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rst_in => cnt.OUTPUTSELECT
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rst_in => cnt.OUTPUTSELECT
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rst_in => cnt.OUTPUTSELECT
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rst_in => cnt.OUTPUTSELECT
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rst_in => cnt.OUTPUTSELECT
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clk_in => cnt[0].CLK
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clk_in => cnt[1].CLK
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clk_in => cnt[2].CLK
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clk_in => cnt[3].CLK
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clk_in => cnt[4].CLK
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clk_in => cnt[5].CLK
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clk_in => cnt[6].CLK
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clk_in => cnt[7].CLK
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clk_in => cnt[8].CLK
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clk_in => cnt[9].CLK
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clk_in => cnt[10].CLK
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clk_in => cnt[11].CLK
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clk_in => cnt[12].CLK
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clk_in => cnt[13].CLK
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clk_in => cnt[14].CLK
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clk_in => cnt[15].CLK
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clk_in => cnt[16].CLK
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clk_in => cnt[17].CLK
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clk_in => cnt[18].CLK
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clk_in => cnt[19].CLK
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clk_in => cnt[20].CLK
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clk_in => cnt[21].CLK
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clk_in => cnt[22].CLK
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clk_in => cnt[23].CLK
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clk_in => cnt[24].CLK
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clk_in => cnt[25].CLK
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clk_in => cnt[26].CLK
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clk_in => cnt[27].CLK
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clk_in => cnt[28].CLK
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clk_in => cnt[29].CLK
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clk_in => cnt[30].CLK
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clk_in => cnt[31].CLK
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clk_in => result_int[0].CLK
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clk_in => result_int[1].CLK
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clk_in => result_int[2].CLK
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clk_in => result_int[3].CLK
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clk_in => result_int[4].CLK
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clk_in => result_int[5].CLK
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clk_in => result_int[6].CLK
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clk_in => result_int[7].CLK
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clk_in => result_int[8].CLK
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clk_in => result[0]~reg0.CLK
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clk_in => result[1]~reg0.CLK
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clk_in => result[2]~reg0.CLK
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clk_in => result[3]~reg0.CLK
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clk_in => result[4]~reg0.CLK
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clk_in => result[5]~reg0.CLK
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clk_in => result[6]~reg0.CLK
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clk_in => result[7]~reg0.CLK
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clk_in => overflow~reg0.CLK
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clk_in => done~reg0.CLK
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in.op[0] => ~NO_FANOUT~
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in.op[1] => ~NO_FANOUT~
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in.op[2] => ~NO_FANOUT~
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in.op[3] => ~NO_FANOUT~
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in.op[4] => ~NO_FANOUT~
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in.op[5] => ~NO_FANOUT~
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in.op[6] => ~NO_FANOUT~
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in.op[7] => ~NO_FANOUT~
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in.op[8] => ~NO_FANOUT~
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in.op[9] => ~NO_FANOUT~
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in.op[10] => ~NO_FANOUT~
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in.op[11] => ~NO_FANOUT~
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in.op[12] => ~NO_FANOUT~
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in.op[13] => ~NO_FANOUT~
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in.op[14] => ~NO_FANOUT~
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in.op[15] => ~NO_FANOUT~
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in.op[16] => ~NO_FANOUT~
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in.op[17] => ~NO_FANOUT~
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in.op[18] => ~NO_FANOUT~
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in.op[19] => ~NO_FANOUT~
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in.op[20] => ~NO_FANOUT~
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in.op[21] => ~NO_FANOUT~
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in.op[22] => ~NO_FANOUT~
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in.op[23] => ~NO_FANOUT~
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in.op[24] => ~NO_FANOUT~
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in.op[25] => ~NO_FANOUT~
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in.op[26] => ~NO_FANOUT~
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in.op[27] => ~NO_FANOUT~
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in.op[28] => ~NO_FANOUT~
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in.op[29] => ~NO_FANOUT~
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in.op[30] => ~NO_FANOUT~
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in.op[31] => ~NO_FANOUT~
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in.operand_b[0] => Add0.IN16
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in.operand_b[1] => Add0.IN15
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in.operand_b[2] => Add0.IN14
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in.operand_b[3] => Add0.IN13
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in.operand_b[4] => Add0.IN12
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in.operand_b[5] => Add0.IN11
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in.operand_b[6] => Add0.IN10
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in.operand_b[7] => Add0.IN9
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in.operand_a[0] => Add0.IN8
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in.operand_a[1] => Add0.IN7
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in.operand_a[2] => Add0.IN6
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in.operand_a[3] => Add0.IN5
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in.operand_a[4] => Add0.IN4
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in.operand_a[5] => Add0.IN3
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in.operand_a[6] => Add0.IN2
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in.operand_a[7] => Add0.IN1
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result[0] <= result[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
result[1] <= result[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
result[2] <= result[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
result[3] <= result[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
result[4] <= result[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
result[5] <= result[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
result[6] <= result[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
result[7] <= result[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
overflow <= overflow~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
done <= done~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
|
||||
|
||||
|chip8|cpu:cpu|st7920_serial_driver:gpu
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue