28 lines
857 B
Systemverilog
28 lines
857 B
Systemverilog
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module memory #(parameter RAM_SIZE_BYTES = 4096) (
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input wire clk_in,
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input wire do_write,
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input wire [$clog2(RAM_SIZE_BYTES)-1:0] write_address,
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input wire [7:0] data_in,
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input wire [$clog2(RAM_SIZE_BYTES)-1:0] read_address,
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output logic [7:0] data_out/*,
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input wire [$clog2(RAM_SIZE_BYTES)-1:0] read_address_gfx,
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output logic [7:0] data_out_gfxA*/
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);
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logic [7:0] mem [0:RAM_SIZE_BYTES-1];
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initial begin
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$readmemh("fontset.bin", mem, 0);
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$readmemb("rom.bin", mem, 'h200);
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end
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always_ff @(negedge clk_in) begin
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if (do_write) begin
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mem[write_address] <= data_in;
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end
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//$display("MEM : Reading address %h (%h)", read_address, mem[read_address]);
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data_out <= mem[read_address];
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//data_out_gfx <= mem[read_address_gfx];
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end
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endmodule
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