90 lines
4.1 KiB
Plaintext
90 lines
4.1 KiB
Plaintext
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--abs_divider DEN_REPRESENTATION="SIGNED" LPM_PIPELINE=0 MAXIMIZE_SPEED=5 NUM_REPRESENTATION="SIGNED" SKIP_BITS=0 WIDTH_D=6 WIDTH_N=32 denominator numerator quotient remainder
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--VERSION_BEGIN 23.1 cbx_cycloneii 2023:11:29:19:33:06:SC cbx_lpm_abs 2023:11:29:19:33:06:SC cbx_lpm_add_sub 2023:11:29:19:33:06:SC cbx_lpm_divide 2023:11:29:19:33:06:SC cbx_mgl 2023:11:29:19:43:53:SC cbx_nadder 2023:11:29:19:33:06:SC cbx_stratix 2023:11:29:19:33:06:SC cbx_stratixii 2023:11:29:19:33:05:SC cbx_util_mgl 2023:11:29:19:33:06:SC VERSION_END
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-- Copyright (C) 2023 Intel Corporation. All rights reserved.
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-- Your use of Intel Corporation's design tools, logic functions
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-- and other software and tools, and any partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Intel Program License
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-- Subscription Agreement, the Intel Quartus Prime License Agreement,
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-- the Intel FPGA IP License Agreement, or other applicable license
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-- agreement, including, without limitation, that your use is for
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-- the sole purpose of programming logic devices manufactured by
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-- Intel and sold by Intel or its authorized distributors. Please
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-- refer to the applicable agreement for further details, at
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-- https://fpgasoftware.intel.com/eula.
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FUNCTION alt_u_div_qve (denominator[5..0], numerator[31..0])
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RETURNS ( quotient[31..0], remainder[5..0]);
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FUNCTION lpm_abs_ln9 (data[5..0])
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RETURNS ( overflow, result[5..0]);
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FUNCTION lpm_abs_4p9 (data[31..0])
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RETURNS ( overflow, result[31..0]);
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--synthesis_resources = lut 311
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SUBDESIGN abs_divider_lbg
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(
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denominator[5..0] : input;
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numerator[31..0] : input;
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quotient[31..0] : output;
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remainder[5..0] : output;
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)
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VARIABLE
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divider : alt_u_div_qve;
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my_abs_den : lpm_abs_ln9;
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my_abs_num : lpm_abs_4p9;
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compl_add_quot_result_int[32..0] : WIRE;
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compl_add_quot_cin : WIRE;
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compl_add_quot_dataa[31..0] : WIRE;
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compl_add_quot_datab[31..0] : WIRE;
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compl_add_quot_result[31..0] : WIRE;
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compl_add_rem_result_int[6..0] : WIRE;
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compl_add_rem_cin : WIRE;
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compl_add_rem_dataa[5..0] : WIRE;
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compl_add_rem_datab[5..0] : WIRE;
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compl_add_rem_result[5..0] : WIRE;
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diff_signs : WIRE;
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gnd_wire : WIRE;
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neg_quot[31..0] : WIRE;
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neg_rem[5..0] : WIRE;
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norm_den[5..0] : WIRE;
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norm_num[31..0] : WIRE;
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num_sign : WIRE;
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protect_quotient[31..0] : WIRE;
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protect_remainder[5..0] : WIRE;
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vcc_wire : WIRE;
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BEGIN
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divider.denominator[] = norm_den[];
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divider.numerator[] = norm_num[];
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my_abs_den.data[] = denominator[];
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my_abs_num.data[] = numerator[];
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compl_add_quot_result_int[] = (compl_add_quot_dataa[], compl_add_quot_cin) + (compl_add_quot_datab[], compl_add_quot_cin);
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compl_add_quot_result[] = compl_add_quot_result_int[32..1];
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compl_add_quot_cin = vcc_wire;
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compl_add_quot_dataa[] = (! protect_quotient[]);
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compl_add_quot_datab[] = ( gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire);
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compl_add_rem_result_int[] = (compl_add_rem_dataa[], compl_add_rem_cin) + (compl_add_rem_datab[], compl_add_rem_cin);
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compl_add_rem_result[] = compl_add_rem_result_int[6..1];
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compl_add_rem_cin = vcc_wire;
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compl_add_rem_dataa[] = (! protect_remainder[]);
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compl_add_rem_datab[] = ( gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire);
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diff_signs = (numerator[31..31] $ denominator[5..5]);
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gnd_wire = B"0";
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neg_quot[] = compl_add_quot_result[];
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neg_rem[] = compl_add_rem_result[];
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norm_den[] = my_abs_den.result[];
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norm_num[] = my_abs_num.result[];
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num_sign = numerator[31..31];
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protect_quotient[] = divider.quotient[];
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protect_remainder[] = divider.remainder[];
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quotient[] = ((protect_quotient[] & (! diff_signs)) # (neg_quot[] & diff_signs));
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remainder[] = ((protect_remainder[] & (! num_sign)) # (neg_rem[] & num_sign));
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vcc_wire = B"1";
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END;
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--VALID FILE
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