144 lines
2.5 KiB
Systemverilog
144 lines
2.5 KiB
Systemverilog
module chip8 (
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input wire clk_in,
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input wire rst_in
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);
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bit vram[0:2047];
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bit [7:0] memory[0:4095];
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bit keyboard[15:0];
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bit [7:0] sound_timer;
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bit [15:0] program_counter;
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int cycle_counter;
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bit rom_ready;
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bit font_ready;
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bit system_ready;
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bit halt;
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bit [7:0] random_number;
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and(system_ready, rom_ready, font_ready);
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beeper beeper (sound_timer);
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cpu cpu (
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system_ready,
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memory,
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clk_in,
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keyboard,
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random_number,
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cycle_counter,
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program_counter,
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vram,
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sound_timer
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);
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gpu gpu (vram);
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keyboard kb (
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clk_in,
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keyboard
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);
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rng randy (
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clk_in,
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program_counter,
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keyboard,
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cycle_counter,
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random_number
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);
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rom_loader loader (clk_in, rst_in, memory, rom_ready);
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always_ff @(negedge clk_in) begin
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if (~font_ready) begin
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bit [7:0] fontset[79:0] = {
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8'hF0,
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8'h90,
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8'h90,
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8'h90,
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8'hF0, // 0
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8'h20,
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8'h60,
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8'h20,
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8'h20,
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8'h70, // 1
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8'hF0,
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8'h10,
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8'hF0,
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8'h80,
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8'hF0, // 2
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8'hF0,
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8'h10,
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8'hF0,
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8'h10,
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8'hF0, // 3
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8'h90,
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8'h90,
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8'hF0,
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8'h10,
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8'h10, // 4
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8'hF0,
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8'h80,
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8'hF0,
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8'h10,
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8'hF0, // 5
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8'hF0,
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8'h80,
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8'hF0,
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8'h90,
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8'hF0, // 6
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8'hF0,
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8'h10,
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8'h20,
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8'h40,
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8'h40, // 7
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8'hF0,
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8'h90,
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8'hF0,
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8'h90,
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8'hF0, // 8
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8'hF0,
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8'h90,
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8'hF0,
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8'h10,
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8'hF0, // 9
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8'hF0,
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8'h90,
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8'hF0,
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8'h90,
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8'h90, // A
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8'hE0,
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8'h90,
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8'hE0,
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8'h90,
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8'hE0, // B
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8'hF0,
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8'h80,
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8'h80,
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8'h80,
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8'hF0, // C
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8'hE0,
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8'h90,
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8'h90,
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8'h90,
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8'hE0, // D
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8'hF0,
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8'h80,
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8'hF0,
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8'h80,
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8'hF0, // E
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8'hF0,
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8'h80,
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8'hF0,
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8'h80,
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8'h80 // F
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};
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// Load fontset into memory
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for (int i = 0; i < 80; i++) begin
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memory[i] = fontset[79-i];
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end
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font_ready = 1;
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end
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end
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endmodule
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