651 lines
62 KiB
Plaintext
651 lines
62 KiB
Plaintext
Analysis & Synthesis report for chip8
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Sun Apr 7 23:45:53 2024
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Quartus Prime Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition
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---------------------
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; Table of Contents ;
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---------------------
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1. Legal Notice
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2. Analysis & Synthesis Summary
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3. Analysis & Synthesis Settings
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4. Parallel Compilation
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5. Analysis & Synthesis Source Files Read
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6. Analysis & Synthesis Resource Usage Summary
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7. Analysis & Synthesis Resource Utilization by Entity
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8. Analysis & Synthesis RAM Summary
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9. Registers Removed During Synthesis
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10. Removed Registers Triggering Further Register Optimizations
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11. General Register Statistics
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12. Inverted Register Statistics
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13. Registers Packed Into Inferred Megafunctions
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14. Multiplexer Restructuring Statistics (Restructuring Performed)
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15. Source assignments for memory:mem|altsyncram:mem_rtl_0|altsyncram_dsq1:auto_generated
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16. Parameter Settings for User Entity Instance: memory:mem
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17. Parameter Settings for Inferred Entity Instance: memory:mem|altsyncram:mem_rtl_0
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18. altsyncram Parameter Settings by Entity Instance
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19. Port Connectivity Checks: "cpu:cpu|st7920_serial_driver:gpu"
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20. Port Connectivity Checks: "cpu:cpu"
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21. Post-Synthesis Netlist Statistics for Top Partition
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22. Elapsed Time Per Partition
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23. Analysis & Synthesis Messages
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----------------
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; Legal Notice ;
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----------------
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Copyright (C) 2023 Intel Corporation. All rights reserved.
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Your use of Intel Corporation's design tools, logic functions
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and other software and tools, and any partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Intel Program License
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Subscription Agreement, the Intel Quartus Prime License Agreement,
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the Intel FPGA IP License Agreement, or other applicable license
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agreement, including, without limitation, that your use is for
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the sole purpose of programming logic devices manufactured by
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Intel and sold by Intel or its authorized distributors. Please
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refer to the applicable agreement for further details, at
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https://fpgasoftware.intel.com/eula.
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+----------------------------------------------------------------------------------+
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; Analysis & Synthesis Summary ;
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+---------------------------------+------------------------------------------------+
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; Analysis & Synthesis Status ; Successful - Sun Apr 7 23:45:53 2024 ;
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; Quartus Prime Version ; 23.1std.0 Build 991 11/28/2023 SC Lite Edition ;
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; Revision Name ; chip8 ;
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; Top-level Entity Name ; chip8 ;
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; Family ; Cyclone V ;
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; Logic utilization (in ALMs) ; N/A ;
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; Total registers ; 8728 ;
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; Total pins ; 10 ;
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; Total virtual pins ; 0 ;
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; Total block memory bits ; 32,768 ;
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; Total DSP Blocks ; 0 ;
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; Total HSSI RX PCSs ; 0 ;
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; Total HSSI PMA RX Deserializers ; 0 ;
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; Total HSSI TX PCSs ; 0 ;
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; Total HSSI PMA TX Serializers ; 0 ;
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; Total PLLs ; 0 ;
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; Total DLLs ; 0 ;
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+---------------------------------+------------------------------------------------+
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+---------------------------------------------------------------------------------------------------------------------------+
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; Analysis & Synthesis Settings ;
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+---------------------------------------------------------------------------------+--------------------+--------------------+
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; Option ; Setting ; Default Value ;
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+---------------------------------------------------------------------------------+--------------------+--------------------+
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; Device ; 5CSEBA6U23I7 ; ;
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; Top-level entity name ; chip8 ; chip8 ;
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; Family name ; Cyclone V ; Cyclone V ;
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; Use smart compilation ; Off ; Off ;
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; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
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; Enable compact report table ; Off ; Off ;
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; Restructure Multiplexers ; Auto ; Auto ;
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; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off ; Off ;
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; Create Debugging Nodes for IP Cores ; Off ; Off ;
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; Preserve fewer node names ; On ; On ;
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; Intel FPGA IP Evaluation Mode ; Enable ; Enable ;
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; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
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; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
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; State Machine Processing ; Auto ; Auto ;
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; Safe State Machine ; Off ; Off ;
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; Extract Verilog State Machines ; On ; On ;
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; Extract VHDL State Machines ; On ; On ;
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; Ignore Verilog initial constructs ; Off ; Off ;
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; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
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; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
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; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
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; Infer RAMs from Raw Logic ; On ; On ;
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; Parallel Synthesis ; On ; On ;
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; DSP Block Balancing ; Auto ; Auto ;
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; NOT Gate Push-Back ; On ; On ;
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; Power-Up Don't Care ; On ; On ;
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; Remove Redundant Logic Cells ; Off ; Off ;
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; Remove Duplicate Registers ; On ; On ;
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; Ignore CARRY Buffers ; Off ; Off ;
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; Ignore CASCADE Buffers ; Off ; Off ;
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; Ignore GLOBAL Buffers ; Off ; Off ;
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; Ignore ROW GLOBAL Buffers ; Off ; Off ;
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; Ignore LCELL Buffers ; Off ; Off ;
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; Ignore SOFT Buffers ; On ; On ;
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; Limit AHDL Integers to 32 Bits ; Off ; Off ;
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; Optimization Technique ; Balanced ; Balanced ;
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; Carry Chain Length ; 70 ; 70 ;
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; Auto Carry Chains ; On ; On ;
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; Auto Open-Drain Pins ; On ; On ;
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; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
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; Auto ROM Replacement ; On ; On ;
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; Auto RAM Replacement ; On ; On ;
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; Auto DSP Block Replacement ; On ; On ;
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; Auto Shift Register Replacement ; Auto ; Auto ;
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; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
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; Auto Clock Enable Replacement ; On ; On ;
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; Strict RAM Replacement ; Off ; Off ;
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; Allow Synchronous Control Signals ; On ; On ;
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; Force Use of Synchronous Clear Signals ; Off ; Off ;
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; Auto Resource Sharing ; Off ; Off ;
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; Allow Any RAM Size For Recognition ; Off ; Off ;
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; Allow Any ROM Size For Recognition ; Off ; Off ;
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; Allow Any Shift Register Size For Recognition ; Off ; Off ;
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; Use LogicLock Constraints during Resource Balancing ; On ; On ;
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; Ignore translate_off and synthesis_off directives ; Off ; Off ;
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; Timing-Driven Synthesis ; On ; On ;
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; Report Parameter Settings ; On ; On ;
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; Report Source Assignments ; On ; On ;
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; Report Connectivity Checks ; On ; On ;
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; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
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; Synchronization Register Chain Length ; 3 ; 3 ;
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; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
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; HDL message level ; Level2 ; Level2 ;
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; Suppress Register Optimization Related Messages ; Off ; Off ;
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; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
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; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
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; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
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; Clock MUX Protection ; On ; On ;
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; Auto Gated Clock Conversion ; Off ; Off ;
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; Block Design Naming ; Auto ; Auto ;
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; SDC constraint protection ; Off ; Off ;
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; Synthesis Effort ; Auto ; Auto ;
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; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
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; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
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; Analysis & Synthesis Message Level ; Medium ; Medium ;
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; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
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; Resource Aware Inference For Block RAM ; On ; On ;
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; Automatic Parallel Synthesis ; On ; On ;
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; Partial Reconfiguration Bitstream ID ; Off ; Off ;
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+---------------------------------------------------------------------------------+--------------------+--------------------+
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+------------------------------------------+
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; Parallel Compilation ;
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+----------------------------+-------------+
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; Processors ; Number ;
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+----------------------------+-------------+
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; Number detected on machine ; 12 ;
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; Maximum allowed ; 12 ;
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; ; ;
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; Average used ; 3.71 ;
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; Maximum used ; 12 ;
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; ; ;
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; Usage by Processor ; % Time Used ;
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; Processor 1 ; 100.0% ;
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; Processor 2 ; 48.5% ;
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; Processor 3 ; 48.3% ;
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; Processor 4 ; 24.0% ;
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; Processor 5 ; 24.0% ;
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; Processor 6 ; 24.0% ;
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; Processor 7 ; 19.2% ;
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; Processor 8 ; 19.2% ;
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; Processor 9 ; 19.2% ;
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; Processor 10 ; 18.8% ;
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; Processor 11 ; 18.8% ;
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; Processor 12 ; 7.5% ;
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+----------------------------+-------------+
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+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Analysis & Synthesis Source Files Read ;
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+---------------------------------------+-----------------+-------------------------------------------------------+----------------------------------------------------------------------------------------------+---------+
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; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
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+---------------------------------------+-----------------+-------------------------------------------------------+----------------------------------------------------------------------------------------------+---------+
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; the-bomb/st7920_serial_driver.sv ; yes ; User SystemVerilog HDL File ; /home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv ; ;
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; chip8.sv ; yes ; User SystemVerilog HDL File ; /home/nickorlow/programming/school/warminster/yayacemu/chip8.sv ; ;
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; cpu.sv ; yes ; User SystemVerilog HDL File ; /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv ; ;
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; memory.sv ; yes ; Auto-Found SystemVerilog HDL File ; /home/nickorlow/programming/school/warminster/yayacemu/memory.sv ; ;
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; rom.bin ; yes ; Auto-Found Unspecified File ; /home/nickorlow/programming/school/warminster/yayacemu/rom.bin ; ;
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; fontset.bin ; yes ; Auto-Found Unspecified File ; /home/nickorlow/programming/school/warminster/yayacemu/fontset.bin ; ;
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; altsyncram.tdf ; yes ; Megafunction ; /opt/intelFPGA/23.1/quartus/libraries/megafunctions/altsyncram.tdf ; ;
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; stratix_ram_block.inc ; yes ; Megafunction ; /opt/intelFPGA/23.1/quartus/libraries/megafunctions/stratix_ram_block.inc ; ;
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; lpm_mux.inc ; yes ; Megafunction ; /opt/intelFPGA/23.1/quartus/libraries/megafunctions/lpm_mux.inc ; ;
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; lpm_decode.inc ; yes ; Megafunction ; /opt/intelFPGA/23.1/quartus/libraries/megafunctions/lpm_decode.inc ; ;
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; aglobal231.inc ; yes ; Megafunction ; /opt/intelFPGA/23.1/quartus/libraries/megafunctions/aglobal231.inc ; ;
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; a_rdenreg.inc ; yes ; Megafunction ; /opt/intelFPGA/23.1/quartus/libraries/megafunctions/a_rdenreg.inc ; ;
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; altrom.inc ; yes ; Megafunction ; /opt/intelFPGA/23.1/quartus/libraries/megafunctions/altrom.inc ; ;
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; altram.inc ; yes ; Megafunction ; /opt/intelFPGA/23.1/quartus/libraries/megafunctions/altram.inc ; ;
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; altdpram.inc ; yes ; Megafunction ; /opt/intelFPGA/23.1/quartus/libraries/megafunctions/altdpram.inc ; ;
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; db/altsyncram_dsq1.tdf ; yes ; Auto-Generated Megafunction ; /home/nickorlow/programming/school/warminster/yayacemu/db/altsyncram_dsq1.tdf ; ;
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; db/chip8.ram0_memory_e9e85012.hdl.mif ; yes ; Auto-Generated Auto-Found Memory Initialization File ; /home/nickorlow/programming/school/warminster/yayacemu/db/chip8.ram0_memory_e9e85012.hdl.mif ; ;
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+---------------------------------------+-----------------+-------------------------------------------------------+----------------------------------------------------------------------------------------------+---------+
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+--------------------------------------------------------------+
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; Analysis & Synthesis Resource Usage Summary ;
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+---------------------------------------------+----------------+
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; Resource ; Usage ;
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+---------------------------------------------+----------------+
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; Estimate of Logic utilization (ALMs needed) ; 10412 ;
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; ; ;
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; Combinational ALUT usage for logic ; 17065 ;
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; -- 7 input functions ; 58 ;
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; -- 6 input functions ; 3654 ;
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; -- 5 input functions ; 5900 ;
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; -- 4 input functions ; 2000 ;
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; -- <=3 input functions ; 5453 ;
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; ; ;
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; Dedicated logic registers ; 8728 ;
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; ; ;
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; I/O pins ; 10 ;
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; Total MLAB memory bits ; 0 ;
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; Total block memory bits ; 32768 ;
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; ; ;
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; Total DSP Blocks ; 0 ;
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; ; ;
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; Maximum fan-out node ; fpga_clk~input ;
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; Maximum fan-out ; 8564 ;
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; Total fan-out ; 102143 ;
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; Average fan-out ; 3.96 ;
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+---------------------------------------------+----------------+
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+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Analysis & Synthesis Resource Utilization by Entity ;
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+-------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+-----------------------------------------------------------------------+----------------------+--------------+
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; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
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+-------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+-----------------------------------------------------------------------+----------------------+--------------+
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; |chip8 ; 17065 (1) ; 8728 (0) ; 32768 ; 0 ; 10 ; 0 ; |chip8 ; chip8 ; work ;
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; |cpu:cpu| ; 17064 (11448) ; 8728 (8546) ; 0 ; 0 ; 0 ; 0 ; |chip8|cpu:cpu ; cpu ; work ;
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; |st7920_serial_driver:gpu| ; 5616 (5570) ; 182 (129) ; 0 ; 0 ; 0 ; 0 ; |chip8|cpu:cpu|st7920_serial_driver:gpu ; st7920_serial_driver ; work ;
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; |commander:com| ; 46 (46) ; 53 (53) ; 0 ; 0 ; 0 ; 0 ; |chip8|cpu:cpu|st7920_serial_driver:gpu|commander:com ; commander ; work ;
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; |memory:mem| ; 0 (0) ; 0 (0) ; 32768 ; 0 ; 0 ; 0 ; |chip8|memory:mem ; memory ; work ;
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; |altsyncram:mem_rtl_0| ; 0 (0) ; 0 (0) ; 32768 ; 0 ; 0 ; 0 ; |chip8|memory:mem|altsyncram:mem_rtl_0 ; altsyncram ; work ;
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; |altsyncram_dsq1:auto_generated| ; 0 (0) ; 0 (0) ; 32768 ; 0 ; 0 ; 0 ; |chip8|memory:mem|altsyncram:mem_rtl_0|altsyncram_dsq1:auto_generated ; altsyncram_dsq1 ; work ;
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+-------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+-----------------------------------------------------------------------+----------------------+--------------+
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Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
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+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Analysis & Synthesis RAM Summary ;
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+---------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+---------------------------------------+
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; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
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+---------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+---------------------------------------+
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; memory:mem|altsyncram:mem_rtl_0|altsyncram_dsq1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 4096 ; 8 ; 4096 ; 8 ; 32768 ; db/chip8.ram0_memory_e9e85012.hdl.mif ;
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+---------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+---------------------------------------+
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+----------------------------------------------------------------------------------------------------------------------+
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; Registers Removed During Synthesis ;
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+------------------------------------------------------------------------+---------------------------------------------+
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; Register name ; Reason for Removal ;
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+------------------------------------------------------------------------+---------------------------------------------+
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; cpu:cpu|st7920_serial_driver:gpu|d_flip_flop:dff|data_out ; Stuck at VCC due to stuck port data_in ;
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; cpu:cpu|wr_memory_address[0..11] ; Stuck at GND due to stuck port data_in ;
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; cpu:cpu|instr.src_sprite_sz[4] ; Stuck at GND due to stuck port data_in ;
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; cpu:cpu|instr.src_sprite_y[5..7] ; Stuck at GND due to stuck port data_in ;
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; cpu:cpu|instr.src_sprite_x[6,7] ; Stuck at GND due to stuck port data_in ;
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; cpu:cpu|instr.dst[1..31] ; Stuck at GND due to stuck port data_in ;
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; cpu:cpu|instr.op[2..31] ; Stuck at GND due to stuck port data_in ;
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; cpu:cpu|wr_memory_data[0..7] ; Stuck at GND due to stuck port clock_enable ;
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; cpu:cpu|draw_state.stage[1..9,11..31] ; Merged with cpu:cpu|draw_state.stage[10] ;
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; cpu:cpu|state[4..9,11..31] ; Merged with cpu:cpu|state[10] ;
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; cpu:cpu|instr.src[3..31] ; Merged with cpu:cpu|instr.src[0] ;
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; cpu:cpu|st7920_serial_driver:gpu|command[8] ; Stuck at GND due to stuck port data_in ;
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; cpu:cpu|st7920_serial_driver:gpu|commander:com|full_command_bits[0..3] ; Stuck at GND due to stuck port data_in ;
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; cpu:cpu|wr_go ; Stuck at GND due to stuck port data_in ;
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; cpu:cpu|draw_state.stage[10] ; Stuck at GND due to stuck port data_in ;
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; cpu:cpu|instr.src[0] ; Stuck at GND due to stuck port data_in ;
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; cpu:cpu|state[10] ; Stuck at GND due to stuck port data_in ;
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; cpu:cpu|program_counter[12..15] ; Lost fanout ;
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; Total Number of Removed Registers = 187 ; ;
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+------------------------------------------------------------------------+---------------------------------------------+
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+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Removed Registers Triggering Further Register Optimizations ;
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+---------------------------------------------------------------------+---------------------------+----------------------------------------------------------------------------------+
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; Register name ; Reason for Removal ; Registers Removed due to This Register ;
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+---------------------------------------------------------------------+---------------------------+----------------------------------------------------------------------------------+
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; cpu:cpu|instr.dst[1] ; Stuck at GND ; cpu:cpu|wr_memory_data[7], cpu:cpu|wr_memory_data[6], cpu:cpu|wr_memory_data[5], ;
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; ; due to stuck port data_in ; cpu:cpu|wr_memory_data[4], cpu:cpu|wr_memory_data[3], cpu:cpu|wr_memory_data[2], ;
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; ; ; cpu:cpu|wr_memory_data[1], cpu:cpu|wr_memory_data[0], cpu:cpu|wr_go ;
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; cpu:cpu|instr.src_sprite_sz[4] ; Stuck at GND ; cpu:cpu|instr.src_sprite_y[5], cpu:cpu|instr.src_sprite_y[6], ;
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; ; due to stuck port data_in ; cpu:cpu|instr.src_sprite_y[7], cpu:cpu|instr.src_sprite_x[6], ;
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; ; ; cpu:cpu|instr.src_sprite_x[7], cpu:cpu|draw_state.stage[10], cpu:cpu|state[10] ;
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; cpu:cpu|st7920_serial_driver:gpu|commander:com|full_command_bits[0] ; Stuck at GND ; cpu:cpu|st7920_serial_driver:gpu|commander:com|full_command_bits[1], ;
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; ; due to stuck port data_in ; cpu:cpu|st7920_serial_driver:gpu|commander:com|full_command_bits[2], ;
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; ; ; cpu:cpu|st7920_serial_driver:gpu|commander:com|full_command_bits[3] ;
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; cpu:cpu|st7920_serial_driver:gpu|d_flip_flop:dff|data_out ; Stuck at VCC ; cpu:cpu|st7920_serial_driver:gpu|command[8] ;
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; ; due to stuck port data_in ; ;
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+---------------------------------------------------------------------+---------------------------+----------------------------------------------------------------------------------+
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+------------------------------------------------------+
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; General Register Statistics ;
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+----------------------------------------------+-------+
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; Statistic ; Value ;
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+----------------------------------------------+-------+
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; Total registers ; 8728 ;
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; Number of registers using Synchronous Clear ; 118 ;
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; Number of registers using Synchronous Load ; 29 ;
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; Number of registers using Asynchronous Clear ; 0 ;
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; Number of registers using Asynchronous Load ; 0 ;
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; Number of registers using Clock Enable ; 8631 ;
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; Number of registers using Preset ; 0 ;
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+----------------------------------------------+-------+
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+--------------------------------------------------+
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; Inverted Register Statistics ;
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+----------------------------------------+---------+
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; Inverted Register ; Fan out ;
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+----------------------------------------+---------+
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; cpu:cpu|program_counter[9] ; 5 ;
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; Total number of inverted registers = 1 ; ;
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+----------------------------------------+---------+
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+---------------------------------------------------------+
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; Registers Packed Into Inferred Megafunctions ;
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+---------------------------+----------------------+------+
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; Register Name ; Megafunction ; Type ;
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+---------------------------+----------------------+------+
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; memory:mem|data_out[0..7] ; memory:mem|mem_rtl_0 ; RAM ;
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+---------------------------+----------------------+------+
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+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Multiplexer Restructuring Statistics (Restructuring Performed) ;
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+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------------------+
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; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
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+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------------------+
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; 3:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|commander:com|full_command_bits[22] ;
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; 3:1 ; 8 bits ; 16 LEs ; 0 LEs ; 16 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|commander:com|full_command_bits[17] ;
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; 3:1 ; 38 bits ; 76 LEs ; 0 LEs ; 76 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|commander:com|i[9] ;
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; 4:1 ; 32 bits ; 64 LEs ; 0 LEs ; 64 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|line_cnt[23] ;
|
|
; 4:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|x[5] ;
|
|
; 4:1 ; 7 bits ; 14 LEs ; 7 LEs ; 7 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|y[6] ;
|
|
; 5:1 ; 32 bits ; 96 LEs ; 32 LEs ; 64 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|i[1] ;
|
|
; 1029:1 ; 2 bits ; 1372 LEs ; 1368 LEs ; 4 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|command[6] ;
|
|
; 1059:1 ; 5 bits ; 3530 LEs ; 3445 LEs ; 85 LEs ; Yes ; |chip8|cpu:cpu|st7920_serial_driver:gpu|command[5] ;
|
|
; 3:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; Yes ; |chip8|cpu:cpu|draw_state.r[4] ;
|
|
; 4:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; Yes ; |chip8|cpu:cpu|draw_state.c[1] ;
|
|
; 16:1 ; 5 bits ; 50 LEs ; 50 LEs ; 0 LEs ; Yes ; |chip8|cpu:cpu|instr.src_sprite_y[4] ;
|
|
; 16:1 ; 6 bits ; 60 LEs ; 60 LEs ; 0 LEs ; Yes ; |chip8|cpu:cpu|instr.src_sprite_x[2] ;
|
|
; 4:1 ; 12 bits ; 24 LEs ; 0 LEs ; 24 LEs ; Yes ; |chip8|cpu:cpu|rd_memory_address[3] ;
|
|
; 5:1 ; 5 bits ; 15 LEs ; 5 LEs ; 10 LEs ; Yes ; |chip8|cpu:cpu|instr.src_sprite_idx[1] ;
|
|
; 5:1 ; 6 bits ; 18 LEs ; 6 LEs ; 12 LEs ; Yes ; |chip8|cpu:cpu|instr.src_byte[9] ;
|
|
; 5:1 ; 2 bits ; 6 LEs ; 2 LEs ; 4 LEs ; Yes ; |chip8|cpu:cpu|draw_state.stage[10] ;
|
|
; 6:1 ; 8 bits ; 32 LEs ; 0 LEs ; 32 LEs ; Yes ; |chip8|cpu:cpu|instr.src_byte[2] ;
|
|
; 6:1 ; 6 bits ; 24 LEs ; 12 LEs ; 12 LEs ; Yes ; |chip8|cpu:cpu|registers[15][5] ;
|
|
; 10:1 ; 4 bits ; 24 LEs ; 8 LEs ; 16 LEs ; Yes ; |chip8|cpu:cpu|program_counter[15] ;
|
|
; 10:1 ; 10 bits ; 60 LEs ; 20 LEs ; 40 LEs ; Yes ; |chip8|cpu:cpu|program_counter[1] ;
|
|
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------------------+
|
|
|
|
|
|
+---------------------------------------------------------------------------------------+
|
|
; Source assignments for memory:mem|altsyncram:mem_rtl_0|altsyncram_dsq1:auto_generated ;
|
|
+---------------------------------+--------------------+------+-------------------------+
|
|
; Assignment ; Value ; From ; To ;
|
|
+---------------------------------+--------------------+------+-------------------------+
|
|
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
|
|
+---------------------------------+--------------------+------+-------------------------+
|
|
|
|
|
|
+---------------------------------------------------------+
|
|
; Parameter Settings for User Entity Instance: memory:mem ;
|
|
+----------------+-------+--------------------------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+----------------+-------+--------------------------------+
|
|
; RAM_SIZE_BYTES ; 4096 ; Signed Integer ;
|
|
+----------------+-------+--------------------------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+---------------------------------------------------------------------------------------------+
|
|
; Parameter Settings for Inferred Entity Instance: memory:mem|altsyncram:mem_rtl_0 ;
|
|
+------------------------------------+---------------------------------------+----------------+
|
|
; Parameter Name ; Value ; Type ;
|
|
+------------------------------------+---------------------------------------+----------------+
|
|
; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
|
|
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
|
|
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
|
|
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
|
|
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
|
|
; WIDTH_BYTEENA ; 1 ; Untyped ;
|
|
; OPERATION_MODE ; DUAL_PORT ; Untyped ;
|
|
; WIDTH_A ; 8 ; Untyped ;
|
|
; WIDTHAD_A ; 12 ; Untyped ;
|
|
; NUMWORDS_A ; 4096 ; Untyped ;
|
|
; OUTDATA_REG_A ; UNREGISTERED ; Untyped ;
|
|
; ADDRESS_ACLR_A ; NONE ; Untyped ;
|
|
; OUTDATA_ACLR_A ; NONE ; Untyped ;
|
|
; WRCONTROL_ACLR_A ; NONE ; Untyped ;
|
|
; INDATA_ACLR_A ; NONE ; Untyped ;
|
|
; BYTEENA_ACLR_A ; NONE ; Untyped ;
|
|
; WIDTH_B ; 8 ; Untyped ;
|
|
; WIDTHAD_B ; 12 ; Untyped ;
|
|
; NUMWORDS_B ; 4096 ; Untyped ;
|
|
; INDATA_REG_B ; CLOCK1 ; Untyped ;
|
|
; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
|
|
; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
|
|
; ADDRESS_REG_B ; CLOCK0 ; Untyped ;
|
|
; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
|
|
; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
|
|
; INDATA_ACLR_B ; NONE ; Untyped ;
|
|
; WRCONTROL_ACLR_B ; NONE ; Untyped ;
|
|
; ADDRESS_ACLR_B ; NONE ; Untyped ;
|
|
; OUTDATA_ACLR_B ; NONE ; Untyped ;
|
|
; RDCONTROL_ACLR_B ; NONE ; Untyped ;
|
|
; BYTEENA_ACLR_B ; NONE ; Untyped ;
|
|
; WIDTH_BYTEENA_A ; 1 ; Untyped ;
|
|
; WIDTH_BYTEENA_B ; 1 ; Untyped ;
|
|
; RAM_BLOCK_TYPE ; AUTO ; Untyped ;
|
|
; BYTE_SIZE ; 8 ; Untyped ;
|
|
; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA ; Untyped ;
|
|
; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ;
|
|
; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ;
|
|
; INIT_FILE ; db/chip8.ram0_memory_e9e85012.hdl.mif ; Untyped ;
|
|
; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
|
|
; MAXIMUM_DEPTH ; 0 ; Untyped ;
|
|
; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ;
|
|
; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
|
|
; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ;
|
|
; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
|
|
; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ;
|
|
; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ;
|
|
; ENABLE_ECC ; FALSE ; Untyped ;
|
|
; ECC_PIPELINE_STAGE_ENABLED ; FALSE ; Untyped ;
|
|
; WIDTH_ECCSTATUS ; 3 ; Untyped ;
|
|
; DEVICE_FAMILY ; Cyclone V ; Untyped ;
|
|
; CBXI_PARAMETER ; altsyncram_dsq1 ; Untyped ;
|
|
+------------------------------------+---------------------------------------+----------------+
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
|
|
|
|
|
+-----------------------------------------------------------------------------+
|
|
; altsyncram Parameter Settings by Entity Instance ;
|
|
+-------------------------------------------+---------------------------------+
|
|
; Name ; Value ;
|
|
+-------------------------------------------+---------------------------------+
|
|
; Number of entity instances ; 1 ;
|
|
; Entity Instance ; memory:mem|altsyncram:mem_rtl_0 ;
|
|
; -- OPERATION_MODE ; DUAL_PORT ;
|
|
; -- WIDTH_A ; 8 ;
|
|
; -- NUMWORDS_A ; 4096 ;
|
|
; -- OUTDATA_REG_A ; UNREGISTERED ;
|
|
; -- WIDTH_B ; 8 ;
|
|
; -- NUMWORDS_B ; 4096 ;
|
|
; -- ADDRESS_REG_B ; CLOCK0 ;
|
|
; -- OUTDATA_REG_B ; UNREGISTERED ;
|
|
; -- RAM_BLOCK_TYPE ; AUTO ;
|
|
; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA ;
|
|
+-------------------------------------------+---------------------------------+
|
|
|
|
|
|
+--------------------------------------------------------------+
|
|
; Port Connectivity Checks: "cpu:cpu|st7920_serial_driver:gpu" ;
|
|
+--------------+-------+----------+----------------------------+
|
|
; Port ; Type ; Severity ; Details ;
|
|
+--------------+-------+----------+----------------------------+
|
|
; sys_rst_n_ms ; Input ; Info ; Stuck at VCC ;
|
|
+--------------+-------+----------+----------------------------+
|
|
|
|
|
|
+-------------------------------------------------------------------------------------------------------------------------+
|
|
; Port Connectivity Checks: "cpu:cpu" ;
|
|
+---------------+--------+----------+-------------------------------------------------------------------------------------+
|
|
; Port ; Type ; Severity ; Details ;
|
|
+---------------+--------+----------+-------------------------------------------------------------------------------------+
|
|
; cycle_counter ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
|
|
+---------------+--------+----------+-------------------------------------------------------------------------------------+
|
|
|
|
|
|
+-----------------------------------------------------+
|
|
; Post-Synthesis Netlist Statistics for Top Partition ;
|
|
+-----------------------+-----------------------------+
|
|
; Type ; Count ;
|
|
+-----------------------+-----------------------------+
|
|
; arriav_ff ; 8728 ;
|
|
; ENA ; 8526 ;
|
|
; ENA SCLR ; 77 ;
|
|
; ENA SLD ; 28 ;
|
|
; SCLR ; 41 ;
|
|
; SLD ; 1 ;
|
|
; plain ; 55 ;
|
|
; arriav_lcell_comb ; 17066 ;
|
|
; arith ; 257 ;
|
|
; 0 data inputs ; 7 ;
|
|
; 1 data inputs ; 229 ;
|
|
; 2 data inputs ; 17 ;
|
|
; 3 data inputs ; 1 ;
|
|
; 4 data inputs ; 1 ;
|
|
; 5 data inputs ; 2 ;
|
|
; extend ; 58 ;
|
|
; 7 data inputs ; 58 ;
|
|
; normal ; 16745 ;
|
|
; 0 data inputs ; 2 ;
|
|
; 1 data inputs ; 1 ;
|
|
; 2 data inputs ; 176 ;
|
|
; 3 data inputs ; 5015 ;
|
|
; 4 data inputs ; 1999 ;
|
|
; 5 data inputs ; 5898 ;
|
|
; 6 data inputs ; 3654 ;
|
|
; shared ; 6 ;
|
|
; 2 data inputs ; 6 ;
|
|
; boundary_port ; 10 ;
|
|
; stratixv_ram_block ; 8 ;
|
|
; ; ;
|
|
; Max LUT depth ; 55.00 ;
|
|
; Average LUT depth ; 17.90 ;
|
|
+-----------------------+-----------------------------+
|
|
|
|
|
|
+-------------------------------+
|
|
; Elapsed Time Per Partition ;
|
|
+----------------+--------------+
|
|
; Partition Name ; Elapsed Time ;
|
|
+----------------+--------------+
|
|
; Top ; 00:00:53 ;
|
|
+----------------+--------------+
|
|
|
|
|
|
+-------------------------------+
|
|
; Analysis & Synthesis Messages ;
|
|
+-------------------------------+
|
|
Info: *******************************************************************
|
|
Info: Running Quartus Prime Analysis & Synthesis
|
|
Info: Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition
|
|
Info: Processing started: Sun Apr 7 23:44:51 2024
|
|
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off chip8 -c chip8
|
|
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
|
Info (20030): Parallel compilation is enabled and will use 12 of the 12 processors detected
|
|
Info (12021): Found 3 design units, including 3 entities, in source file the-bomb/st7920_serial_driver.sv
|
|
Info (12023): Found entity 1: st7920_serial_driver File: /home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv Line: 4
|
|
Info (12023): Found entity 2: d_flip_flop File: /home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv Line: 137
|
|
Info (12023): Found entity 3: commander File: /home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv Line: 147
|
|
Info (12021): Found 1 design units, including 1 entities, in source file chip8.sv
|
|
Info (12023): Found entity 1: chip8 File: /home/nickorlow/programming/school/warminster/yayacemu/chip8.sv Line: 1
|
|
Info (12021): Found 1 design units, including 1 entities, in source file cpu.sv
|
|
Info (12023): Found entity 1: cpu File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 1
|
|
Info (12127): Elaborating entity "chip8" for the top level hierarchy
|
|
Warning (12125): Using design file memory.sv, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
|
|
Info (12023): Found entity 1: memory File: /home/nickorlow/programming/school/warminster/yayacemu/memory.sv Line: 1
|
|
Info (12128): Elaborating entity "memory" for hierarchy "memory:mem" File: /home/nickorlow/programming/school/warminster/yayacemu/chip8.sv Line: 21
|
|
Warning (10850): Verilog HDL warning at memory.sv(14): number of words (80) in memory file does not match the number of elements in the address range [0:4095] File: /home/nickorlow/programming/school/warminster/yayacemu/memory.sv Line: 14
|
|
Warning (10850): Verilog HDL warning at memory.sv(15): number of words (260) in memory file does not match the number of elements in the address range [512:4095] File: /home/nickorlow/programming/school/warminster/yayacemu/memory.sv Line: 15
|
|
Info (12128): Elaborating entity "cpu" for hierarchy "cpu:cpu" File: /home/nickorlow/programming/school/warminster/yayacemu/chip8.sv Line: 35
|
|
Warning (10230): Verilog HDL assignment warning at cpu.sv(124): truncated value with size 32 to match size of target (16) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 124
|
|
Warning (10230): Verilog HDL assignment warning at cpu.sv(130): truncated value with size 32 to match size of target (16) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 130
|
|
Warning (10230): Verilog HDL assignment warning at cpu.sv(147): truncated value with size 32 to match size of target (16) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 147
|
|
Warning (10230): Verilog HDL assignment warning at cpu.sv(210): truncated value with size 32 to match size of target (5) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 210
|
|
Warning (10230): Verilog HDL assignment warning at cpu.sv(213): truncated value with size 32 to match size of target (5) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 213
|
|
Warning (10230): Verilog HDL assignment warning at cpu.sv(242): truncated value with size 32 to match size of target (16) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 242
|
|
Warning (10230): Verilog HDL assignment warning at cpu.sv(246): truncated value with size 32 to match size of target (5) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 246
|
|
Warning (10230): Verilog HDL assignment warning at cpu.sv(257): truncated value with size 32 to match size of target (5) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 257
|
|
Warning (10230): Verilog HDL assignment warning at cpu.sv(284): truncated value with size 32 to match size of target (16) File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 284
|
|
Warning (10030): Net "instr.src_reg" at cpu.sv(108) has no driver or initial value, using a default initial value '0' File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 108
|
|
Warning (10030): Net "instr.src_addr" at cpu.sv(108) has no driver or initial value, using a default initial value '0' File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 108
|
|
Warning (10030): Net "instr.dst_addr" at cpu.sv(108) has no driver or initial value, using a default initial value '0' File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 108
|
|
Info (12128): Elaborating entity "st7920_serial_driver" for hierarchy "cpu:cpu|st7920_serial_driver:gpu" File: /home/nickorlow/programming/school/warminster/yayacemu/cpu.sv Line: 28
|
|
Warning (10036): Verilog HDL or VHDL warning at st7920_serial_driver.sv(23): object "line_idx" assigned a value but never read File: /home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv Line: 23
|
|
Warning (10230): Verilog HDL assignment warning at st7920_serial_driver.sv(71): truncated value with size 32 to match size of target (7) File: /home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv Line: 71
|
|
Warning (10230): Verilog HDL assignment warning at st7920_serial_driver.sv(84): truncated value with size 32 to match size of target (7) File: /home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv Line: 84
|
|
Warning (10230): Verilog HDL assignment warning at st7920_serial_driver.sv(103): truncated value with size 32 to match size of target (6) File: /home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv Line: 103
|
|
Warning (10230): Verilog HDL assignment warning at st7920_serial_driver.sv(131): truncated value with size 32 to match size of target (9) File: /home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv Line: 131
|
|
Warning (10030): Net "commands[6..10]" at st7920_serial_driver.sv(26) has no driver or initial value, using a default initial value '0' File: /home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv Line: 26
|
|
Info (12128): Elaborating entity "commander" for hierarchy "cpu:cpu|st7920_serial_driver:gpu|commander:com" File: /home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv Line: 42
|
|
Info (12128): Elaborating entity "d_flip_flop" for hierarchy "cpu:cpu|st7920_serial_driver:gpu|d_flip_flop:dff" File: /home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv Line: 50
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "memory:mem|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 8
|
|
Info (286033): Parameter WIDTHAD_A set to 12
|
|
Info (286033): Parameter NUMWORDS_A set to 4096
|
|
Info (286033): Parameter WIDTH_B set to 8
|
|
Info (286033): Parameter WIDTHAD_B set to 12
|
|
Info (286033): Parameter NUMWORDS_B set to 4096
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to db/chip8.ram0_memory_e9e85012.hdl.mif
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (12130): Elaborated megafunction instantiation "memory:mem|altsyncram:mem_rtl_0"
|
|
Info (12133): Instantiated megafunction "memory:mem|altsyncram:mem_rtl_0" with the following parameter:
|
|
Info (12134): Parameter "OPERATION_MODE" = "DUAL_PORT"
|
|
Info (12134): Parameter "WIDTH_A" = "8"
|
|
Info (12134): Parameter "WIDTHAD_A" = "12"
|
|
Info (12134): Parameter "NUMWORDS_A" = "4096"
|
|
Info (12134): Parameter "WIDTH_B" = "8"
|
|
Info (12134): Parameter "WIDTHAD_B" = "12"
|
|
Info (12134): Parameter "NUMWORDS_B" = "4096"
|
|
Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE"
|
|
Info (12134): Parameter "OUTDATA_REG_B" = "UNREGISTERED"
|
|
Info (12134): Parameter "ADDRESS_ACLR_B" = "NONE"
|
|
Info (12134): Parameter "OUTDATA_ACLR_B" = "NONE"
|
|
Info (12134): Parameter "ADDRESS_REG_B" = "CLOCK0"
|
|
Info (12134): Parameter "INDATA_ACLR_A" = "NONE"
|
|
Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE"
|
|
Info (12134): Parameter "INIT_FILE" = "db/chip8.ram0_memory_e9e85012.hdl.mif"
|
|
Info (12134): Parameter "READ_DURING_WRITE_MODE_MIXED_PORTS" = "OLD_DATA"
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_dsq1.tdf
|
|
Info (12023): Found entity 1: altsyncram_dsq1 File: /home/nickorlow/programming/school/warminster/yayacemu/db/altsyncram_dsq1.tdf Line: 28
|
|
Warning (13024): Output pins are stuck at VCC or GND
|
|
Warning (13410): Pin "led[5]" is stuck at VCC File: /home/nickorlow/programming/school/warminster/yayacemu/chip8.sv Line: 7
|
|
Info (286030): Timing-Driven Synthesis is running
|
|
Info (17049): 4 registers lost all their fanouts during netlist optimizations.
|
|
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
|
|
Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
|
|
Warning (21074): Design contains 1 input pin(s) that do not drive logic
|
|
Warning (15610): No output dependent on input pin "rst_in" File: /home/nickorlow/programming/school/warminster/yayacemu/chip8.sv Line: 3
|
|
Info (21057): Implemented 17374 device resources after synthesis - the final resource count might be different
|
|
Info (21058): Implemented 2 input pins
|
|
Info (21059): Implemented 8 output pins
|
|
Info (21061): Implemented 17356 logic cells
|
|
Info (21064): Implemented 8 RAM segments
|
|
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 26 warnings
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Info: Peak virtual memory: 698 megabytes
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Info: Processing ended: Sun Apr 7 23:45:53 2024
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Info: Elapsed time: 00:01:02
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Info: Total CPU time (on all processors): 00:01:46
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