30 lines
566 B
Systemverilog
30 lines
566 B
Systemverilog
module keypad(
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input clk_in,
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input wire [3:0] row,
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output logic [3:0] col,
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output [5:0] cur_press
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);
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logic [1:0] col_idx;
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logic [15:0] keymap;
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assign cur_press = {clk_in, 1'b0, keymap[3:0]};
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initial begin
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col_idx = 0;
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col = 0;
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keymap = 0;
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end
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always_ff @(posedge clk_in) begin
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for(logic [2:0] i = 0; i < 4; i++) begin
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keymap[(i*4)+col_idx] <= row[i[1:0]];
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end
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col[col_idx] <= 1;
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col[col_idx+1] <= 0;
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col_idx <= col_idx + 1;
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end
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endmodule
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