77 lines
1.2 KiB
Systemverilog
77 lines
1.2 KiB
Systemverilog
module chip8 (
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input wire fpga_clk,
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input wire rst_in,
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output logic lcd_clk,
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output logic lcd_data,
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output logic [5:0] led,
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input wire [3:0] row,
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output logic [3:0] col,
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output logic beep
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);
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logic debug_overlay;
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logic slow_clk;
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downclocker #(1) dc (
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fpga_clk,
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slow_clk
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);
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logic key_clk;
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downclocker #(12) dck (
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fpga_clk,
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key_clk
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);
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logic [7:0] rd_memory_data;
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logic [11:0] rd_memory_address;
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logic [11:0] wr_memory_address;
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logic [7:0] wr_memory_data;
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logic wr_go;
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memory #(4096) mem (
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slow_clk,
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wr_go,
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wr_memory_address,
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wr_memory_data,
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rd_memory_address,
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rd_memory_data
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);
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logic [15:0] keymap;
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keypad keypad (
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`ifndef DUMMY_KEYPAD
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key_clk,
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`endif
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`ifdef DUMMY_KEYPAD
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slow_clk,
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`endif
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row,
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col,
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keymap
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);
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assign led = { key_clk, 1'b0, slow_clk, 1'b0, fpga_clk, 1'b0};
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int cycle_counter;
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logic [5:0] nc;
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cpu cpu (
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slow_clk,
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fpga_clk,
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rd_memory_data,
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keymap,
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cycle_counter,
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rd_memory_address,
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wr_memory_address,
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wr_memory_data,
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wr_go,
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lcd_clk,
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lcd_data,
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nc,
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beep,
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row,
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col,
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debug_overlay
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);
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endmodule
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