20 lines
555 B
Systemverilog
20 lines
555 B
Systemverilog
module rng (
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input wire clk_in,
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input wire [15:0] bor16,
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input bit [15:0] keyboard,
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input int cycle_counter,
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output bit [7:0] rand_bit
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);
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bit [7:0] last;
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always_ff @(posedge clk_in) begin
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for (int i = 0; i < 5; i++) begin
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rand_bit[i] <= ~keyboard[i == 0 ? 7 : i-1] ? cycle_counter[i] : cycle_counter[7-i];
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rand_bit[i+1%8] <= rand_bit[i] ^ (cycle_counter % 7) == 0 ? bor16[i] : ~bor16[i];
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rand_bit[i+2%8] <= rand_bit[i+1%8] ^ keyboard[i+7] ? ~last[i] : last[i];
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end
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last <= rand_bit;
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end
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endmodule
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