867 lines
28 KiB
Systemverilog
867 lines
28 KiB
Systemverilog
import structs::*;
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module cpu (
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input wire clk_in,
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input wire fpga_clk,
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input wire [7:0] rd_memory_data,
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input wire [15:0] keymap,
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input wire [7:0] random_byte,
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output int cycle_counter,
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output logic [11:0] rd_memory_address,
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output logic [11:0] wr_memory_address,
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output logic [7:0] wr_memory_data,
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output logic wr_go,
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output logic lcd_clk,
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output logic lcd_data,
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output logic [5:0] led,
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output logic beep,
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input wire [3:0] row,
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input wire [3:0] col,
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input wire debug_overlay
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);
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assign beep = sound_timer > 0;
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logic [5:0] lcd_led;
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logic alu_rst;
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logic [7:0] alu_result;
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logic [15:0] alu_result_long;
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logic alu_overflow;
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logic alu_done;
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logic compute_of;
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logic [4:0] vblank;
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assign led = state[5:0];
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alu alu (
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alu_rst,
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clk_in,
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instr.alu_i,
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alu_result,
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alu_result_long,
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alu_overflow,
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alu_done
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);
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logic [7:0] vram [0:1023];
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`ifdef DUMMY_GPU
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gpu gpu(
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`endif
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`ifndef DUMMY_GPU
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st7920_serial_driver gpu(
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`endif
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fpga_clk,
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1'b1,
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vram,
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lcd_clk,
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lcd_data,
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lcd_led
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);
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task write_pixels;
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input [31:0] x;
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input [31:0] y;
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begin
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// bottom left
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`define BLP ((y*128*2) + x*2 +128)
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if (vram[`BLP/8][7-(`BLP%8)] == 1) begin
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registers[15] <= 1;
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end
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vram[`BLP/8][7-(`BLP%8)] <= vram[`BLP/8][7-(`BLP%8)] ^ 1;
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// bottom right
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`define BRP ((y*128*2) + x*2 +129)
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vram[`BRP/8][7-(`BRP%8)] <= vram[`BRP/8][7-(`BRP%8)] ^ 1;
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// top left
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`define TLP ((y*128*2) + x*2)
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vram[`TLP/8][7-(`TLP%8)] <= vram[`TLP/8][7-(`TLP%8)] ^ 1;
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// top right
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`define TRP ((y*128*2) + x*2+1)
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vram[`TRP/8][7-(`TRP%8)] <= vram[`TRP/8][7-(`TRP%8)] ^ 1;
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end
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endtask
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logic [15:0] program_counter;
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logic [7:0] registers[0:15];
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logic [15:0] index_reg;
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logic [15:0] stack[0:15];
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logic [3:0] stack_pointer;
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logic [15:0] opcode;
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logic [7:0] sound_timer;
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logic [7:0] delay_timer;
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logic [7:0] ldl_cnt;
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int clr_cnt;
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typedef enum {ST_FETCH_HI, ST_FETCH_LO, ST_FETCH_LO2, ST_DECODE, ST_EXEC, ST_DRAW, ST_FETCH_MEM, ST_WB, ST_CLEANUP, ST_HALT} cpu_state;
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cpu_state state;
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typedef enum {INIT, DRAW} draw_stage;
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typedef enum {CLS, LD, DRW, JP, ALU, CALU, CALL, RET, ALUJ, LDL, BCD, IOJ, IOW, NIOJ} cpu_opcode;
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typedef enum {REG, IDX_REG, BYTE, MEM, SPRITE_MEM, KEY, DELAY_TIMER, SOUND_TIMER, RAND} data_type;
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struct {
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draw_stage stage;
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logic [4:0] r;
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logic [4:0] c;
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logic [7:0] x;
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logic [7:0] y;
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} draw_state;
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struct packed {
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cpu_opcode op;
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data_type src;
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data_type dst;
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logic [3:0] dst_reg;
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logic [3:0] src_reg;
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alu_input alu_i;
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logic [11:0] src_byte;
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logic [3:0] src_key;
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logic [(8*16)-1:0] src_sprite;
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logic [11:0] src_sprite_addr;
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logic [3:0] src_sprite_vx;
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logic [3:0] src_sprite_vy;
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logic [7:0] src_sprite_x;
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logic [7:0] src_sprite_y;
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logic [4:0] src_sprite_sz;
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logic [4:0] src_sprite_idx;
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logic [11:0] src_addr;
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logic [11:0] dst_addr;
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} instr;
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logic [12:0] wait_key;
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initial begin
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state = ST_FETCH_HI;
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cycle_counter = 0;
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program_counter = 'h200;
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wr_go = 0;
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alu_rst = 1;
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stack_pointer = 0;
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for (int i = 0; i < 1024; i++) begin
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vram[i] = 0;
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end
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end
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always_ff @(posedge clk_in) begin
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if (cycle_counter % 200 == 0) begin
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vblank <= 0;
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if (delay_timer > 0)
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delay_timer <= delay_timer - 1;
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if (sound_timer > 0)
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sound_timer <= sound_timer - 1;
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end else begin
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vblank <= 1;
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end
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case (state)
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ST_FETCH_HI: begin
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rd_memory_address <= program_counter[11:0];
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program_counter <= program_counter + 1;
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state <= ST_FETCH_LO;
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end
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ST_FETCH_LO: begin
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rd_memory_address <= program_counter[11:0];
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program_counter <= program_counter - 1;
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opcode <= { rd_memory_data, 8'h00 };
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state <= ST_FETCH_LO2;
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end
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ST_FETCH_LO2: begin
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opcode <= { opcode[15:8], rd_memory_data};
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state <= ST_DECODE;
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end
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ST_DECODE: begin
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casez (opcode)
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16'h0???: begin
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if (opcode == 16'h00e0) begin
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instr.op <= CLS;
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state <= ST_EXEC;
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clr_cnt <= 0;
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end else if (opcode == 16'h00EE) begin
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instr.op <= RET;
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state <= ST_EXEC;
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end else begin
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program_counter <= program_counter + 2;
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state <= ST_CLEANUP;
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end
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end
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16'h1???: begin
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instr.op <= JP;
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instr.src_byte <= opcode[11:0];
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state <= ST_EXEC;
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end
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16'h2???: begin
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instr.op <= CALL;
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instr.src_byte <= opcode[11:0];
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state <= ST_EXEC;
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end
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16'h3???: begin
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instr.op <= CALU;
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instr.alu_i.op <= structs::SE;
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instr.alu_i.operand_a <= opcode[7:0];
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instr.alu_i.operand_b <= registers[opcode[11:8]];
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compute_of <= 0;
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state <= ST_EXEC;
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end
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16'h4???: begin
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instr.op <= CALU;
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instr.alu_i.op <= structs::SNE;
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instr.alu_i.operand_a <= opcode[7:0];
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instr.alu_i.operand_b <= registers[opcode[11:8]];
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compute_of <= 0;
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state <= ST_EXEC;
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end
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16'h5??0: begin
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instr.op <= CALU;
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instr.alu_i.op <= structs::SE;
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instr.alu_i.operand_a <= registers[opcode[7:4]];
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instr.alu_i.operand_b <= registers[opcode[11:8]];
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compute_of <= 0;
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state <= ST_EXEC;
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end
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16'h6???: begin
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instr.op <= LD;
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instr.src <= BYTE;
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instr.src_byte <= {4'h00, opcode[7:0]};
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instr.dst <= REG;
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instr.dst_reg <= opcode[11:8];
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state <= ST_EXEC;
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end
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16'h7???: begin
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instr.op <= ALU;
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instr.src <= BYTE;
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instr.dst <= REG;
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instr.dst_reg <= opcode[11:8];
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instr.alu_i.op <= structs::ADD;
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instr.alu_i.operand_a <= opcode[7:0];
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instr.alu_i.operand_b <= registers[opcode[11:8]];
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compute_of <= 0;
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state <= ST_EXEC;
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end
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16'h8??0: begin
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instr.op <= LD;
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instr.src <= REG;
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instr.src_reg <= opcode[7:4];
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instr.dst <= REG;
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instr.dst_reg <= opcode[11:8];
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state <= ST_EXEC;
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end
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16'h8??1: begin
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instr.op <= ALU;
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instr.src <= BYTE;
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instr.dst <= REG;
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instr.dst_reg <= opcode[11:8];
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instr.alu_i.op <= structs::OR;
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instr.alu_i.operand_a <= registers[opcode[7:4]];
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instr.alu_i.operand_b <= registers[opcode[11:8]];
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compute_of <= 1;
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state <= ST_EXEC;
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end
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16'h8??2: begin
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instr.op <= ALU;
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instr.src <= BYTE;
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instr.dst <= REG;
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instr.dst_reg <= opcode[11:8];
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instr.alu_i.op <= structs::AND;
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instr.alu_i.operand_a <= registers[opcode[7:4]];
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instr.alu_i.operand_b <= registers[opcode[11:8]];
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compute_of <= 1;
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state <= ST_EXEC;
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end
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16'h8??3: begin
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instr.op <= ALU;
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instr.src <= BYTE;
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instr.dst <= REG;
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instr.dst_reg <= opcode[11:8];
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instr.alu_i.op <= structs::XOR;
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instr.alu_i.operand_a <= registers[opcode[7:4]];
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instr.alu_i.operand_b <= registers[opcode[11:8]];
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compute_of <= 1;
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state <= ST_EXEC;
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end
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16'h8??4: begin
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instr.op <= ALU;
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instr.src <= BYTE;
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instr.dst <= REG;
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instr.dst_reg <= opcode[11:8];
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instr.alu_i.op <= structs::ADD;
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instr.alu_i.operand_a <= registers[opcode[7:4]];
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instr.alu_i.operand_b <= registers[opcode[11:8]];
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compute_of <= 1;
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state <= ST_EXEC;
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end
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16'h8??5: begin
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instr.op <= ALU;
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instr.src <= BYTE;
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instr.dst <= REG;
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instr.dst_reg <= opcode[11:8];
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instr.alu_i.op <= structs::SUB;
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instr.alu_i.operand_a <= registers[opcode[11:8]];
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instr.alu_i.operand_b <= registers[opcode[7:4]];
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compute_of <= 1;
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state <= ST_EXEC;
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end
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16'h8??6: begin
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instr.op <= ALU;
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instr.src <= BYTE;
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instr.dst <= REG;
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instr.dst_reg <= opcode[11:8];
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instr.alu_i.op <= structs::SHR;
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instr.alu_i.operand_a <= registers[opcode[7:4]];
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instr.alu_i.operand_b <= 1;
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compute_of <= 1;
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state <= ST_EXEC;
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end
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16'h8??7: begin
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instr.op <= ALU;
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instr.src <= BYTE;
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instr.dst <= REG;
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instr.dst_reg <= opcode[11:8];
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instr.alu_i.op <= structs::SUB;
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instr.alu_i.operand_a <= registers[opcode[7:4]];
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instr.alu_i.operand_b <= registers[opcode[11:8]];
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compute_of <= 1;
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state <= ST_EXEC;
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end
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16'h8??E: begin
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instr.op <= ALU;
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instr.src <= BYTE;
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instr.dst <= REG;
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instr.dst_reg <= opcode[11:8];
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instr.alu_i.op <= structs::SHL;
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instr.alu_i.operand_a <= registers[opcode[7:4]];
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instr.alu_i.operand_b <= 1;
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compute_of <= 1;
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state <= ST_EXEC;
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end
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16'h9??0: begin
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instr.op <= CALU;
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instr.alu_i.op <= structs::SNE;
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instr.alu_i.operand_a <= registers[opcode[7:4]];
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instr.alu_i.operand_b <= registers[opcode[11:8]];
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compute_of <= 0;
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state <= ST_EXEC;
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end
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16'hA???: begin
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instr.op <= LD;
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instr.src <= BYTE;
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instr.src_byte <= opcode[11:0];
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instr.dst <= IDX_REG;
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state <= ST_EXEC;
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end
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16'hB???: begin
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instr.op <= ALUJ;
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instr.alu_i.op <= structs::ADDL;
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instr.alu_i.operand_a <= registers[0];
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instr.alu_i.operand_b_long <= opcode[11:0];
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compute_of <= 0;
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state <= ST_EXEC;
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end
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16'hC???: begin
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instr.op <= LD;
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instr.src <= RAND;
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instr.src_byte <= {4'h0, opcode[7:0]};
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instr.dst <= REG;
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instr.dst_reg <= opcode[11:8];
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state <= ST_EXEC;
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end
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16'hD???: begin
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instr.op <= DRW;
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instr.src <= SPRITE_MEM;
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instr.src_sprite_sz <= {1'b0, opcode[3:0]};
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instr.src_sprite_addr <= index_reg[11:0];
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instr.src_sprite_vx <= opcode[11:8];
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instr.src_sprite_vy <= opcode[7:4];
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instr.src_sprite_idx <= 0;
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state <= ST_FETCH_MEM;
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end
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16'hE?9E: begin
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instr.op <= IOJ;
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instr.src <= KEY;
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instr.src_key <= registers[opcode[11:8]][3:0];
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state <= ST_EXEC;
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end
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16'hE?A1: begin
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instr.op <= NIOJ;
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instr.src <= KEY;
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instr.src_key <= registers[opcode[11:8]][3:0];
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state <= ST_EXEC;
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end
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16'hF?07: begin
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instr.op <= LD;
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instr.src <= DELAY_TIMER;
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instr.dst <= REG;
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instr.dst_reg <= opcode[11:8];
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state <= ST_EXEC;
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end
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16'hF?0A: begin
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instr.op <= IOW;
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wait_key[12] <= 1;
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instr.src <= KEY;
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instr.dst <= REG;
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instr.dst_reg <= opcode[11:8];
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state <= ST_EXEC;
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end
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16'hF?15: begin
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instr.op <= LD;
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instr.src <= REG;
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instr.src_reg <= opcode[11:8];
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instr.dst <= DELAY_TIMER;
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state <= ST_EXEC;
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end
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16'hF?18: begin
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instr.op <= LD;
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instr.src <= REG;
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instr.src_reg <= opcode[11:8];
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instr.dst <= SOUND_TIMER;
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state <= ST_EXEC;
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end
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16'hF?1E: begin
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instr.op <= ALU;
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instr.src <= BYTE;
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instr.dst <= IDX_REG;
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instr.alu_i.op <= structs::ADDL;
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instr.alu_i.operand_a <= registers[opcode[11:8]];
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instr.alu_i.operand_b_long <= index_reg[11:0];
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compute_of <= 0;
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state <= ST_EXEC;
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end
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16'hF?29: begin
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instr.op <= LD;
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instr.src <= BYTE;
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instr.src_byte <= registers[opcode[11:8]] * 5;
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instr.dst <= IDX_REG;
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state <= ST_EXEC;
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end
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16'hF?33: begin
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instr.op <= BCD;
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instr.src <= REG;
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instr.src_reg <= opcode[11:8];
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instr.dst <= MEM;
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instr.dst_addr <= index_reg[11:0];
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ldl_cnt <= 0;
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state <= ST_EXEC;
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end
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16'hF?55: begin
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instr.op <= LDL;
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index_reg <= index_reg + 1;
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instr.src <= REG;
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instr.src_reg <= opcode[11:8]; //FIXME: need to expand mem?
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instr.dst <= MEM;
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/* verilator lint_off WIDTHEXPAND */
|
|
instr.dst_addr <= index_reg[11:0] + opcode[11:8] + 1; //FIXME: need to expand mem?
|
|
|
|
/* verilator lint_off WIDTHEXPAND */
|
|
ldl_cnt <= opcode[11:8];
|
|
|
|
state <= ST_EXEC;
|
|
end
|
|
16'hF?65: begin
|
|
instr.op <= LDL;
|
|
index_reg <= index_reg + 1;
|
|
|
|
instr.src <= MEM;
|
|
/* verilator lint_off WIDTHEXPAND */
|
|
instr.src_addr <= index_reg[11:0] + opcode[11:8]; //FIXME: need to expand mem?
|
|
|
|
instr.dst <= REG;
|
|
instr.dst_reg <= opcode[11:8];
|
|
|
|
state <= ST_FETCH_MEM;
|
|
end
|
|
default: begin
|
|
state <= ST_HALT;
|
|
end
|
|
endcase
|
|
end
|
|
|
|
ST_FETCH_MEM: begin
|
|
if (instr.src == MEM) begin
|
|
if (rd_memory_address == instr.src_addr) begin
|
|
instr.src_byte <= { 4'h0, rd_memory_data};
|
|
instr.src <= BYTE;
|
|
state <= ST_EXEC;
|
|
end else begin
|
|
rd_memory_address <= instr.src_addr;
|
|
end
|
|
end
|
|
|
|
if (instr.src == SPRITE_MEM) begin
|
|
if (instr.src_sprite_idx == 0) begin
|
|
rd_memory_address <= instr.src_sprite_addr + {7'b0000000, instr.src_sprite_idx};
|
|
instr.src_sprite_idx <= instr.src_sprite_idx + 1;
|
|
end else if (instr.src_sprite_idx <= instr.src_sprite_sz) begin
|
|
rd_memory_address <= instr.src_sprite_addr + {7'b0000000, instr.src_sprite_idx};
|
|
instr.src_sprite_idx <= instr.src_sprite_idx + 1;
|
|
for (int l = 0; l < 8; l++)
|
|
instr.src_sprite[(instr.src_sprite_idx-1)*8+l] <= rd_memory_data[7-l];
|
|
end else begin
|
|
instr.src_sprite_x <= registers[instr.src_sprite_vx] % 8'd64;
|
|
instr.src_sprite_y <= registers[instr.src_sprite_vy] % 8'd32;
|
|
state <= ST_DRAW;
|
|
draw_state.stage <= INIT;
|
|
end
|
|
end
|
|
end
|
|
|
|
ST_HALT: begin end
|
|
|
|
ST_DRAW: begin
|
|
if (draw_state.stage == INIT) begin
|
|
if (vblank == 0) begin
|
|
draw_state.x <= instr.src_sprite_x;
|
|
draw_state.y <= instr.src_sprite_y;
|
|
|
|
draw_state.r <= 0;
|
|
draw_state.c <= 0;
|
|
|
|
draw_state.stage <= DRAW;
|
|
registers[15] <= 0;
|
|
end
|
|
end else begin
|
|
if (draw_state.r == instr.src_sprite_sz) begin
|
|
state <= ST_CLEANUP;
|
|
program_counter <= program_counter + 2;
|
|
end else begin
|
|
if (draw_state.c == 5'd8) begin
|
|
draw_state.c <= 0;
|
|
draw_state.r <= draw_state.r + 1;
|
|
end else begin
|
|
/* verilator lint_off WIDTHEXPAND */
|
|
if (draw_state.r + instr.src_sprite_y < 32 && draw_state.c + instr.src_sprite_x < 64) begin
|
|
`define DRAW_PX ((draw_state.r + instr.src_sprite_y)*64 + (draw_state.c + instr.src_sprite_x))
|
|
|
|
/* verilator lint_off WIDTHEXPAND */
|
|
if (instr.src_sprite[(draw_state.r*8) + draw_state.c]) begin
|
|
write_pixels(draw_state.c + instr.src_sprite_x, draw_state.r + instr.src_sprite_y);
|
|
end
|
|
end
|
|
draw_state.c <= draw_state.c + 1;
|
|
end
|
|
end
|
|
|
|
end
|
|
end
|
|
|
|
ST_EXEC: begin
|
|
case (instr.op)
|
|
LD: begin
|
|
if (instr.src == REG) begin
|
|
instr.src_byte <= { 4'h0, registers[instr.src_reg] };
|
|
instr.src <= BYTE;
|
|
end else if (instr.src == DELAY_TIMER) begin
|
|
instr.src_byte <= { 4'h0, delay_timer };
|
|
instr.src <= BYTE;
|
|
end else if (instr.src == RAND) begin
|
|
instr.src_byte <= {4'h0, random_byte} & instr.src_byte ;
|
|
instr.src <= BYTE;
|
|
end
|
|
end
|
|
LDL: begin
|
|
if (instr.dst == REG) begin
|
|
registers[instr.dst_reg] <= instr.src_byte[7:0];
|
|
|
|
if (instr.dst_reg == 0) begin
|
|
program_counter <= program_counter + 2;
|
|
state <= ST_CLEANUP;
|
|
end else begin
|
|
instr.src <= MEM;
|
|
instr.dst_reg <= instr.dst_reg - 1;
|
|
instr.src_addr <= instr.src_addr - 1;
|
|
state <= ST_FETCH_MEM;
|
|
end
|
|
end
|
|
if (instr.dst == MEM) begin
|
|
instr.src <= BYTE;
|
|
|
|
instr.src_byte <= {4'h0, registers[instr.src_reg]};
|
|
instr.src_reg <= instr.src_reg - 1;
|
|
instr.dst_addr <= instr.dst_addr - 1;
|
|
ldl_cnt <= ldl_cnt - 1;
|
|
|
|
|
|
if (ldl_cnt > 15) begin
|
|
program_counter <= program_counter + 2;
|
|
// state <= ST_HALT;
|
|
state <= ST_CLEANUP;
|
|
end else begin
|
|
state <= ST_WB;
|
|
end
|
|
end
|
|
end
|
|
BCD: begin
|
|
instr.src <= BYTE;
|
|
ldl_cnt <= ldl_cnt + 1;
|
|
case (ldl_cnt)
|
|
0: begin
|
|
instr.src_byte <= (registers[instr.src_reg]/100) % 10;
|
|
state <= ST_WB;
|
|
end
|
|
1: begin
|
|
instr.dst_addr <= instr.dst_addr + 1;
|
|
instr.src_byte <= (registers[instr.src_reg]/10) % 10;
|
|
state <= ST_WB;
|
|
end
|
|
2: begin
|
|
instr.dst_addr <= instr.dst_addr + 1;
|
|
instr.src_byte <= registers[instr.src_reg] % 10;
|
|
state <= ST_WB;
|
|
end
|
|
3: begin
|
|
program_counter <= program_counter + 2;
|
|
state <= ST_CLEANUP;
|
|
end
|
|
endcase
|
|
end
|
|
JP: begin
|
|
program_counter <= {4'h00, instr.src_byte};
|
|
state <= ST_CLEANUP;
|
|
end
|
|
CALU,
|
|
ALUJ,
|
|
ALU: begin
|
|
alu_rst <= 0;
|
|
if (alu_done) begin
|
|
instr.src <= BYTE;
|
|
|
|
if (instr.dst == IDX_REG)
|
|
instr.src_byte <= alu_result_long[11:0];
|
|
else if (instr.dst_reg != 15 || !compute_of) begin
|
|
instr.src_byte <= alu_result;
|
|
end else begin
|
|
instr.src_byte <= alu_overflow;
|
|
end
|
|
|
|
registers[15] <= compute_of ? alu_overflow : registers[15];
|
|
|
|
if (instr.op === ALU) begin
|
|
state <= ST_WB;
|
|
program_counter <= program_counter + 2;
|
|
|
|
end else if (instr.op === CALU) begin
|
|
|
|
state <= ST_CLEANUP;
|
|
if (|alu_result) begin
|
|
program_counter <= program_counter + 4;
|
|
end else begin
|
|
program_counter <= program_counter + 2;
|
|
end
|
|
end else if (instr.op === ALUJ) begin
|
|
|
|
state <= ST_CLEANUP;
|
|
program_counter <= alu_result_long;
|
|
|
|
end
|
|
end
|
|
end
|
|
CALL: begin
|
|
stack[stack_pointer] <= program_counter;
|
|
stack_pointer <= stack_pointer + 1;
|
|
program_counter <= instr.src_byte;
|
|
state <= ST_CLEANUP;
|
|
end
|
|
RET: begin
|
|
stack_pointer <= stack_pointer - 1;
|
|
program_counter <= stack[stack_pointer-1] + 2;
|
|
state <= ST_CLEANUP;
|
|
end
|
|
IOJ: begin
|
|
if (keymap[instr.src_key] == 1) begin
|
|
program_counter <= program_counter + 4;
|
|
end else begin
|
|
program_counter <= program_counter + 2;
|
|
end
|
|
state <= ST_CLEANUP;
|
|
end
|
|
NIOJ: begin
|
|
if (keymap[instr.src_key] != 1) begin
|
|
program_counter <= program_counter + 4;
|
|
end else begin
|
|
program_counter <= program_counter + 2;
|
|
end
|
|
state <= ST_CLEANUP;
|
|
end
|
|
IOW: begin
|
|
if (|keymap != 0 && wait_key[12] == 1) begin
|
|
for(int m = 0; m < 16; m++) begin
|
|
if (keymap[m]) begin
|
|
wait_key[11:0] <= m[11:0];
|
|
wait_key[12] <= 0;
|
|
end
|
|
end
|
|
end
|
|
if (keymap[wait_key[3:0]] == 0 && wait_key[12] == 0) begin
|
|
instr.src_byte <= wait_key[11:0];
|
|
program_counter <= program_counter + 2;
|
|
state <= ST_WB;
|
|
instr.src <= BYTE;
|
|
end
|
|
end
|
|
CLS: begin
|
|
if (clr_cnt == 1024) begin
|
|
state <= ST_CLEANUP;
|
|
program_counter <= program_counter + 2;
|
|
end else begin
|
|
clr_cnt <= clr_cnt + 1;
|
|
vram[clr_cnt] <= 8'h00;
|
|
end
|
|
end
|
|
|
|
endcase
|
|
|
|
case (instr.op)
|
|
LD,
|
|
DRW: begin
|
|
|
|
program_counter <= program_counter + 2;
|
|
state <= ST_WB;
|
|
end
|
|
endcase
|
|
end
|
|
|
|
ST_WB: begin
|
|
if (instr.src != BYTE)
|
|
$fatal();
|
|
|
|
case (instr.dst)
|
|
MEM: begin
|
|
wr_memory_address <= instr.dst_addr;
|
|
wr_memory_data <= instr.src_byte[7:0];
|
|
wr_go <= 1'b1;
|
|
end
|
|
REG: registers[instr.dst_reg] <= instr.src_byte[7:0];
|
|
IDX_REG: index_reg <= {4'h0, instr.src_byte};
|
|
DELAY_TIMER: delay_timer <= instr.src_byte[7:0];
|
|
SOUND_TIMER: sound_timer <= instr.src_byte[7:0];
|
|
endcase
|
|
|
|
if (instr.op != LDL && instr.op != BCD)
|
|
state <= ST_CLEANUP;
|
|
else begin
|
|
state <= ST_EXEC;
|
|
instr.src <= REG;
|
|
end
|
|
end
|
|
|
|
ST_CLEANUP: begin
|
|
wr_go <= 0;
|
|
state <= ST_FETCH_HI;
|
|
alu_rst <= 1;
|
|
end
|
|
endcase
|
|
|
|
if (debug_overlay) begin
|
|
for(int w = 0; w < 16; w++) begin
|
|
vram[16+w] <= keymap[w] ? 8'hff : 0;
|
|
end
|
|
|
|
for (int z = 0; z < 4; z++) begin
|
|
vram[32 + z] = col[z] ? 8'hff : 0;
|
|
vram[64 + z] = row[z] ? 8'hff : 0;
|
|
end
|
|
end
|
|
|
|
cycle_counter <= cycle_counter + 1;
|
|
end
|
|
endmodule
|