--lpm_abs CARRY_CHAIN="MANUAL" DEVICE_FAMILY="Cyclone V" IGNORE_CARRY_BUFFERS="OFF" LPM_WIDTH=6 data result --VERSION_BEGIN 23.1 cbx_cycloneii 2023:11:29:19:33:06:SC cbx_lpm_abs 2023:11:29:19:33:06:SC cbx_lpm_add_sub 2023:11:29:19:33:06:SC cbx_mgl 2023:11:29:19:43:53:SC cbx_nadder 2023:11:29:19:33:06:SC cbx_stratix 2023:11:29:19:33:06:SC cbx_stratixii 2023:11:29:19:33:05:SC cbx_util_mgl 2023:11:29:19:33:06:SC VERSION_END -- Copyright (C) 2023 Intel Corporation. All rights reserved. -- Your use of Intel Corporation's design tools, logic functions -- and other software and tools, and any partner logic -- functions, and any output files from any of the foregoing -- (including device programming or simulation files), and any -- associated documentation or information are expressly subject -- to the terms and conditions of the Intel Program License -- Subscription Agreement, the Intel Quartus Prime License Agreement, -- the Intel FPGA IP License Agreement, or other applicable license -- agreement, including, without limitation, that your use is for -- the sole purpose of programming logic devices manufactured by -- Intel and sold by Intel or its authorized distributors. Please -- refer to the applicable agreement for further details, at -- https://fpgasoftware.intel.com/eula. --synthesis_resources = lut 6 SUBDESIGN lpm_abs_ln9 ( data[5..0] : input; overflow : output; result[5..0] : output; ) VARIABLE adder_result_int[6..0] : WIRE; adder_cin : WIRE; adder_dataa[5..0] : WIRE; adder_datab[5..0] : WIRE; adder_result[5..0] : WIRE; gnd_wire : WIRE; result_tmp[5..0] : WIRE; BEGIN adder_result_int[] = (adder_dataa[], adder_cin) + (adder_datab[], adder_cin); adder_result[] = adder_result_int[6..1]; adder_cin = data[5..5]; adder_dataa[] = (data[] $ data[5..5]); adder_datab[] = ( gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire); gnd_wire = B"0"; overflow = (result_tmp[5..5] & data[5..5]); result[] = result_tmp[]; result_tmp[] = adder_result[]; END; --VALID FILE