--lpm_abs CARRY_CHAIN="MANUAL" DEVICE_FAMILY="Cyclone V" IGNORE_CARRY_BUFFERS="OFF" LPM_WIDTH=4 data result --VERSION_BEGIN 23.1 cbx_cycloneii 2023:11:29:19:33:06:SC cbx_lpm_abs 2023:11:29:19:33:06:SC cbx_lpm_add_sub 2023:11:29:19:33:06:SC cbx_mgl 2023:11:29:19:43:53:SC cbx_nadder 2023:11:29:19:33:06:SC cbx_stratix 2023:11:29:19:33:06:SC cbx_stratixii 2023:11:29:19:33:05:SC cbx_util_mgl 2023:11:29:19:33:06:SC VERSION_END -- Copyright (C) 2023 Intel Corporation. All rights reserved. -- Your use of Intel Corporation's design tools, logic functions -- and other software and tools, and any partner logic -- functions, and any output files from any of the foregoing -- (including device programming or simulation files), and any -- associated documentation or information are expressly subject -- to the terms and conditions of the Intel Program License -- Subscription Agreement, the Intel Quartus Prime License Agreement, -- the Intel FPGA IP License Agreement, or other applicable license -- agreement, including, without limitation, that your use is for -- the sole purpose of programming logic devices manufactured by -- Intel and sold by Intel or its authorized distributors. Please -- refer to the applicable agreement for further details, at -- https://fpgasoftware.intel.com/eula. --synthesis_resources = lut 3 SUBDESIGN lpm_abs_jn9 ( data[3..0] : input; overflow : output; result[3..0] : output; ) VARIABLE result_tmp[3..0] : WIRE; BEGIN overflow = (result_tmp[3..3] & data[3..3]); result[] = result_tmp[]; result_tmp[] = ( (data[3..3] & (! ((data[2..2] # data[1..1]) # data[0..0]))), (((data[2..2] $ (data[1..1] # data[0..0])) & data[3..3]) # (data[2..2] & (! data[3..3]))), (((data[1..1] $ data[0..0]) & data[3..3]) # (data[1..1] & (! data[3..3]))), data[0..0]); END; --VALID FILE