--abs_divider DEN_REPRESENTATION="SIGNED" LPM_PIPELINE=0 MAXIMIZE_SPEED=5 NUM_REPRESENTATION="SIGNED" SKIP_BITS=0 WIDTH_D=6 WIDTH_N=32 denominator numerator quotient remainder --VERSION_BEGIN 23.1 cbx_cycloneii 2023:11:29:19:33:06:SC cbx_lpm_abs 2023:11:29:19:33:06:SC cbx_lpm_add_sub 2023:11:29:19:33:06:SC cbx_lpm_divide 2023:11:29:19:33:06:SC cbx_mgl 2023:11:29:19:43:53:SC cbx_nadder 2023:11:29:19:33:06:SC cbx_stratix 2023:11:29:19:33:06:SC cbx_stratixii 2023:11:29:19:33:05:SC cbx_util_mgl 2023:11:29:19:33:06:SC VERSION_END -- Copyright (C) 2023 Intel Corporation. All rights reserved. -- Your use of Intel Corporation's design tools, logic functions -- and other software and tools, and any partner logic -- functions, and any output files from any of the foregoing -- (including device programming or simulation files), and any -- associated documentation or information are expressly subject -- to the terms and conditions of the Intel Program License -- Subscription Agreement, the Intel Quartus Prime License Agreement, -- the Intel FPGA IP License Agreement, or other applicable license -- agreement, including, without limitation, that your use is for -- the sole purpose of programming logic devices manufactured by -- Intel and sold by Intel or its authorized distributors. Please -- refer to the applicable agreement for further details, at -- https://fpgasoftware.intel.com/eula. FUNCTION alt_u_div_qve (denominator[5..0], numerator[31..0]) RETURNS ( quotient[31..0], remainder[5..0]); FUNCTION lpm_abs_ln9 (data[5..0]) RETURNS ( overflow, result[5..0]); FUNCTION lpm_abs_4p9 (data[31..0]) RETURNS ( overflow, result[31..0]); --synthesis_resources = lut 311 SUBDESIGN abs_divider_lbg ( denominator[5..0] : input; numerator[31..0] : input; quotient[31..0] : output; remainder[5..0] : output; ) VARIABLE divider : alt_u_div_qve; my_abs_den : lpm_abs_ln9; my_abs_num : lpm_abs_4p9; compl_add_quot_result_int[32..0] : WIRE; compl_add_quot_cin : WIRE; compl_add_quot_dataa[31..0] : WIRE; compl_add_quot_datab[31..0] : WIRE; compl_add_quot_result[31..0] : WIRE; compl_add_rem_result_int[6..0] : WIRE; compl_add_rem_cin : WIRE; compl_add_rem_dataa[5..0] : WIRE; compl_add_rem_datab[5..0] : WIRE; compl_add_rem_result[5..0] : WIRE; diff_signs : WIRE; gnd_wire : WIRE; neg_quot[31..0] : WIRE; neg_rem[5..0] : WIRE; norm_den[5..0] : WIRE; norm_num[31..0] : WIRE; num_sign : WIRE; protect_quotient[31..0] : WIRE; protect_remainder[5..0] : WIRE; vcc_wire : WIRE; BEGIN divider.denominator[] = norm_den[]; divider.numerator[] = norm_num[]; my_abs_den.data[] = denominator[]; my_abs_num.data[] = numerator[]; compl_add_quot_result_int[] = (compl_add_quot_dataa[], compl_add_quot_cin) + (compl_add_quot_datab[], compl_add_quot_cin); compl_add_quot_result[] = compl_add_quot_result_int[32..1]; compl_add_quot_cin = vcc_wire; compl_add_quot_dataa[] = (! protect_quotient[]); compl_add_quot_datab[] = ( gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire); compl_add_rem_result_int[] = (compl_add_rem_dataa[], compl_add_rem_cin) + (compl_add_rem_datab[], compl_add_rem_cin); compl_add_rem_result[] = compl_add_rem_result_int[6..1]; compl_add_rem_cin = vcc_wire; compl_add_rem_dataa[] = (! protect_remainder[]); compl_add_rem_datab[] = ( gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire); diff_signs = (numerator[31..31] $ denominator[5..5]); gnd_wire = B"0"; neg_quot[] = compl_add_quot_result[]; neg_rem[] = compl_add_rem_result[]; norm_den[] = my_abs_den.result[]; norm_num[] = my_abs_num.result[]; num_sign = numerator[31..31]; protect_quotient[] = divider.quotient[]; protect_remainder[] = divider.remainder[]; quotient[] = ((protect_quotient[] & (! diff_signs)) # (neg_quot[] & diff_signs)); remainder[] = ((protect_remainder[] & (! num_sign)) # (neg_rem[] & num_sign)); vcc_wire = B"1"; END; --VALID FILE