alu simple

2024-04-08 01:28:28 -05:00 · 2024-04-08 01:28:28 -05:00 · f63cc9738f
parent a93cc69e2c
commit f63cc9738f
4 changed files with 162 additions and 243 deletions
--- a/.nvim/svlangserver/linter.vc
+++ b/.nvim/svlangserver/linter.vc
@ -1,3 +1,6 @@
+-v /work/structs.sv
+-v /work/astructs.sv
+-v /work/aastructs.sv
 +incdir+/work
 +incdir+/work/the-bomb
 +incdir+/work
--- a/cpu.sv
+++ b/cpu.sv
@ -1,3 +1,5 @@
+import structs::*;
+
 module cpu (
    input wire clk_in,
    input wire [7:0] rd_memory_data,
@ -11,6 +13,20 @@ module cpu (
    output logic [5:0] led
 );

+  logic alu_rst;
+  logic [7:0] alu_result;
+  logic alu_overflow;
+  logic alu_done;
+
+  alu alu (
+      alu_rst,
+      clk_in, 
+      instr.alu_i,
+      alu_result,
+      alu_overflow,
+      alu_done
+      );
+
  logic [7:0] vram [0:1023];

 `ifdef DUMMY_GPU
@ -72,7 +88,7 @@ module cpu (
  
  typedef enum {INIT, DRAW} draw_stage;
  
-  typedef enum {CLS, LD, DRW, JP} cpu_opcode;
+  typedef enum {CLS, LD, DRW, JP, ALU} cpu_opcode;
  typedef enum {REG, IDX_REG, BYTE, MEM, SPRITE_MEM} data_type;

  struct {
@ -92,6 +108,8 @@ module cpu (
      logic [3:0] dst_reg;
      logic [3:0] src_reg;

+      alu_input alu_i; 
+
      logic [11:0] src_byte;

      logic [(8*16)-1:0] src_sprite;
@ -112,6 +130,7 @@ module cpu (
    cycle_counter = 0;
    program_counter = 'h200;
    wr_go = 0;
+    alu_rst = 1;
    for (int i = 0; i < 1024; i++) begin
        vram[i] = 0;
    end
@ -163,6 +182,20 @@ module cpu (

                   state <= ST_EXEC;
                end
+                16'h7???: begin
+                    instr.op <= ALU;
+
+                    instr.src <= BYTE;
+
+                    instr.dst <= REG;
+                    instr.dst_reg <= opcode[11:8];
+
+                    instr.alu_i.op <= structs::ADD;
+                    instr.alu_i.operand_a <= opcode[7:0];
+                    instr.alu_i.operand_b <= registers[opcode[11:8]];
+
+                    state <= ST_EXEC;
+                end
                16'hA???: begin
                   $display("Instruction is LD I, Byte"); 
                   instr.op <= LD; 
@ -274,6 +307,16 @@ module cpu (
                   program_counter <= {4'h00, instr.src_byte}; 
                   state <= ST_CLEANUP;
                end
+                ALU: begin
+                    alu_rst <= 0;
+                    if (alu_done) begin
+                        instr.src <= BYTE;
+                        instr.src_byte <= alu_result;
+                        registers[15] <= alu_overflow;
+                        state <= ST_WB;
+                        program_counter <= program_counter + 2;
+                    end
+                end
            endcase

            case (instr.op) 
@ -309,6 +352,7 @@ module cpu (
        ST_CLEANUP: begin
           wr_go <= 0; 
           state <= ST_FETCH_HI;
+           alu_rst <= 1;
        end
    endcase

--- a/4
+++ b/4
@ -2,7 +2,7 @@

 SDL_CFLAGS = `sdl2-config --cflags`
 SDL_LDFLAGS = `sdl2-config --libs`
-SV_FILES=cpu.sv chip8.sv gpu.sv
+SV_FILES=aastructs.sv cpu.sv chip8.sv gpu.sv alu.sv

 lint:
 	verilator --lint-only -DDUMMY_GPU --timing ${SV_FILES} 
@ -10,7 +10,7 @@ lint:
 build-rom:
 	python3 ./gen_rom.py ${ROM_FILE} rom.bin

-build: lint build-rom
+build: build-rom
 	verilator --cc --exe --build --timing -j 0 --top-module chip8 *.sv yayacemu.cpp -DDUMMY_GPU -CFLAGS "${SDL_CFLAGS}" -LDFLAGS "${SDL_LDFLAGS}" && clear

 run: build
--- a/rom.bin
+++ b/rom.bin
@ -1,260 +1,132 @@
 00000000
 11100000
-01100001
-00000001
+10100010
+00101010
 01100000
+00001100
+01100001
+00001000
+11010000
+00011111
+01110000
+00001001
+10100010
+00111001
+11010000
+00011111
+10100010
+01001000
+01110000
+00001000
+11010000
+00011111
+01110000
+00000100
+10100010
+01010111
+11010000
+00011111
+01110000
 00001000
 10100010
-01010000
+01100110
 11010000
 00011111
-01100000
-00010000
-10100010
-01011111
-11010000
-00011111
-01100000
-00011000
-10100010
-01101110
-11010000
-00011111
-01100000
-00100000
-10100010
-01111101
-11010000
-00011111
-01100000
-00101000
-10100010
-10001100
-11010000
-00011111
-01100000
-00110000
-10100010
-10011011
-11010000
-00011111
-01100001
-00010000
-01100000
+01110000
 00001000
 10100010
-10101010
-11010000
-00011111
-01100000
-00010000
-10100010
-10111001
-11010000
-00011111
-01100000
-00011000
-10100010
-11001000
-11010000
-00011111
-01100000
-00100000
-10100010
-11010111
-11010000
-00011111
-01100000
-00101000
-10100010
-11100110
-11010000
-00011111
-01100000
-00110000
-10100010
-11110101
+01110101
 11010000
 00011111
 00010010
-01001110
+00101000
+11111111
+00000000
+11111111
+00000000
+00111100
+00000000
+00111100
+00000000
+00111100
+00000000
+00111100
+00000000
+11111111
+00000000
+11111111
+11111111
+00000000
+11111111
+00000000
+00111000
+00000000
+00111111
+00000000
+00111111
+00000000
+00111000
+00000000
+11111111
+00000000
+11111111
+10000000
+00000000
+11100000
+00000000
+11100000
+00000000
+10000000
+00000000
+10000000
+00000000
+11100000
+00000000
+11100000
+00000000
+10000000
+11111000
+00000000
+11111100
+00000000
+00111110
+00000000
+00111111
+00000000
+00111011
+00000000
+00111001
+00000000
+11111000
+00000000
+11111000
+00000011
+00000000
+00000111
+00000000
 00001111
-00000010
-00000010
-00000010
-00000010
-00000010
 00000000
-00000000
-00011111
-00111111
-01110001
-11100000
-11100101
-11100000
-11101000
-10100000
-00001101
-00101010
-00101000
-00101000
-00101000
-00000000
-00000000
-00011000
-10111000
-10111000
-00111000
-00111000
-00111111
 10111111
 00000000
-00011001
-10100101
-10111101
-10100001
-10011101
+11111011
 00000000
+11110011
 00000000
-00001100
-00011101
-00011101
+11100011
+00000000
+01000011
+11100101
+00000101
+11100010
+00000000
+10000101
+00000111
+10000001
 00000001
-00001101
-00011101
-10011101
-00000001
-11000111
-00101001
-00101001
-00101001
-00100111
-00000000
-00000000
-11111000
-11111100
-11001110
-11000110
-11000110
-11000110
-11000110
-00000000
-01001001
-01001010
-01001001
-01001000
-00111011
-00000000
-00000000
-00000000
-00000001
-00000011
-00000011
-00000011
-00000001
-11110000
-00110000
-10010000
-00000000
-00000000
 10000000
-00000000
-00000000
-00000000
-11111110
-11000111
-10000011
-10000011
-10000011
-11000110
-11111100
+00000010
+10000000
+00000010
+11100110
+00000010
 11100111
-11100000
-11100000
-11100000
-11100000
-01110001
-00111111
-00011111
-00000000
-00000000
-00000111
-00000010
-00000010
-00000010
-00000010
-00111001
-00111000
-00111000
-00111000
-00111000
-10111000
-10111000
-00111000
-00000000
-00000000
-00110001
-01001010
-01111001
-01000000
-00111011
-11011101
-11011101
-11011101
-11011101
-11011101
-11011101
-11011101
-11011101
-00000000
-00000000
-10100000
-00111000
-00100000
-10100000
-00011000
-11001110
-11111100
-11111000
-11000000
-11010100
-11011100
-11000100
-11000101
-00000000
-00000000
-00110000
-01000100
-00100100
-00010100
-01100011
-11110001
-00000011
-00000111
-00000111
-00100111
-01100111
-00100011
-01110001
-00000000
-00000000
-00101000
-10001110
-10101000
-10101000
-10100110
-11001110
-10000111
-00000011
-00000011
-00000011
-10000111
-11111110
-11111100
-00000000
-00000000
-01100000
-10010000
-11110000
-10000000
-01110000