make better
This commit is contained in:
		
							parent
							
								
									fdd6553f11
								
							
						
					
					
						commit
						f2c0935b60
					
				
					 128 changed files with 39530 additions and 530 deletions
				
			
		
							
								
								
									
										43
									
								
								db/lpm_divide_82m.tdf
									
										
									
									
									
										Normal file
									
								
							
							
						
						
									
										43
									
								
								db/lpm_divide_82m.tdf
									
										
									
									
									
										Normal file
									
								
							| 
						 | 
				
			
			@ -0,0 +1,43 @@
 | 
			
		|||
--lpm_divide DEVICE_FAMILY="Cyclone V" LPM_DREPRESENTATION="UNSIGNED" LPM_NREPRESENTATION="UNSIGNED" LPM_WIDTHD=4 LPM_WIDTHN=8 OPTIMIZE_FOR_SPEED=5 denom numer remain CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 IGNORE_CARRY_BUFFERS="OFF"
 | 
			
		||||
--VERSION_BEGIN 23.1 cbx_cycloneii 2023:11:29:19:33:06:SC cbx_lpm_abs 2023:11:29:19:33:06:SC cbx_lpm_add_sub 2023:11:29:19:33:06:SC cbx_lpm_divide 2023:11:29:19:33:06:SC cbx_mgl 2023:11:29:19:43:53:SC cbx_nadder 2023:11:29:19:33:06:SC cbx_stratix 2023:11:29:19:33:06:SC cbx_stratixii 2023:11:29:19:33:05:SC cbx_util_mgl 2023:11:29:19:33:06:SC  VERSION_END
 | 
			
		||||
 | 
			
		||||
 | 
			
		||||
-- Copyright (C) 2023  Intel Corporation. All rights reserved.
 | 
			
		||||
--  Your use of Intel Corporation's design tools, logic functions 
 | 
			
		||||
--  and other software and tools, and any partner logic 
 | 
			
		||||
--  functions, and any output files from any of the foregoing 
 | 
			
		||||
--  (including device programming or simulation files), and any 
 | 
			
		||||
--  associated documentation or information are expressly subject 
 | 
			
		||||
--  to the terms and conditions of the Intel Program License 
 | 
			
		||||
--  Subscription Agreement, the Intel Quartus Prime License Agreement,
 | 
			
		||||
--  the Intel FPGA IP License Agreement, or other applicable license
 | 
			
		||||
--  agreement, including, without limitation, that your use is for
 | 
			
		||||
--  the sole purpose of programming logic devices manufactured by
 | 
			
		||||
--  Intel and sold by Intel or its authorized distributors.  Please
 | 
			
		||||
--  refer to the applicable agreement for further details, at
 | 
			
		||||
--  https://fpgasoftware.intel.com/eula.
 | 
			
		||||
 | 
			
		||||
 | 
			
		||||
FUNCTION sign_div_unsign_bkh (denominator[3..0], numerator[7..0])
 | 
			
		||||
RETURNS ( quotient[7..0], remainder[3..0]);
 | 
			
		||||
 | 
			
		||||
--synthesis_resources = lut 38 
 | 
			
		||||
SUBDESIGN lpm_divide_82m
 | 
			
		||||
( 
 | 
			
		||||
	denom[3..0]	:	input;
 | 
			
		||||
	numer[7..0]	:	input;
 | 
			
		||||
	quotient[7..0]	:	output;
 | 
			
		||||
	remain[3..0]	:	output;
 | 
			
		||||
) 
 | 
			
		||||
VARIABLE 
 | 
			
		||||
	divider : sign_div_unsign_bkh;
 | 
			
		||||
	numer_tmp[7..0]	: WIRE;
 | 
			
		||||
 | 
			
		||||
BEGIN 
 | 
			
		||||
	divider.denominator[] = denom[];
 | 
			
		||||
	divider.numerator[] = numer_tmp[];
 | 
			
		||||
	numer_tmp[] = numer[];
 | 
			
		||||
	quotient[] = divider.quotient[];
 | 
			
		||||
	remain[] = divider.remainder[];
 | 
			
		||||
END;
 | 
			
		||||
--VALID FILE
 | 
			
		||||
		Loading…
	
	Add table
		Add a link
		
	
		Reference in a new issue