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This commit is contained in:
Nicholas Orlowsky 2024-04-07 23:39:15 -05:00
parent fdd6553f11
commit f2c0935b60
Signed by: nickorlow
GPG key ID: 838827D8C4611687
128 changed files with 39530 additions and 530 deletions
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--abs_divider DEN_REPRESENTATION="SIGNED" LPM_PIPELINE=0 MAXIMIZE_SPEED=5 NUM_REPRESENTATION="SIGNED" SKIP_BITS=0 WIDTH_D=4 WIDTH_N=32 denominator numerator quotient remainder
--VERSION_BEGIN 23.1 cbx_cycloneii 2023:11:29:19:33:06:SC cbx_lpm_abs 2023:11:29:19:33:06:SC cbx_lpm_add_sub 2023:11:29:19:33:06:SC cbx_lpm_divide 2023:11:29:19:33:06:SC cbx_mgl 2023:11:29:19:43:53:SC cbx_nadder 2023:11:29:19:33:06:SC cbx_stratix 2023:11:29:19:33:06:SC cbx_stratixii 2023:11:29:19:33:05:SC cbx_util_mgl 2023:11:29:19:33:06:SC VERSION_END
-- Copyright (C) 2023 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details, at
-- https://fpgasoftware.intel.com/eula.
FUNCTION alt_u_div_mve (denominator[3..0], numerator[31..0])
RETURNS ( quotient[31..0], remainder[3..0]);
FUNCTION lpm_abs_jn9 (data[3..0])
RETURNS ( overflow, result[3..0]);
FUNCTION lpm_abs_4p9 (data[31..0])
RETURNS ( result[31..0]);
--synthesis_resources = lut 221
SUBDESIGN abs_divider_jbg
(
denominator[3..0] : input;
numerator[31..0] : input;
quotient[31..0] : output;
remainder[3..0] : output;
)
VARIABLE
divider : alt_u_div_mve;
my_abs_den : lpm_abs_jn9;
my_abs_num : lpm_abs_4p9;
compl_add_quot_result_int[32..0] : WIRE;
compl_add_quot_cin : WIRE;
compl_add_quot_dataa[31..0] : WIRE;
compl_add_quot_datab[31..0] : WIRE;
compl_add_quot_result[31..0] : WIRE;
compl_add_rem_result_int[4..0] : WIRE;
compl_add_rem_cin : WIRE;
compl_add_rem_dataa[3..0] : WIRE;
compl_add_rem_datab[3..0] : WIRE;
compl_add_rem_result[3..0] : WIRE;
diff_signs : WIRE;
gnd_wire : WIRE;
neg_quot[31..0] : WIRE;
neg_rem[3..0] : WIRE;
norm_den[3..0] : WIRE;
norm_num[31..0] : WIRE;
num_sign : WIRE;
protect_quotient[31..0] : WIRE;
protect_remainder[3..0] : WIRE;
vcc_wire : WIRE;
BEGIN
divider.denominator[] = norm_den[];
divider.numerator[] = norm_num[];
my_abs_den.data[] = denominator[];
my_abs_num.data[] = numerator[];
compl_add_quot_result_int[] = (compl_add_quot_dataa[], compl_add_quot_cin) + (compl_add_quot_datab[], compl_add_quot_cin);
compl_add_quot_result[] = compl_add_quot_result_int[32..1];
compl_add_quot_cin = vcc_wire;
compl_add_quot_dataa[] = (! protect_quotient[]);
compl_add_quot_datab[] = ( gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire);
compl_add_rem_result_int[] = (compl_add_rem_dataa[], compl_add_rem_cin) + (compl_add_rem_datab[], compl_add_rem_cin);
compl_add_rem_result[] = compl_add_rem_result_int[4..1];
compl_add_rem_cin = vcc_wire;
compl_add_rem_dataa[] = (! protect_remainder[]);
compl_add_rem_datab[] = ( gnd_wire, gnd_wire, gnd_wire, gnd_wire);
diff_signs = (numerator[31..31] $ denominator[3..3]);
gnd_wire = B"0";
neg_quot[] = compl_add_quot_result[];
neg_rem[] = compl_add_rem_result[];
norm_den[] = my_abs_den.result[];
norm_num[] = my_abs_num.result[];
num_sign = numerator[31..31];
protect_quotient[] = divider.quotient[];
protect_remainder[] = divider.remainder[];
quotient[] = ((protect_quotient[] & (! diff_signs)) # (neg_quot[] & diff_signs));
remainder[] = ((protect_remainder[] & (! num_sign)) # (neg_rem[] & num_sign));
vcc_wire = B"1";
END;
--VALID FILE

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--abs_divider DEN_REPRESENTATION="SIGNED" LPM_PIPELINE=0 MAXIMIZE_SPEED=5 NUM_REPRESENTATION="SIGNED" SKIP_BITS=0 WIDTH_D=6 WIDTH_N=32 denominator numerator quotient remainder
--VERSION_BEGIN 23.1 cbx_cycloneii 2023:11:29:19:33:06:SC cbx_lpm_abs 2023:11:29:19:33:06:SC cbx_lpm_add_sub 2023:11:29:19:33:06:SC cbx_lpm_divide 2023:11:29:19:33:06:SC cbx_mgl 2023:11:29:19:43:53:SC cbx_nadder 2023:11:29:19:33:06:SC cbx_stratix 2023:11:29:19:33:06:SC cbx_stratixii 2023:11:29:19:33:05:SC cbx_util_mgl 2023:11:29:19:33:06:SC VERSION_END
-- Copyright (C) 2023 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details, at
-- https://fpgasoftware.intel.com/eula.
FUNCTION alt_u_div_qve (denominator[5..0], numerator[31..0])
RETURNS ( quotient[31..0], remainder[5..0]);
FUNCTION lpm_abs_ln9 (data[5..0])
RETURNS ( overflow, result[5..0]);
FUNCTION lpm_abs_4p9 (data[31..0])
RETURNS ( overflow, result[31..0]);
--synthesis_resources = lut 311
SUBDESIGN abs_divider_lbg
(
denominator[5..0] : input;
numerator[31..0] : input;
quotient[31..0] : output;
remainder[5..0] : output;
)
VARIABLE
divider : alt_u_div_qve;
my_abs_den : lpm_abs_ln9;
my_abs_num : lpm_abs_4p9;
compl_add_quot_result_int[32..0] : WIRE;
compl_add_quot_cin : WIRE;
compl_add_quot_dataa[31..0] : WIRE;
compl_add_quot_datab[31..0] : WIRE;
compl_add_quot_result[31..0] : WIRE;
compl_add_rem_result_int[6..0] : WIRE;
compl_add_rem_cin : WIRE;
compl_add_rem_dataa[5..0] : WIRE;
compl_add_rem_datab[5..0] : WIRE;
compl_add_rem_result[5..0] : WIRE;
diff_signs : WIRE;
gnd_wire : WIRE;
neg_quot[31..0] : WIRE;
neg_rem[5..0] : WIRE;
norm_den[5..0] : WIRE;
norm_num[31..0] : WIRE;
num_sign : WIRE;
protect_quotient[31..0] : WIRE;
protect_remainder[5..0] : WIRE;
vcc_wire : WIRE;
BEGIN
divider.denominator[] = norm_den[];
divider.numerator[] = norm_num[];
my_abs_den.data[] = denominator[];
my_abs_num.data[] = numerator[];
compl_add_quot_result_int[] = (compl_add_quot_dataa[], compl_add_quot_cin) + (compl_add_quot_datab[], compl_add_quot_cin);
compl_add_quot_result[] = compl_add_quot_result_int[32..1];
compl_add_quot_cin = vcc_wire;
compl_add_quot_dataa[] = (! protect_quotient[]);
compl_add_quot_datab[] = ( gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire);
compl_add_rem_result_int[] = (compl_add_rem_dataa[], compl_add_rem_cin) + (compl_add_rem_datab[], compl_add_rem_cin);
compl_add_rem_result[] = compl_add_rem_result_int[6..1];
compl_add_rem_cin = vcc_wire;
compl_add_rem_dataa[] = (! protect_remainder[]);
compl_add_rem_datab[] = ( gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire);
diff_signs = (numerator[31..31] $ denominator[5..5]);
gnd_wire = B"0";
neg_quot[] = compl_add_quot_result[];
neg_rem[] = compl_add_rem_result[];
norm_den[] = my_abs_den.result[];
norm_num[] = my_abs_num.result[];
num_sign = numerator[31..31];
protect_quotient[] = divider.quotient[];
protect_remainder[] = divider.remainder[];
quotient[] = ((protect_quotient[] & (! diff_signs)) # (neg_quot[] & diff_signs));
remainder[] = ((protect_remainder[] & (! num_sign)) # (neg_rem[] & num_sign));
vcc_wire = B"1";
END;
--VALID FILE

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--alt_u_div DEVICE_FAMILY="Cyclone V" LPM_PIPELINE=0 MAXIMIZE_SPEED=5 SKIP_BITS=0 WIDTH_D=4 WIDTH_N=8 WIDTH_Q=8 WIDTH_R=4 denominator numerator quotient remainder
--VERSION_BEGIN 23.1 cbx_cycloneii 2023:11:29:19:33:06:SC cbx_lpm_abs 2023:11:29:19:33:06:SC cbx_lpm_add_sub 2023:11:29:19:33:06:SC cbx_lpm_divide 2023:11:29:19:33:06:SC cbx_mgl 2023:11:29:19:43:53:SC cbx_nadder 2023:11:29:19:33:06:SC cbx_stratix 2023:11:29:19:33:06:SC cbx_stratixii 2023:11:29:19:33:05:SC cbx_util_mgl 2023:11:29:19:33:06:SC VERSION_END
-- Copyright (C) 2023 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details, at
-- https://fpgasoftware.intel.com/eula.
--synthesis_resources = lut 38
SUBDESIGN alt_u_div_sse
(
denominator[3..0] : input;
numerator[7..0] : input;
quotient[7..0] : output;
remainder[3..0] : output;
)
VARIABLE
add_sub_0_result_int[1..0] : WIRE;
add_sub_0_cout : WIRE;
add_sub_0_dataa[0..0] : WIRE;
add_sub_0_datab[0..0] : WIRE;
add_sub_0_result[0..0] : WIRE;
add_sub_1_result_int[2..0] : WIRE;
add_sub_1_cout : WIRE;
add_sub_1_dataa[1..0] : WIRE;
add_sub_1_datab[1..0] : WIRE;
add_sub_1_result[1..0] : WIRE;
add_sub_2_result_int[3..0] : WIRE;
add_sub_2_cout : WIRE;
add_sub_2_dataa[2..0] : WIRE;
add_sub_2_datab[2..0] : WIRE;
add_sub_2_result[2..0] : WIRE;
add_sub_3_result_int[4..0] : WIRE;
add_sub_3_cout : WIRE;
add_sub_3_dataa[3..0] : WIRE;
add_sub_3_datab[3..0] : WIRE;
add_sub_3_result[3..0] : WIRE;
add_sub_4_result_int[5..0] : WIRE;
add_sub_4_cout : WIRE;
add_sub_4_dataa[4..0] : WIRE;
add_sub_4_datab[4..0] : WIRE;
add_sub_4_result[4..0] : WIRE;
add_sub_5_result_int[5..0] : WIRE;
add_sub_5_cout : WIRE;
add_sub_5_dataa[4..0] : WIRE;
add_sub_5_datab[4..0] : WIRE;
add_sub_5_result[4..0] : WIRE;
add_sub_6_result_int[5..0] : WIRE;
add_sub_6_cout : WIRE;
add_sub_6_dataa[4..0] : WIRE;
add_sub_6_datab[4..0] : WIRE;
add_sub_6_result[4..0] : WIRE;
add_sub_7_result_int[5..0] : WIRE;
add_sub_7_cout : WIRE;
add_sub_7_dataa[4..0] : WIRE;
add_sub_7_datab[4..0] : WIRE;
add_sub_7_result[4..0] : WIRE;
DenominatorIn[44..0] : WIRE;
DenominatorIn_tmp[44..0] : WIRE;
gnd_wire : WIRE;
nose[71..0] : WIRE;
NumeratorIn[71..0] : WIRE;
NumeratorIn_tmp[71..0] : WIRE;
prestg[39..0] : WIRE;
quotient_tmp[7..0] : WIRE;
sel[35..0] : WIRE;
selnose[71..0] : WIRE;
StageIn[44..0] : WIRE;
StageIn_tmp[44..0] : WIRE;
StageOut[39..0] : WIRE;
BEGIN
add_sub_0_result_int[] = (0, add_sub_0_dataa[]) - (0, add_sub_0_datab[]);
add_sub_0_result[] = add_sub_0_result_int[0..0];
add_sub_0_cout = !add_sub_0_result_int[1];
add_sub_0_dataa[] = NumeratorIn[7..7];
add_sub_0_datab[] = DenominatorIn[0..0];
add_sub_1_result_int[] = (0, add_sub_1_dataa[]) - (0, add_sub_1_datab[]);
add_sub_1_result[] = add_sub_1_result_int[1..0];
add_sub_1_cout = !add_sub_1_result_int[2];
add_sub_1_dataa[] = ( StageIn[5..5], NumeratorIn[14..14]);
add_sub_1_datab[] = DenominatorIn[6..5];
add_sub_2_result_int[] = (0, add_sub_2_dataa[]) - (0, add_sub_2_datab[]);
add_sub_2_result[] = add_sub_2_result_int[2..0];
add_sub_2_cout = !add_sub_2_result_int[3];
add_sub_2_dataa[] = ( StageIn[11..10], NumeratorIn[21..21]);
add_sub_2_datab[] = DenominatorIn[12..10];
add_sub_3_result_int[] = (0, add_sub_3_dataa[]) - (0, add_sub_3_datab[]);
add_sub_3_result[] = add_sub_3_result_int[3..0];
add_sub_3_cout = !add_sub_3_result_int[4];
add_sub_3_dataa[] = ( StageIn[17..15], NumeratorIn[28..28]);
add_sub_3_datab[] = DenominatorIn[18..15];
add_sub_4_result_int[] = (0, add_sub_4_dataa[]) - (0, add_sub_4_datab[]);
add_sub_4_result[] = add_sub_4_result_int[4..0];
add_sub_4_cout = !add_sub_4_result_int[5];
add_sub_4_dataa[] = ( StageIn[23..20], NumeratorIn[35..35]);
add_sub_4_datab[] = DenominatorIn[24..20];
add_sub_5_result_int[] = (0, add_sub_5_dataa[]) - (0, add_sub_5_datab[]);
add_sub_5_result[] = add_sub_5_result_int[4..0];
add_sub_5_cout = !add_sub_5_result_int[5];
add_sub_5_dataa[] = ( StageIn[28..25], NumeratorIn[42..42]);
add_sub_5_datab[] = DenominatorIn[29..25];
add_sub_6_result_int[] = (0, add_sub_6_dataa[]) - (0, add_sub_6_datab[]);
add_sub_6_result[] = add_sub_6_result_int[4..0];
add_sub_6_cout = !add_sub_6_result_int[5];
add_sub_6_dataa[] = ( StageIn[33..30], NumeratorIn[49..49]);
add_sub_6_datab[] = DenominatorIn[34..30];
add_sub_7_result_int[] = (0, add_sub_7_dataa[]) - (0, add_sub_7_datab[]);
add_sub_7_result[] = add_sub_7_result_int[4..0];
add_sub_7_cout = !add_sub_7_result_int[5];
add_sub_7_dataa[] = ( StageIn[38..35], NumeratorIn[56..56]);
add_sub_7_datab[] = DenominatorIn[39..35];
DenominatorIn[] = DenominatorIn_tmp[];
DenominatorIn_tmp[] = ( DenominatorIn[39..0], ( gnd_wire, denominator[]));
gnd_wire = B"0";
nose[] = ( B"00000000", add_sub_7_cout, B"00000000", add_sub_6_cout, B"00000000", add_sub_5_cout, B"00000000", add_sub_4_cout, B"00000000", add_sub_3_cout, B"00000000", add_sub_2_cout, B"00000000", add_sub_1_cout, B"00000000", add_sub_0_cout);
NumeratorIn[] = NumeratorIn_tmp[];
NumeratorIn_tmp[] = ( NumeratorIn[63..0], numerator[]);
prestg[] = ( add_sub_7_result[], add_sub_6_result[], add_sub_5_result[], add_sub_4_result[], GND, add_sub_3_result[], B"00", add_sub_2_result[], B"000", add_sub_1_result[], B"0000", add_sub_0_result[]);
quotient[] = quotient_tmp[];
quotient_tmp[] = ( (! selnose[0..0]), (! selnose[9..9]), (! selnose[18..18]), (! selnose[27..27]), (! selnose[36..36]), (! selnose[45..45]), (! selnose[54..54]), (! selnose[63..63]));
remainder[3..0] = StageIn[43..40];
sel[] = ( gnd_wire, (sel[35..35] # DenominatorIn[43..43]), (sel[34..34] # DenominatorIn[42..42]), (sel[33..33] # DenominatorIn[41..41]), gnd_wire, (sel[31..31] # DenominatorIn[38..38]), (sel[30..30] # DenominatorIn[37..37]), (sel[29..29] # DenominatorIn[36..36]), gnd_wire, (sel[27..27] # DenominatorIn[33..33]), (sel[26..26] # DenominatorIn[32..32]), (sel[25..25] # DenominatorIn[31..31]), gnd_wire, (sel[23..23] # DenominatorIn[28..28]), (sel[22..22] # DenominatorIn[27..27]), (sel[21..21] # DenominatorIn[26..26]), gnd_wire, (sel[19..19] # DenominatorIn[23..23]), (sel[18..18] # DenominatorIn[22..22]), (sel[17..17] # DenominatorIn[21..21]), gnd_wire, (sel[15..15] # DenominatorIn[18..18]), (sel[14..14] # DenominatorIn[17..17]), (sel[13..13] # DenominatorIn[16..16]), gnd_wire, (sel[11..11] # DenominatorIn[13..13]), (sel[10..10] # DenominatorIn[12..12]), (sel[9..9] # DenominatorIn[11..11]), gnd_wire, (sel[7..7] # DenominatorIn[8..8]), (sel[6..6] # DenominatorIn[7..7]), (sel[5..5] # DenominatorIn[6..6]), gnd_wire, (sel[3..3] # DenominatorIn[3..3]), (sel[2..2] # DenominatorIn[2..2]), (sel[1..1] # DenominatorIn[1..1]));
selnose[] = ( (! nose[71..71]), (! nose[70..70]), (! nose[69..69]), (! nose[68..68]), ((! nose[67..67]) # sel[35..35]), ((! nose[66..66]) # sel[34..34]), ((! nose[65..65]) # sel[33..33]), ((! nose[64..64]) # sel[32..32]), (! nose[63..63]), (! nose[62..62]), (! nose[61..61]), (! nose[60..60]), ((! nose[59..59]) # sel[31..31]), ((! nose[58..58]) # sel[30..30]), ((! nose[57..57]) # sel[29..29]), ((! nose[56..56]) # sel[28..28]), (! nose[55..55]), (! nose[54..54]), (! nose[53..53]), (! nose[52..52]), ((! nose[51..51]) # sel[27..27]), ((! nose[50..50]) # sel[26..26]), ((! nose[49..49]) # sel[25..25]), ((! nose[48..48]) # sel[24..24]), (! nose[47..47]), (! nose[46..46]), (! nose[45..45]), (! nose[44..44]), ((! nose[43..43]) # sel[23..23]), ((! nose[42..42]) # sel[22..22]), ((! nose[41..41]) # sel[21..21]), ((! nose[40..40]) # sel[20..20]), (! nose[39..39]), (! nose[38..38]), (! nose[37..37]), (! nose[36..36]), ((! nose[35..35]) # sel[19..19]), ((! nose[34..34]) # sel[18..18]), ((! nose[33..33]) # sel[17..17]), ((! nose[32..32]) # sel[16..16]), (! nose[31..31]), (! nose[30..30]), (! nose[29..29]), (! nose[28..28]), ((! nose[27..27]) # sel[15..15]), ((! nose[26..26]) # sel[14..14]), ((! nose[25..25]) # sel[13..13]), ((! nose[24..24]) # sel[12..12]), (! nose[23..23]), (! nose[22..22]), (! nose[21..21]), (! nose[20..20]), ((! nose[19..19]) # sel[11..11]), ((! nose[18..18]) # sel[10..10]), ((! nose[17..17]) # sel[9..9]), ((! nose[16..16]) # sel[8..8]), (! nose[15..15]), (! nose[14..14]), (! nose[13..13]), (! nose[12..12]), ((! nose[11..11]) # sel[7..7]), ((! nose[10..10]) # sel[6..6]), ((! nose[9..9]) # sel[5..5]), ((! nose[8..8]) # sel[4..4]), (! nose[7..7]), (! nose[6..6]), (! nose[5..5]), (! nose[4..4]), ((! nose[3..3]) # sel[3..3]), ((! nose[2..2]) # sel[2..2]), ((! nose[1..1]) # sel[1..1]), ((! nose[0..0]) # sel[0..0]));
StageIn[] = StageIn_tmp[];
StageIn_tmp[] = ( StageOut[39..0], B"00000");
StageOut[] = ( ((( StageIn[38..35], NumeratorIn[56..56]) & selnose[63..63]) # (prestg[39..35] & (! selnose[63..63]))), ((( StageIn[33..30], NumeratorIn[49..49]) & selnose[54..54]) # (prestg[34..30] & (! selnose[54..54]))), ((( StageIn[28..25], NumeratorIn[42..42]) & selnose[45..45]) # (prestg[29..25] & (! selnose[45..45]))), ((( StageIn[23..20], NumeratorIn[35..35]) & selnose[36..36]) # (prestg[24..20] & (! selnose[36..36]))), ((( StageIn[18..15], NumeratorIn[28..28]) & selnose[27..27]) # (prestg[19..15] & (! selnose[27..27]))), ((( StageIn[13..10], NumeratorIn[21..21]) & selnose[18..18]) # (prestg[14..10] & (! selnose[18..18]))), ((( StageIn[8..5], NumeratorIn[14..14]) & selnose[9..9]) # (prestg[9..5] & (! selnose[9..9]))), ((( StageIn[3..0], NumeratorIn[7..7]) & selnose[0..0]) # (prestg[4..0] & (! selnose[0..0]))));
END;
--VALID FILE

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<?xml version="1.0" ?>
<LOG_ROOT>
<PROJECT NAME="chip8">
</PROJECT>
</LOG_ROOT>

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Quartus_Version = Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition
Version_Index = 570679040
Creation_Time = Sun Apr 7 15:25:35 2024

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{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1712529585582 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "12 12 " "Parallel compilation is enabled and will use 12 of the 12 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1712529585582 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "chip8 5CSEBA6U23I7 " "Selected device 5CSEBA6U23I7 for design \"chip8\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1712529587114 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature -40 degrees C " "Low junction temperature is -40 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1712529587136 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 100 degrees C " "High junction temperature is 100 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1712529587136 ""}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1712529592466 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1712529592564 ""}
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1712529600469 ""}
{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1712529632442 ""}
{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "2 s (2 global) " "Automatically promoted 2 clocks (2 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "dc:dc\|clk_out~CLKENA0 35217 global CLKCTRL_G2 " "dc:dc\|clk_out~CLKENA0 with 35217 fanout uses global clock CLKCTRL_G2" { { "Info" "ICCLK_UNLOCKED_FOR_VPR" "" "This signal is driven by core routing -- it may be moved during placement to reduce routing delays" { } { } 0 12525 "This signal is driven by core routing -- it may be moved during placement to reduce routing delays" 0 0 "Design Software" 0 -1 1712529642530 ""} } { } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1712529642530 ""} { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "clk_in~inputCLKENA0 31 global CLKCTRL_G5 " "clk_in~inputCLKENA0 with 31 fanout uses global clock CLKCTRL_G5" { } { } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1712529642530 ""} } { } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1712529642530 ""}

36265
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<TABLE>
<TR bgcolor="#C0C0C0">
<TH>Hierarchy</TH>
<TH>Input</TH>
<TH>Constant Input</TH>
<TH>Unused Input</TH>
<TH>Floating Input</TH>
<TH>Output</TH>
<TH>Constant Output</TH>
<TH>Unused Output</TH>
<TH>Floating Output</TH>
<TH>Bidir</TH>
<TH>Constant Bidir</TH>
<TH>Unused Bidir</TH>
<TH>Input only Bidir</TH>
<TH>Output only Bidir</TH>
</TR>
<TR >
<TD >randy</TD>
<TD >65</TD>
<TD >32</TD>
<TD >0</TD>
<TD >32</TD>
<TD >8</TD>
<TD >32</TD>
<TD >32</TD>
<TD >32</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >gpu|dff</TD>
<TD >2</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >gpu|com</TD>
<TD >12</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >gpu</TD>
<TD >10</TD>
<TD >1</TD>
<TD >0</TD>
<TD >1</TD>
<TD >18</TD>
<TD >1</TD>
<TD >1</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >cpu</TD>
<TD >37</TD>
<TD >25</TD>
<TD >0</TD>
<TD >25</TD>
<TD >48</TD>
<TD >25</TD>
<TD >25</TD>
<TD >25</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >dc</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
</TABLE>

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+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Legal Partition Candidates ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; randy ; 65 ; 32 ; 0 ; 32 ; 8 ; 32 ; 32 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; gpu|dff ; 2 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; gpu|com ; 12 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; gpu ; 10 ; 1 ; 0 ; 1 ; 18 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; cpu ; 37 ; 25 ; 0 ; 25 ; 48 ; 25 ; 25 ; 25 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; dc ; 1 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1712551112815 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition " "Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1712551112815 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 7 23:38:32 2024 " "Processing started: Sun Apr 7 23:38:32 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1712551112815 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712551112815 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off chip8 -c chip8 " "Command: quartus_map --read_settings_files=on --write_settings_files=off chip8 -c chip8" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712551112816 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1712551112956 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "12 12 " "Parallel compilation is enabled and will use 12 of the 12 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1712551112956 ""}
{ "Critical Warning" "WVRFX_VERI_UNDEFINED_MACRO" "DELAY_BITS st7920_serial_driver.sv(12) " "Verilog HDL Compiler Directive warning at st7920_serial_driver.sv(12): text macro \"DELAY_BITS\" is undefined" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 12 0 0 } } } 1 10191 "Verilog HDL Compiler Directive warning at %2!s!: text macro \"%1!s!\" is undefined" 0 0 "Analysis & Synthesis" 0 -1 1712551118395 ""}
{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\":\"; expecting an operand st7920_serial_driver.sv(12) " "Verilog HDL syntax error at st7920_serial_driver.sv(12) near text: \":\"; expecting an operand. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 12 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1712551118395 ""}
{ "Critical Warning" "WVRFX_VERI_UNDEFINED_MACRO" "BOOTSTRAP_INSTRS st7920_serial_driver.sv(64) " "Verilog HDL Compiler Directive warning at st7920_serial_driver.sv(64): text macro \"BOOTSTRAP_INSTRS\" is undefined" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 64 0 0 } } } 1 10191 "Verilog HDL Compiler Directive warning at %2!s!: text macro \"%1!s!\" is undefined" 0 0 "Analysis & Synthesis" 0 -1 1712551118395 ""}
{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\")\"; expecting an operand st7920_serial_driver.sv(64) " "Verilog HDL syntax error at st7920_serial_driver.sv(64) near text: \")\"; expecting an operand. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 64 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1712551118395 ""}
{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"else\"; expecting \"end\" st7920_serial_driver.sv(70) " "Verilog HDL syntax error at st7920_serial_driver.sv(70) near text: \"else\"; expecting \"end\". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 70 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1712551118395 ""}
{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\")\"; expecting an operand st7920_serial_driver.sv(94) " "Verilog HDL syntax error at st7920_serial_driver.sv(94) near text: \")\"; expecting an operand. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 94 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1712551118395 ""}
{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\")\"; expecting an operand st7920_serial_driver.sv(97) " "Verilog HDL syntax error at st7920_serial_driver.sv(97) near text: \")\"; expecting an operand. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 97 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1712551118395 ""}
{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"\]\"; expecting an operand st7920_serial_driver.sv(124) " "Verilog HDL syntax error at st7920_serial_driver.sv(124) near text: \"\]\"; expecting an operand. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 124 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1712551118395 ""}
{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"else\"; expecting \"end\" st7920_serial_driver.sv(127) " "Verilog HDL syntax error at st7920_serial_driver.sv(127) near text: \"else\"; expecting \"end\". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 127 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1712551118395 ""}
{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "st7920_serial_driver st7920_serial_driver.sv(1) " "Ignored design unit \"st7920_serial_driver\" at st7920_serial_driver.sv(1) due to previous errors" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 1 0 0 } } } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Analysis & Synthesis" 0 -1 1712551118395 ""}
{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "d_flip_flop st7920_serial_driver.sv(134) " "Ignored design unit \"d_flip_flop\" at st7920_serial_driver.sv(134) due to previous errors" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 134 0 0 } } } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Analysis & Synthesis" 0 -1 1712551118395 ""}
{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "commander st7920_serial_driver.sv(144) " "Ignored design unit \"commander\" at st7920_serial_driver.sv(144) due to previous errors" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 144 0 0 } } } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Analysis & Synthesis" 0 -1 1712551118396 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "the-bomb/st7920_serial_driver.sv 0 0 " "Found 0 design units, including 0 entities, in source file the-bomb/st7920_serial_driver.sv" { } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712551118396 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "chip8.sv 1 1 " "Found 1 design units, including 1 entities, in source file chip8.sv" { { "Info" "ISGN_ENTITY_NAME" "1 chip8 " "Found entity 1: chip8" { } { { "chip8.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/chip8.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712551118397 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712551118397 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu.sv 1 1 " "Found 1 design units, including 1 entities, in source file cpu.sv" { { "Info" "ISGN_ENTITY_NAME" "1 cpu " "Found entity 1: cpu" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712551118398 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712551118398 ""}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 10 s 3 s Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 10 errors, 3 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "383 " "Peak virtual memory: 383 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1712551118425 ""} { "Error" "EQEXE_END_BANNER_TIME" "Sun Apr 7 23:38:38 2024 " "Processing ended: Sun Apr 7 23:38:38 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1712551118425 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1712551118425 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:14 " "Total CPU time (on all processors): 00:00:14" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1712551118425 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1712551118425 ""}

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SOURCE

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start_analysis_synthesis:s:01:10:32
start_analysis_elaboration:s

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{
"partitions" : [
{
"name" : "Top",
"pins" : [
{
"name" : "lcd_clk",
"strict" : false
},
{
"name" : "lcd_data",
"strict" : false
},
{
"name" : "led[0]",
"strict" : false
},
{
"name" : "led[1]",
"strict" : false
},
{
"name" : "led[2]",
"strict" : false
},
{
"name" : "led[3]",
"strict" : false
},
{
"name" : "led[4]",
"strict" : false
},
{
"name" : "clk_in",
"strict" : false
}
]
}
]
}

49
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--lpm_abs CARRY_CHAIN="MANUAL" DEVICE_FAMILY="Cyclone V" IGNORE_CARRY_BUFFERS="OFF" LPM_WIDTH=32 data result
--VERSION_BEGIN 23.1 cbx_cycloneii 2023:11:29:19:33:06:SC cbx_lpm_abs 2023:11:29:19:33:06:SC cbx_lpm_add_sub 2023:11:29:19:33:06:SC cbx_mgl 2023:11:29:19:43:53:SC cbx_nadder 2023:11:29:19:33:06:SC cbx_stratix 2023:11:29:19:33:06:SC cbx_stratixii 2023:11:29:19:33:05:SC cbx_util_mgl 2023:11:29:19:33:06:SC VERSION_END
-- Copyright (C) 2023 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details, at
-- https://fpgasoftware.intel.com/eula.
--synthesis_resources = lut 32
SUBDESIGN lpm_abs_4p9
(
data[31..0] : input;
overflow : output;
result[31..0] : output;
)
VARIABLE
adder_result_int[32..0] : WIRE;
adder_cin : WIRE;
adder_dataa[31..0] : WIRE;
adder_datab[31..0] : WIRE;
adder_result[31..0] : WIRE;
gnd_wire : WIRE;
result_tmp[31..0] : WIRE;
BEGIN
adder_result_int[] = (adder_dataa[], adder_cin) + (adder_datab[], adder_cin);
adder_result[] = adder_result_int[32..1];
adder_cin = data[31..31];
adder_dataa[] = (data[] $ data[31..31]);
adder_datab[] = ( gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire);
gnd_wire = B"0";
overflow = (result_tmp[31..31] & data[31..31]);
result[] = result_tmp[];
result_tmp[] = adder_result[];
END;
--VALID FILE

37
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--lpm_abs CARRY_CHAIN="MANUAL" DEVICE_FAMILY="Cyclone V" IGNORE_CARRY_BUFFERS="OFF" LPM_WIDTH=4 data result
--VERSION_BEGIN 23.1 cbx_cycloneii 2023:11:29:19:33:06:SC cbx_lpm_abs 2023:11:29:19:33:06:SC cbx_lpm_add_sub 2023:11:29:19:33:06:SC cbx_mgl 2023:11:29:19:43:53:SC cbx_nadder 2023:11:29:19:33:06:SC cbx_stratix 2023:11:29:19:33:06:SC cbx_stratixii 2023:11:29:19:33:05:SC cbx_util_mgl 2023:11:29:19:33:06:SC VERSION_END
-- Copyright (C) 2023 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details, at
-- https://fpgasoftware.intel.com/eula.
--synthesis_resources = lut 3
SUBDESIGN lpm_abs_jn9
(
data[3..0] : input;
overflow : output;
result[3..0] : output;
)
VARIABLE
result_tmp[3..0] : WIRE;
BEGIN
overflow = (result_tmp[3..3] & data[3..3]);
result[] = result_tmp[];
result_tmp[] = ( (data[3..3] & (! ((data[2..2] # data[1..1]) # data[0..0]))), (((data[2..2] $ (data[1..1] # data[0..0])) & data[3..3]) # (data[2..2] & (! data[3..3]))), (((data[1..1] $ data[0..0]) & data[3..3]) # (data[1..1] & (! data[3..3]))), data[0..0]);
END;
--VALID FILE

49
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--lpm_abs CARRY_CHAIN="MANUAL" DEVICE_FAMILY="Cyclone V" IGNORE_CARRY_BUFFERS="OFF" LPM_WIDTH=6 data result
--VERSION_BEGIN 23.1 cbx_cycloneii 2023:11:29:19:33:06:SC cbx_lpm_abs 2023:11:29:19:33:06:SC cbx_lpm_add_sub 2023:11:29:19:33:06:SC cbx_mgl 2023:11:29:19:43:53:SC cbx_nadder 2023:11:29:19:33:06:SC cbx_stratix 2023:11:29:19:33:06:SC cbx_stratixii 2023:11:29:19:33:05:SC cbx_util_mgl 2023:11:29:19:33:06:SC VERSION_END
-- Copyright (C) 2023 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details, at
-- https://fpgasoftware.intel.com/eula.
--synthesis_resources = lut 6
SUBDESIGN lpm_abs_ln9
(
data[5..0] : input;
overflow : output;
result[5..0] : output;
)
VARIABLE
adder_result_int[6..0] : WIRE;
adder_cin : WIRE;
adder_dataa[5..0] : WIRE;
adder_datab[5..0] : WIRE;
adder_result[5..0] : WIRE;
gnd_wire : WIRE;
result_tmp[5..0] : WIRE;
BEGIN
adder_result_int[] = (adder_dataa[], adder_cin) + (adder_datab[], adder_cin);
adder_result[] = adder_result_int[6..1];
adder_cin = data[5..5];
adder_dataa[] = (data[] $ data[5..5]);
adder_datab[] = ( gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire);
gnd_wire = B"0";
overflow = (result_tmp[5..5] & data[5..5]);
result[] = result_tmp[];
result_tmp[] = adder_result[];
END;
--VALID FILE

43
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--lpm_divide DEVICE_FAMILY="Cyclone V" LPM_DREPRESENTATION="UNSIGNED" LPM_NREPRESENTATION="UNSIGNED" LPM_WIDTHD=4 LPM_WIDTHN=8 OPTIMIZE_FOR_SPEED=5 denom numer quotient CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 IGNORE_CARRY_BUFFERS="OFF"
--VERSION_BEGIN 23.1 cbx_cycloneii 2023:11:29:19:33:06:SC cbx_lpm_abs 2023:11:29:19:33:06:SC cbx_lpm_add_sub 2023:11:29:19:33:06:SC cbx_lpm_divide 2023:11:29:19:33:06:SC cbx_mgl 2023:11:29:19:43:53:SC cbx_nadder 2023:11:29:19:33:06:SC cbx_stratix 2023:11:29:19:33:06:SC cbx_stratixii 2023:11:29:19:33:05:SC cbx_util_mgl 2023:11:29:19:33:06:SC VERSION_END
-- Copyright (C) 2023 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details, at
-- https://fpgasoftware.intel.com/eula.
FUNCTION sign_div_unsign_bkh (denominator[3..0], numerator[7..0])
RETURNS ( quotient[7..0], remainder[3..0]);
--synthesis_resources =
SUBDESIGN lpm_divide_5am
(
denom[3..0] : input;
numer[7..0] : input;
quotient[7..0] : output;
remain[3..0] : output;
)
VARIABLE
divider : sign_div_unsign_bkh;
numer_tmp[7..0] : WIRE;
BEGIN
divider.denominator[] = denom[];
divider.numerator[] = numer_tmp[];
numer_tmp[] = numer[];
quotient[] = divider.quotient[];
remain[] = divider.remainder[];
END;
--VALID FILE

43
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--lpm_divide DEVICE_FAMILY="Cyclone V" LPM_DREPRESENTATION="UNSIGNED" LPM_NREPRESENTATION="UNSIGNED" LPM_WIDTHD=4 LPM_WIDTHN=8 OPTIMIZE_FOR_SPEED=5 denom numer remain CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 IGNORE_CARRY_BUFFERS="OFF"
--VERSION_BEGIN 23.1 cbx_cycloneii 2023:11:29:19:33:06:SC cbx_lpm_abs 2023:11:29:19:33:06:SC cbx_lpm_add_sub 2023:11:29:19:33:06:SC cbx_lpm_divide 2023:11:29:19:33:06:SC cbx_mgl 2023:11:29:19:43:53:SC cbx_nadder 2023:11:29:19:33:06:SC cbx_stratix 2023:11:29:19:33:06:SC cbx_stratixii 2023:11:29:19:33:05:SC cbx_util_mgl 2023:11:29:19:33:06:SC VERSION_END
-- Copyright (C) 2023 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details, at
-- https://fpgasoftware.intel.com/eula.
FUNCTION sign_div_unsign_bkh (denominator[3..0], numerator[7..0])
RETURNS ( quotient[7..0], remainder[3..0]);
--synthesis_resources = lut 38
SUBDESIGN lpm_divide_82m
(
denom[3..0] : input;
numer[7..0] : input;
quotient[7..0] : output;
remain[3..0] : output;
)
VARIABLE
divider : sign_div_unsign_bkh;
numer_tmp[7..0] : WIRE;
BEGIN
divider.denominator[] = denom[];
divider.numerator[] = numer_tmp[];
numer_tmp[] = numer[];
quotient[] = divider.quotient[];
remain[] = divider.remainder[];
END;
--VALID FILE

43
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--lpm_divide DEVICE_FAMILY="Cyclone V" LPM_DREPRESENTATION="SIGNED" LPM_NREPRESENTATION="SIGNED" LPM_REMAINDERPOSITIVE="FALSE" LPM_WIDTHD=4 LPM_WIDTHN=32 OPTIMIZE_FOR_SPEED=5 denom numer remain CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 IGNORE_CARRY_BUFFERS="OFF"
--VERSION_BEGIN 23.1 cbx_cycloneii 2023:11:29:19:33:06:SC cbx_lpm_abs 2023:11:29:19:33:06:SC cbx_lpm_add_sub 2023:11:29:19:33:06:SC cbx_lpm_divide 2023:11:29:19:33:06:SC cbx_mgl 2023:11:29:19:43:53:SC cbx_nadder 2023:11:29:19:33:06:SC cbx_stratix 2023:11:29:19:33:06:SC cbx_stratixii 2023:11:29:19:33:05:SC cbx_util_mgl 2023:11:29:19:33:06:SC VERSION_END
-- Copyright (C) 2023 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details, at
-- https://fpgasoftware.intel.com/eula.
FUNCTION abs_divider_jbg (denominator[3..0], numerator[31..0])
RETURNS ( quotient[31..0], remainder[3..0]);
--synthesis_resources = lut 221
SUBDESIGN lpm_divide_dho
(
denom[3..0] : input;
numer[31..0] : input;
quotient[31..0] : output;
remain[3..0] : output;
)
VARIABLE
divider : abs_divider_jbg;
numer_tmp[31..0] : WIRE;
BEGIN
divider.denominator[] = denom[];
divider.numerator[] = numer_tmp[];
numer_tmp[] = numer[];
quotient[] = divider.quotient[];
remain[] = divider.remainder[];
END;
--VALID FILE

43
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@ -0,0 +1,43 @@
--lpm_divide DEVICE_FAMILY="Cyclone V" LPM_DREPRESENTATION="SIGNED" LPM_NREPRESENTATION="SIGNED" LPM_REMAINDERPOSITIVE="FALSE" LPM_WIDTHD=6 LPM_WIDTHN=32 OPTIMIZE_FOR_SPEED=5 denom numer remain CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 IGNORE_CARRY_BUFFERS="OFF"
--VERSION_BEGIN 23.1 cbx_cycloneii 2023:11:29:19:33:06:SC cbx_lpm_abs 2023:11:29:19:33:06:SC cbx_lpm_add_sub 2023:11:29:19:33:06:SC cbx_lpm_divide 2023:11:29:19:33:06:SC cbx_mgl 2023:11:29:19:43:53:SC cbx_nadder 2023:11:29:19:33:06:SC cbx_stratix 2023:11:29:19:33:06:SC cbx_stratixii 2023:11:29:19:33:05:SC cbx_util_mgl 2023:11:29:19:33:06:SC VERSION_END
-- Copyright (C) 2023 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details, at
-- https://fpgasoftware.intel.com/eula.
FUNCTION abs_divider_lbg (denominator[5..0], numerator[31..0])
RETURNS ( quotient[31..0], remainder[5..0]);
--synthesis_resources = lut 311
SUBDESIGN lpm_divide_fho
(
denom[5..0] : input;
numer[31..0] : input;
quotient[31..0] : output;
remain[5..0] : output;
)
VARIABLE
divider : abs_divider_lbg;
numer_tmp[31..0] : WIRE;
BEGIN
divider.denominator[] = denom[];
divider.numerator[] = numer_tmp[];
numer_tmp[] = numer[];
quotient[] = divider.quotient[];
remain[] = divider.remainder[];
END;
--VALID FILE

85
db/prev_cmp_chip8.qmsg Normal file
View file

@ -0,0 +1,85 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1712524771801 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition " "Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1712524771802 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 7 16:19:31 2024 " "Processing started: Sun Apr 7 16:19:31 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1712524771802 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712524771802 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off chip8 -c chip8 " "Command: quartus_map --read_settings_files=on --write_settings_files=off chip8 -c chip8" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712524771802 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1712524771959 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "12 12 " "Parallel compilation is enabled and will use 12 of the 12 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1712524771959 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "the-bomb/st7920_serial_driver.sv 3 3 " "Found 3 design units, including 3 entities, in source file the-bomb/st7920_serial_driver.sv" { { "Info" "ISGN_ENTITY_NAME" "1 st7920_serial_driver " "Found entity 1: st7920_serial_driver" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712524777280 ""} { "Info" "ISGN_ENTITY_NAME" "2 d_flip_flop " "Found entity 2: d_flip_flop" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 138 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712524777280 ""} { "Info" "ISGN_ENTITY_NAME" "3 commander " "Found entity 3: commander" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 148 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712524777280 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712524777280 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "chip8.sv 2 2 " "Found 2 design units, including 2 entities, in source file chip8.sv" { { "Info" "ISGN_ENTITY_NAME" "1 chip8 " "Found entity 1: chip8" { } { { "chip8.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/chip8.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712524777281 ""} { "Info" "ISGN_ENTITY_NAME" "2 dc " "Found entity 2: dc" { } { { "chip8.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/chip8.sv" 65 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712524777281 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712524777281 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu.sv 1 1 " "Found 1 design units, including 1 entities, in source file cpu.sv" { { "Info" "ISGN_ENTITY_NAME" "1 cpu " "Found entity 1: cpu" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712524777281 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712524777281 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rng.sv 1 1 " "Found 1 design units, including 1 entities, in source file rng.sv" { { "Info" "ISGN_ENTITY_NAME" "1 rng " "Found entity 1: rng" { } { { "rng.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/rng.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712524777282 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712524777282 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "chip8 " "Elaborating entity \"chip8\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1712524777314 ""}
{ "Warning" "WVRFX_VERI_2106_UNCONVERTED" "keyboard chip8.sv(9) " "Verilog HDL warning at chip8.sv(9): object keyboard used but never assigned" { } { { "chip8.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/chip8.sv" 9 0 0 } } } 0 10858 "Verilog HDL warning at %2!s!: object %1!s! used but never assigned" 0 0 "Analysis & Synthesis" 0 -1 1712524777315 "|chip8"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "keyboard 0 chip8.sv(9) " "Net \"keyboard\" at chip8.sv(9) has no driver or initial value, using a default initial value '0'" { } { { "chip8.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/chip8.sv" 9 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1712524777316 "|chip8"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dc dc:dc " "Elaborating entity \"dc\" for hierarchy \"dc:dc\"" { } { { "chip8.sv" "dc" { Text "/home/nickorlow/programming/school/warminster/yayacemu/chip8.sv" 24 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712524777325 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 21 chip8.sv(77) " "Verilog HDL assignment warning at chip8.sv(77): truncated value with size 32 to match size of target (21)" { } { { "chip8.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/chip8.sv" 77 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712524777325 "|chip8|dc:dc"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu cpu:cpu " "Elaborating entity \"cpu\" for hierarchy \"cpu:cpu\"" { } { { "chip8.sv" "cpu" { Text "/home/nickorlow/programming/school/warminster/yayacemu/chip8.sv" 39 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712524777328 ""}
{ "Warning" "WVRFX_L2_HDL_INDEX_EXPR_NOT_WIDE_ENOUGH" "cpu.sv(16) " "Verilog HDL or VHDL warning at the cpu.sv(16): index expression is not wide enough to address all of the elements in the array" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 16 0 0 } } } 0 10027 "Verilog HDL or VHDL warning at the %1!s!: index expression is not wide enough to address all of the elements in the array" 0 0 "Analysis & Synthesis" 0 -1 1712524777339 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_VERI_2111_UNCONVERTED" "80 0 4095 cpu.sv(44) " "Verilog HDL warning at cpu.sv(44): number of words (80) in memory file does not match the number of elements in the address range \[0:4095\]" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 44 0 0 } } } 0 10850 "Verilog HDL warning at %4!s!: number of words (%1!d!) in memory file does not match the number of elements in the address range \[%2!d!:%3!d!\]" 0 0 "Analysis & Synthesis" 0 -1 1712524777340 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_VERI_2111_UNCONVERTED" "697 512 4095 cpu.sv(45) " "Verilog HDL warning at cpu.sv(45): number of words (697) in memory file does not match the number of elements in the address range \[512:4095\]" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 45 0 0 } } } 0 10850 "Verilog HDL warning at %4!s!: number of words (%1!d!) in memory file does not match the number of elements in the address range \[%2!d!:%3!d!\]" 0 0 "Analysis & Synthesis" 0 -1 1712524777341 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_VERI_2116_UNCONVERTED" "memory cpu.sv(43) " "Verilog HDL warning at cpu.sv(43): initial value for variable memory should be constant" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 43 0 0 } } } 0 10855 "Verilog HDL warning at %2!s!: initial value for variable %1!s! should be constant" 0 0 "Analysis & Synthesis" 0 -1 1712524777342 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(80) " "Verilog HDL assignment warning at cpu.sv(80): truncated value with size 32 to match size of target (16)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 80 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712524777795 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(85) " "Verilog HDL assignment warning at cpu.sv(85): truncated value with size 32 to match size of target (16)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 85 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712524777803 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(88) " "Verilog HDL assignment warning at cpu.sv(88): truncated value with size 32 to match size of target (16)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 88 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712524777811 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(90) " "Verilog HDL assignment warning at cpu.sv(90): truncated value with size 32 to match size of target (16)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 90 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712524777819 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(94) " "Verilog HDL assignment warning at cpu.sv(94): truncated value with size 32 to match size of target (16)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 94 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712524777827 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(96) " "Verilog HDL assignment warning at cpu.sv(96): truncated value with size 32 to match size of target (16)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 96 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712524777835 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(101) " "Verilog HDL assignment warning at cpu.sv(101): truncated value with size 32 to match size of target (16)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 101 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712524777849 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(105) " "Verilog HDL assignment warning at cpu.sv(105): truncated value with size 32 to match size of target (16)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 105 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712524777857 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(109) " "Verilog HDL assignment warning at cpu.sv(109): truncated value with size 32 to match size of target (16)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 109 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712524777873 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(156) " "Verilog HDL assignment warning at cpu.sv(156): truncated value with size 32 to match size of target (16)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 156 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712524778155 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(160) " "Verilog HDL assignment warning at cpu.sv(160): truncated value with size 32 to match size of target (16)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 160 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712524778161 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(163) " "Verilog HDL assignment warning at cpu.sv(163): truncated value with size 32 to match size of target (16)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 163 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712524778168 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(168) " "Verilog HDL assignment warning at cpu.sv(168): truncated value with size 32 to match size of target (16)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 168 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712524778174 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(180) " "Verilog HDL assignment warning at cpu.sv(180): truncated value with size 32 to match size of target (16)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 180 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712524778200 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 cpu.sv(188) " "Verilog HDL assignment warning at cpu.sv(188): truncated value with size 32 to match size of target (8)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 188 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712524778206 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(203) " "Verilog HDL assignment warning at cpu.sv(203): truncated value with size 32 to match size of target (16)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 203 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712524825848 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(209) " "Verilog HDL assignment warning at cpu.sv(209): truncated value with size 32 to match size of target (16)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 209 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712524825855 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(246) " "Verilog HDL assignment warning at cpu.sv(246): truncated value with size 32 to match size of target (16)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 246 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712524825922 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(251) " "Verilog HDL assignment warning at cpu.sv(251): truncated value with size 32 to match size of target (16)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 251 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712524825929 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(254) " "Verilog HDL assignment warning at cpu.sv(254): truncated value with size 32 to match size of target (16)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 254 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712524826017 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(257) " "Verilog HDL assignment warning at cpu.sv(257): truncated value with size 32 to match size of target (16)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 257 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712524826069 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(262) " "Verilog HDL assignment warning at cpu.sv(262): truncated value with size 32 to match size of target (16)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 262 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712524826130 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(271) " "Verilog HDL assignment warning at cpu.sv(271): truncated value with size 32 to match size of target (16)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 271 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712524827860 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(280) " "Verilog HDL assignment warning at cpu.sv(280): truncated value with size 32 to match size of target (16)" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 280 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712524828187 "|chip8|cpu:cpu"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "st7920_serial_driver st7920_serial_driver:gpu " "Elaborating entity \"st7920_serial_driver\" for hierarchy \"st7920_serial_driver:gpu\"" { } { { "chip8.sv" "gpu" { Text "/home/nickorlow/programming/school/warminster/yayacemu/chip8.sv" 49 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712525046026 ""}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "line_idx st7920_serial_driver.sv(25) " "Verilog HDL or VHDL warning at st7920_serial_driver.sv(25): object \"line_idx\" assigned a value but never read" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 25 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1712525046026 "|chip8|st7920_serial_driver:gpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 st7920_serial_driver.sv(73) " "Verilog HDL assignment warning at st7920_serial_driver.sv(73): truncated value with size 32 to match size of target (7)" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 73 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712525046027 "|chip8|st7920_serial_driver:gpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 st7920_serial_driver.sv(86) " "Verilog HDL assignment warning at st7920_serial_driver.sv(86): truncated value with size 32 to match size of target (7)" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 86 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712525046027 "|chip8|st7920_serial_driver:gpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 st7920_serial_driver.sv(98) " "Verilog HDL assignment warning at st7920_serial_driver.sv(98): truncated value with size 32 to match size of target (10)" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 98 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712525046027 "|chip8|st7920_serial_driver:gpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 st7920_serial_driver.sv(100) " "Verilog HDL assignment warning at st7920_serial_driver.sv(100): truncated value with size 32 to match size of target (10)" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 100 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712525046028 "|chip8|st7920_serial_driver:gpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 st7920_serial_driver.sv(104) " "Verilog HDL assignment warning at st7920_serial_driver.sv(104): truncated value with size 32 to match size of target (6)" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 104 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712525046028 "|chip8|st7920_serial_driver:gpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 9 st7920_serial_driver.sv(132) " "Verilog HDL assignment warning at st7920_serial_driver.sv(132): truncated value with size 32 to match size of target (9)" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 132 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712525046029 "|chip8|st7920_serial_driver:gpu"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "commands\[6..10\] 0 st7920_serial_driver.sv(28) " "Net \"commands\[6..10\]\" at st7920_serial_driver.sv(28) has no driver or initial value, using a default initial value '0'" { } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 28 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1712525046030 "|chip8|st7920_serial_driver:gpu"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "commander st7920_serial_driver:gpu\|commander:com " "Elaborating entity \"commander\" for hierarchy \"st7920_serial_driver:gpu\|commander:com\"" { } { { "the-bomb/st7920_serial_driver.sv" "com" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 44 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712525046041 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "d_flip_flop st7920_serial_driver:gpu\|d_flip_flop:dff " "Elaborating entity \"d_flip_flop\" for hierarchy \"st7920_serial_driver:gpu\|d_flip_flop:dff\"" { } { { "the-bomb/st7920_serial_driver.sv" "dff" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 52 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712525046045 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rng rng:randy " "Elaborating entity \"rng\" for hierarchy \"rng:randy\"" { } { { "chip8.sv" "randy" { Text "/home/nickorlow/programming/school/warminster/yayacemu/chip8.sv" 57 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712525046046 ""}
{ "Info" "IINFER_UNINFERRED_RAM_SUMMARY" "1 " "Found 1 instances of uninferred RAM logic" { { "Info" "IINFER_READ_LOGIC_IS_ASYNCHRONOUS" "cpu:cpu\|stack " "RAM logic \"cpu:cpu\|stack\" is uninferred due to asynchronous read logic" { } { { "cpu.sv" "stack" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 24 -1 0 } } } 0 276007 "RAM logic \"%1!s!\" is uninferred due to asynchronous read logic" 0 0 "Design Software" 0 -1 1712525143856 ""} } { } 0 276014 "Found %1!d! instances of uninferred RAM logic" 0 0 "Analysis & Synthesis" 0 -1 1712525143856 ""}
{ "Info" "ILPMS_INFERENCING_SUMMARY" "7 " "Inferred 7 megafunctions from design logic" { { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "cpu:cpu\|Mod0 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"cpu:cpu\|Mod0\"" { } { { "cpu.sv" "Mod0" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 64 -1 0 } } } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1712525681962 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "cpu:cpu\|Mod1 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"cpu:cpu\|Mod1\"" { } { { "cpu.sv" "Mod1" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 251 -1 0 } } } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1712525681962 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "cpu:cpu\|Div0 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"cpu:cpu\|Div0\"" { } { { "cpu.sv" "Div0" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 253 -1 0 } } } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1712525681962 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "cpu:cpu\|Mod2 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"cpu:cpu\|Mod2\"" { } { { "cpu.sv" "Mod2" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 254 -1 0 } } } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1712525681962 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "cpu:cpu\|Div1 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"cpu:cpu\|Div1\"" { } { { "cpu.sv" "Div1" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 256 -1 0 } } } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1712525681962 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "cpu:cpu\|Mod3 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"cpu:cpu\|Mod3\"" { } { { "cpu.sv" "Mod3" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 257 -1 0 } } } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1712525681962 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "rng:randy\|Mod0 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"rng:randy\|Mod0\"" { } { { "rng.sv" "Mod0" { Text "/home/nickorlow/programming/school/warminster/yayacemu/rng.sv" 14 -1 0 } } } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1712525681962 ""} } { } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Analysis & Synthesis" 0 -1 1712525681962 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "cpu:cpu\|lpm_divide:Mod0 " "Elaborated megafunction instantiation \"cpu:cpu\|lpm_divide:Mod0\"" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 64 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712525682315 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "cpu:cpu\|lpm_divide:Mod0 " "Instantiated megafunction \"cpu:cpu\|lpm_divide:Mod0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 32 " "Parameter \"LPM_WIDTHN\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712525682315 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 6 " "Parameter \"LPM_WIDTHD\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712525682315 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION SIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"SIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712525682315 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION SIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"SIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712525682315 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_HINT LPM_REMAINDERPOSITIVE=FALSE " "Parameter \"LPM_HINT\" = \"LPM_REMAINDERPOSITIVE=FALSE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712525682315 ""} } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 64 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1712525682315 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_fho.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_fho.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_fho " "Found entity 1: lpm_divide_fho" { } { { "db/lpm_divide_fho.tdf" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/db/lpm_divide_fho.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712525682358 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712525682358 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/abs_divider_lbg.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/abs_divider_lbg.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 abs_divider_lbg " "Found entity 1: abs_divider_lbg" { } { { "db/abs_divider_lbg.tdf" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/db/abs_divider_lbg.tdf" 29 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712525682362 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712525682362 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_qve.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/alt_u_div_qve.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_qve " "Found entity 1: alt_u_div_qve" { } { { "db/alt_u_div_qve.tdf" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/db/alt_u_div_qve.tdf" 23 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712525682376 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712525682376 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_abs_ln9.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_abs_ln9.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_abs_ln9 " "Found entity 1: lpm_abs_ln9" { } { { "db/lpm_abs_ln9.tdf" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/db/lpm_abs_ln9.tdf" 23 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712525682406 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712525682406 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_abs_4p9.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_abs_4p9.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_abs_4p9 " "Found entity 1: lpm_abs_4p9" { } { { "db/lpm_abs_4p9.tdf" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/db/lpm_abs_4p9.tdf" 23 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712525682409 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712525682409 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "cpu:cpu\|lpm_divide:Mod1 " "Elaborated megafunction instantiation \"cpu:cpu\|lpm_divide:Mod1\"" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 251 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712525682420 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "cpu:cpu\|lpm_divide:Mod1 " "Instantiated megafunction \"cpu:cpu\|lpm_divide:Mod1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 8 " "Parameter \"LPM_WIDTHN\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712525682420 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 4 " "Parameter \"LPM_WIDTHD\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712525682420 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712525682420 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712525682420 ""} } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 251 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1712525682420 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_82m.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_82m.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_82m " "Found entity 1: lpm_divide_82m" { } { { "db/lpm_divide_82m.tdf" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/db/lpm_divide_82m.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712525682439 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712525682439 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_bkh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/sign_div_unsign_bkh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_bkh " "Found entity 1: sign_div_unsign_bkh" { } { { "db/sign_div_unsign_bkh.tdf" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/db/sign_div_unsign_bkh.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712525682441 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712525682441 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_sse.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/alt_u_div_sse.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_sse " "Found entity 1: alt_u_div_sse" { } { { "db/alt_u_div_sse.tdf" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/db/alt_u_div_sse.tdf" 23 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712525682445 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712525682445 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "cpu:cpu\|lpm_divide:Div0 " "Elaborated megafunction instantiation \"cpu:cpu\|lpm_divide:Div0\"" { } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 253 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712525682452 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "cpu:cpu\|lpm_divide:Div0 " "Instantiated megafunction \"cpu:cpu\|lpm_divide:Div0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 8 " "Parameter \"LPM_WIDTHN\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712525682452 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 4 " "Parameter \"LPM_WIDTHD\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712525682452 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712525682452 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712525682452 ""} } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 253 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1712525682452 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_5am.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_5am.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_5am " "Found entity 1: lpm_divide_5am" { } { { "db/lpm_divide_5am.tdf" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/db/lpm_divide_5am.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712525682471 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712525682471 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "rng:randy\|lpm_divide:Mod0 " "Elaborated megafunction instantiation \"rng:randy\|lpm_divide:Mod0\"" { } { { "rng.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/rng.sv" 14 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712525682655 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "rng:randy\|lpm_divide:Mod0 " "Instantiated megafunction \"rng:randy\|lpm_divide:Mod0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 32 " "Parameter \"LPM_WIDTHN\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712525682655 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 4 " "Parameter \"LPM_WIDTHD\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712525682655 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION SIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"SIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712525682655 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION SIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"SIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712525682655 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_HINT LPM_REMAINDERPOSITIVE=FALSE " "Parameter \"LPM_HINT\" = \"LPM_REMAINDERPOSITIVE=FALSE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712525682655 ""} } { { "rng.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/rng.sv" 14 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1712525682655 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_dho.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_dho.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_dho " "Found entity 1: lpm_divide_dho" { } { { "db/lpm_divide_dho.tdf" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/db/lpm_divide_dho.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712525682674 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712525682674 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/abs_divider_jbg.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/abs_divider_jbg.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 abs_divider_jbg " "Found entity 1: abs_divider_jbg" { } { { "db/abs_divider_jbg.tdf" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/db/abs_divider_jbg.tdf" 29 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712525682677 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712525682677 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_mve.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/alt_u_div_mve.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_mve " "Found entity 1: alt_u_div_mve" { } { { "db/alt_u_div_mve.tdf" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/db/alt_u_div_mve.tdf" 23 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712525682692 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712525682692 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_abs_jn9.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_abs_jn9.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_abs_jn9 " "Found entity 1: lpm_abs_jn9" { } { { "db/lpm_abs_jn9.tdf" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/db/lpm_abs_jn9.tdf" 23 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712525682724 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712525682724 ""}
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "led\[5\] VCC " "Pin \"led\[5\]\" is stuck at VCC" { } { { "chip8.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/chip8.sv" 7 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1712527323052 "|chip8|led[5]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1712527323052 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1712527352880 ""}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "68 " "68 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1712528930026 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1712528973164 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712528973164 ""}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "1 " "Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "rst_in " "No output dependent on input pin \"rst_in\"" { } { { "chip8.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/chip8.sv" 3 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1712528998444 "|chip8|rst_in"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1712528998444 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "782597 " "Implemented 782597 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Implemented 2 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1712529000632 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1712529000632 ""} { "Info" "ICUT_CUT_TM_LCELLS" "782587 " "Implemented 782587 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1712529000632 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1712529000632 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 44 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 44 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5759 " "Peak virtual memory: 5759 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1712529001428 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 7 17:30:01 2024 " "Processing ended: Sun Apr 7 17:30:01 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1712529001428 ""} { "Info" "IQEXE_ELAPSED_TIME" "01:10:30 " "Elapsed time: 01:10:30" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1712529001428 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "01:37:11 " "Total CPU time (on all processors): 01:37:11" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1712529001428 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1712529001428 ""}

47
db/sign_div_unsign_bkh.tdf Normal file
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@ -0,0 +1,47 @@
--sign_div_unsign DEN_REPRESENTATION="UNSIGNED" DEN_WIDTH=4 LPM_PIPELINE=0 MAXIMIZE_SPEED=5 NUM_REPRESENTATION="UNSIGNED" NUM_WIDTH=8 SKIP_BITS=0 denominator numerator quotient remainder
--VERSION_BEGIN 23.1 cbx_cycloneii 2023:11:29:19:33:06:SC cbx_lpm_abs 2023:11:29:19:33:06:SC cbx_lpm_add_sub 2023:11:29:19:33:06:SC cbx_lpm_divide 2023:11:29:19:33:06:SC cbx_mgl 2023:11:29:19:43:53:SC cbx_nadder 2023:11:29:19:33:06:SC cbx_stratix 2023:11:29:19:33:06:SC cbx_stratixii 2023:11:29:19:33:05:SC cbx_util_mgl 2023:11:29:19:33:06:SC VERSION_END
-- Copyright (C) 2023 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details, at
-- https://fpgasoftware.intel.com/eula.
FUNCTION alt_u_div_sse (denominator[3..0], numerator[7..0])
RETURNS ( quotient[7..0], remainder[3..0]);
--synthesis_resources = lut 38
SUBDESIGN sign_div_unsign_bkh
(
denominator[3..0] : input;
numerator[7..0] : input;
quotient[7..0] : output;
remainder[3..0] : output;
)
VARIABLE
divider : alt_u_div_sse;
norm_num[7..0] : WIRE;
protect_quotient[7..0] : WIRE;
protect_remainder[3..0] : WIRE;
BEGIN
divider.denominator[] = denominator[];
divider.numerator[] = norm_num[];
norm_num[] = numerator[];
protect_quotient[] = divider.quotient[];
protect_remainder[] = divider.remainder[];
quotient[] = protect_quotient[];
remainder[] = protect_remainder[];
END;
--VALID FILE