fix flags
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26f6dc5ce3
commit
c1adfc84c0
7
alu.sv
7
alu.sv
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@ -14,7 +14,7 @@ module alu(
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int cnt;
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int cnt;
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initial begin
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initial begin
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overflow = 1'bx;
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overflow = 0;
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result = 8'hxx;
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result = 8'hxx;
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result_int = 9'bxxxxxxxxx;
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result_int = 9'bxxxxxxxxx;
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done = 0;
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done = 0;
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@ -24,7 +24,7 @@ module alu(
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always_ff @(posedge clk_in) begin
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always_ff @(posedge clk_in) begin
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if (rst_in) begin
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if (rst_in) begin
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done <= 0;
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done <= 0;
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overflow <= 1'bx;
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overflow <= 0;
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result <= 8'hxx;
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result <= 8'hxx;
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result_int <= 9'bxxxxxxxxx;
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result_int <= 9'bxxxxxxxxx;
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cnt <= 0;
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cnt <= 0;
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@ -65,14 +65,17 @@ module alu(
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end
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end
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structs::OR: begin
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structs::OR: begin
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result <= in.operand_a | in.operand_b;
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result <= in.operand_a | in.operand_b;
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overflow <= 0;
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done <= 1;
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done <= 1;
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end
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end
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structs::AND: begin
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structs::AND: begin
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result <= in.operand_a & in.operand_b;
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result <= in.operand_a & in.operand_b;
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overflow <= 0;
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done <= 1;
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done <= 1;
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end
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end
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structs::XOR: begin
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structs::XOR: begin
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result <= in.operand_a ^ in.operand_b;
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result <= in.operand_a ^ in.operand_b;
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overflow <= 0;
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done <= 1;
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done <= 1;
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end
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end
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structs::SHR: begin
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structs::SHR: begin
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12
cpu.sv
12
cpu.sv
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@ -264,7 +264,7 @@ logic [5:0] lcd_led;
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instr.alu_i.op <= structs::OR;
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instr.alu_i.op <= structs::OR;
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instr.alu_i.operand_a <= registers[opcode[7:4]];
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instr.alu_i.operand_a <= registers[opcode[7:4]];
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instr.alu_i.operand_b <= registers[opcode[11:8]];
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instr.alu_i.operand_b <= registers[opcode[11:8]];
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compute_of <= 0;
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compute_of <= 1;
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state <= ST_EXEC;
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state <= ST_EXEC;
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end
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end
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@ -279,7 +279,7 @@ logic [5:0] lcd_led;
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instr.alu_i.op <= structs::AND;
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instr.alu_i.op <= structs::AND;
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instr.alu_i.operand_a <= registers[opcode[7:4]];
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instr.alu_i.operand_a <= registers[opcode[7:4]];
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instr.alu_i.operand_b <= registers[opcode[11:8]];
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instr.alu_i.operand_b <= registers[opcode[11:8]];
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compute_of <= 0;
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compute_of <= 1;
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state <= ST_EXEC;
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state <= ST_EXEC;
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end
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end
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@ -294,7 +294,7 @@ logic [5:0] lcd_led;
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instr.alu_i.op <= structs::XOR;
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instr.alu_i.op <= structs::XOR;
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instr.alu_i.operand_a <= registers[opcode[7:4]];
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instr.alu_i.operand_a <= registers[opcode[7:4]];
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instr.alu_i.operand_b <= registers[opcode[11:8]];
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instr.alu_i.operand_b <= registers[opcode[11:8]];
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compute_of <= 0;
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compute_of <= 1;
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state <= ST_EXEC;
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state <= ST_EXEC;
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end
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end
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@ -620,8 +620,12 @@ logic [5:0] lcd_led;
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instr.src <= BYTE;
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instr.src <= BYTE;
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if (instr.dst == IDX_REG)
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if (instr.dst == IDX_REG)
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instr.src_byte <= alu_result_long[11:0];
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instr.src_byte <= alu_result_long[11:0];
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else
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else if (instr.dst_reg != 15 || !compute_of) begin
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instr.src_byte <= alu_result;
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instr.src_byte <= alu_result;
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end else begin
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instr.src_byte <= alu_overflow;
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end
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registers[15] <= compute_of ? alu_overflow : registers[15];
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registers[15] <= compute_of ? alu_overflow : registers[15];
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if (instr.op == ALU) begin
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if (instr.op == ALU) begin
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state <= ST_WB;
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state <= ST_WB;
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