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draw bug fix, beeper, and rng (tetris works)

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Nicholas Orlowsky 2024-04-15 19:05:34 -05:00
parent 6ef29f55e7
commit a3960bb56d
Signed by: nickorlow
GPG key ID: 838827D8C4611687
3 changed files with 26 additions and 5 deletions
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4
chip8.qsf
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@ -85,3 +85,7 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to row[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to row[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to row[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to row
set_location_assignment PIN_AH19 -to beep
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to beep

8
cpu.sv
View file

@ -444,6 +444,7 @@ logic [5:0] lcd_led;
instr.src_sprite_vy <= opcode[7:4];
instr.src_sprite_idx <= 0;
state <= ST_FETCH_MEM;
end
16'hE?9E: begin
@ -569,7 +570,6 @@ logic [5:0] lcd_led;
state <= ST_FETCH_MEM;
end
default: begin
$display("ILLEGAL INSTRUCTION %h at PC 0x%h (%0d)", opcode, program_counter, program_counter);
state <= ST_HALT;
end
endcase
@ -594,7 +594,7 @@ logic [5:0] lcd_led;
rd_memory_address <= instr.src_sprite_addr + {7'b0000000, instr.src_sprite_idx};
instr.src_sprite_idx <= instr.src_sprite_idx + 1;
for (int l = 0; l < 8; l++)
instr.src_sprite[(instr.src_sprite_idx)*8+l] <= rd_memory_data[7-l];
instr.src_sprite[(instr.src_sprite_idx-1)*8+l] <= rd_memory_data[7-l];
end else begin
instr.src_sprite_x <= registers[instr.src_sprite_vx] % 8'd64;
instr.src_sprite_y <= registers[instr.src_sprite_vy] % 8'd32;
@ -619,7 +619,7 @@ logic [5:0] lcd_led;
registers[15] <= 0;
end
end else begin
if (draw_state.r == instr.src_sprite_sz + 1) begin
if (draw_state.r == instr.src_sprite_sz) begin
state <= ST_CLEANUP;
program_counter <= program_counter + 2;
end else begin
@ -692,7 +692,6 @@ logic [5:0] lcd_led;
BCD: begin
instr.src <= BYTE;
ldl_cnt <= ldl_cnt + 1;
$display("%0d ldl", ldl_cnt);
case (ldl_cnt)
0: begin
instr.src_byte <= (registers[instr.src_reg]/100) % 10;
@ -784,7 +783,6 @@ logic [5:0] lcd_led;
end
IOW: begin
if (|keymap != 0 && wait_key[12] == 1) begin
$display("IO not waiting");
for(int m = 0; m < 16; m++) begin
if (keymap[m]) begin
wait_key[11:0] <= m[11:0];

19
rng.sv Normal file
View file

@ -0,0 +1,19 @@
module rng (
input wire clk_in,
input wire [15:0] bor16,
input bit [15:0] keyboard,
input int cycle_counter,
output bit [7:0] rand_bit
);
bit [7:0] last;
always_ff @(posedge clk_in) begin
for (int i = 0; i < 5; i++) begin
rand_bit[i] <= ~keyboard[i == 0 ? 7 : i-1] ? cycle_counter[i] : cycle_counter[7-i];
rand_bit[i+1%8] <= rand_bit[i] ^ (cycle_counter % 7) == 0 ? bor16[i] : ~bor16[i];
rand_bit[i+2%8] <= rand_bit[i+1%8] ^ keyboard[i+7] ? ~last[i] : last[i];
end
last <= rand_bit;
end
endmodule