fpga passes corax+

makefile

@@ -11,13 +11,13 @@ build-rom:
 	python3 ./gen_rom.py ${ROM_FILE} rom.bin
 
 build: build-rom
-	verilator --cc --exe --build --timing -j 0 --top-module chip8 *.sv yayacemu.cpp -DDUMMY_GPU -CFLAGS "${SDL_CFLAGS}" -LDFLAGS "${SDL_LDFLAGS}" && clear
+	verilator --cc --exe --build --timing -j 0 --top-module chip8 *.sv yayacemu.cpp -DDUMMY_GPU -DFAST_CLK -CFLAGS "${SDL_CFLAGS}" -LDFLAGS "${SDL_LDFLAGS}" && clear
 
 run: build
 	obj_dir/Vchip8	
 
 clean:
-	rm -rf obj_dir
+	rm -rf obj_dir db incremental_db
 
 format:
 	verible-verilog-format *.sv --inplace && clang-format *.cpp -i