fpga passes corax+

This commit is contained in:
Nicholas Orlowsky 2024-04-10 21:59:00 -05:00
parent 4ee5e3c231
commit 26f6dc5ce3
Signed by: nickorlow
GPG key ID: 838827D8C4611687
7 changed files with 402 additions and 21 deletions

46
alu.sv
View file

@ -5,6 +5,7 @@ module alu(
input wire clk_in,
input alu_input in,
output logic [7:0] result,
output logic [15:0] result_long,
output logic overflow,
output logic done
);
@ -39,6 +40,51 @@ module alu(
end
cnt <= cnt + 1;
end
structs::ADDL: begin
result_long <= {8'h00, in.operand_a} + {4'h0, in.operand_b_long};
done <= 1;
cnt <= cnt + 1;
end
structs::SUB: begin
result_int <= in.operand_a - in.operand_b;
result <= result_int[7:0];
// FIXME: if this fails, just do vx > vy
overflow <= !result_int[8];
if (cnt >= 2) begin
done <= 1;
end
cnt <= cnt + 1;
end
structs::SE: begin
result <= {7'b0000000, in.operand_a == in.operand_b};
done <= 1;
end
structs::SNE: begin
result <= {7'b0000000, in.operand_a != in.operand_b};
done <= 1;
end
structs::OR: begin
result <= in.operand_a | in.operand_b;
done <= 1;
end
structs::AND: begin
result <= in.operand_a & in.operand_b;
done <= 1;
end
structs::XOR: begin
result <= in.operand_a ^ in.operand_b;
done <= 1;
end
structs::SHR: begin
result <= in.operand_a >> in.operand_b;
overflow <= in.operand_a[0];
done <= 1;
end
structs::SHL: begin
result <= in.operand_a << in.operand_b;
overflow <= in.operand_a[7];
done <= 1;
end
endcase
end
end