fpga passes corax+
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7 changed files with 402 additions and 21 deletions
46
alu.sv
46
alu.sv
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@ -5,6 +5,7 @@ module alu(
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input wire clk_in,
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input alu_input in,
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output logic [7:0] result,
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output logic [15:0] result_long,
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output logic overflow,
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output logic done
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);
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@ -39,6 +40,51 @@ module alu(
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end
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cnt <= cnt + 1;
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end
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structs::ADDL: begin
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result_long <= {8'h00, in.operand_a} + {4'h0, in.operand_b_long};
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done <= 1;
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cnt <= cnt + 1;
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end
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structs::SUB: begin
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result_int <= in.operand_a - in.operand_b;
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result <= result_int[7:0];
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// FIXME: if this fails, just do vx > vy
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overflow <= !result_int[8];
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if (cnt >= 2) begin
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done <= 1;
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end
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cnt <= cnt + 1;
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end
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structs::SE: begin
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result <= {7'b0000000, in.operand_a == in.operand_b};
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done <= 1;
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end
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structs::SNE: begin
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result <= {7'b0000000, in.operand_a != in.operand_b};
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done <= 1;
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end
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structs::OR: begin
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result <= in.operand_a | in.operand_b;
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done <= 1;
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end
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structs::AND: begin
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result <= in.operand_a & in.operand_b;
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done <= 1;
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end
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structs::XOR: begin
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result <= in.operand_a ^ in.operand_b;
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done <= 1;
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end
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structs::SHR: begin
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result <= in.operand_a >> in.operand_b;
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overflow <= in.operand_a[0];
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done <= 1;
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end
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structs::SHL: begin
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result <= in.operand_a << in.operand_b;
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overflow <= in.operand_a[7];
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done <= 1;
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end
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endcase
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end
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end
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