20 lines
535 B
Systemverilog
20 lines
535 B
Systemverilog
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module rng (
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input wire clk_in,
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input wire [15:0] pc,
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input bit keyboard [15:0],
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input int cycle_counter,
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output bit [7:0] rand_bit
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);
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bit [7:0] last;
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always_ff @(posedge clk_in) begin
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for (int i = 0; i < 8; i++) begin
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rand_bit[i] ^= ~keyboard[i] ? cycle_counter[i] : cycle_counter[7-i];
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rand_bit[i] ^= (cycle_counter % 7) == 0 ? pc[i] : ~pc[i];
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rand_bit[i] ^= keyboard[i+7] ? ~last[i] : last[i];
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end
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last = rand_bit;
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end
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endmodule
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