47 lines
1.1 KiB
Systemverilog
47 lines
1.1 KiB
Systemverilog
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import structs::*;
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module alu(
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input wire rst_in,
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input wire clk_in,
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input alu_input in,
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output logic [7:0] result,
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output logic overflow,
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output logic done
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);
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logic [8:0] result_int;
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int cnt;
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initial begin
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overflow = 1'bx;
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result = 8'hxx;
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result_int = 9'bxxxxxxxxx;
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done = 0;
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cnt = 0;
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end
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always_ff @(posedge clk_in) begin
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if (rst_in) begin
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done <= 0;
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overflow <= 1'bx;
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result <= 8'hxx;
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result_int <= 9'bxxxxxxxxx;
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cnt <= 0;
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end else begin
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case(in.op)
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structs::ADD: begin
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result_int <= in.operand_a + in.operand_b;
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result <= result_int[7:0];
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overflow <= result_int[8];
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if (cnt == 2) begin
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$display("%b %b + %b %b ya", result, in.operand_a, in.operand_b, result_int);
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done <= 1;
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end
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cnt <= cnt + 1;
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end
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endcase
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end
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end
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endmodule
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