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yayacemu/output_files/chip8.sta.rpt

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Timing Analyzer report for chip8
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Mon Apr 8 08:52:45 2024
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Quartus Prime Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Parallel Compilation
4. Clocks
5. Slow 1100mV 100C Model Fmax Summary
6. Timing Closure Recommendations
7. Slow 1100mV 100C Model Setup Summary
8. Slow 1100mV 100C Model Hold Summary
9. Slow 1100mV 100C Model Recovery Summary
10. Slow 1100mV 100C Model Removal Summary
11. Slow 1100mV 100C Model Minimum Pulse Width Summary
12. Slow 1100mV 100C Model Metastability Summary
13. Slow 1100mV -40C Model Fmax Summary
14. Slow 1100mV -40C Model Setup Summary
15. Slow 1100mV -40C Model Hold Summary
16. Slow 1100mV -40C Model Recovery Summary
17. Slow 1100mV -40C Model Removal Summary
18. Slow 1100mV -40C Model Minimum Pulse Width Summary
19. Slow 1100mV -40C Model Metastability Summary
20. Fast 1100mV 100C Model Setup Summary
21. Fast 1100mV 100C Model Hold Summary
22. Fast 1100mV 100C Model Recovery Summary
23. Fast 1100mV 100C Model Removal Summary
24. Fast 1100mV 100C Model Minimum Pulse Width Summary
25. Fast 1100mV 100C Model Metastability Summary
26. Fast 1100mV -40C Model Setup Summary
27. Fast 1100mV -40C Model Hold Summary
28. Fast 1100mV -40C Model Recovery Summary
29. Fast 1100mV -40C Model Removal Summary
30. Fast 1100mV -40C Model Minimum Pulse Width Summary
31. Fast 1100mV -40C Model Metastability Summary
32. Multicorner Timing Analysis Summary
33. Board Trace Model Assignments
34. Input Transition Times
35. Signal Integrity Metrics (Slow 1100mv n40c Model)
36. Signal Integrity Metrics (Slow 1100mv 100c Model)
37. Signal Integrity Metrics (Fast 1100mv n40c Model)
38. Signal Integrity Metrics (Fast 1100mv 100c Model)
39. Setup Transfers
40. Hold Transfers
41. Report TCCS
42. Report RSKM
43. Unconstrained Paths Summary
44. Clock Status Summary
45. Unconstrained Output Ports
46. Unconstrained Output Ports
47. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2023 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
+--------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+-----------------------+--------------------------------------------------------+
; Quartus Prime Version ; Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition ;
; Timing Analyzer ; Legacy Timing Analyzer ;
; Revision Name ; chip8 ;
; Device Family ; Cyclone V ;
; Device Name ; 5CSEBA6U23I7 ;
; Timing Models ; Final ;
; Delay Model ; Combined ;
; Rise/Fall Delays ; Enabled ;
+-----------------------+--------------------------------------------------------+
+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 12 ;
; Maximum allowed ; 12 ;
; ; ;
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; Average used ; 5.48 ;
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; Maximum used ; 12 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
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; Processor 2 ; 56.2% ;
; Processor 3 ; 54.6% ;
; Processor 4 ; 54.0% ;
; Processor 5 ; 35.4% ;
; Processor 6 ; 35.4% ;
; Processor 7 ; 35.4% ;
; Processor 8 ; 35.4% ;
; Processor 9 ; 35.4% ;
; Processor 10 ; 35.4% ;
; Processor 11 ; 35.4% ;
; Processor 12 ; 35.4% ;
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+----------------------------+-------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks ;
+------------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------------------------------------------+
; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
+------------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------------------------------------------+
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { cpu:cpu|st7920_serial_driver:gpu|lcd_clk } ;
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; downclocker:dc|clk_out ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { downclocker:dc|clk_out } ;
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; fpga_clk ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { fpga_clk } ;
+------------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------------------------------------------+
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+--------------------------------------------------------------------------------+
; Slow 1100mV 100C Model Fmax Summary ;
+------------+-----------------+------------------------------------------+------+
; Fmax ; Restricted Fmax ; Clock Name ; Note ;
+------------+-----------------+------------------------------------------+------+
; 31.39 MHz ; 31.39 MHz ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; ;
; 82.93 MHz ; 82.93 MHz ; downclocker:dc|clk_out ; ;
; 189.18 MHz ; 189.18 MHz ; fpga_clk ; ;
+------------+-----------------+------------------------------------------+------+
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This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
----------------------------------
; Timing Closure Recommendations ;
----------------------------------
HTML report is unavailable in plain text report export.
+--------------------------------------------------------------------+
; Slow 1100mV 100C Model Setup Summary ;
+------------------------------------------+---------+---------------+
; Clock ; Slack ; End Point TNS ;
+------------------------------------------+---------+---------------+
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; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -31.412 ; -1884.356 ;
; downclocker:dc|clk_out ; -11.058 ; -87363.415 ;
; fpga_clk ; -4.953 ; -27.713 ;
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+------------------------------------------+---------+---------------+
+------------------------------------------------------------------+
; Slow 1100mV 100C Model Hold Summary ;
+------------------------------------------+-------+---------------+
; Clock ; Slack ; End Point TNS ;
+------------------------------------------+-------+---------------+
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; downclocker:dc|clk_out ; 0.429 ; 0.000 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 0.501 ; 0.000 ;
; fpga_clk ; 0.814 ; 0.000 ;
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+------------------------------------------+-------+---------------+
-------------------------------------------
; Slow 1100mV 100C Model Recovery Summary ;
-------------------------------------------
No paths to report.
------------------------------------------
; Slow 1100mV 100C Model Removal Summary ;
------------------------------------------
No paths to report.
+-------------------------------------------------------------------+
; Slow 1100mV 100C Model Minimum Pulse Width Summary ;
+------------------------------------------+--------+---------------+
; Clock ; Slack ; End Point TNS ;
+------------------------------------------+--------+---------------+
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; downclocker:dc|clk_out ; -2.636 ; -8430.055 ;
; fpga_clk ; -0.622 ; -17.105 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -0.538 ; -172.550 ;
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+------------------------------------------+--------+---------------+
------------------------------------------------
; Slow 1100mV 100C Model Metastability Summary ;
------------------------------------------------
Design MTBF is not calculated because the design doesn't meet its timing requirements.
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+--------------------------------------------------------------------------------+
; Slow 1100mV -40C Model Fmax Summary ;
+------------+-----------------+------------------------------------------+------+
; Fmax ; Restricted Fmax ; Clock Name ; Note ;
+------------+-----------------+------------------------------------------+------+
; 33.23 MHz ; 33.23 MHz ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; ;
; 82.94 MHz ; 82.94 MHz ; downclocker:dc|clk_out ; ;
; 185.36 MHz ; 185.36 MHz ; fpga_clk ; ;
+------------+-----------------+------------------------------------------+------+
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This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+--------------------------------------------------------------------+
; Slow 1100mV -40C Model Setup Summary ;
+------------------------------------------+---------+---------------+
; Clock ; Slack ; End Point TNS ;
+------------------------------------------+---------+---------------+
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; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -29.494 ; -1798.010 ;
; downclocker:dc|clk_out ; -11.057 ; -87142.095 ;
; fpga_clk ; -4.658 ; -29.299 ;
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+------------------------------------------+---------+---------------+
+------------------------------------------------------------------+
; Slow 1100mV -40C Model Hold Summary ;
+------------------------------------------+-------+---------------+
; Clock ; Slack ; End Point TNS ;
+------------------------------------------+-------+---------------+
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; downclocker:dc|clk_out ; 0.483 ; 0.000 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 0.546 ; 0.000 ;
; fpga_clk ; 0.786 ; 0.000 ;
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+------------------------------------------+-------+---------------+
-------------------------------------------
; Slow 1100mV -40C Model Recovery Summary ;
-------------------------------------------
No paths to report.
------------------------------------------
; Slow 1100mV -40C Model Removal Summary ;
------------------------------------------
No paths to report.
+-------------------------------------------------------------------+
; Slow 1100mV -40C Model Minimum Pulse Width Summary ;
+------------------------------------------+--------+---------------+
; Clock ; Slack ; End Point TNS ;
+------------------------------------------+--------+---------------+
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; downclocker:dc|clk_out ; -2.636 ; -8301.987 ;
; fpga_clk ; -0.627 ; -18.184 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -0.538 ; -170.070 ;
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+------------------------------------------+--------+---------------+
------------------------------------------------
; Slow 1100mV -40C Model Metastability Summary ;
------------------------------------------------
Design MTBF is not calculated because the design doesn't meet its timing requirements.
+--------------------------------------------------------------------+
; Fast 1100mV 100C Model Setup Summary ;
+------------------------------------------+---------+---------------+
; Clock ; Slack ; End Point TNS ;
+------------------------------------------+---------+---------------+
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; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -16.301 ; -1018.017 ;
; downclocker:dc|clk_out ; -5.608 ; -44394.911 ;
; fpga_clk ; -3.718 ; -8.178 ;
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+------------------------------------------+---------+---------------+
+------------------------------------------------------------------+
; Fast 1100mV 100C Model Hold Summary ;
+------------------------------------------+-------+---------------+
; Clock ; Slack ; End Point TNS ;
+------------------------------------------+-------+---------------+
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; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 0.160 ; 0.000 ;
; downclocker:dc|clk_out ; 0.177 ; 0.000 ;
; fpga_clk ; 0.303 ; 0.000 ;
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+------------------------------------------+-------+---------------+
-------------------------------------------
; Fast 1100mV 100C Model Recovery Summary ;
-------------------------------------------
No paths to report.
------------------------------------------
; Fast 1100mV 100C Model Removal Summary ;
------------------------------------------
No paths to report.
+-------------------------------------------------------------------+
; Fast 1100mV 100C Model Minimum Pulse Width Summary ;
+------------------------------------------+--------+---------------+
; Clock ; Slack ; End Point TNS ;
+------------------------------------------+--------+---------------+
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; downclocker:dc|clk_out ; -2.174 ; -537.344 ;
; fpga_clk ; -0.517 ; -2.901 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -0.144 ; -6.507 ;
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+------------------------------------------+--------+---------------+
------------------------------------------------
; Fast 1100mV 100C Model Metastability Summary ;
------------------------------------------------
Design MTBF is not calculated because the design doesn't meet its timing requirements.
+--------------------------------------------------------------------+
; Fast 1100mV -40C Model Setup Summary ;
+------------------------------------------+---------+---------------+
; Clock ; Slack ; End Point TNS ;
+------------------------------------------+---------+---------------+
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; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -14.004 ; -820.600 ;
; downclocker:dc|clk_out ; -4.541 ; -36337.093 ;
; fpga_clk ; -2.859 ; -5.427 ;
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+------------------------------------------+---------+---------------+
+------------------------------------------------------------------+
; Fast 1100mV -40C Model Hold Summary ;
+------------------------------------------+-------+---------------+
; Clock ; Slack ; End Point TNS ;
+------------------------------------------+-------+---------------+
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; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 0.138 ; 0.000 ;
; downclocker:dc|clk_out ; 0.164 ; 0.000 ;
; fpga_clk ; 0.289 ; 0.000 ;
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+------------------------------------------+-------+---------------+
-------------------------------------------
; Fast 1100mV -40C Model Recovery Summary ;
-------------------------------------------
No paths to report.
------------------------------------------
; Fast 1100mV -40C Model Removal Summary ;
------------------------------------------
No paths to report.
+-------------------------------------------------------------------+
; Fast 1100mV -40C Model Minimum Pulse Width Summary ;
+------------------------------------------+--------+---------------+
; Clock ; Slack ; End Point TNS ;
+------------------------------------------+--------+---------------+
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; downclocker:dc|clk_out ; -2.174 ; -534.258 ;
; fpga_clk ; -0.533 ; -2.899 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -0.057 ; -2.411 ;
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+------------------------------------------+--------+---------------+
------------------------------------------------
; Fast 1100mV -40C Model Metastability Summary ;
------------------------------------------------
Design MTBF is not calculated because the design doesn't meet its timing requirements.
+-----------------------------------------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary ;
+-------------------------------------------+------------+-------+----------+---------+---------------------+
; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
+-------------------------------------------+------------+-------+----------+---------+---------------------+
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; Worst-case Slack ; -31.412 ; 0.138 ; N/A ; N/A ; -2.636 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -31.412 ; 0.138 ; N/A ; N/A ; -0.538 ;
; downclocker:dc|clk_out ; -11.058 ; 0.164 ; N/A ; N/A ; -2.636 ;
; fpga_clk ; -4.953 ; 0.289 ; N/A ; N/A ; -0.627 ;
; Design-wide TNS ; -89275.484 ; 0.0 ; 0.0 ; 0.0 ; -8619.71 ;
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; -1884.356 ; 0.000 ; N/A ; N/A ; -172.550 ;
; downclocker:dc|clk_out ; -87363.415 ; 0.000 ; N/A ; N/A ; -8430.055 ;
; fpga_clk ; -29.299 ; 0.000 ; N/A ; N/A ; -18.184 ;
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+-------------------------------------------+------------+-------+----------+---------+---------------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments ;
+----------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
+----------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; lcd_clk ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; lcd_data ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; led[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; led[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; led[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; led[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; led[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; led[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+----------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+-------------------------------------------------------------+
; Input Transition Times ;
+----------+--------------+-----------------+-----------------+
; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+----------+--------------+-----------------+-----------------+
; rst_in ; 2.5 V ; 2000 ps ; 2000 ps ;
; fpga_clk ; 2.5 V ; 2000 ps ; 2000 ps ;
+----------+--------------+-----------------+-----------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1100mv n40c Model) ;
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; lcd_clk ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.56e-08 V ; 2.43 V ; -0.0607 V ; 0.35 V ; 0.108 V ; 3.1e-10 s ; 4.28e-10 s ; No ; No ; 2.32 V ; 1.56e-08 V ; 2.43 V ; -0.0607 V ; 0.35 V ; 0.108 V ; 3.1e-10 s ; 4.28e-10 s ; No ; No ;
; lcd_data ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.47e-08 V ; 3.11 V ; -0.195 V ; 0.108 V ; 0.32 V ; 4.03e-10 s ; 1.44e-10 s ; Yes ; No ; 3.08 V ; 1.47e-08 V ; 3.11 V ; -0.195 V ; 0.108 V ; 0.32 V ; 4.03e-10 s ; 1.44e-10 s ; Yes ; No ;
; led[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.47e-08 V ; 3.11 V ; -0.195 V ; 0.108 V ; 0.32 V ; 4.03e-10 s ; 1.44e-10 s ; Yes ; No ; 3.08 V ; 1.47e-08 V ; 3.11 V ; -0.195 V ; 0.108 V ; 0.32 V ; 4.03e-10 s ; 1.44e-10 s ; Yes ; No ;
; led[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.91e-08 V ; 3.17 V ; -0.306 V ; 0.142 V ; 0.425 V ; 4.17e-10 s ; 1.36e-10 s ; Yes ; No ; 3.08 V ; 1.91e-08 V ; 3.17 V ; -0.306 V ; 0.142 V ; 0.425 V ; 4.17e-10 s ; 1.36e-10 s ; Yes ; No ;
; led[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2e-08 V ; 3.17 V ; -0.245 V ; 0.166 V ; 0.398 V ; 4.33e-10 s ; 1.46e-10 s ; Yes ; No ; 3.08 V ; 2e-08 V ; 3.17 V ; -0.245 V ; 0.166 V ; 0.398 V ; 4.33e-10 s ; 1.46e-10 s ; Yes ; No ;
; led[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.47e-08 V ; 3.11 V ; -0.195 V ; 0.108 V ; 0.32 V ; 4.03e-10 s ; 1.44e-10 s ; Yes ; No ; 3.08 V ; 1.47e-08 V ; 3.11 V ; -0.195 V ; 0.108 V ; 0.32 V ; 4.03e-10 s ; 1.44e-10 s ; Yes ; No ;
; led[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.91e-08 V ; 3.17 V ; -0.306 V ; 0.142 V ; 0.425 V ; 4.17e-10 s ; 1.36e-10 s ; Yes ; No ; 3.08 V ; 1.91e-08 V ; 3.17 V ; -0.306 V ; 0.142 V ; 0.425 V ; 4.17e-10 s ; 1.36e-10 s ; Yes ; No ;
; led[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.91e-08 V ; 3.17 V ; -0.311 V ; 0.143 V ; 0.424 V ; 4.17e-10 s ; 1.36e-10 s ; Yes ; No ; 3.08 V ; 1.91e-08 V ; 3.17 V ; -0.311 V ; 0.143 V ; 0.424 V ; 4.17e-10 s ; 1.36e-10 s ; Yes ; No ;
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1100mv 100c Model) ;
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; lcd_clk ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.73e-05 V ; 2.38 V ; -0.0297 V ; 0.21 V ; 0.199 V ; 4.77e-10 s ; 4.97e-10 s ; No ; Yes ; 2.32 V ; 4.73e-05 V ; 2.38 V ; -0.0297 V ; 0.21 V ; 0.199 V ; 4.77e-10 s ; 4.97e-10 s ; No ; Yes ;
; lcd_data ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.09e-05 V ; 3.09 V ; -0.0462 V ; 0.045 V ; 0.085 V ; 5.49e-10 s ; 3.06e-10 s ; Yes ; Yes ; 3.08 V ; 3.09e-05 V ; 3.09 V ; -0.0462 V ; 0.045 V ; 0.085 V ; 5.49e-10 s ; 3.06e-10 s ; Yes ; Yes ;
; led[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.09e-05 V ; 3.09 V ; -0.0462 V ; 0.045 V ; 0.085 V ; 5.49e-10 s ; 3.06e-10 s ; Yes ; Yes ; 3.08 V ; 3.09e-05 V ; 3.09 V ; -0.0462 V ; 0.045 V ; 0.085 V ; 5.49e-10 s ; 3.06e-10 s ; Yes ; Yes ;
; led[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.73e-05 V ; 3.11 V ; -0.104 V ; 0.101 V ; 0.139 V ; 5.54e-10 s ; 3.16e-10 s ; Yes ; Yes ; 3.08 V ; 3.73e-05 V ; 3.11 V ; -0.104 V ; 0.101 V ; 0.139 V ; 5.54e-10 s ; 3.16e-10 s ; Yes ; Yes ;
; led[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.87e-05 V ; 3.11 V ; -0.0814 V ; 0.131 V ; 0.136 V ; 5.88e-10 s ; 3.2e-10 s ; Yes ; Yes ; 3.08 V ; 3.87e-05 V ; 3.11 V ; -0.0814 V ; 0.131 V ; 0.136 V ; 5.88e-10 s ; 3.2e-10 s ; Yes ; Yes ;
; led[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.09e-05 V ; 3.09 V ; -0.0462 V ; 0.045 V ; 0.085 V ; 5.49e-10 s ; 3.06e-10 s ; Yes ; Yes ; 3.08 V ; 3.09e-05 V ; 3.09 V ; -0.0462 V ; 0.045 V ; 0.085 V ; 5.49e-10 s ; 3.06e-10 s ; Yes ; Yes ;
; led[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.73e-05 V ; 3.11 V ; -0.104 V ; 0.101 V ; 0.139 V ; 5.54e-10 s ; 3.16e-10 s ; Yes ; Yes ; 3.08 V ; 3.73e-05 V ; 3.11 V ; -0.104 V ; 0.101 V ; 0.139 V ; 5.54e-10 s ; 3.16e-10 s ; Yes ; Yes ;
; led[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.73e-05 V ; 3.11 V ; -0.105 V ; 0.101 V ; 0.142 V ; 5.54e-10 s ; 3.16e-10 s ; Yes ; Yes ; 3.08 V ; 3.73e-05 V ; 3.11 V ; -0.105 V ; 0.101 V ; 0.142 V ; 5.54e-10 s ; 3.16e-10 s ; Yes ; Yes ;
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Fast 1100mv n40c Model) ;
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; lcd_clk ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 2.38e-07 V ; 2.94 V ; -0.139 V ; 0.31 V ; 0.268 V ; 2.65e-10 s ; 2.63e-10 s ; No ; Yes ; 2.75 V ; 2.38e-07 V ; 2.94 V ; -0.139 V ; 0.31 V ; 0.268 V ; 2.65e-10 s ; 2.63e-10 s ; No ; Yes ;
; lcd_data ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.38e-07 V ; 3.67 V ; -0.403 V ; 0.084 V ; 0.542 V ; 3.5e-10 s ; 1.32e-10 s ; Yes ; No ; 3.63 V ; 3.38e-07 V ; 3.67 V ; -0.403 V ; 0.084 V ; 0.542 V ; 3.5e-10 s ; 1.32e-10 s ; Yes ; No ;
; led[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.38e-07 V ; 3.67 V ; -0.403 V ; 0.084 V ; 0.542 V ; 3.5e-10 s ; 1.32e-10 s ; Yes ; No ; 3.63 V ; 3.38e-07 V ; 3.67 V ; -0.403 V ; 0.084 V ; 0.542 V ; 3.5e-10 s ; 1.32e-10 s ; Yes ; No ;
; led[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.42e-07 V ; 3.75 V ; -0.588 V ; 0.329 V ; 0.704 V ; 2.77e-10 s ; 1.3e-10 s ; Yes ; No ; 3.63 V ; 4.42e-07 V ; 3.75 V ; -0.588 V ; 0.329 V ; 0.704 V ; 2.77e-10 s ; 1.3e-10 s ; Yes ; No ;
; led[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.64e-07 V ; 3.74 V ; -0.508 V ; 0.391 V ; 0.647 V ; 3.08e-10 s ; 1.34e-10 s ; No ; No ; 3.63 V ; 4.64e-07 V ; 3.74 V ; -0.508 V ; 0.391 V ; 0.647 V ; 3.08e-10 s ; 1.34e-10 s ; No ; No ;
; led[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.38e-07 V ; 3.67 V ; -0.403 V ; 0.084 V ; 0.542 V ; 3.5e-10 s ; 1.32e-10 s ; Yes ; No ; 3.63 V ; 3.38e-07 V ; 3.67 V ; -0.403 V ; 0.084 V ; 0.542 V ; 3.5e-10 s ; 1.32e-10 s ; Yes ; No ;
; led[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.42e-07 V ; 3.75 V ; -0.588 V ; 0.329 V ; 0.704 V ; 2.77e-10 s ; 1.3e-10 s ; Yes ; No ; 3.63 V ; 4.42e-07 V ; 3.75 V ; -0.588 V ; 0.329 V ; 0.704 V ; 2.77e-10 s ; 1.3e-10 s ; Yes ; No ;
; led[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.42e-07 V ; 3.75 V ; -0.589 V ; 0.329 V ; 0.706 V ; 2.77e-10 s ; 1.3e-10 s ; Yes ; No ; 3.63 V ; 4.42e-07 V ; 3.75 V ; -0.589 V ; 0.329 V ; 0.706 V ; 2.77e-10 s ; 1.3e-10 s ; Yes ; No ;
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Fast 1100mv 100c Model) ;
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; lcd_clk ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.00041 V ; 2.85 V ; -0.0763 V ; 0.365 V ; 0.161 V ; 3.08e-10 s ; 4.37e-10 s ; No ; No ; 2.75 V ; 0.00041 V ; 2.85 V ; -0.0763 V ; 0.365 V ; 0.161 V ; 3.08e-10 s ; 4.37e-10 s ; No ; No ;
; lcd_data ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000307 V ; 3.64 V ; -0.165 V ; 0.022 V ; 0.425 V ; 4.58e-10 s ; 2e-10 s ; Yes ; No ; 3.63 V ; 0.000307 V ; 3.64 V ; -0.165 V ; 0.022 V ; 0.425 V ; 4.58e-10 s ; 2e-10 s ; Yes ; No ;
; led[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000307 V ; 3.64 V ; -0.165 V ; 0.022 V ; 0.425 V ; 4.58e-10 s ; 2e-10 s ; Yes ; No ; 3.63 V ; 0.000307 V ; 3.64 V ; -0.165 V ; 0.022 V ; 0.425 V ; 4.58e-10 s ; 2e-10 s ; Yes ; No ;
; led[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000379 V ; 3.65 V ; -0.289 V ; 0.051 V ; 0.523 V ; 4.36e-10 s ; 1.95e-10 s ; Yes ; No ; 3.63 V ; 0.000379 V ; 3.65 V ; -0.289 V ; 0.051 V ; 0.523 V ; 4.36e-10 s ; 1.95e-10 s ; Yes ; No ;
; led[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000395 V ; 3.65 V ; -0.232 V ; 0.065 V ; 0.547 V ; 4.68e-10 s ; 2.07e-10 s ; Yes ; No ; 3.63 V ; 0.000395 V ; 3.65 V ; -0.232 V ; 0.065 V ; 0.547 V ; 4.68e-10 s ; 2.07e-10 s ; Yes ; No ;
; led[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000307 V ; 3.64 V ; -0.165 V ; 0.022 V ; 0.425 V ; 4.58e-10 s ; 2e-10 s ; Yes ; No ; 3.63 V ; 0.000307 V ; 3.64 V ; -0.165 V ; 0.022 V ; 0.425 V ; 4.58e-10 s ; 2e-10 s ; Yes ; No ;
; led[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000379 V ; 3.65 V ; -0.289 V ; 0.051 V ; 0.523 V ; 4.36e-10 s ; 1.95e-10 s ; Yes ; No ; 3.63 V ; 0.000379 V ; 3.65 V ; -0.289 V ; 0.051 V ; 0.523 V ; 4.36e-10 s ; 1.95e-10 s ; Yes ; No ;
; led[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000379 V ; 3.65 V ; -0.292 V ; 0.053 V ; 0.524 V ; 4.36e-10 s ; 1.95e-10 s ; Yes ; No ; 3.63 V ; 0.000379 V ; 3.65 V ; -0.292 V ; 0.053 V ; 0.524 V ; 4.36e-10 s ; 1.95e-10 s ; Yes ; No ;
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+---------------------------------------------------------------------------------------------------------------------------------+
; Setup Transfers ;
+------------------------------------------+------------------------------------------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------------------------------------+------------------------------------------+----------+----------+----------+----------+
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; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 2393 ; 126 ; 0 ; 1681819 ;
; downclocker:dc|clk_out ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 0 ; 0 ; 9878 ; 0 ;
; downclocker:dc|clk_out ; downclocker:dc|clk_out ; 13182899 ; 148 ; 48 ; 0 ;
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; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; fpga_clk ; 1 ; 1 ; 0 ; 0 ;
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; downclocker:dc|clk_out ; fpga_clk ; 1 ; 1 ; 0 ; 0 ;
; fpga_clk ; fpga_clk ; 121 ; 0 ; 0 ; 0 ;
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+------------------------------------------+------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+---------------------------------------------------------------------------------------------------------------------------------+
; Hold Transfers ;
+------------------------------------------+------------------------------------------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------------------------------------+------------------------------------------+----------+----------+----------+----------+
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; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 2393 ; 126 ; 0 ; 1681819 ;
; downclocker:dc|clk_out ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; 0 ; 0 ; 9878 ; 0 ;
; downclocker:dc|clk_out ; downclocker:dc|clk_out ; 13182899 ; 148 ; 48 ; 0 ;
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; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; fpga_clk ; 1 ; 1 ; 0 ; 0 ;
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; downclocker:dc|clk_out ; fpga_clk ; 1 ; 1 ; 0 ; 0 ;
; fpga_clk ; fpga_clk ; 121 ; 0 ; 0 ; 0 ;
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+------------------------------------------+------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design
---------------
; Report RSKM ;
---------------
No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
+------------------------------------------------+
; Unconstrained Paths Summary ;
+---------------------------------+-------+------+
; Property ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks ; 0 ; 0 ;
; Unconstrained Clocks ; 0 ; 0 ;
; Unconstrained Input Ports ; 0 ; 0 ;
; Unconstrained Input Port Paths ; 0 ; 0 ;
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; Unconstrained Output Ports ; 6 ; 6 ;
; Unconstrained Output Port Paths ; 6 ; 6 ;
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+---------------------------------+-------+------+
+----------------------------------------------------------------------------------------------------------+
; Clock Status Summary ;
+------------------------------------------+------------------------------------------+------+-------------+
; Target ; Clock ; Type ; Status ;
+------------------------------------------+------------------------------------------+------+-------------+
; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; cpu:cpu|st7920_serial_driver:gpu|lcd_clk ; Base ; Constrained ;
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; downclocker:dc|clk_out ; downclocker:dc|clk_out ; Base ; Constrained ;
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; fpga_clk ; fpga_clk ; Base ; Constrained ;
+------------------------------------------+------------------------------------------+------+-------------+
+-----------------------------------------------------------------------------------------------------+
; Unconstrained Output Ports ;
+-------------+---------------------------------------------------------------------------------------+
; Output Port ; Comment ;
+-------------+---------------------------------------------------------------------------------------+
; lcd_clk ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; lcd_data ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; led[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; led[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; led[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; led[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+-------------+---------------------------------------------------------------------------------------+
+-----------------------------------------------------------------------------------------------------+
; Unconstrained Output Ports ;
+-------------+---------------------------------------------------------------------------------------+
; Output Port ; Comment ;
+-------------+---------------------------------------------------------------------------------------+
; lcd_clk ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; lcd_data ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; led[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; led[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; led[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; led[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+-------------+---------------------------------------------------------------------------------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Timing Analyzer
Info: Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition
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Info: Processing started: Mon Apr 8 08:52:26 2024
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Info: Command: quartus_sta chip8 -c chip8
Info: qsta_default_script.tcl version: #1
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 12 of the 12 processors detected
Info (21077): Low junction temperature is -40 degrees C
Info (21077): High junction temperature is 100 degrees C
Critical Warning (332012): Synopsys Design Constraints File file not found: 'chip8.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332105): Deriving Clocks
Info (332105): create_clock -period 1.000 -name fpga_clk fpga_clk
Info (332105): create_clock -period 1.000 -name cpu:cpu|st7920_serial_driver:gpu|lcd_clk cpu:cpu|st7920_serial_driver:gpu|lcd_clk
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Info (332105): create_clock -period 1.000 -name downclocker:dc|clk_out downclocker:dc|clk_out
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Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Analyzing Slow 1100mV 100C Model
Critical Warning (332148): Timing requirements not met
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer.
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Info (332146): Worst-case setup slack is -31.412
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Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
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Info (332119): -31.412 -1884.356 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332119): -11.058 -87363.415 downclocker:dc|clk_out
Info (332119): -4.953 -27.713 fpga_clk
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Info (332146): Worst-case hold slack is 0.429
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
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Info (332119): 0.429 0.000 downclocker:dc|clk_out
Info (332119): 0.501 0.000 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332119): 0.814 0.000 fpga_clk
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Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is -2.636
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
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Info (332119): -2.636 -8430.055 downclocker:dc|clk_out
Info (332119): -0.622 -17.105 fpga_clk
Info (332119): -0.538 -172.550 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
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Info (332114): Report Metastability: Found 8 synchronizer chains.
Info (332114): Design MTBF is not calculated because the design doesn't meet its timing requirements.
Info: Analyzing Slow 1100mV -40C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer.
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Info (332146): Worst-case setup slack is -29.494
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Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
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Info (332119): -29.494 -1798.010 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332119): -11.057 -87142.095 downclocker:dc|clk_out
Info (332119): -4.658 -29.299 fpga_clk
Info (332146): Worst-case hold slack is 0.483
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Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
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Info (332119): 0.483 0.000 downclocker:dc|clk_out
Info (332119): 0.546 0.000 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332119): 0.786 0.000 fpga_clk
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Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is -2.636
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
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Info (332119): -2.636 -8301.987 downclocker:dc|clk_out
Info (332119): -0.627 -18.184 fpga_clk
Info (332119): -0.538 -170.070 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
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Info (332114): Report Metastability: Found 8 synchronizer chains.
Info (332114): Design MTBF is not calculated because the design doesn't meet its timing requirements.
Info: Analyzing Fast 1100mV 100C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer.
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Info (332146): Worst-case setup slack is -16.301
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Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
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Info (332119): -16.301 -1018.017 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332119): -5.608 -44394.911 downclocker:dc|clk_out
Info (332119): -3.718 -8.178 fpga_clk
Info (332146): Worst-case hold slack is 0.160
add new pic
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Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
alu works on fpga
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Info (332119): 0.160 0.000 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332119): 0.177 0.000 downclocker:dc|clk_out
Info (332119): 0.303 0.000 fpga_clk
add new pic
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Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is -2.174
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
alu works on fpga
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Info (332119): -2.174 -537.344 downclocker:dc|clk_out
Info (332119): -0.517 -2.901 fpga_clk
Info (332119): -0.144 -6.507 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
add new pic
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Info (332114): Report Metastability: Found 8 synchronizer chains.
Info (332114): Design MTBF is not calculated because the design doesn't meet its timing requirements.
Info: Analyzing Fast 1100mV -40C Model
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer.
alu works on fpga
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Info (332146): Worst-case setup slack is -14.004
add new pic
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Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
alu works on fpga
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Info (332119): -14.004 -820.600 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332119): -4.541 -36337.093 downclocker:dc|clk_out
Info (332119): -2.859 -5.427 fpga_clk
Info (332146): Worst-case hold slack is 0.138
add new pic
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Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
alu works on fpga
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Info (332119): 0.138 0.000 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
Info (332119): 0.164 0.000 downclocker:dc|clk_out
Info (332119): 0.289 0.000 fpga_clk
add new pic
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Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is -2.174
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
alu works on fpga
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Info (332119): -2.174 -534.258 downclocker:dc|clk_out
Info (332119): -0.533 -2.899 fpga_clk
Info (332119): -0.057 -2.411 cpu:cpu|st7920_serial_driver:gpu|lcd_clk
add new pic
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Info (332114): Report Metastability: Found 8 synchronizer chains.
Info (332114): Design MTBF is not calculated because the design doesn't meet its timing requirements.
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings
alu works on fpga
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Info: Peak virtual memory: 1312 megabytes
Info: Processing ended: Mon Apr 8 08:52:45 2024
Info: Elapsed time: 00:00:19
Info: Total CPU time (on all processors): 00:01:25
add new pic
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