{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1712524771801 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition " "Version 23.1std.0 Build 991 11/28/2023 SC Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1712524771802 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr  7 16:19:31 2024 " "Processing started: Sun Apr  7 16:19:31 2024" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1712524771802 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712524771802 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off chip8 -c chip8 " "Command: quartus_map --read_settings_files=on --write_settings_files=off chip8 -c chip8" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712524771802 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1712524771959 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "12 12 " "Parallel compilation is enabled and will use 12 of the 12 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1712524771959 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "the-bomb/st7920_serial_driver.sv 3 3 " "Found 3 design units, including 3 entities, in source file the-bomb/st7920_serial_driver.sv" { { "Info" "ISGN_ENTITY_NAME" "1 st7920_serial_driver " "Found entity 1: st7920_serial_driver" {  } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 4 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712524777280 ""} { "Info" "ISGN_ENTITY_NAME" "2 d_flip_flop " "Found entity 2: d_flip_flop" {  } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 138 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712524777280 ""} { "Info" "ISGN_ENTITY_NAME" "3 commander " "Found entity 3: commander" {  } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 148 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712524777280 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712524777280 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "chip8.sv 2 2 " "Found 2 design units, including 2 entities, in source file chip8.sv" { { "Info" "ISGN_ENTITY_NAME" "1 chip8 " "Found entity 1: chip8" {  } { { "chip8.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/chip8.sv" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712524777281 ""} { "Info" "ISGN_ENTITY_NAME" "2 dc " "Found entity 2: dc" {  } { { "chip8.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/chip8.sv" 65 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712524777281 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712524777281 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu.sv 1 1 " "Found 1 design units, including 1 entities, in source file cpu.sv" { { "Info" "ISGN_ENTITY_NAME" "1 cpu " "Found entity 1: cpu" {  } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712524777281 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712524777281 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rng.sv 1 1 " "Found 1 design units, including 1 entities, in source file rng.sv" { { "Info" "ISGN_ENTITY_NAME" "1 rng " "Found entity 1: rng" {  } { { "rng.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/rng.sv" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712524777282 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712524777282 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "chip8 " "Elaborating entity \"chip8\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1712524777314 ""}
{ "Warning" "WVRFX_VERI_2106_UNCONVERTED" "keyboard chip8.sv(9) " "Verilog HDL warning at chip8.sv(9): object keyboard used but never assigned" {  } { { "chip8.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/chip8.sv" 9 0 0 } }  } 0 10858 "Verilog HDL warning at %2!s!: object %1!s! used but never assigned" 0 0 "Analysis & Synthesis" 0 -1 1712524777315 "|chip8"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "keyboard 0 chip8.sv(9) " "Net \"keyboard\" at chip8.sv(9) has no driver or initial value, using a default initial value '0'" {  } { { "chip8.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/chip8.sv" 9 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1712524777316 "|chip8"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dc dc:dc " "Elaborating entity \"dc\" for hierarchy \"dc:dc\"" {  } { { "chip8.sv" "dc" { Text "/home/nickorlow/programming/school/warminster/yayacemu/chip8.sv" 24 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712524777325 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 21 chip8.sv(77) " "Verilog HDL assignment warning at chip8.sv(77): truncated value with size 32 to match size of target (21)" {  } { { "chip8.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/chip8.sv" 77 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712524777325 "|chip8|dc:dc"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu cpu:cpu " "Elaborating entity \"cpu\" for hierarchy \"cpu:cpu\"" {  } { { "chip8.sv" "cpu" { Text "/home/nickorlow/programming/school/warminster/yayacemu/chip8.sv" 39 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712524777328 ""}
{ "Warning" "WVRFX_L2_HDL_INDEX_EXPR_NOT_WIDE_ENOUGH" "cpu.sv(16) " "Verilog HDL or VHDL warning at the cpu.sv(16): index expression is not wide enough to address all of the elements in the array" {  } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 16 0 0 } }  } 0 10027 "Verilog HDL or VHDL warning at the %1!s!: index expression is not wide enough to address all of the elements in the array" 0 0 "Analysis & Synthesis" 0 -1 1712524777339 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_VERI_2111_UNCONVERTED" "80 0 4095 cpu.sv(44) " "Verilog HDL warning at cpu.sv(44): number of words (80) in memory file does not match the number of elements in the address range \[0:4095\]" {  } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 44 0 0 } }  } 0 10850 "Verilog HDL warning at %4!s!: number of words (%1!d!) in memory file does not match the number of elements in the address range \[%2!d!:%3!d!\]" 0 0 "Analysis & Synthesis" 0 -1 1712524777340 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_VERI_2111_UNCONVERTED" "697 512 4095 cpu.sv(45) " "Verilog HDL warning at cpu.sv(45): number of words (697) in memory file does not match the number of elements in the address range \[512:4095\]" {  } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 45 0 0 } }  } 0 10850 "Verilog HDL warning at %4!s!: number of words (%1!d!) in memory file does not match the number of elements in the address range \[%2!d!:%3!d!\]" 0 0 "Analysis & Synthesis" 0 -1 1712524777341 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_VERI_2116_UNCONVERTED" "memory cpu.sv(43) " "Verilog HDL warning at cpu.sv(43): initial value for variable memory should be constant" {  } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 43 0 0 } }  } 0 10855 "Verilog HDL warning at %2!s!: initial value for variable %1!s! should be constant" 0 0 "Analysis & Synthesis" 0 -1 1712524777342 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(80) " "Verilog HDL assignment warning at cpu.sv(80): truncated value with size 32 to match size of target (16)" {  } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 80 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712524777795 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(85) " "Verilog HDL assignment warning at cpu.sv(85): truncated value with size 32 to match size of target (16)" {  } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 85 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712524777803 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(88) " "Verilog HDL assignment warning at cpu.sv(88): truncated value with size 32 to match size of target (16)" {  } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 88 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712524777811 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(90) " "Verilog HDL assignment warning at cpu.sv(90): truncated value with size 32 to match size of target (16)" {  } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 90 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712524777819 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(94) " "Verilog HDL assignment warning at cpu.sv(94): truncated value with size 32 to match size of target (16)" {  } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 94 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712524777827 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(96) " "Verilog HDL assignment warning at cpu.sv(96): truncated value with size 32 to match size of target (16)" {  } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 96 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712524777835 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(101) " "Verilog HDL assignment warning at cpu.sv(101): truncated value with size 32 to match size of target (16)" {  } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 101 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712524777849 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(105) " "Verilog HDL assignment warning at cpu.sv(105): truncated value with size 32 to match size of target (16)" {  } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 105 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712524777857 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(109) " "Verilog HDL assignment warning at cpu.sv(109): truncated value with size 32 to match size of target (16)" {  } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 109 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712524777873 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(156) " "Verilog HDL assignment warning at cpu.sv(156): truncated value with size 32 to match size of target (16)" {  } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 156 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712524778155 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(160) " "Verilog HDL assignment warning at cpu.sv(160): truncated value with size 32 to match size of target (16)" {  } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 160 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712524778161 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(163) " "Verilog HDL assignment warning at cpu.sv(163): truncated value with size 32 to match size of target (16)" {  } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 163 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712524778168 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(168) " "Verilog HDL assignment warning at cpu.sv(168): truncated value with size 32 to match size of target (16)" {  } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 168 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712524778174 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(180) " "Verilog HDL assignment warning at cpu.sv(180): truncated value with size 32 to match size of target (16)" {  } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 180 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712524778200 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 cpu.sv(188) " "Verilog HDL assignment warning at cpu.sv(188): truncated value with size 32 to match size of target (8)" {  } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 188 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712524778206 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(203) " "Verilog HDL assignment warning at cpu.sv(203): truncated value with size 32 to match size of target (16)" {  } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 203 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712524825848 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(209) " "Verilog HDL assignment warning at cpu.sv(209): truncated value with size 32 to match size of target (16)" {  } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 209 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712524825855 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(246) " "Verilog HDL assignment warning at cpu.sv(246): truncated value with size 32 to match size of target (16)" {  } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 246 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712524825922 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(251) " "Verilog HDL assignment warning at cpu.sv(251): truncated value with size 32 to match size of target (16)" {  } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 251 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712524825929 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(254) " "Verilog HDL assignment warning at cpu.sv(254): truncated value with size 32 to match size of target (16)" {  } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 254 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712524826017 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(257) " "Verilog HDL assignment warning at cpu.sv(257): truncated value with size 32 to match size of target (16)" {  } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 257 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712524826069 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(262) " "Verilog HDL assignment warning at cpu.sv(262): truncated value with size 32 to match size of target (16)" {  } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 262 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712524826130 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(271) " "Verilog HDL assignment warning at cpu.sv(271): truncated value with size 32 to match size of target (16)" {  } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 271 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712524827860 "|chip8|cpu:cpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 cpu.sv(280) " "Verilog HDL assignment warning at cpu.sv(280): truncated value with size 32 to match size of target (16)" {  } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 280 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712524828187 "|chip8|cpu:cpu"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "st7920_serial_driver st7920_serial_driver:gpu " "Elaborating entity \"st7920_serial_driver\" for hierarchy \"st7920_serial_driver:gpu\"" {  } { { "chip8.sv" "gpu" { Text "/home/nickorlow/programming/school/warminster/yayacemu/chip8.sv" 49 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712525046026 ""}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "line_idx st7920_serial_driver.sv(25) " "Verilog HDL or VHDL warning at st7920_serial_driver.sv(25): object \"line_idx\" assigned a value but never read" {  } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 25 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1712525046026 "|chip8|st7920_serial_driver:gpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 st7920_serial_driver.sv(73) " "Verilog HDL assignment warning at st7920_serial_driver.sv(73): truncated value with size 32 to match size of target (7)" {  } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 73 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712525046027 "|chip8|st7920_serial_driver:gpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 st7920_serial_driver.sv(86) " "Verilog HDL assignment warning at st7920_serial_driver.sv(86): truncated value with size 32 to match size of target (7)" {  } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 86 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712525046027 "|chip8|st7920_serial_driver:gpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 st7920_serial_driver.sv(98) " "Verilog HDL assignment warning at st7920_serial_driver.sv(98): truncated value with size 32 to match size of target (10)" {  } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 98 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712525046027 "|chip8|st7920_serial_driver:gpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 st7920_serial_driver.sv(100) " "Verilog HDL assignment warning at st7920_serial_driver.sv(100): truncated value with size 32 to match size of target (10)" {  } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 100 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712525046028 "|chip8|st7920_serial_driver:gpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 st7920_serial_driver.sv(104) " "Verilog HDL assignment warning at st7920_serial_driver.sv(104): truncated value with size 32 to match size of target (6)" {  } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 104 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712525046028 "|chip8|st7920_serial_driver:gpu"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 9 st7920_serial_driver.sv(132) " "Verilog HDL assignment warning at st7920_serial_driver.sv(132): truncated value with size 32 to match size of target (9)" {  } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 132 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1712525046029 "|chip8|st7920_serial_driver:gpu"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "commands\[6..10\] 0 st7920_serial_driver.sv(28) " "Net \"commands\[6..10\]\" at st7920_serial_driver.sv(28) has no driver or initial value, using a default initial value '0'" {  } { { "the-bomb/st7920_serial_driver.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 28 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1712525046030 "|chip8|st7920_serial_driver:gpu"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "commander st7920_serial_driver:gpu\|commander:com " "Elaborating entity \"commander\" for hierarchy \"st7920_serial_driver:gpu\|commander:com\"" {  } { { "the-bomb/st7920_serial_driver.sv" "com" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 44 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712525046041 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "d_flip_flop st7920_serial_driver:gpu\|d_flip_flop:dff " "Elaborating entity \"d_flip_flop\" for hierarchy \"st7920_serial_driver:gpu\|d_flip_flop:dff\"" {  } { { "the-bomb/st7920_serial_driver.sv" "dff" { Text "/home/nickorlow/programming/school/warminster/yayacemu/the-bomb/st7920_serial_driver.sv" 52 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712525046045 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rng rng:randy " "Elaborating entity \"rng\" for hierarchy \"rng:randy\"" {  } { { "chip8.sv" "randy" { Text "/home/nickorlow/programming/school/warminster/yayacemu/chip8.sv" 57 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712525046046 ""}
{ "Info" "IINFER_UNINFERRED_RAM_SUMMARY" "1 " "Found 1 instances of uninferred RAM logic" { { "Info" "IINFER_READ_LOGIC_IS_ASYNCHRONOUS" "cpu:cpu\|stack " "RAM logic \"cpu:cpu\|stack\" is uninferred due to asynchronous read logic" {  } { { "cpu.sv" "stack" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 24 -1 0 } }  } 0 276007 "RAM logic \"%1!s!\" is uninferred due to asynchronous read logic" 0 0 "Design Software" 0 -1 1712525143856 ""}  } {  } 0 276014 "Found %1!d! instances of uninferred RAM logic" 0 0 "Analysis & Synthesis" 0 -1 1712525143856 ""}
{ "Info" "ILPMS_INFERENCING_SUMMARY" "7 " "Inferred 7 megafunctions from design logic" { { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "cpu:cpu\|Mod0 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"cpu:cpu\|Mod0\"" {  } { { "cpu.sv" "Mod0" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 64 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1712525681962 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "cpu:cpu\|Mod1 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"cpu:cpu\|Mod1\"" {  } { { "cpu.sv" "Mod1" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 251 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1712525681962 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "cpu:cpu\|Div0 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"cpu:cpu\|Div0\"" {  } { { "cpu.sv" "Div0" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 253 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1712525681962 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "cpu:cpu\|Mod2 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"cpu:cpu\|Mod2\"" {  } { { "cpu.sv" "Mod2" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 254 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1712525681962 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "cpu:cpu\|Div1 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"cpu:cpu\|Div1\"" {  } { { "cpu.sv" "Div1" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 256 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1712525681962 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "cpu:cpu\|Mod3 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"cpu:cpu\|Mod3\"" {  } { { "cpu.sv" "Mod3" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 257 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1712525681962 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "rng:randy\|Mod0 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"rng:randy\|Mod0\"" {  } { { "rng.sv" "Mod0" { Text "/home/nickorlow/programming/school/warminster/yayacemu/rng.sv" 14 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1712525681962 ""}  } {  } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Analysis & Synthesis" 0 -1 1712525681962 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "cpu:cpu\|lpm_divide:Mod0 " "Elaborated megafunction instantiation \"cpu:cpu\|lpm_divide:Mod0\"" {  } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 64 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712525682315 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "cpu:cpu\|lpm_divide:Mod0 " "Instantiated megafunction \"cpu:cpu\|lpm_divide:Mod0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 32 " "Parameter \"LPM_WIDTHN\" = \"32\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712525682315 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 6 " "Parameter \"LPM_WIDTHD\" = \"6\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712525682315 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION SIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"SIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712525682315 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION SIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"SIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712525682315 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_HINT LPM_REMAINDERPOSITIVE=FALSE " "Parameter \"LPM_HINT\" = \"LPM_REMAINDERPOSITIVE=FALSE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712525682315 ""}  } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 64 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1712525682315 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_fho.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_fho.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_fho " "Found entity 1: lpm_divide_fho" {  } { { "db/lpm_divide_fho.tdf" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/db/lpm_divide_fho.tdf" 25 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712525682358 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712525682358 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/abs_divider_lbg.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/abs_divider_lbg.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 abs_divider_lbg " "Found entity 1: abs_divider_lbg" {  } { { "db/abs_divider_lbg.tdf" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/db/abs_divider_lbg.tdf" 29 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712525682362 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712525682362 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_qve.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/alt_u_div_qve.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_qve " "Found entity 1: alt_u_div_qve" {  } { { "db/alt_u_div_qve.tdf" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/db/alt_u_div_qve.tdf" 23 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712525682376 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712525682376 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_abs_ln9.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_abs_ln9.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_abs_ln9 " "Found entity 1: lpm_abs_ln9" {  } { { "db/lpm_abs_ln9.tdf" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/db/lpm_abs_ln9.tdf" 23 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712525682406 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712525682406 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_abs_4p9.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_abs_4p9.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_abs_4p9 " "Found entity 1: lpm_abs_4p9" {  } { { "db/lpm_abs_4p9.tdf" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/db/lpm_abs_4p9.tdf" 23 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712525682409 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712525682409 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "cpu:cpu\|lpm_divide:Mod1 " "Elaborated megafunction instantiation \"cpu:cpu\|lpm_divide:Mod1\"" {  } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 251 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712525682420 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "cpu:cpu\|lpm_divide:Mod1 " "Instantiated megafunction \"cpu:cpu\|lpm_divide:Mod1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 8 " "Parameter \"LPM_WIDTHN\" = \"8\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712525682420 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 4 " "Parameter \"LPM_WIDTHD\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712525682420 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712525682420 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712525682420 ""}  } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 251 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1712525682420 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_82m.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_82m.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_82m " "Found entity 1: lpm_divide_82m" {  } { { "db/lpm_divide_82m.tdf" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/db/lpm_divide_82m.tdf" 25 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712525682439 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712525682439 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_bkh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/sign_div_unsign_bkh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_bkh " "Found entity 1: sign_div_unsign_bkh" {  } { { "db/sign_div_unsign_bkh.tdf" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/db/sign_div_unsign_bkh.tdf" 25 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712525682441 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712525682441 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_sse.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/alt_u_div_sse.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_sse " "Found entity 1: alt_u_div_sse" {  } { { "db/alt_u_div_sse.tdf" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/db/alt_u_div_sse.tdf" 23 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712525682445 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712525682445 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "cpu:cpu\|lpm_divide:Div0 " "Elaborated megafunction instantiation \"cpu:cpu\|lpm_divide:Div0\"" {  } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 253 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712525682452 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "cpu:cpu\|lpm_divide:Div0 " "Instantiated megafunction \"cpu:cpu\|lpm_divide:Div0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 8 " "Parameter \"LPM_WIDTHN\" = \"8\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712525682452 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 4 " "Parameter \"LPM_WIDTHD\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712525682452 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712525682452 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712525682452 ""}  } { { "cpu.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/cpu.sv" 253 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1712525682452 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_5am.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_5am.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_5am " "Found entity 1: lpm_divide_5am" {  } { { "db/lpm_divide_5am.tdf" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/db/lpm_divide_5am.tdf" 25 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712525682471 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712525682471 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "rng:randy\|lpm_divide:Mod0 " "Elaborated megafunction instantiation \"rng:randy\|lpm_divide:Mod0\"" {  } { { "rng.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/rng.sv" 14 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712525682655 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "rng:randy\|lpm_divide:Mod0 " "Instantiated megafunction \"rng:randy\|lpm_divide:Mod0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 32 " "Parameter \"LPM_WIDTHN\" = \"32\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712525682655 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 4 " "Parameter \"LPM_WIDTHD\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712525682655 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION SIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"SIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712525682655 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION SIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"SIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712525682655 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_HINT LPM_REMAINDERPOSITIVE=FALSE " "Parameter \"LPM_HINT\" = \"LPM_REMAINDERPOSITIVE=FALSE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1712525682655 ""}  } { { "rng.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/rng.sv" 14 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1712525682655 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_dho.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_dho.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_dho " "Found entity 1: lpm_divide_dho" {  } { { "db/lpm_divide_dho.tdf" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/db/lpm_divide_dho.tdf" 25 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712525682674 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712525682674 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/abs_divider_jbg.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/abs_divider_jbg.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 abs_divider_jbg " "Found entity 1: abs_divider_jbg" {  } { { "db/abs_divider_jbg.tdf" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/db/abs_divider_jbg.tdf" 29 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712525682677 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712525682677 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_mve.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/alt_u_div_mve.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_mve " "Found entity 1: alt_u_div_mve" {  } { { "db/alt_u_div_mve.tdf" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/db/alt_u_div_mve.tdf" 23 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712525682692 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712525682692 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_abs_jn9.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_abs_jn9.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_abs_jn9 " "Found entity 1: lpm_abs_jn9" {  } { { "db/lpm_abs_jn9.tdf" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/db/lpm_abs_jn9.tdf" 23 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1712525682724 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1712525682724 ""}
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "led\[5\] VCC " "Pin \"led\[5\]\" is stuck at VCC" {  } { { "chip8.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/chip8.sv" 7 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1712527323052 "|chip8|led[5]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1712527323052 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1712527352880 ""}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "68 " "68 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1712528930026 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1712528973164 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1712528973164 ""}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "1 " "Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "rst_in " "No output dependent on input pin \"rst_in\"" {  } { { "chip8.sv" "" { Text "/home/nickorlow/programming/school/warminster/yayacemu/chip8.sv" 3 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1712528998444 "|chip8|rst_in"}  } {  } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1712528998444 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "782597 " "Implemented 782597 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Implemented 2 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1712529000632 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1712529000632 ""} { "Info" "ICUT_CUT_TM_LCELLS" "782587 " "Implemented 782587 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1712529000632 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1712529000632 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 44 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 44 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5759 " "Peak virtual memory: 5759 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1712529001428 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr  7 17:30:01 2024 " "Processing ended: Sun Apr  7 17:30:01 2024" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1712529001428 ""} { "Info" "IQEXE_ELAPSED_TIME" "01:10:30 " "Elapsed time: 01:10:30" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1712529001428 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "01:37:11 " "Total CPU time (on all processors): 01:37:11" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1712529001428 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1712529001428 ""}
