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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
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||||
// Date : Tue Jun 24 11:58:34 2025
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||||
// Host : media-wawa running 64-bit NixOS 25.05 (Warbler)
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||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
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||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ top_axi_bram_ctrl_0_0_stub.v
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||||
// Design : top_axi_bram_ctrl_0_0
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||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7a100tlfgg484-2L
|
||||
// --------------------------------------------------------------------------------
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||||
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||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
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||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
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||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
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||||
(* x_core_info = "axi_bram_ctrl,Vivado 2022.1" *)
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||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(s_axi_aclk, s_axi_aresetn, s_axi_awaddr,
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s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
|
||||
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wlast, s_axi_wvalid,
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||||
s_axi_wready, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arlen,
|
||||
s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache, s_axi_arprot, s_axi_arvalid,
|
||||
s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rlast, s_axi_rvalid, s_axi_rready, bram_rst_a,
|
||||
bram_clk_a, bram_en_a, bram_we_a, bram_addr_a, bram_wrdata_a, bram_rddata_a, bram_rst_b,
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||||
bram_clk_b, bram_en_b, bram_we_b, bram_addr_b, bram_wrdata_b, bram_rddata_b)
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/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awaddr[15:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock,s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[15:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock,s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,bram_rst_a,bram_clk_a,bram_en_a,bram_we_a[3:0],bram_addr_a[15:0],bram_wrdata_a[31:0],bram_rddata_a[31:0],bram_rst_b,bram_clk_b,bram_en_b,bram_we_b[3:0],bram_addr_b[15:0],bram_wrdata_b[31:0],bram_rddata_b[31:0]" */;
|
||||
input s_axi_aclk;
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input s_axi_aresetn;
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input [15:0]s_axi_awaddr;
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input [7:0]s_axi_awlen;
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||||
input [2:0]s_axi_awsize;
|
||||
input [1:0]s_axi_awburst;
|
||||
input s_axi_awlock;
|
||||
input [3:0]s_axi_awcache;
|
||||
input [2:0]s_axi_awprot;
|
||||
input s_axi_awvalid;
|
||||
output s_axi_awready;
|
||||
input [31:0]s_axi_wdata;
|
||||
input [3:0]s_axi_wstrb;
|
||||
input s_axi_wlast;
|
||||
input s_axi_wvalid;
|
||||
output s_axi_wready;
|
||||
output [1:0]s_axi_bresp;
|
||||
output s_axi_bvalid;
|
||||
input s_axi_bready;
|
||||
input [15:0]s_axi_araddr;
|
||||
input [7:0]s_axi_arlen;
|
||||
input [2:0]s_axi_arsize;
|
||||
input [1:0]s_axi_arburst;
|
||||
input s_axi_arlock;
|
||||
input [3:0]s_axi_arcache;
|
||||
input [2:0]s_axi_arprot;
|
||||
input s_axi_arvalid;
|
||||
output s_axi_arready;
|
||||
output [31:0]s_axi_rdata;
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||||
output [1:0]s_axi_rresp;
|
||||
output s_axi_rlast;
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||||
output s_axi_rvalid;
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||||
input s_axi_rready;
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||||
output bram_rst_a;
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||||
output bram_clk_a;
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||||
output bram_en_a;
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||||
output [3:0]bram_we_a;
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||||
output [15:0]bram_addr_a;
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||||
output [31:0]bram_wrdata_a;
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||||
input [31:0]bram_rddata_a;
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||||
output bram_rst_b;
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||||
output bram_clk_b;
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||||
output bram_en_b;
|
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output [3:0]bram_we_b;
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||||
output [15:0]bram_addr_b;
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||||
output [31:0]bram_wrdata_b;
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||||
input [31:0]bram_rddata_b;
|
||||
endmodule
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||||
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@ -0,0 +1,76 @@
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|||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
|
||||
-- Date : Tue Jun 24 11:58:34 2025
|
||||
-- Host : media-wawa running 64-bit NixOS 25.05 (Warbler)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ top_axi_bram_ctrl_0_0_stub.vhdl
|
||||
-- Design : top_axi_bram_ctrl_0_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7a100tlfgg484-2L
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
s_axi_aclk : in STD_LOGIC;
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||||
s_axi_aresetn : in STD_LOGIC;
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||||
s_axi_awaddr : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
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||||
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_awlock : in STD_LOGIC;
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||||
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
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||||
s_axi_awvalid : in STD_LOGIC;
|
||||
s_axi_awready : out STD_LOGIC;
|
||||
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
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||||
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
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||||
s_axi_wlast : in STD_LOGIC;
|
||||
s_axi_wvalid : in STD_LOGIC;
|
||||
s_axi_wready : out STD_LOGIC;
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||||
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_bvalid : out STD_LOGIC;
|
||||
s_axi_bready : in STD_LOGIC;
|
||||
s_axi_araddr : in STD_LOGIC_VECTOR ( 15 downto 0 );
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||||
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_arlock : in STD_LOGIC;
|
||||
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_arvalid : in STD_LOGIC;
|
||||
s_axi_arready : out STD_LOGIC;
|
||||
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_rlast : out STD_LOGIC;
|
||||
s_axi_rvalid : out STD_LOGIC;
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||||
s_axi_rready : in STD_LOGIC;
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||||
bram_rst_a : out STD_LOGIC;
|
||||
bram_clk_a : out STD_LOGIC;
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||||
bram_en_a : out STD_LOGIC;
|
||||
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
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||||
bram_addr_a : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
bram_rddata_a : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
bram_rst_b : out STD_LOGIC;
|
||||
bram_clk_b : out STD_LOGIC;
|
||||
bram_en_b : out STD_LOGIC;
|
||||
bram_we_b : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
bram_addr_b : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
bram_wrdata_b : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 )
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "s_axi_aclk,s_axi_aresetn,s_axi_awaddr[15:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock,s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[15:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock,s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,bram_rst_a,bram_clk_a,bram_en_a,bram_we_a[3:0],bram_addr_a[15:0],bram_wrdata_a[31:0],bram_rddata_a[31:0],bram_rst_b,bram_clk_b,bram_en_b,bram_we_b[3:0],bram_addr_b[15:0],bram_wrdata_b[31:0],bram_rddata_b[31:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "axi_bram_ctrl,Vivado 2022.1";
|
||||
begin
|
||||
end;
|
||||
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|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">E</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">8704c60805dd810f</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCL">$Change: 3513466 $</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCRC">ea2a5533</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">167</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">27</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2022.1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
Binary file not shown.
|
|
@ -0,0 +1,582 @@
|
|||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
|
||||
// Date : Tue Jun 24 11:58:34 2025
|
||||
// Host : media-wawa running 64-bit NixOS 25.05 (Warbler)
|
||||
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ top_util_ds_buf_0_sim_netlist.v
|
||||
// Design : top_util_ds_buf_0
|
||||
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
||||
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
// Device : xc7a100tlfgg484-2L
|
||||
// --------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
(* CHECK_LICENSE_TYPE = "top_util_ds_buf_0,util_ds_buf,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "util_ds_buf,Vivado 2022.1" *)
|
||||
(* NotValidForBitStream *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
|
||||
(IBUF_DS_P,
|
||||
IBUF_DS_N,
|
||||
IBUF_OUT,
|
||||
IBUF_DS_ODIV2);
|
||||
(* x_interface_info = "xilinx.com:interface:diff_clock:1.0 CLK_IN_D CLK_P" *) (* x_interface_parameter = "XIL_INTERFACENAME CLK_IN_D, BOARD.ASSOCIATED_PARAM DIFF_CLK_IN_BOARD_INTERFACE, CAN_DEBUG false, FREQ_HZ 100000000" *) input [0:0]IBUF_DS_P;
|
||||
(* x_interface_info = "xilinx.com:interface:diff_clock:1.0 CLK_IN_D CLK_N" *) input [0:0]IBUF_DS_N;
|
||||
(* x_interface_info = "xilinx.com:signal:clock:1.0 IBUF_OUT CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME IBUF_OUT, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN top_util_ds_buf_0_IBUF_OUT, INSERT_VIP 0" *) output [0:0]IBUF_OUT;
|
||||
(* x_interface_info = "xilinx.com:signal:clock:1.0 IBUF_DS_ODIV2 CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME IBUF_DS_ODIV2, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN top_util_ds_buf_0_IBUF_DS_ODIV2, INSERT_VIP 0" *) output [0:0]IBUF_DS_ODIV2;
|
||||
|
||||
(* IBUF_LOW_PWR *) wire [0:0]IBUF_DS_N;
|
||||
wire [0:0]IBUF_DS_ODIV2;
|
||||
(* IBUF_LOW_PWR *) wire [0:0]IBUF_DS_P;
|
||||
wire [0:0]IBUF_OUT;
|
||||
wire [0:0]NLW_U0_BUFGCE_O_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_BUFG_FABRIC_O_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_BUFG_GT_O_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_BUFG_O_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_BUFG_PS_O_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_BUFHCE_O_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_BUFH_O_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_IBUFDS_GTME5_O_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_IBUFDS_GTME5_ODIV2_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_IBUFDS_GTM_O_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_IBUFDS_GTM_ODIV2_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_IOBUF_DS_N_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_IOBUF_DS_P_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_IOBUF_IO_IO_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_IOBUF_IO_O_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_MBUFG_GT_O1_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_MBUFG_GT_O2_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_MBUFG_GT_O3_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_MBUFG_GT_O4_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_MBUFG_PS_O1_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_MBUFG_PS_O2_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_MBUFG_PS_O3_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_MBUFG_PS_O4_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_OBUFDS_GTE3_ADV_O_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_OBUFDS_GTE3_ADV_OB_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_OBUFDS_GTE3_O_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_OBUFDS_GTE3_OB_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_OBUFDS_GTE4_ADV_O_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_OBUFDS_GTE4_ADV_OB_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_OBUFDS_GTE4_O_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_OBUFDS_GTE4_OB_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_OBUFDS_GTE5_ADV_O_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_OBUFDS_GTE5_ADV_OB_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_OBUFDS_GTE5_O_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_OBUFDS_GTE5_OB_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_OBUFDS_GTME5_ADV_O_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_OBUFDS_GTME5_ADV_OB_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_OBUFDS_GTME5_O_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_OBUFDS_GTME5_OB_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_OBUFDS_GTM_ADV_O_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_OBUFDS_GTM_ADV_OB_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_OBUFDS_GTM_O_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_OBUFDS_GTM_OB_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_OBUF_DS_N_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_OBUF_DS_P_UNCONNECTED;
|
||||
|
||||
(* C_BUFGCE_DIV = "1" *)
|
||||
(* C_BUFG_GT_SYNC = "0" *)
|
||||
(* C_BUF_TYPE = "ibufdsgte2" *)
|
||||
(* C_MODE = "PERFORMANCE" *)
|
||||
(* C_OBUFDS_GTE5_ADV = "2'b00" *)
|
||||
(* C_REFCLK_ICNTL_TX = "5'b00000" *)
|
||||
(* C_SIM_DEVICE = "VERSAL_AI_CORE_ES1" *)
|
||||
(* C_SIZE = "1" *)
|
||||
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_util_ds_buf U0
|
||||
(.BUFGCE_CE(1'b0),
|
||||
.BUFGCE_CLR(1'b0),
|
||||
.BUFGCE_I(1'b0),
|
||||
.BUFGCE_O(NLW_U0_BUFGCE_O_UNCONNECTED[0]),
|
||||
.BUFG_FABRIC_I(1'b0),
|
||||
.BUFG_FABRIC_O(NLW_U0_BUFG_FABRIC_O_UNCONNECTED[0]),
|
||||
.BUFG_GT_CE(1'b1),
|
||||
.BUFG_GT_CEMASK(1'b0),
|
||||
.BUFG_GT_CLR(1'b0),
|
||||
.BUFG_GT_CLRMASK(1'b0),
|
||||
.BUFG_GT_DIV({1'b0,1'b0,1'b0}),
|
||||
.BUFG_GT_I(1'b0),
|
||||
.BUFG_GT_O(NLW_U0_BUFG_GT_O_UNCONNECTED[0]),
|
||||
.BUFG_I(1'b0),
|
||||
.BUFG_O(NLW_U0_BUFG_O_UNCONNECTED[0]),
|
||||
.BUFG_PS_I(1'b0),
|
||||
.BUFG_PS_O(NLW_U0_BUFG_PS_O_UNCONNECTED[0]),
|
||||
.BUFHCE_CE(1'b0),
|
||||
.BUFHCE_I(1'b0),
|
||||
.BUFHCE_O(NLW_U0_BUFHCE_O_UNCONNECTED[0]),
|
||||
.BUFH_I(1'b0),
|
||||
.BUFH_O(NLW_U0_BUFH_O_UNCONNECTED[0]),
|
||||
.IBUFDS_GTME5_CEB(1'b0),
|
||||
.IBUFDS_GTME5_I(1'b0),
|
||||
.IBUFDS_GTME5_IB(1'b0),
|
||||
.IBUFDS_GTME5_O(NLW_U0_IBUFDS_GTME5_O_UNCONNECTED[0]),
|
||||
.IBUFDS_GTME5_ODIV2(NLW_U0_IBUFDS_GTME5_ODIV2_UNCONNECTED[0]),
|
||||
.IBUFDS_GTM_CEB(1'b0),
|
||||
.IBUFDS_GTM_I(1'b0),
|
||||
.IBUFDS_GTM_IB(1'b0),
|
||||
.IBUFDS_GTM_O(NLW_U0_IBUFDS_GTM_O_UNCONNECTED[0]),
|
||||
.IBUFDS_GTM_ODIV2(NLW_U0_IBUFDS_GTM_ODIV2_UNCONNECTED[0]),
|
||||
.IBUF_DS_CEB(1'b0),
|
||||
.IBUF_DS_N(IBUF_DS_N),
|
||||
.IBUF_DS_ODIV2(IBUF_DS_ODIV2),
|
||||
.IBUF_DS_P(IBUF_DS_P),
|
||||
.IBUF_OUT(IBUF_OUT),
|
||||
.IOBUF_DS_N(NLW_U0_IOBUF_DS_N_UNCONNECTED[0]),
|
||||
.IOBUF_DS_P(NLW_U0_IOBUF_DS_P_UNCONNECTED[0]),
|
||||
.IOBUF_IO_I(1'b0),
|
||||
.IOBUF_IO_IO(NLW_U0_IOBUF_IO_IO_UNCONNECTED[0]),
|
||||
.IOBUF_IO_O(NLW_U0_IOBUF_IO_O_UNCONNECTED[0]),
|
||||
.IOBUF_IO_T(1'b0),
|
||||
.MBUFG_GT_CE(1'b1),
|
||||
.MBUFG_GT_CEMASK(1'b0),
|
||||
.MBUFG_GT_CLR(1'b0),
|
||||
.MBUFG_GT_CLRB_LEAF(1'b1),
|
||||
.MBUFG_GT_CLRMASK(1'b0),
|
||||
.MBUFG_GT_DIV({1'b0,1'b0,1'b0}),
|
||||
.MBUFG_GT_I(1'b0),
|
||||
.MBUFG_GT_O1(NLW_U0_MBUFG_GT_O1_UNCONNECTED[0]),
|
||||
.MBUFG_GT_O2(NLW_U0_MBUFG_GT_O2_UNCONNECTED[0]),
|
||||
.MBUFG_GT_O3(NLW_U0_MBUFG_GT_O3_UNCONNECTED[0]),
|
||||
.MBUFG_GT_O4(NLW_U0_MBUFG_GT_O4_UNCONNECTED[0]),
|
||||
.MBUFG_PS_CLRB_LEAF(1'b1),
|
||||
.MBUFG_PS_I(1'b0),
|
||||
.MBUFG_PS_O1(NLW_U0_MBUFG_PS_O1_UNCONNECTED[0]),
|
||||
.MBUFG_PS_O2(NLW_U0_MBUFG_PS_O2_UNCONNECTED[0]),
|
||||
.MBUFG_PS_O3(NLW_U0_MBUFG_PS_O3_UNCONNECTED[0]),
|
||||
.MBUFG_PS_O4(NLW_U0_MBUFG_PS_O4_UNCONNECTED[0]),
|
||||
.OBUFDS_GTE3_ADV_CEB(1'b0),
|
||||
.OBUFDS_GTE3_ADV_I({1'b0,1'b0,1'b0,1'b0}),
|
||||
.OBUFDS_GTE3_ADV_O(NLW_U0_OBUFDS_GTE3_ADV_O_UNCONNECTED[0]),
|
||||
.OBUFDS_GTE3_ADV_OB(NLW_U0_OBUFDS_GTE3_ADV_OB_UNCONNECTED[0]),
|
||||
.OBUFDS_GTE3_CEB(1'b0),
|
||||
.OBUFDS_GTE3_I(1'b0),
|
||||
.OBUFDS_GTE3_O(NLW_U0_OBUFDS_GTE3_O_UNCONNECTED[0]),
|
||||
.OBUFDS_GTE3_OB(NLW_U0_OBUFDS_GTE3_OB_UNCONNECTED[0]),
|
||||
.OBUFDS_GTE4_ADV_CEB(1'b0),
|
||||
.OBUFDS_GTE4_ADV_I({1'b0,1'b0,1'b0,1'b0}),
|
||||
.OBUFDS_GTE4_ADV_O(NLW_U0_OBUFDS_GTE4_ADV_O_UNCONNECTED[0]),
|
||||
.OBUFDS_GTE4_ADV_OB(NLW_U0_OBUFDS_GTE4_ADV_OB_UNCONNECTED[0]),
|
||||
.OBUFDS_GTE4_CEB(1'b0),
|
||||
.OBUFDS_GTE4_I(1'b0),
|
||||
.OBUFDS_GTE4_O(NLW_U0_OBUFDS_GTE4_O_UNCONNECTED[0]),
|
||||
.OBUFDS_GTE4_OB(NLW_U0_OBUFDS_GTE4_OB_UNCONNECTED[0]),
|
||||
.OBUFDS_GTE5_ADV_CEB(1'b0),
|
||||
.OBUFDS_GTE5_ADV_I({1'b0,1'b0,1'b0,1'b0}),
|
||||
.OBUFDS_GTE5_ADV_O(NLW_U0_OBUFDS_GTE5_ADV_O_UNCONNECTED[0]),
|
||||
.OBUFDS_GTE5_ADV_OB(NLW_U0_OBUFDS_GTE5_ADV_OB_UNCONNECTED[0]),
|
||||
.OBUFDS_GTE5_ADV_RXRECCLKSEL({1'b0,1'b0}),
|
||||
.OBUFDS_GTE5_CEB(1'b0),
|
||||
.OBUFDS_GTE5_I(1'b0),
|
||||
.OBUFDS_GTE5_O(NLW_U0_OBUFDS_GTE5_O_UNCONNECTED[0]),
|
||||
.OBUFDS_GTE5_OB(NLW_U0_OBUFDS_GTE5_OB_UNCONNECTED[0]),
|
||||
.OBUFDS_GTME5_ADV_CEB(1'b0),
|
||||
.OBUFDS_GTME5_ADV_I({1'b0,1'b0,1'b0,1'b0}),
|
||||
.OBUFDS_GTME5_ADV_O(NLW_U0_OBUFDS_GTME5_ADV_O_UNCONNECTED[0]),
|
||||
.OBUFDS_GTME5_ADV_OB(NLW_U0_OBUFDS_GTME5_ADV_OB_UNCONNECTED[0]),
|
||||
.OBUFDS_GTME5_ADV_RXRECCLKSEL({1'b0,1'b0}),
|
||||
.OBUFDS_GTME5_CEB(1'b0),
|
||||
.OBUFDS_GTME5_I(1'b0),
|
||||
.OBUFDS_GTME5_O(NLW_U0_OBUFDS_GTME5_O_UNCONNECTED[0]),
|
||||
.OBUFDS_GTME5_OB(NLW_U0_OBUFDS_GTME5_OB_UNCONNECTED[0]),
|
||||
.OBUFDS_GTM_ADV_CEB(1'b0),
|
||||
.OBUFDS_GTM_ADV_I({1'b0,1'b0,1'b0,1'b0}),
|
||||
.OBUFDS_GTM_ADV_O(NLW_U0_OBUFDS_GTM_ADV_O_UNCONNECTED[0]),
|
||||
.OBUFDS_GTM_ADV_OB(NLW_U0_OBUFDS_GTM_ADV_OB_UNCONNECTED[0]),
|
||||
.OBUFDS_GTM_CEB(1'b0),
|
||||
.OBUFDS_GTM_I(1'b0),
|
||||
.OBUFDS_GTM_O(NLW_U0_OBUFDS_GTM_O_UNCONNECTED[0]),
|
||||
.OBUFDS_GTM_OB(NLW_U0_OBUFDS_GTM_OB_UNCONNECTED[0]),
|
||||
.OBUF_DS_N(NLW_U0_OBUF_DS_N_UNCONNECTED[0]),
|
||||
.OBUF_DS_P(NLW_U0_OBUF_DS_P_UNCONNECTED[0]),
|
||||
.OBUF_IN(1'b0),
|
||||
.RXRECCLK_SEL_GTE3_ADV({1'b0,1'b0}),
|
||||
.RXRECCLK_SEL_GTE4_ADV({1'b0,1'b0}));
|
||||
endmodule
|
||||
|
||||
(* C_BUFGCE_DIV = "1" *) (* C_BUFG_GT_SYNC = "0" *) (* C_BUF_TYPE = "ibufdsgte2" *)
|
||||
(* C_MODE = "PERFORMANCE" *) (* C_OBUFDS_GTE5_ADV = "2'b00" *) (* C_REFCLK_ICNTL_TX = "5'b00000" *)
|
||||
(* C_SIM_DEVICE = "VERSAL_AI_CORE_ES1" *) (* C_SIZE = "1" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_util_ds_buf
|
||||
(IBUF_DS_P,
|
||||
IBUF_DS_N,
|
||||
IBUF_OUT,
|
||||
IBUF_DS_ODIV2,
|
||||
IBUF_DS_CEB,
|
||||
OBUF_IN,
|
||||
OBUF_DS_P,
|
||||
OBUF_DS_N,
|
||||
IOBUF_DS_P,
|
||||
IOBUF_DS_N,
|
||||
IOBUF_IO_T,
|
||||
IOBUF_IO_I,
|
||||
IOBUF_IO_O,
|
||||
IOBUF_IO_IO,
|
||||
BUFG_I,
|
||||
BUFG_O,
|
||||
BUFGCE_I,
|
||||
BUFGCE_CE,
|
||||
BUFGCE_O,
|
||||
BUFGCE_CLR,
|
||||
BUFH_I,
|
||||
BUFH_O,
|
||||
BUFHCE_I,
|
||||
BUFHCE_CE,
|
||||
BUFHCE_O,
|
||||
BUFG_FABRIC_I,
|
||||
BUFG_FABRIC_O,
|
||||
OBUFDS_GTE5_CEB,
|
||||
OBUFDS_GTE5_I,
|
||||
OBUFDS_GTE5_O,
|
||||
OBUFDS_GTE5_OB,
|
||||
OBUFDS_GTE5_ADV_CEB,
|
||||
OBUFDS_GTE5_ADV_I,
|
||||
OBUFDS_GTE5_ADV_O,
|
||||
OBUFDS_GTE5_ADV_OB,
|
||||
OBUFDS_GTE5_ADV_RXRECCLKSEL,
|
||||
OBUFDS_GTE3_CEB,
|
||||
OBUFDS_GTE3_I,
|
||||
OBUFDS_GTE3_O,
|
||||
OBUFDS_GTE3_OB,
|
||||
OBUFDS_GTE3_ADV_CEB,
|
||||
OBUFDS_GTE3_ADV_I,
|
||||
OBUFDS_GTE3_ADV_O,
|
||||
OBUFDS_GTE3_ADV_OB,
|
||||
RXRECCLK_SEL_GTE3_ADV,
|
||||
OBUFDS_GTE4_CEB,
|
||||
OBUFDS_GTE4_I,
|
||||
OBUFDS_GTE4_O,
|
||||
OBUFDS_GTE4_OB,
|
||||
OBUFDS_GTE4_ADV_CEB,
|
||||
OBUFDS_GTE4_ADV_I,
|
||||
OBUFDS_GTE4_ADV_O,
|
||||
OBUFDS_GTE4_ADV_OB,
|
||||
RXRECCLK_SEL_GTE4_ADV,
|
||||
IBUFDS_GTM_O,
|
||||
IBUFDS_GTM_ODIV2,
|
||||
IBUFDS_GTM_CEB,
|
||||
IBUFDS_GTM_I,
|
||||
IBUFDS_GTM_IB,
|
||||
OBUFDS_GTM_O,
|
||||
OBUFDS_GTM_OB,
|
||||
OBUFDS_GTM_CEB,
|
||||
OBUFDS_GTM_I,
|
||||
OBUFDS_GTM_ADV_CEB,
|
||||
OBUFDS_GTM_ADV_I,
|
||||
OBUFDS_GTM_ADV_O,
|
||||
OBUFDS_GTM_ADV_OB,
|
||||
IBUFDS_GTME5_O,
|
||||
IBUFDS_GTME5_ODIV2,
|
||||
IBUFDS_GTME5_CEB,
|
||||
IBUFDS_GTME5_I,
|
||||
IBUFDS_GTME5_IB,
|
||||
OBUFDS_GTME5_CEB,
|
||||
OBUFDS_GTME5_I,
|
||||
OBUFDS_GTME5_O,
|
||||
OBUFDS_GTME5_OB,
|
||||
OBUFDS_GTME5_ADV_CEB,
|
||||
OBUFDS_GTME5_ADV_I,
|
||||
OBUFDS_GTME5_ADV_O,
|
||||
OBUFDS_GTME5_ADV_OB,
|
||||
OBUFDS_GTME5_ADV_RXRECCLKSEL,
|
||||
BUFG_GT_I,
|
||||
BUFG_GT_CE,
|
||||
BUFG_GT_CEMASK,
|
||||
BUFG_GT_CLR,
|
||||
BUFG_GT_CLRMASK,
|
||||
BUFG_GT_DIV,
|
||||
BUFG_GT_O,
|
||||
BUFG_PS_I,
|
||||
BUFG_PS_O,
|
||||
MBUFG_GT_I,
|
||||
MBUFG_GT_CE,
|
||||
MBUFG_GT_CEMASK,
|
||||
MBUFG_GT_CLR,
|
||||
MBUFG_GT_CLRB_LEAF,
|
||||
MBUFG_GT_CLRMASK,
|
||||
MBUFG_GT_DIV,
|
||||
MBUFG_GT_O1,
|
||||
MBUFG_GT_O2,
|
||||
MBUFG_GT_O3,
|
||||
MBUFG_GT_O4,
|
||||
MBUFG_PS_I,
|
||||
MBUFG_PS_CLRB_LEAF,
|
||||
MBUFG_PS_O1,
|
||||
MBUFG_PS_O2,
|
||||
MBUFG_PS_O3,
|
||||
MBUFG_PS_O4);
|
||||
input [0:0]IBUF_DS_P;
|
||||
input [0:0]IBUF_DS_N;
|
||||
output [0:0]IBUF_OUT;
|
||||
output [0:0]IBUF_DS_ODIV2;
|
||||
input [0:0]IBUF_DS_CEB;
|
||||
input [0:0]OBUF_IN;
|
||||
output [0:0]OBUF_DS_P;
|
||||
output [0:0]OBUF_DS_N;
|
||||
inout [0:0]IOBUF_DS_P;
|
||||
inout [0:0]IOBUF_DS_N;
|
||||
input [0:0]IOBUF_IO_T;
|
||||
input [0:0]IOBUF_IO_I;
|
||||
output [0:0]IOBUF_IO_O;
|
||||
inout [0:0]IOBUF_IO_IO;
|
||||
input [0:0]BUFG_I;
|
||||
output [0:0]BUFG_O;
|
||||
input [0:0]BUFGCE_I;
|
||||
input [0:0]BUFGCE_CE;
|
||||
output [0:0]BUFGCE_O;
|
||||
input [0:0]BUFGCE_CLR;
|
||||
input [0:0]BUFH_I;
|
||||
output [0:0]BUFH_O;
|
||||
input [0:0]BUFHCE_I;
|
||||
input [0:0]BUFHCE_CE;
|
||||
output [0:0]BUFHCE_O;
|
||||
input [0:0]BUFG_FABRIC_I;
|
||||
output [0:0]BUFG_FABRIC_O;
|
||||
input [0:0]OBUFDS_GTE5_CEB;
|
||||
input [0:0]OBUFDS_GTE5_I;
|
||||
output [0:0]OBUFDS_GTE5_O;
|
||||
output [0:0]OBUFDS_GTE5_OB;
|
||||
input [0:0]OBUFDS_GTE5_ADV_CEB;
|
||||
input [3:0]OBUFDS_GTE5_ADV_I;
|
||||
output [0:0]OBUFDS_GTE5_ADV_O;
|
||||
output [0:0]OBUFDS_GTE5_ADV_OB;
|
||||
input [1:0]OBUFDS_GTE5_ADV_RXRECCLKSEL;
|
||||
input [0:0]OBUFDS_GTE3_CEB;
|
||||
input [0:0]OBUFDS_GTE3_I;
|
||||
output [0:0]OBUFDS_GTE3_O;
|
||||
output [0:0]OBUFDS_GTE3_OB;
|
||||
input [0:0]OBUFDS_GTE3_ADV_CEB;
|
||||
input [3:0]OBUFDS_GTE3_ADV_I;
|
||||
output [0:0]OBUFDS_GTE3_ADV_O;
|
||||
output [0:0]OBUFDS_GTE3_ADV_OB;
|
||||
input [1:0]RXRECCLK_SEL_GTE3_ADV;
|
||||
input [0:0]OBUFDS_GTE4_CEB;
|
||||
input [0:0]OBUFDS_GTE4_I;
|
||||
output [0:0]OBUFDS_GTE4_O;
|
||||
output [0:0]OBUFDS_GTE4_OB;
|
||||
input [0:0]OBUFDS_GTE4_ADV_CEB;
|
||||
input [3:0]OBUFDS_GTE4_ADV_I;
|
||||
output [0:0]OBUFDS_GTE4_ADV_O;
|
||||
output [0:0]OBUFDS_GTE4_ADV_OB;
|
||||
input [1:0]RXRECCLK_SEL_GTE4_ADV;
|
||||
output [0:0]IBUFDS_GTM_O;
|
||||
output [0:0]IBUFDS_GTM_ODIV2;
|
||||
input [0:0]IBUFDS_GTM_CEB;
|
||||
input [0:0]IBUFDS_GTM_I;
|
||||
input [0:0]IBUFDS_GTM_IB;
|
||||
output [0:0]OBUFDS_GTM_O;
|
||||
output [0:0]OBUFDS_GTM_OB;
|
||||
input [0:0]OBUFDS_GTM_CEB;
|
||||
input [0:0]OBUFDS_GTM_I;
|
||||
input [0:0]OBUFDS_GTM_ADV_CEB;
|
||||
input [3:0]OBUFDS_GTM_ADV_I;
|
||||
output [0:0]OBUFDS_GTM_ADV_O;
|
||||
output [0:0]OBUFDS_GTM_ADV_OB;
|
||||
output [0:0]IBUFDS_GTME5_O;
|
||||
output [0:0]IBUFDS_GTME5_ODIV2;
|
||||
input [0:0]IBUFDS_GTME5_CEB;
|
||||
input [0:0]IBUFDS_GTME5_I;
|
||||
input [0:0]IBUFDS_GTME5_IB;
|
||||
input [0:0]OBUFDS_GTME5_CEB;
|
||||
input [0:0]OBUFDS_GTME5_I;
|
||||
output [0:0]OBUFDS_GTME5_O;
|
||||
output [0:0]OBUFDS_GTME5_OB;
|
||||
input [0:0]OBUFDS_GTME5_ADV_CEB;
|
||||
input [3:0]OBUFDS_GTME5_ADV_I;
|
||||
output [0:0]OBUFDS_GTME5_ADV_O;
|
||||
output [0:0]OBUFDS_GTME5_ADV_OB;
|
||||
input [1:0]OBUFDS_GTME5_ADV_RXRECCLKSEL;
|
||||
input [0:0]BUFG_GT_I;
|
||||
input [0:0]BUFG_GT_CE;
|
||||
input [0:0]BUFG_GT_CEMASK;
|
||||
input [0:0]BUFG_GT_CLR;
|
||||
input [0:0]BUFG_GT_CLRMASK;
|
||||
input [2:0]BUFG_GT_DIV;
|
||||
output [0:0]BUFG_GT_O;
|
||||
input [0:0]BUFG_PS_I;
|
||||
output [0:0]BUFG_PS_O;
|
||||
input [0:0]MBUFG_GT_I;
|
||||
input [0:0]MBUFG_GT_CE;
|
||||
input [0:0]MBUFG_GT_CEMASK;
|
||||
input [0:0]MBUFG_GT_CLR;
|
||||
input [0:0]MBUFG_GT_CLRB_LEAF;
|
||||
input [0:0]MBUFG_GT_CLRMASK;
|
||||
input [2:0]MBUFG_GT_DIV;
|
||||
output [0:0]MBUFG_GT_O1;
|
||||
output [0:0]MBUFG_GT_O2;
|
||||
output [0:0]MBUFG_GT_O3;
|
||||
output [0:0]MBUFG_GT_O4;
|
||||
input [0:0]MBUFG_PS_I;
|
||||
input [0:0]MBUFG_PS_CLRB_LEAF;
|
||||
output [0:0]MBUFG_PS_O1;
|
||||
output [0:0]MBUFG_PS_O2;
|
||||
output [0:0]MBUFG_PS_O3;
|
||||
output [0:0]MBUFG_PS_O4;
|
||||
|
||||
wire \<const0> ;
|
||||
wire [0:0]IBUF_DS_N;
|
||||
wire [0:0]IBUF_DS_ODIV2;
|
||||
wire [0:0]IBUF_DS_P;
|
||||
wire [0:0]IBUF_OUT;
|
||||
wire \USE_IBUFDS_GTE2.IBUF_OUT_N ;
|
||||
wire \USE_IBUFDS_GTE2.IBUF_OUT_P ;
|
||||
|
||||
assign BUFGCE_O[0] = IOBUF_DS_P[0];
|
||||
assign BUFG_FABRIC_O[0] = IOBUF_DS_P[0];
|
||||
assign BUFG_GT_O[0] = IOBUF_DS_P[0];
|
||||
assign BUFG_O[0] = IOBUF_DS_P[0];
|
||||
assign BUFG_PS_O[0] = IOBUF_DS_P[0];
|
||||
assign BUFHCE_O[0] = IOBUF_DS_P[0];
|
||||
assign BUFH_O[0] = IOBUF_DS_P[0];
|
||||
assign IBUFDS_GTME5_O[0] = IOBUF_DS_P[0];
|
||||
assign IBUFDS_GTME5_ODIV2[0] = IOBUF_DS_P[0];
|
||||
assign IBUFDS_GTM_O[0] = IOBUF_DS_P[0];
|
||||
assign IBUFDS_GTM_ODIV2[0] = IOBUF_DS_P[0];
|
||||
assign IOBUF_IO_O[0] = IOBUF_DS_P[0];
|
||||
assign MBUFG_GT_O1[0] = IOBUF_DS_P[0];
|
||||
assign MBUFG_GT_O2[0] = IOBUF_DS_P[0];
|
||||
assign MBUFG_GT_O3[0] = IOBUF_DS_P[0];
|
||||
assign MBUFG_GT_O4[0] = IOBUF_DS_P[0];
|
||||
assign MBUFG_PS_O1[0] = IOBUF_DS_P[0];
|
||||
assign MBUFG_PS_O2[0] = IOBUF_DS_P[0];
|
||||
assign MBUFG_PS_O3[0] = IOBUF_DS_P[0];
|
||||
assign MBUFG_PS_O4[0] = IOBUF_DS_P[0];
|
||||
assign OBUFDS_GTE3_ADV_O[0] = IOBUF_DS_P[0];
|
||||
assign OBUFDS_GTE3_ADV_OB[0] = IOBUF_DS_P[0];
|
||||
assign OBUFDS_GTE3_O[0] = IOBUF_DS_P[0];
|
||||
assign OBUFDS_GTE3_OB[0] = IOBUF_DS_P[0];
|
||||
assign OBUFDS_GTE4_ADV_O[0] = IOBUF_DS_P[0];
|
||||
assign OBUFDS_GTE4_ADV_OB[0] = IOBUF_DS_P[0];
|
||||
assign OBUFDS_GTE4_O[0] = IOBUF_DS_P[0];
|
||||
assign OBUFDS_GTE4_OB[0] = IOBUF_DS_P[0];
|
||||
assign OBUFDS_GTE5_ADV_O[0] = IOBUF_DS_P[0];
|
||||
assign OBUFDS_GTE5_ADV_OB[0] = IOBUF_DS_P[0];
|
||||
assign OBUFDS_GTE5_O[0] = IOBUF_DS_P[0];
|
||||
assign OBUFDS_GTE5_OB[0] = IOBUF_DS_P[0];
|
||||
assign OBUFDS_GTME5_ADV_O[0] = IOBUF_DS_P[0];
|
||||
assign OBUFDS_GTME5_ADV_OB[0] = IOBUF_DS_P[0];
|
||||
assign OBUFDS_GTME5_O[0] = IOBUF_DS_P[0];
|
||||
assign OBUFDS_GTME5_OB[0] = IOBUF_DS_P[0];
|
||||
assign OBUFDS_GTM_ADV_O[0] = IOBUF_DS_P[0];
|
||||
assign OBUFDS_GTM_ADV_OB[0] = IOBUF_DS_P[0];
|
||||
assign OBUFDS_GTM_O[0] = IOBUF_DS_P[0];
|
||||
assign OBUFDS_GTM_OB[0] = IOBUF_DS_P[0];
|
||||
assign OBUF_DS_N[0] = IOBUF_DS_P[0];
|
||||
assign OBUF_DS_P[0] = IOBUF_DS_P[0];
|
||||
xVIA IOBUF_DS_N_0via (IOBUF_DS_N[0], IOBUF_DS_P[0]);
|
||||
GND GND
|
||||
(.G(IOBUF_DS_P[0]));
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
IBUFDS_GTE2 #(
|
||||
.CLKCM_CFG("TRUE"),
|
||||
.CLKRCV_TRST("TRUE"),
|
||||
.CLKSWING_CFG(2'b11))
|
||||
\USE_IBUFDS_GTE2.GEN_IBUFDS_GTE2[0].IBUFDS_GTE2_I
|
||||
(.CEB(IOBUF_DS_P[0]),
|
||||
.I(\USE_IBUFDS_GTE2.IBUF_OUT_P ),
|
||||
.IB(\USE_IBUFDS_GTE2.IBUF_OUT_N ),
|
||||
.O(IBUF_OUT),
|
||||
.ODIV2(IBUF_DS_ODIV2));
|
||||
(* CAPACITANCE = "DONT_CARE" *)
|
||||
(* IBUF_DELAY_VALUE = "0" *)
|
||||
(* IFD_DELAY_VALUE = "AUTO" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
IBUF #(
|
||||
.IOSTANDARD("DEFAULT"))
|
||||
\USE_IBUFDS_GTE2.GEN_IBUFDS_GTE2[0].IBUF_N_I
|
||||
(.I(IBUF_DS_N),
|
||||
.O(\USE_IBUFDS_GTE2.IBUF_OUT_N ));
|
||||
(* CAPACITANCE = "DONT_CARE" *)
|
||||
(* IBUF_DELAY_VALUE = "0" *)
|
||||
(* IFD_DELAY_VALUE = "AUTO" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
IBUF #(
|
||||
.IOSTANDARD("DEFAULT"))
|
||||
\USE_IBUFDS_GTE2.GEN_IBUFDS_GTE2[0].IBUF_P_I
|
||||
(.I(IBUF_DS_P),
|
||||
.O(\USE_IBUFDS_GTE2.IBUF_OUT_P ));
|
||||
endmodule
|
||||
module xVIA(.a(w),.b(w));
|
||||
inout w;
|
||||
endmodule
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
parameter GRES_WIDTH = 10000;
|
||||
parameter GRES_START = 10000;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
wire GRESTORE;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
reg GRESTORE_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
assign (strong1, weak0) GRESTORE = GRESTORE_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GRESTORE_int = 1'b0;
|
||||
#(GRES_START);
|
||||
GRESTORE_int = 1'b1;
|
||||
#(GRES_WIDTH);
|
||||
GRESTORE_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
|
|
@ -0,0 +1,444 @@
|
|||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
|
||||
-- Date : Tue Jun 24 11:58:34 2025
|
||||
-- Host : media-wawa running 64-bit NixOS 25.05 (Warbler)
|
||||
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ top_util_ds_buf_0_sim_netlist.vhdl
|
||||
-- Design : top_util_ds_buf_0
|
||||
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
|
||||
-- synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
-- Device : xc7a100tlfgg484-2L
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_util_ds_buf is
|
||||
port (
|
||||
IBUF_DS_P : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
IBUF_DS_N : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
IBUF_OUT : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
IBUF_DS_ODIV2 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
IBUF_DS_CEB : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUF_IN : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUF_DS_P : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUF_DS_N : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
IOBUF_DS_P : inout STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
IOBUF_DS_N : inout STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
IOBUF_IO_T : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
IOBUF_IO_I : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
IOBUF_IO_O : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
IOBUF_IO_IO : inout STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
BUFG_I : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
BUFG_O : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
BUFGCE_I : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
BUFGCE_CE : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
BUFGCE_O : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
BUFGCE_CLR : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
BUFH_I : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
BUFH_O : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
BUFHCE_I : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
BUFHCE_CE : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
BUFHCE_O : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
BUFG_FABRIC_I : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
BUFG_FABRIC_O : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTE5_CEB : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTE5_I : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTE5_O : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTE5_OB : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTE5_ADV_CEB : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTE5_ADV_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
OBUFDS_GTE5_ADV_O : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTE5_ADV_OB : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTE5_ADV_RXRECCLKSEL : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
OBUFDS_GTE3_CEB : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTE3_I : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTE3_O : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTE3_OB : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTE3_ADV_CEB : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTE3_ADV_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
OBUFDS_GTE3_ADV_O : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTE3_ADV_OB : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
RXRECCLK_SEL_GTE3_ADV : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
OBUFDS_GTE4_CEB : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTE4_I : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTE4_O : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTE4_OB : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTE4_ADV_CEB : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTE4_ADV_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
OBUFDS_GTE4_ADV_O : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTE4_ADV_OB : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
RXRECCLK_SEL_GTE4_ADV : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
IBUFDS_GTM_O : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
IBUFDS_GTM_ODIV2 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
IBUFDS_GTM_CEB : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
IBUFDS_GTM_I : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
IBUFDS_GTM_IB : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTM_O : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTM_OB : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTM_CEB : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTM_I : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTM_ADV_CEB : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTM_ADV_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
OBUFDS_GTM_ADV_O : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTM_ADV_OB : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
IBUFDS_GTME5_O : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
IBUFDS_GTME5_ODIV2 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
IBUFDS_GTME5_CEB : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
IBUFDS_GTME5_I : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
IBUFDS_GTME5_IB : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTME5_CEB : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTME5_I : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTME5_O : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTME5_OB : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTME5_ADV_CEB : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTME5_ADV_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
OBUFDS_GTME5_ADV_O : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTME5_ADV_OB : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTME5_ADV_RXRECCLKSEL : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
BUFG_GT_I : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
BUFG_GT_CE : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
BUFG_GT_CEMASK : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
BUFG_GT_CLR : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
BUFG_GT_CLRMASK : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
BUFG_GT_DIV : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
BUFG_GT_O : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
BUFG_PS_I : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
BUFG_PS_O : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
MBUFG_GT_I : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
MBUFG_GT_CE : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
MBUFG_GT_CEMASK : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
MBUFG_GT_CLR : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
MBUFG_GT_CLRB_LEAF : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
MBUFG_GT_CLRMASK : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
MBUFG_GT_DIV : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
MBUFG_GT_O1 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
MBUFG_GT_O2 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
MBUFG_GT_O3 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
MBUFG_GT_O4 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
MBUFG_PS_I : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
MBUFG_PS_CLRB_LEAF : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
MBUFG_PS_O1 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
MBUFG_PS_O2 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
MBUFG_PS_O3 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
MBUFG_PS_O4 : out STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
);
|
||||
attribute C_BUFGCE_DIV : integer;
|
||||
attribute C_BUFGCE_DIV of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_util_ds_buf : entity is 1;
|
||||
attribute C_BUFG_GT_SYNC : integer;
|
||||
attribute C_BUFG_GT_SYNC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_util_ds_buf : entity is 0;
|
||||
attribute C_BUF_TYPE : string;
|
||||
attribute C_BUF_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_util_ds_buf : entity is "ibufdsgte2";
|
||||
attribute C_MODE : string;
|
||||
attribute C_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_util_ds_buf : entity is "PERFORMANCE";
|
||||
attribute C_OBUFDS_GTE5_ADV : string;
|
||||
attribute C_OBUFDS_GTE5_ADV of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_util_ds_buf : entity is "2'b00";
|
||||
attribute C_REFCLK_ICNTL_TX : string;
|
||||
attribute C_REFCLK_ICNTL_TX of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_util_ds_buf : entity is "5'b00000";
|
||||
attribute C_SIM_DEVICE : string;
|
||||
attribute C_SIM_DEVICE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_util_ds_buf : entity is "VERSAL_AI_CORE_ES1";
|
||||
attribute C_SIZE : integer;
|
||||
attribute C_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_util_ds_buf : entity is 1;
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_util_ds_buf;
|
||||
|
||||
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_util_ds_buf is
|
||||
signal \<const0>\ : STD_LOGIC;
|
||||
signal \USE_IBUFDS_GTE2.IBUF_OUT_N\ : STD_LOGIC;
|
||||
signal \USE_IBUFDS_GTE2.IBUF_OUT_P\ : STD_LOGIC;
|
||||
attribute box_type : string;
|
||||
attribute box_type of \USE_IBUFDS_GTE2.GEN_IBUFDS_GTE2[0].IBUFDS_GTE2_I\ : label is "PRIMITIVE";
|
||||
attribute CAPACITANCE : string;
|
||||
attribute CAPACITANCE of \USE_IBUFDS_GTE2.GEN_IBUFDS_GTE2[0].IBUF_N_I\ : label is "DONT_CARE";
|
||||
attribute IBUF_DELAY_VALUE : string;
|
||||
attribute IBUF_DELAY_VALUE of \USE_IBUFDS_GTE2.GEN_IBUFDS_GTE2[0].IBUF_N_I\ : label is "0";
|
||||
attribute IFD_DELAY_VALUE : string;
|
||||
attribute IFD_DELAY_VALUE of \USE_IBUFDS_GTE2.GEN_IBUFDS_GTE2[0].IBUF_N_I\ : label is "AUTO";
|
||||
attribute box_type of \USE_IBUFDS_GTE2.GEN_IBUFDS_GTE2[0].IBUF_N_I\ : label is "PRIMITIVE";
|
||||
attribute CAPACITANCE of \USE_IBUFDS_GTE2.GEN_IBUFDS_GTE2[0].IBUF_P_I\ : label is "DONT_CARE";
|
||||
attribute IBUF_DELAY_VALUE of \USE_IBUFDS_GTE2.GEN_IBUFDS_GTE2[0].IBUF_P_I\ : label is "0";
|
||||
attribute IFD_DELAY_VALUE of \USE_IBUFDS_GTE2.GEN_IBUFDS_GTE2[0].IBUF_P_I\ : label is "AUTO";
|
||||
attribute box_type of \USE_IBUFDS_GTE2.GEN_IBUFDS_GTE2[0].IBUF_P_I\ : label is "PRIMITIVE";
|
||||
begin
|
||||
BUFGCE_O(0) <= \<const0>\;
|
||||
BUFG_FABRIC_O(0) <= \<const0>\;
|
||||
BUFG_GT_O(0) <= \<const0>\;
|
||||
BUFG_O(0) <= \<const0>\;
|
||||
BUFG_PS_O(0) <= \<const0>\;
|
||||
BUFHCE_O(0) <= \<const0>\;
|
||||
BUFH_O(0) <= \<const0>\;
|
||||
IBUFDS_GTME5_O(0) <= \<const0>\;
|
||||
IBUFDS_GTME5_ODIV2(0) <= \<const0>\;
|
||||
IBUFDS_GTM_O(0) <= \<const0>\;
|
||||
IBUFDS_GTM_ODIV2(0) <= \<const0>\;
|
||||
IOBUF_DS_N(0) <= \<const0>\;
|
||||
IOBUF_DS_P(0) <= \<const0>\;
|
||||
IOBUF_IO_O(0) <= \<const0>\;
|
||||
MBUFG_GT_O1(0) <= \<const0>\;
|
||||
MBUFG_GT_O2(0) <= \<const0>\;
|
||||
MBUFG_GT_O3(0) <= \<const0>\;
|
||||
MBUFG_GT_O4(0) <= \<const0>\;
|
||||
MBUFG_PS_O1(0) <= \<const0>\;
|
||||
MBUFG_PS_O2(0) <= \<const0>\;
|
||||
MBUFG_PS_O3(0) <= \<const0>\;
|
||||
MBUFG_PS_O4(0) <= \<const0>\;
|
||||
OBUFDS_GTE3_ADV_O(0) <= \<const0>\;
|
||||
OBUFDS_GTE3_ADV_OB(0) <= \<const0>\;
|
||||
OBUFDS_GTE3_O(0) <= \<const0>\;
|
||||
OBUFDS_GTE3_OB(0) <= \<const0>\;
|
||||
OBUFDS_GTE4_ADV_O(0) <= \<const0>\;
|
||||
OBUFDS_GTE4_ADV_OB(0) <= \<const0>\;
|
||||
OBUFDS_GTE4_O(0) <= \<const0>\;
|
||||
OBUFDS_GTE4_OB(0) <= \<const0>\;
|
||||
OBUFDS_GTE5_ADV_O(0) <= \<const0>\;
|
||||
OBUFDS_GTE5_ADV_OB(0) <= \<const0>\;
|
||||
OBUFDS_GTE5_O(0) <= \<const0>\;
|
||||
OBUFDS_GTE5_OB(0) <= \<const0>\;
|
||||
OBUFDS_GTME5_ADV_O(0) <= \<const0>\;
|
||||
OBUFDS_GTME5_ADV_OB(0) <= \<const0>\;
|
||||
OBUFDS_GTME5_O(0) <= \<const0>\;
|
||||
OBUFDS_GTME5_OB(0) <= \<const0>\;
|
||||
OBUFDS_GTM_ADV_O(0) <= \<const0>\;
|
||||
OBUFDS_GTM_ADV_OB(0) <= \<const0>\;
|
||||
OBUFDS_GTM_O(0) <= \<const0>\;
|
||||
OBUFDS_GTM_OB(0) <= \<const0>\;
|
||||
OBUF_DS_N(0) <= \<const0>\;
|
||||
OBUF_DS_P(0) <= \<const0>\;
|
||||
GND: unisim.vcomponents.GND
|
||||
port map (
|
||||
G => \<const0>\
|
||||
);
|
||||
\USE_IBUFDS_GTE2.GEN_IBUFDS_GTE2[0].IBUFDS_GTE2_I\: unisim.vcomponents.IBUFDS_GTE2
|
||||
generic map(
|
||||
CLKCM_CFG => true,
|
||||
CLKRCV_TRST => true,
|
||||
CLKSWING_CFG => B"11"
|
||||
)
|
||||
port map (
|
||||
CEB => \<const0>\,
|
||||
I => \USE_IBUFDS_GTE2.IBUF_OUT_P\,
|
||||
IB => \USE_IBUFDS_GTE2.IBUF_OUT_N\,
|
||||
O => IBUF_OUT(0),
|
||||
ODIV2 => IBUF_DS_ODIV2(0)
|
||||
);
|
||||
\USE_IBUFDS_GTE2.GEN_IBUFDS_GTE2[0].IBUF_N_I\: unisim.vcomponents.IBUF
|
||||
generic map(
|
||||
IOSTANDARD => "DEFAULT"
|
||||
)
|
||||
port map (
|
||||
I => IBUF_DS_N(0),
|
||||
O => \USE_IBUFDS_GTE2.IBUF_OUT_N\
|
||||
);
|
||||
\USE_IBUFDS_GTE2.GEN_IBUFDS_GTE2[0].IBUF_P_I\: unisim.vcomponents.IBUF
|
||||
generic map(
|
||||
IOSTANDARD => "DEFAULT"
|
||||
)
|
||||
port map (
|
||||
I => IBUF_DS_P(0),
|
||||
O => \USE_IBUFDS_GTE2.IBUF_OUT_P\
|
||||
);
|
||||
end STRUCTURE;
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
port (
|
||||
IBUF_DS_P : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
IBUF_DS_N : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
IBUF_OUT : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
IBUF_DS_ODIV2 : out STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
);
|
||||
attribute NotValidForBitStream : boolean;
|
||||
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
|
||||
attribute CHECK_LICENSE_TYPE : string;
|
||||
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "top_util_ds_buf_0,util_ds_buf,{}";
|
||||
attribute downgradeipidentifiedwarnings : string;
|
||||
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "util_ds_buf,Vivado 2022.1";
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
signal NLW_U0_BUFGCE_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_BUFG_FABRIC_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_BUFG_GT_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_BUFG_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_BUFG_PS_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_BUFHCE_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_BUFH_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_IBUFDS_GTME5_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_IBUFDS_GTME5_ODIV2_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_IBUFDS_GTM_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_IBUFDS_GTM_ODIV2_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_IOBUF_DS_N_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_IOBUF_DS_P_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_IOBUF_IO_IO_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_IOBUF_IO_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_MBUFG_GT_O1_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_MBUFG_GT_O2_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_MBUFG_GT_O3_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_MBUFG_GT_O4_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_MBUFG_PS_O1_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_MBUFG_PS_O2_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_MBUFG_PS_O3_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_MBUFG_PS_O4_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_OBUFDS_GTE3_ADV_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_OBUFDS_GTE3_ADV_OB_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_OBUFDS_GTE3_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_OBUFDS_GTE3_OB_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_OBUFDS_GTE4_ADV_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_OBUFDS_GTE4_ADV_OB_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_OBUFDS_GTE4_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_OBUFDS_GTE4_OB_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_OBUFDS_GTE5_ADV_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_OBUFDS_GTE5_ADV_OB_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_OBUFDS_GTE5_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_OBUFDS_GTE5_OB_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_OBUFDS_GTME5_ADV_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_OBUFDS_GTME5_ADV_OB_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_OBUFDS_GTME5_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_OBUFDS_GTME5_OB_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_OBUFDS_GTM_ADV_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_OBUFDS_GTM_ADV_OB_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_OBUFDS_GTM_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_OBUFDS_GTM_OB_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_OBUF_DS_N_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_OBUF_DS_P_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
attribute C_BUFGCE_DIV : integer;
|
||||
attribute C_BUFGCE_DIV of U0 : label is 1;
|
||||
attribute C_BUFG_GT_SYNC : integer;
|
||||
attribute C_BUFG_GT_SYNC of U0 : label is 0;
|
||||
attribute C_BUF_TYPE : string;
|
||||
attribute C_BUF_TYPE of U0 : label is "ibufdsgte2";
|
||||
attribute C_MODE : string;
|
||||
attribute C_MODE of U0 : label is "PERFORMANCE";
|
||||
attribute C_OBUFDS_GTE5_ADV : string;
|
||||
attribute C_OBUFDS_GTE5_ADV of U0 : label is "2'b00";
|
||||
attribute C_REFCLK_ICNTL_TX : string;
|
||||
attribute C_REFCLK_ICNTL_TX of U0 : label is "5'b00000";
|
||||
attribute C_SIM_DEVICE : string;
|
||||
attribute C_SIM_DEVICE of U0 : label is "VERSAL_AI_CORE_ES1";
|
||||
attribute C_SIZE : integer;
|
||||
attribute C_SIZE of U0 : label is 1;
|
||||
attribute x_interface_info : string;
|
||||
attribute x_interface_info of IBUF_DS_N : signal is "xilinx.com:interface:diff_clock:1.0 CLK_IN_D CLK_N";
|
||||
attribute x_interface_info of IBUF_DS_ODIV2 : signal is "xilinx.com:signal:clock:1.0 IBUF_DS_ODIV2 CLK";
|
||||
attribute x_interface_parameter : string;
|
||||
attribute x_interface_parameter of IBUF_DS_ODIV2 : signal is "XIL_INTERFACENAME IBUF_DS_ODIV2, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN top_util_ds_buf_0_IBUF_DS_ODIV2, INSERT_VIP 0";
|
||||
attribute x_interface_info of IBUF_DS_P : signal is "xilinx.com:interface:diff_clock:1.0 CLK_IN_D CLK_P";
|
||||
attribute x_interface_parameter of IBUF_DS_P : signal is "XIL_INTERFACENAME CLK_IN_D, BOARD.ASSOCIATED_PARAM DIFF_CLK_IN_BOARD_INTERFACE, CAN_DEBUG false, FREQ_HZ 100000000";
|
||||
attribute x_interface_info of IBUF_OUT : signal is "xilinx.com:signal:clock:1.0 IBUF_OUT CLK";
|
||||
attribute x_interface_parameter of IBUF_OUT : signal is "XIL_INTERFACENAME IBUF_OUT, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN top_util_ds_buf_0_IBUF_OUT, INSERT_VIP 0";
|
||||
begin
|
||||
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_util_ds_buf
|
||||
port map (
|
||||
BUFGCE_CE(0) => '0',
|
||||
BUFGCE_CLR(0) => '0',
|
||||
BUFGCE_I(0) => '0',
|
||||
BUFGCE_O(0) => NLW_U0_BUFGCE_O_UNCONNECTED(0),
|
||||
BUFG_FABRIC_I(0) => '0',
|
||||
BUFG_FABRIC_O(0) => NLW_U0_BUFG_FABRIC_O_UNCONNECTED(0),
|
||||
BUFG_GT_CE(0) => '1',
|
||||
BUFG_GT_CEMASK(0) => '0',
|
||||
BUFG_GT_CLR(0) => '0',
|
||||
BUFG_GT_CLRMASK(0) => '0',
|
||||
BUFG_GT_DIV(2 downto 0) => B"000",
|
||||
BUFG_GT_I(0) => '0',
|
||||
BUFG_GT_O(0) => NLW_U0_BUFG_GT_O_UNCONNECTED(0),
|
||||
BUFG_I(0) => '0',
|
||||
BUFG_O(0) => NLW_U0_BUFG_O_UNCONNECTED(0),
|
||||
BUFG_PS_I(0) => '0',
|
||||
BUFG_PS_O(0) => NLW_U0_BUFG_PS_O_UNCONNECTED(0),
|
||||
BUFHCE_CE(0) => '0',
|
||||
BUFHCE_I(0) => '0',
|
||||
BUFHCE_O(0) => NLW_U0_BUFHCE_O_UNCONNECTED(0),
|
||||
BUFH_I(0) => '0',
|
||||
BUFH_O(0) => NLW_U0_BUFH_O_UNCONNECTED(0),
|
||||
IBUFDS_GTME5_CEB(0) => '0',
|
||||
IBUFDS_GTME5_I(0) => '0',
|
||||
IBUFDS_GTME5_IB(0) => '0',
|
||||
IBUFDS_GTME5_O(0) => NLW_U0_IBUFDS_GTME5_O_UNCONNECTED(0),
|
||||
IBUFDS_GTME5_ODIV2(0) => NLW_U0_IBUFDS_GTME5_ODIV2_UNCONNECTED(0),
|
||||
IBUFDS_GTM_CEB(0) => '0',
|
||||
IBUFDS_GTM_I(0) => '0',
|
||||
IBUFDS_GTM_IB(0) => '0',
|
||||
IBUFDS_GTM_O(0) => NLW_U0_IBUFDS_GTM_O_UNCONNECTED(0),
|
||||
IBUFDS_GTM_ODIV2(0) => NLW_U0_IBUFDS_GTM_ODIV2_UNCONNECTED(0),
|
||||
IBUF_DS_CEB(0) => '0',
|
||||
IBUF_DS_N(0) => IBUF_DS_N(0),
|
||||
IBUF_DS_ODIV2(0) => IBUF_DS_ODIV2(0),
|
||||
IBUF_DS_P(0) => IBUF_DS_P(0),
|
||||
IBUF_OUT(0) => IBUF_OUT(0),
|
||||
IOBUF_DS_N(0) => NLW_U0_IOBUF_DS_N_UNCONNECTED(0),
|
||||
IOBUF_DS_P(0) => NLW_U0_IOBUF_DS_P_UNCONNECTED(0),
|
||||
IOBUF_IO_I(0) => '0',
|
||||
IOBUF_IO_IO(0) => NLW_U0_IOBUF_IO_IO_UNCONNECTED(0),
|
||||
IOBUF_IO_O(0) => NLW_U0_IOBUF_IO_O_UNCONNECTED(0),
|
||||
IOBUF_IO_T(0) => '0',
|
||||
MBUFG_GT_CE(0) => '1',
|
||||
MBUFG_GT_CEMASK(0) => '0',
|
||||
MBUFG_GT_CLR(0) => '0',
|
||||
MBUFG_GT_CLRB_LEAF(0) => '1',
|
||||
MBUFG_GT_CLRMASK(0) => '0',
|
||||
MBUFG_GT_DIV(2 downto 0) => B"000",
|
||||
MBUFG_GT_I(0) => '0',
|
||||
MBUFG_GT_O1(0) => NLW_U0_MBUFG_GT_O1_UNCONNECTED(0),
|
||||
MBUFG_GT_O2(0) => NLW_U0_MBUFG_GT_O2_UNCONNECTED(0),
|
||||
MBUFG_GT_O3(0) => NLW_U0_MBUFG_GT_O3_UNCONNECTED(0),
|
||||
MBUFG_GT_O4(0) => NLW_U0_MBUFG_GT_O4_UNCONNECTED(0),
|
||||
MBUFG_PS_CLRB_LEAF(0) => '1',
|
||||
MBUFG_PS_I(0) => '0',
|
||||
MBUFG_PS_O1(0) => NLW_U0_MBUFG_PS_O1_UNCONNECTED(0),
|
||||
MBUFG_PS_O2(0) => NLW_U0_MBUFG_PS_O2_UNCONNECTED(0),
|
||||
MBUFG_PS_O3(0) => NLW_U0_MBUFG_PS_O3_UNCONNECTED(0),
|
||||
MBUFG_PS_O4(0) => NLW_U0_MBUFG_PS_O4_UNCONNECTED(0),
|
||||
OBUFDS_GTE3_ADV_CEB(0) => '0',
|
||||
OBUFDS_GTE3_ADV_I(3 downto 0) => B"0000",
|
||||
OBUFDS_GTE3_ADV_O(0) => NLW_U0_OBUFDS_GTE3_ADV_O_UNCONNECTED(0),
|
||||
OBUFDS_GTE3_ADV_OB(0) => NLW_U0_OBUFDS_GTE3_ADV_OB_UNCONNECTED(0),
|
||||
OBUFDS_GTE3_CEB(0) => '0',
|
||||
OBUFDS_GTE3_I(0) => '0',
|
||||
OBUFDS_GTE3_O(0) => NLW_U0_OBUFDS_GTE3_O_UNCONNECTED(0),
|
||||
OBUFDS_GTE3_OB(0) => NLW_U0_OBUFDS_GTE3_OB_UNCONNECTED(0),
|
||||
OBUFDS_GTE4_ADV_CEB(0) => '0',
|
||||
OBUFDS_GTE4_ADV_I(3 downto 0) => B"0000",
|
||||
OBUFDS_GTE4_ADV_O(0) => NLW_U0_OBUFDS_GTE4_ADV_O_UNCONNECTED(0),
|
||||
OBUFDS_GTE4_ADV_OB(0) => NLW_U0_OBUFDS_GTE4_ADV_OB_UNCONNECTED(0),
|
||||
OBUFDS_GTE4_CEB(0) => '0',
|
||||
OBUFDS_GTE4_I(0) => '0',
|
||||
OBUFDS_GTE4_O(0) => NLW_U0_OBUFDS_GTE4_O_UNCONNECTED(0),
|
||||
OBUFDS_GTE4_OB(0) => NLW_U0_OBUFDS_GTE4_OB_UNCONNECTED(0),
|
||||
OBUFDS_GTE5_ADV_CEB(0) => '0',
|
||||
OBUFDS_GTE5_ADV_I(3 downto 0) => B"0000",
|
||||
OBUFDS_GTE5_ADV_O(0) => NLW_U0_OBUFDS_GTE5_ADV_O_UNCONNECTED(0),
|
||||
OBUFDS_GTE5_ADV_OB(0) => NLW_U0_OBUFDS_GTE5_ADV_OB_UNCONNECTED(0),
|
||||
OBUFDS_GTE5_ADV_RXRECCLKSEL(1 downto 0) => B"00",
|
||||
OBUFDS_GTE5_CEB(0) => '0',
|
||||
OBUFDS_GTE5_I(0) => '0',
|
||||
OBUFDS_GTE5_O(0) => NLW_U0_OBUFDS_GTE5_O_UNCONNECTED(0),
|
||||
OBUFDS_GTE5_OB(0) => NLW_U0_OBUFDS_GTE5_OB_UNCONNECTED(0),
|
||||
OBUFDS_GTME5_ADV_CEB(0) => '0',
|
||||
OBUFDS_GTME5_ADV_I(3 downto 0) => B"0000",
|
||||
OBUFDS_GTME5_ADV_O(0) => NLW_U0_OBUFDS_GTME5_ADV_O_UNCONNECTED(0),
|
||||
OBUFDS_GTME5_ADV_OB(0) => NLW_U0_OBUFDS_GTME5_ADV_OB_UNCONNECTED(0),
|
||||
OBUFDS_GTME5_ADV_RXRECCLKSEL(1 downto 0) => B"00",
|
||||
OBUFDS_GTME5_CEB(0) => '0',
|
||||
OBUFDS_GTME5_I(0) => '0',
|
||||
OBUFDS_GTME5_O(0) => NLW_U0_OBUFDS_GTME5_O_UNCONNECTED(0),
|
||||
OBUFDS_GTME5_OB(0) => NLW_U0_OBUFDS_GTME5_OB_UNCONNECTED(0),
|
||||
OBUFDS_GTM_ADV_CEB(0) => '0',
|
||||
OBUFDS_GTM_ADV_I(3 downto 0) => B"0000",
|
||||
OBUFDS_GTM_ADV_O(0) => NLW_U0_OBUFDS_GTM_ADV_O_UNCONNECTED(0),
|
||||
OBUFDS_GTM_ADV_OB(0) => NLW_U0_OBUFDS_GTM_ADV_OB_UNCONNECTED(0),
|
||||
OBUFDS_GTM_CEB(0) => '0',
|
||||
OBUFDS_GTM_I(0) => '0',
|
||||
OBUFDS_GTM_O(0) => NLW_U0_OBUFDS_GTM_O_UNCONNECTED(0),
|
||||
OBUFDS_GTM_OB(0) => NLW_U0_OBUFDS_GTM_OB_UNCONNECTED(0),
|
||||
OBUF_DS_N(0) => NLW_U0_OBUF_DS_N_UNCONNECTED(0),
|
||||
OBUF_DS_P(0) => NLW_U0_OBUF_DS_P_UNCONNECTED(0),
|
||||
OBUF_IN(0) => '0',
|
||||
RXRECCLK_SEL_GTE3_ADV(1 downto 0) => B"00",
|
||||
RXRECCLK_SEL_GTE4_ADV(1 downto 0) => B"00"
|
||||
);
|
||||
end STRUCTURE;
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
|
||||
// Date : Tue Jun 24 11:58:34 2025
|
||||
// Host : media-wawa running 64-bit NixOS 25.05 (Warbler)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ top_util_ds_buf_0_stub.v
|
||||
// Design : top_util_ds_buf_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7a100tlfgg484-2L
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "util_ds_buf,Vivado 2022.1" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(IBUF_DS_P, IBUF_DS_N, IBUF_OUT, IBUF_DS_ODIV2)
|
||||
/* synthesis syn_black_box black_box_pad_pin="IBUF_DS_P[0:0],IBUF_DS_N[0:0],IBUF_OUT[0:0],IBUF_DS_ODIV2[0:0]" */;
|
||||
input [0:0]IBUF_DS_P;
|
||||
input [0:0]IBUF_DS_N;
|
||||
output [0:0]IBUF_OUT;
|
||||
output [0:0]IBUF_DS_ODIV2;
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
|
||||
-- Date : Tue Jun 24 11:58:34 2025
|
||||
-- Host : media-wawa running 64-bit NixOS 25.05 (Warbler)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ top_util_ds_buf_0_stub.vhdl
|
||||
-- Design : top_util_ds_buf_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7a100tlfgg484-2L
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
IBUF_DS_P : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
IBUF_DS_N : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
IBUF_OUT : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
IBUF_DS_ODIV2 : out STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "IBUF_DS_P[0:0],IBUF_DS_N[0:0],IBUF_OUT[0:0],IBUF_DS_ODIV2[0:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "util_ds_buf,Vivado 2022.1";
|
||||
begin
|
||||
end;
|
||||
|
|
@ -0,0 +1,112 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>ipcache</spirit:library>
|
||||
<spirit:name>9b0ca356c30d2ee1</spirit:name>
|
||||
<spirit:version>0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>top_axi_smc_0</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="smartconnect" spirit:version="1.0"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.ASSOCIATED_PORT"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_HZ">125000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M00_AXI.ADDR_WIDTH">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M00_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M00_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M00_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M00_AXI.DATA_WIDTH">32</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M00_AXI.HAS_WSTRB">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M00_AXI.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M00_AXI.MAX_BURST_LENGTH">256</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M00_AXI.NUM_READ_OUTSTANDING">32</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M00_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M00_AXI.NUM_WRITE_OUTSTANDING">16</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M00_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M00_AXI.PHASE">0.0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M00_AXI.PROTOCOL">AXI4</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M00_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M00_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M00_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M00_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.ARESETN.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.ARESETN.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.DATA_WIDTH">64</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.FREQ_HZ">125000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_BRESP">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_BURST">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_CACHE">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_LOCK">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_PROT">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_QOS">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_RRESP">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_WSTRB">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.MAX_BURST_LENGTH">256</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.NUM_WRITE_OUTSTANDING">16</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.NUM_WRITE_THREADS">2</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.PHASE">0.0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.PROTOCOL">AXI4</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADVANCED_PROPERTIES">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">top_axi_smc_0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ARESETN">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_CLKS">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_MI">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_SI">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">artix7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7a100tl</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fgg484</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2L</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">E</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEELABORATESCRC">580d1a4f</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">9b0ca356c30d2ee1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESPECIALDATA">top_axi_smc_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCL">$Change: 3513466 $</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCRC">9a15d5e9</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">77</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">18</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2022.1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
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</spirit:componentInstance>
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</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
NumberHits:1
|
||||
Timestamp: Tue Jun 24 12:25:38 UTC 2025
|
||||
Binary file not shown.
41010
hello_world_dma.cache/ip/2022.1/9/b/9b0ca356c30d2ee1/top_axi_smc_0_sim_netlist.v
Executable file
41010
hello_world_dma.cache/ip/2022.1/9/b/9b0ca356c30d2ee1/top_axi_smc_0_sim_netlist.v
Executable file
File diff suppressed because one or more lines are too long
46899
hello_world_dma.cache/ip/2022.1/9/b/9b0ca356c30d2ee1/top_axi_smc_0_sim_netlist.vhdl
Executable file
46899
hello_world_dma.cache/ip/2022.1/9/b/9b0ca356c30d2ee1/top_axi_smc_0_sim_netlist.vhdl
Executable file
File diff suppressed because it is too large
Load diff
105
hello_world_dma.cache/ip/2022.1/9/b/9b0ca356c30d2ee1/top_axi_smc_0_stub.v
Executable file
105
hello_world_dma.cache/ip/2022.1/9/b/9b0ca356c30d2ee1/top_axi_smc_0_stub.v
Executable file
|
|
@ -0,0 +1,105 @@
|
|||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
|
||||
// Date : Tue Jun 24 12:00:32 2025
|
||||
// Host : media-wawa running 64-bit NixOS 25.05 (Warbler)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ top_axi_smc_0_stub.v
|
||||
// Design : top_axi_smc_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7a100tlfgg484-2L
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "bd_b43a,Vivado 2022.1" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, aresetn, S00_AXI_awid, S00_AXI_awaddr,
|
||||
S00_AXI_awlen, S00_AXI_awsize, S00_AXI_awburst, S00_AXI_awlock, S00_AXI_awcache,
|
||||
S00_AXI_awprot, S00_AXI_awqos, S00_AXI_awvalid, S00_AXI_awready, S00_AXI_wdata,
|
||||
S00_AXI_wstrb, S00_AXI_wlast, S00_AXI_wvalid, S00_AXI_wready, S00_AXI_bid, S00_AXI_bresp,
|
||||
S00_AXI_bvalid, S00_AXI_bready, S00_AXI_arid, S00_AXI_araddr, S00_AXI_arlen,
|
||||
S00_AXI_arsize, S00_AXI_arburst, S00_AXI_arlock, S00_AXI_arcache, S00_AXI_arprot,
|
||||
S00_AXI_arqos, S00_AXI_arvalid, S00_AXI_arready, S00_AXI_rid, S00_AXI_rdata, S00_AXI_rresp,
|
||||
S00_AXI_rlast, S00_AXI_rvalid, S00_AXI_rready, M00_AXI_awaddr, M00_AXI_awlen,
|
||||
M00_AXI_awsize, M00_AXI_awburst, M00_AXI_awlock, M00_AXI_awcache, M00_AXI_awprot,
|
||||
M00_AXI_awqos, M00_AXI_awvalid, M00_AXI_awready, M00_AXI_wdata, M00_AXI_wstrb,
|
||||
M00_AXI_wlast, M00_AXI_wvalid, M00_AXI_wready, M00_AXI_bresp, M00_AXI_bvalid,
|
||||
M00_AXI_bready, M00_AXI_araddr, M00_AXI_arlen, M00_AXI_arsize, M00_AXI_arburst,
|
||||
M00_AXI_arlock, M00_AXI_arcache, M00_AXI_arprot, M00_AXI_arqos, M00_AXI_arvalid,
|
||||
M00_AXI_arready, M00_AXI_rdata, M00_AXI_rresp, M00_AXI_rlast, M00_AXI_rvalid,
|
||||
M00_AXI_rready)
|
||||
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,S00_AXI_awid[3:0],S00_AXI_awaddr[63:0],S00_AXI_awlen[7:0],S00_AXI_awsize[2:0],S00_AXI_awburst[1:0],S00_AXI_awlock[0:0],S00_AXI_awcache[3:0],S00_AXI_awprot[2:0],S00_AXI_awqos[3:0],S00_AXI_awvalid,S00_AXI_awready,S00_AXI_wdata[63:0],S00_AXI_wstrb[7:0],S00_AXI_wlast,S00_AXI_wvalid,S00_AXI_wready,S00_AXI_bid[3:0],S00_AXI_bresp[1:0],S00_AXI_bvalid,S00_AXI_bready,S00_AXI_arid[3:0],S00_AXI_araddr[63:0],S00_AXI_arlen[7:0],S00_AXI_arsize[2:0],S00_AXI_arburst[1:0],S00_AXI_arlock[0:0],S00_AXI_arcache[3:0],S00_AXI_arprot[2:0],S00_AXI_arqos[3:0],S00_AXI_arvalid,S00_AXI_arready,S00_AXI_rid[3:0],S00_AXI_rdata[63:0],S00_AXI_rresp[1:0],S00_AXI_rlast,S00_AXI_rvalid,S00_AXI_rready,M00_AXI_awaddr[15:0],M00_AXI_awlen[7:0],M00_AXI_awsize[2:0],M00_AXI_awburst[1:0],M00_AXI_awlock[0:0],M00_AXI_awcache[3:0],M00_AXI_awprot[2:0],M00_AXI_awqos[3:0],M00_AXI_awvalid,M00_AXI_awready,M00_AXI_wdata[31:0],M00_AXI_wstrb[3:0],M00_AXI_wlast,M00_AXI_wvalid,M00_AXI_wready,M00_AXI_bresp[1:0],M00_AXI_bvalid,M00_AXI_bready,M00_AXI_araddr[15:0],M00_AXI_arlen[7:0],M00_AXI_arsize[2:0],M00_AXI_arburst[1:0],M00_AXI_arlock[0:0],M00_AXI_arcache[3:0],M00_AXI_arprot[2:0],M00_AXI_arqos[3:0],M00_AXI_arvalid,M00_AXI_arready,M00_AXI_rdata[31:0],M00_AXI_rresp[1:0],M00_AXI_rlast,M00_AXI_rvalid,M00_AXI_rready" */;
|
||||
input aclk;
|
||||
input aresetn;
|
||||
input [3:0]S00_AXI_awid;
|
||||
input [63:0]S00_AXI_awaddr;
|
||||
input [7:0]S00_AXI_awlen;
|
||||
input [2:0]S00_AXI_awsize;
|
||||
input [1:0]S00_AXI_awburst;
|
||||
input [0:0]S00_AXI_awlock;
|
||||
input [3:0]S00_AXI_awcache;
|
||||
input [2:0]S00_AXI_awprot;
|
||||
input [3:0]S00_AXI_awqos;
|
||||
input S00_AXI_awvalid;
|
||||
output S00_AXI_awready;
|
||||
input [63:0]S00_AXI_wdata;
|
||||
input [7:0]S00_AXI_wstrb;
|
||||
input S00_AXI_wlast;
|
||||
input S00_AXI_wvalid;
|
||||
output S00_AXI_wready;
|
||||
output [3:0]S00_AXI_bid;
|
||||
output [1:0]S00_AXI_bresp;
|
||||
output S00_AXI_bvalid;
|
||||
input S00_AXI_bready;
|
||||
input [3:0]S00_AXI_arid;
|
||||
input [63:0]S00_AXI_araddr;
|
||||
input [7:0]S00_AXI_arlen;
|
||||
input [2:0]S00_AXI_arsize;
|
||||
input [1:0]S00_AXI_arburst;
|
||||
input [0:0]S00_AXI_arlock;
|
||||
input [3:0]S00_AXI_arcache;
|
||||
input [2:0]S00_AXI_arprot;
|
||||
input [3:0]S00_AXI_arqos;
|
||||
input S00_AXI_arvalid;
|
||||
output S00_AXI_arready;
|
||||
output [3:0]S00_AXI_rid;
|
||||
output [63:0]S00_AXI_rdata;
|
||||
output [1:0]S00_AXI_rresp;
|
||||
output S00_AXI_rlast;
|
||||
output S00_AXI_rvalid;
|
||||
input S00_AXI_rready;
|
||||
output [15:0]M00_AXI_awaddr;
|
||||
output [7:0]M00_AXI_awlen;
|
||||
output [2:0]M00_AXI_awsize;
|
||||
output [1:0]M00_AXI_awburst;
|
||||
output [0:0]M00_AXI_awlock;
|
||||
output [3:0]M00_AXI_awcache;
|
||||
output [2:0]M00_AXI_awprot;
|
||||
output [3:0]M00_AXI_awqos;
|
||||
output M00_AXI_awvalid;
|
||||
input M00_AXI_awready;
|
||||
output [31:0]M00_AXI_wdata;
|
||||
output [3:0]M00_AXI_wstrb;
|
||||
output M00_AXI_wlast;
|
||||
output M00_AXI_wvalid;
|
||||
input M00_AXI_wready;
|
||||
input [1:0]M00_AXI_bresp;
|
||||
input M00_AXI_bvalid;
|
||||
output M00_AXI_bready;
|
||||
output [15:0]M00_AXI_araddr;
|
||||
output [7:0]M00_AXI_arlen;
|
||||
output [2:0]M00_AXI_arsize;
|
||||
output [1:0]M00_AXI_arburst;
|
||||
output [0:0]M00_AXI_arlock;
|
||||
output [3:0]M00_AXI_arcache;
|
||||
output [2:0]M00_AXI_arprot;
|
||||
output [3:0]M00_AXI_arqos;
|
||||
output M00_AXI_arvalid;
|
||||
input M00_AXI_arready;
|
||||
input [31:0]M00_AXI_rdata;
|
||||
input [1:0]M00_AXI_rresp;
|
||||
input M00_AXI_rlast;
|
||||
input M00_AXI_rvalid;
|
||||
output M00_AXI_rready;
|
||||
endmodule
|
||||
101
hello_world_dma.cache/ip/2022.1/9/b/9b0ca356c30d2ee1/top_axi_smc_0_stub.vhdl
Executable file
101
hello_world_dma.cache/ip/2022.1/9/b/9b0ca356c30d2ee1/top_axi_smc_0_stub.vhdl
Executable file
|
|
@ -0,0 +1,101 @@
|
|||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
|
||||
-- Date : Tue Jun 24 12:00:32 2025
|
||||
-- Host : media-wawa running 64-bit NixOS 25.05 (Warbler)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ top_axi_smc_0_stub.vhdl
|
||||
-- Design : top_axi_smc_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7a100tlfgg484-2L
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
S00_AXI_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 63 downto 0 );
|
||||
S00_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S00_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S00_AXI_awvalid : in STD_LOGIC;
|
||||
S00_AXI_awready : out STD_LOGIC;
|
||||
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
|
||||
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
S00_AXI_wlast : in STD_LOGIC;
|
||||
S00_AXI_wvalid : in STD_LOGIC;
|
||||
S00_AXI_wready : out STD_LOGIC;
|
||||
S00_AXI_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S00_AXI_bvalid : out STD_LOGIC;
|
||||
S00_AXI_bready : in STD_LOGIC;
|
||||
S00_AXI_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 63 downto 0 );
|
||||
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S00_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S00_AXI_arvalid : in STD_LOGIC;
|
||||
S00_AXI_arready : out STD_LOGIC;
|
||||
S00_AXI_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
|
||||
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S00_AXI_rlast : out STD_LOGIC;
|
||||
S00_AXI_rvalid : out STD_LOGIC;
|
||||
S00_AXI_rready : in STD_LOGIC;
|
||||
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
M00_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
M00_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M00_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M00_AXI_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
M00_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M00_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M00_AXI_awvalid : out STD_LOGIC;
|
||||
M00_AXI_awready : in STD_LOGIC;
|
||||
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M00_AXI_wlast : out STD_LOGIC;
|
||||
M00_AXI_wvalid : out STD_LOGIC;
|
||||
M00_AXI_wready : in STD_LOGIC;
|
||||
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M00_AXI_bvalid : in STD_LOGIC;
|
||||
M00_AXI_bready : out STD_LOGIC;
|
||||
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
M00_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
M00_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M00_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M00_AXI_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
M00_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M00_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M00_AXI_arvalid : out STD_LOGIC;
|
||||
M00_AXI_arready : in STD_LOGIC;
|
||||
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M00_AXI_rlast : in STD_LOGIC;
|
||||
M00_AXI_rvalid : in STD_LOGIC;
|
||||
M00_AXI_rready : out STD_LOGIC
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "aclk,aresetn,S00_AXI_awid[3:0],S00_AXI_awaddr[63:0],S00_AXI_awlen[7:0],S00_AXI_awsize[2:0],S00_AXI_awburst[1:0],S00_AXI_awlock[0:0],S00_AXI_awcache[3:0],S00_AXI_awprot[2:0],S00_AXI_awqos[3:0],S00_AXI_awvalid,S00_AXI_awready,S00_AXI_wdata[63:0],S00_AXI_wstrb[7:0],S00_AXI_wlast,S00_AXI_wvalid,S00_AXI_wready,S00_AXI_bid[3:0],S00_AXI_bresp[1:0],S00_AXI_bvalid,S00_AXI_bready,S00_AXI_arid[3:0],S00_AXI_araddr[63:0],S00_AXI_arlen[7:0],S00_AXI_arsize[2:0],S00_AXI_arburst[1:0],S00_AXI_arlock[0:0],S00_AXI_arcache[3:0],S00_AXI_arprot[2:0],S00_AXI_arqos[3:0],S00_AXI_arvalid,S00_AXI_arready,S00_AXI_rid[3:0],S00_AXI_rdata[63:0],S00_AXI_rresp[1:0],S00_AXI_rlast,S00_AXI_rvalid,S00_AXI_rready,M00_AXI_awaddr[15:0],M00_AXI_awlen[7:0],M00_AXI_awsize[2:0],M00_AXI_awburst[1:0],M00_AXI_awlock[0:0],M00_AXI_awcache[3:0],M00_AXI_awprot[2:0],M00_AXI_awqos[3:0],M00_AXI_awvalid,M00_AXI_awready,M00_AXI_wdata[31:0],M00_AXI_wstrb[3:0],M00_AXI_wlast,M00_AXI_wvalid,M00_AXI_wready,M00_AXI_bresp[1:0],M00_AXI_bvalid,M00_AXI_bready,M00_AXI_araddr[15:0],M00_AXI_arlen[7:0],M00_AXI_arsize[2:0],M00_AXI_arburst[1:0],M00_AXI_arlock[0:0],M00_AXI_arcache[3:0],M00_AXI_arprot[2:0],M00_AXI_arqos[3:0],M00_AXI_arvalid,M00_AXI_arready,M00_AXI_rdata[31:0],M00_AXI_rresp[1:0],M00_AXI_rlast,M00_AXI_rvalid,M00_AXI_rready";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "bd_b43a,Vivado 2022.1";
|
||||
begin
|
||||
end;
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>ipcache</spirit:library>
|
||||
<spirit:name>c41041b85e2924fb</spirit:name>
|
||||
<spirit:version>0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>top_util_vector_logic_0_0</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="util_vector_logic" spirit:version="2.0"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_OPERATION">not</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SIZE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">top_util_vector_logic_0_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOGO_FILE">data/sym_notgate.png</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">artix7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7a100tl</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fgg484</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2L</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">E</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">c41041b85e2924fb</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCL">$Change: 3513466 $</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCRC">3a5a0b3d</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">167</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2022.1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
Binary file not shown.
|
|
@ -0,0 +1,114 @@
|
|||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
|
||||
// Date : Tue Jun 24 11:58:34 2025
|
||||
// Host : media-wawa running 64-bit NixOS 25.05 (Warbler)
|
||||
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ top_util_vector_logic_0_0_sim_netlist.v
|
||||
// Design : top_util_vector_logic_0_0
|
||||
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
||||
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
// Device : xc7a100tlfgg484-2L
|
||||
// --------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
(* CHECK_LICENSE_TYPE = "top_util_vector_logic_0_0,util_vector_logic_v2_0_2_util_vector_logic,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "util_vector_logic_v2_0_2_util_vector_logic,Vivado 2022.1" *)
|
||||
(* NotValidForBitStream *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
|
||||
(Op1,
|
||||
Res);
|
||||
input [0:0]Op1;
|
||||
output [0:0]Res;
|
||||
|
||||
wire [0:0]Op1;
|
||||
wire [0:0]Res;
|
||||
|
||||
LUT1 #(
|
||||
.INIT(2'h1))
|
||||
\Res[0]_INST_0
|
||||
(.I0(Op1),
|
||||
.O(Res));
|
||||
endmodule
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
parameter GRES_WIDTH = 10000;
|
||||
parameter GRES_START = 10000;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
wire GRESTORE;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
reg GRESTORE_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
assign (strong1, weak0) GRESTORE = GRESTORE_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GRESTORE_int = 1'b0;
|
||||
#(GRES_START);
|
||||
GRESTORE_int = 1'b1;
|
||||
#(GRES_WIDTH);
|
||||
GRESTORE_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
|
||||
-- Date : Tue Jun 24 11:58:34 2025
|
||||
-- Host : media-wawa running 64-bit NixOS 25.05 (Warbler)
|
||||
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ top_util_vector_logic_0_0_sim_netlist.vhdl
|
||||
-- Design : top_util_vector_logic_0_0
|
||||
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
|
||||
-- synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
-- Device : xc7a100tlfgg484-2L
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
port (
|
||||
Op1 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
Res : out STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
);
|
||||
attribute NotValidForBitStream : boolean;
|
||||
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
|
||||
attribute CHECK_LICENSE_TYPE : string;
|
||||
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "top_util_vector_logic_0_0,util_vector_logic_v2_0_2_util_vector_logic,{}";
|
||||
attribute DowngradeIPIdentifiedWarnings : string;
|
||||
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "util_vector_logic_v2_0_2_util_vector_logic,Vivado 2022.1";
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
begin
|
||||
\Res[0]_INST_0\: unisim.vcomponents.LUT1
|
||||
generic map(
|
||||
INIT => X"1"
|
||||
)
|
||||
port map (
|
||||
I0 => Op1(0),
|
||||
O => Res(0)
|
||||
);
|
||||
end STRUCTURE;
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
|
||||
// Date : Tue Jun 24 11:58:34 2025
|
||||
// Host : media-wawa running 64-bit NixOS 25.05 (Warbler)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ top_util_vector_logic_0_0_stub.v
|
||||
// Design : top_util_vector_logic_0_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7a100tlfgg484-2L
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "util_vector_logic_v2_0_2_util_vector_logic,Vivado 2022.1" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(Op1, Res)
|
||||
/* synthesis syn_black_box black_box_pad_pin="Op1[0:0],Res[0:0]" */;
|
||||
input [0:0]Op1;
|
||||
output [0:0]Res;
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
|
||||
-- Date : Tue Jun 24 11:58:34 2025
|
||||
-- Host : media-wawa running 64-bit NixOS 25.05 (Warbler)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ top_util_vector_logic_0_0_stub.vhdl
|
||||
-- Design : top_util_vector_logic_0_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7a100tlfgg484-2L
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
Op1 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
Res : out STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "Op1[0:0],Res[0:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "util_vector_logic_v2_0_2_util_vector_logic,Vivado 2022.1";
|
||||
begin
|
||||
end;
|
||||
|
|
@ -0,0 +1,985 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>ipcache</spirit:library>
|
||||
<spirit:name>d86a665de0dcbae9</spirit:name>
|
||||
<spirit:version>0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>top_xdma_0_0</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="xdma" spirit:version="4.1"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.AXI_ACLK.FREQ_HZ">125000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.SYS_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ">125000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_LITE.FREQ_HZ">125000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BASEADDR">0x00001000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">top_xdma_0_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EGW_IS_PARENT_IP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HIGHADDR">0x00001FFF</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INS_LOSS_NYQ">15</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MSI_X_OPTIONS">None</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCIE_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_DEVICE_ID_mqdma">9014</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_MSIX_CAP_PBA_BIR_mqdma">BAR_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_MSIX_CAP_PBA_OFFSET_mqdma">00000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_MSIX_CAP_TABLE_BIR_mqdma">BAR_0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_MSIX_CAP_TABLE_OFFSET_mqdma">00000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_MSIX_CAP_TABLE_SIZE_mqdma">000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_REVISION_ID_mqdma">00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SRIOV_CAP_INITIAL_VF">0</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SRIOV_FIRST_VF_OFFSET">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SRIOV_FUNC_DEP_LINK">0000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SRIOV_SUPPORTED_PAGE_SIZE">00000553</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SRIOV_VF_DEVICE_ID">A034</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SUBSYSTEM_ID_mqdma">0007</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF0_SUBSYSTEM_VENDOR_ID_mqdma">10EE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_DEVICE_ID_mqdma">0007</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_INTERRUPT_PIN">NONE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_MSIX_CAP_PBA_BIR_mqdma">BAR_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_MSIX_CAP_PBA_OFFSET_mqdma">00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_MSIX_CAP_TABLE_BIR_mqdma">BAR_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_MSIX_CAP_TABLE_OFFSET_mqdma">00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_MSIX_CAP_TABLE_SIZE_mqdma">000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_REVISION_ID">00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_REVISION_ID_mqdma">00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SRIOV_CAP_INITIAL_VF">0</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SRIOV_CAP_VER">1</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SRIOV_FIRST_VF_OFFSET">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SRIOV_FUNC_DEP_LINK">0001</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SRIOV_SUPPORTED_PAGE_SIZE">00000553</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SRIOV_VF_DEVICE_ID">A134</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SUBSYSTEM_ID">0007</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SUBSYSTEM_ID_mqdma">0007</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SUBSYSTEM_VENDOR_ID">10EE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_SUBSYSTEM_VENDOR_ID_mqdma">10EE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF1_Use_Class_Code_Lookup_Assistant">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF2_DEVICE_ID_mqdma">9214</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF2_INTERRUPT_PIN">NONE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF2_MSIX_CAP_PBA_BIR_mqdma">BAR_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF2_MSIX_CAP_PBA_OFFSET_mqdma">00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF2_MSIX_CAP_TABLE_BIR_mqdma">BAR_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF2_MSIX_CAP_TABLE_OFFSET_mqdma">00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF2_MSIX_CAP_TABLE_SIZE_mqdma">000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF2_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF2_REVISION_ID">00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF2_REVISION_ID_mqdma">00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF2_SRIOV_CAP_INITIAL_VF">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF2_SRIOV_CAP_VER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF2_SRIOV_FIRST_VF_OFFSET">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF2_SRIOV_FUNC_DEP_LINK">0002</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF2_SRIOV_SUPPORTED_PAGE_SIZE">00000553</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF2_SRIOV_VF_DEVICE_ID">A234</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF2_SUBSYSTEM_ID">0007</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF2_SUBSYSTEM_ID_mqdma">0007</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF2_SUBSYSTEM_VENDOR_ID">10EE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF2_SUBSYSTEM_VENDOR_ID_mqdma">10EE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF2_Use_Class_Code_Lookup_Assistant">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF3_DEVICE_ID_mqdma">9314</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF3_INTERRUPT_PIN">NONE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF3_MSIX_CAP_PBA_BIR_mqdma">BAR_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF3_MSIX_CAP_PBA_OFFSET_mqdma">00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF3_MSIX_CAP_TABLE_BIR_mqdma">BAR_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF3_MSIX_CAP_TABLE_OFFSET_mqdma">00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF3_MSIX_CAP_TABLE_SIZE_mqdma">000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF3_MSI_CAP_MULTIMSGCAP">1_vector</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF3_REVISION_ID">00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF3_REVISION_ID_mqdma">00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF3_SRIOV_CAP_INITIAL_VF">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF3_SRIOV_CAP_VER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF3_SRIOV_FIRST_VF_OFFSET">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF3_SRIOV_FUNC_DEP_LINK">0003</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF3_SRIOV_SUPPORTED_PAGE_SIZE">00000553</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF3_SRIOV_VF_DEVICE_ID">A334</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF3_SUBSYSTEM_ID">0007</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF3_SUBSYSTEM_ID_mqdma">0007</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF3_SUBSYSTEM_VENDOR_ID">10EE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF3_SUBSYSTEM_VENDOR_ID_mqdma">10EE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PF3_Use_Class_Code_Lookup_Assistant">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHY_LP_TXPRESET">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RX_PPM_OFFSET">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RX_SSC_PPM">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SRIOV_CAP_ENABLE">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SRIOV_FIRST_VF_OFFSET">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SYS_RST_N_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Shared_Logic">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Shared_Logic_Both">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Shared_Logic_Both_7xG2">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Shared_Logic_Clk">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Shared_Logic_Clk_7xG2">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Shared_Logic_Gtc">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Shared_Logic_Gtc_7xG2">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.acs_ext_cap_enable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.aspm_support">No_ASPM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axi_aclk_loopback">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axi_addr_width">64</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axi_bypass_64bit_en">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axi_bypass_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axi_data_width">64_bit</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axi_id_width">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axi_vip_in_exdes">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axibar2pciebar_0">0x0000000000000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axibar2pciebar_1">0x0000000000000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axibar2pciebar_2">0x0000000000000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axibar2pciebar_3">0x0000000000000000</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axibar2pciebar_4">0x0000000000000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axibar2pciebar_5">0x0000000000000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axibar_0">0x0000000000000000</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axibar_1">0x0000000000000000</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axibar_2">0x0000000000000000</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axibar_3">0x0000000000000000</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axibar_4">0x0000000000000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axibar_5">0x0000000000000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axibar_highaddr_0">0x0000000000000000</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axibar_highaddr_1">0x0000000000000000</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axibar_highaddr_2">0x0000000000000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axibar_highaddr_3">0x0000000000000000</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axibar_highaddr_4">0x0000000000000000</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axibar_highaddr_5">0x0000000000000000</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axibar_num">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axil_master_64bit_en">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axil_master_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axilite_master_en">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axilite_master_scale">Megabytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axilite_master_size">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_pipe_line_stage">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axist_bypass_en">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axist_bypass_scale">Megabytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axist_bypass_size">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axisten_freq">125</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axisten_if_enable_msg_route">27FFF</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axsize_byte_access_en">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.bar0_indicator">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.bar1_indicator">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.bar2_indicator">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.bar3_indicator">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.bar4_indicator">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.bar5_indicator">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.bar_indicator">BAR_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.barlite2">7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.bridge_burst">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.bridge_registers_offset_enable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_ats_enable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_ats_switch_unique_bdf">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_m_axi_num_read">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_m_axi_num_readq">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_m_axi_num_write">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_pri_enable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_s_axi_num_read">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_s_axi_num_write">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_s_axi_supports_narrow_burst">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.c_smmu_en">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_ext_if">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_mgmt_if">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cfg_space_enable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.comp_timeout">50ms</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.copy_pf0">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.copy_sriov_pf0">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.coreclk_freq">500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ctrl_skip_mask">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dedicate_perst">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.descriptor_bypass_exdes">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.device_port_type">PCI_Express_Endpoint_device</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.disable_bram_pipeline">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.disable_eq_synchronizer">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.disable_gt_loc">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.disable_user_clock_root">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dma_2rp">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dma_reset_source_sel">User_Reset</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.drp_clk_sel">Internal</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dsc_bypass_rd">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dsc_bypass_rd_out">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dsc_bypass_wr">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dsc_bypass_wr_out">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_en">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_axi_master_if">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_axi_mm_mqdma">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_axi_slave_if">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_axi_st_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_bridge">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_bridge_slv">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_coreclk_es1">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_dbg_descramble">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_debug_ports">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_dma_and_bridge">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_ext_ch_gt_drp">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_gt_selection">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_l23_entry">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_pcie_drp">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_slot_cap_reg">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.en_transceiver_status_ports">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_ats_switch">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_auto_rxeq">False</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_ccix">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_clock_delay_grp">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_code">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_dvsec">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_epyc_chipset_fix">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_error_injection">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_gen4">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_ibert">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_jtag_dbg">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_lane_reversal">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_ltssm_dbg">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_mark_debug">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_more_clk">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_multi_pcie">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_pcie_debug">False</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_pcie_debug_axi4_st">False</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_resource_reduction">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_slave_read_64os">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.errc_dec_en">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.example_design_type">RTL</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ext_startup_primitive">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ext_sys_clk_bufg">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ext_xvc_vsec_enable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.flr_enable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.free_run_freq">100_MHz</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.functional_mode">DMA</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gen4_eieos_0s7">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gen_pipe_debug">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_loc_num">X99Y99</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtcom_in_core_usp">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtwiz_in_core_us">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtwiz_in_core_usp">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.include_baroffset_reg">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ins_loss_profile">Add-in_Card</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.insert_cips">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.intx_rx_pin_en">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.lane_order">Bottom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.legacy_cfg_ext_if">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.local_test">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.m_axib_num_write_scale">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.master_cal_only">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.mcap_enablement">None</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.mcap_fpga_bitstream_version">00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.mode_selection">Basic</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.mpsoc_pl_rp_enable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.msi_rx_pin_en">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.msix_pcie_internal">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.msix_rx_decode_en">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.msix_rx_pin_en">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.msix_type">HARD</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.mult_pf_des">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.num_queues">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.old_bridge_timeout">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.parity_settings">None</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_blk_locn">X0Y0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_extended_tag">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_id_if">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pciebar2axibar_0">0x0000000000000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pciebar2axibar_1">0x0000000000000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pciebar2axibar_2">0x0000000000000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pciebar2axibar_3">0x0000000000000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pciebar2axibar_4">0x0000000000000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pciebar2axibar_5">0x0000000000000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pciebar2axibar_6">0x0000000000000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pciebar2axibar_axil_master">0x00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pciebar2axibar_axist_bypass">0x0000000000000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pciebar2axibar_xdma">0x0000000000000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.performance">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.performance_exdes">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_Use_Class_Code_Lookup_Assistant">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_Use_Class_Code_Lookup_Assistant_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_aer_cap_ecrc_gen_and_check_capable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_ari_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_ats_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_64bit_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_enabled">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_enabled_mqdma">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_index">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_prefetchable_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_scale_mqdma">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_size">128</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_size_mqdma">128</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_type">Memory</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar0_type_mqdma">DMA</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_64bit_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_enabled_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_index">7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_prefetchable_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_scale_mqdma">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_size">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_size_mqdma">128</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_type">Memory</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar1_type_mqdma">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_64bit_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_enabled_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_index">7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_prefetchable_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_scale_mqdma">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_size">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_size_mqdma">128</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_type">Memory</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar2_type_mqdma">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_64bit_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_enabled_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_index">7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_prefetchable_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_scale_mqdma">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_size">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_size_mqdma">128</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_type">Memory</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar3_type_mqdma">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_64bit_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_enabled_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_index">7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_prefetchable_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_scale_mqdma">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_size">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_size_mqdma">128</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_type">Memory</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar4_type_mqdma">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_enabled_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_index">7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_prefetchable_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_scale_mqdma">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_size">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_size_mqdma">128</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_type">Memory</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_bar5_type_mqdma">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_base_class_menu">Simple_communication_controllers</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_base_class_menu_mqdma">Memory_controller</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_class_code">070001</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_class_code_base">07</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_class_code_base_mqdma">05</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_class_code_interface">01</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_class_code_interface_mqdma">00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_class_code_mqdma">058000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_class_code_sub">00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_class_code_sub_mqdma">80</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_device_id">7014</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_expansion_rom_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_expansion_rom_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_expansion_rom_size">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_expansion_rom_type">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_interrupt_pin">INTA</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_link_status_slot_clock_config">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_msi_cap_multimsgcap">1_vector</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_msi_enabled">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_msix_cap_pba_bir">BAR_1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_msix_cap_pba_offset">00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_msix_cap_table_bir">BAR_1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_msix_cap_table_offset">00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_msix_cap_table_size">000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_msix_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_msix_enabled_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_msix_impl_locn">Internal</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_pri_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_rbar_cap_bar0">0x00000000fff0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_rbar_cap_bar1">0x000000000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_rbar_cap_bar2">0x000000000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_rbar_cap_bar3">0x000000000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_rbar_cap_bar4">0x000000000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_rbar_cap_bar5">0x000000000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_rbar_num">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_revision_id">00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_enabled">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_size">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar0_type">DMA</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_size">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar1_type">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_size">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar2_type">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_size">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar3_type">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_size">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar4_type">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar5_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar5_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar5_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar5_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar5_size">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_bar5_type">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sriov_cap_ver">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sub_class_interface_menu">16450_compatible_serial_controller</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_sub_class_interface_menu_mqdma">Other_memory_controller</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_subsystem_id">0007</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_subsystem_vendor_id">10EE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf0_vendor_id_mqdma">10EE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_Use_Class_Code_Lookup_Assistant_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_64bit_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_enabled">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_enabled_mqdma">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_index">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_prefetchable_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_scale">Megabytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_scale_mqdma">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_size">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_size_mqdma">128</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_type">Memory</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar0_type_mqdma">DMA</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_64bit_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_enabled">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_enabled_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_index">7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_prefetchable_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_scale_mqdma">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_size">128</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_size_mqdma">128</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_type">Memory</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar1_type_mqdma">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_64bit">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_64bit_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_enabled">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_enabled_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_index">7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_prefetchable_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_scale_mqdma">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_size">128</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_size_mqdma">128</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_type">Memory</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar2_type_mqdma">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_64bit_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_enabled_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_index">7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_prefetchable_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_scale_mqdma">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_size">128</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_size_mqdma">128</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_type">Memory</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar3_type_mqdma">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_64bit">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_64bit_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_enabled">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_enabled_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_index">7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_prefetchable_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_scale_mqdma">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_size">128</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_size_mqdma">128</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_type">Memory</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar4_type_mqdma">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_enabled_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_index">7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_prefetchable_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_scale_mqdma">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_size">128</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_size_mqdma">128</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_type">Memory</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_bar5_type_mqdma">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_base_class_menu">Simple_communication_controllers</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_base_class_menu_mqdma">Memory_controller</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_class_code">070001</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_class_code_base">07</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_class_code_base_mqdma">05</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_class_code_interface">01</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_class_code_interface_mqdma">00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_class_code_mqdma">058000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_class_code_sub">00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_class_code_sub_mqdma">80</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_device_id">1041</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_expansion_rom_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_expansion_rom_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_expansion_rom_size">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_expansion_rom_type">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_msi_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_msix_cap_pba_bir">BAR_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_msix_cap_pba_offset">00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_msix_cap_table_bir">BAR_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_msix_cap_table_offset">00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_msix_cap_table_size">000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_msix_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_msix_enabled_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_pciebar2axibar_0">0x0000000000000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_pciebar2axibar_1">0x0000000000000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_pciebar2axibar_2">0x0000000000000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_pciebar2axibar_3">0x0000000000000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_pciebar2axibar_4">0x0000000000000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_pciebar2axibar_5">0x0000000000000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_pciebar2axibar_6">0x0000000000000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_rbar_cap_bar0">0x00000000fff0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_rbar_cap_bar1">0x000000000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_rbar_cap_bar2">0x000000000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_rbar_cap_bar3">0x000000000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_rbar_cap_bar4">0x000000000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_rbar_cap_bar5">0x000000000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_rbar_num">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_enabled">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_size">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar0_type">DMA</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_size">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar1_type">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_size">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar2_type">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_size">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar3_type">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_size">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar4_type">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar5_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar5_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar5_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar5_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar5_size">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sriov_bar5_type">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sub_class_interface_menu">16450_compatible_serial_controller</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_sub_class_interface_menu_mqdma">Other_memory_controller</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_vendor_id">10EE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf1_vendor_id_mqdma">10EE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_Use_Class_Code_Lookup_Assistant_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar0_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar0_64bit_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar0_enabled">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar0_enabled_mqdma">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar0_index">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar0_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar0_prefetchable_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar0_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar0_scale_mqdma">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar0_size">128</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar0_size_mqdma">128</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar0_type">Memory</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar0_type_mqdma">DMA</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar1_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar1_64bit_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar1_enabled">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar1_enabled_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar1_index">7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar1_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar1_prefetchable_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar1_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar1_scale_mqdma">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar1_size">128</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar1_size_mqdma">128</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar1_type">Memory</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar1_type_mqdma">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar2_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar2_64bit_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar2_enabled">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar2_enabled_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar2_index">7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar2_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar2_prefetchable_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar2_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar2_scale_mqdma">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar2_size">128</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar2_size_mqdma">128</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar2_type">Memory</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar2_type_mqdma">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar3_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar3_64bit_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar3_enabled">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar3_enabled_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar3_index">7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar3_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar3_prefetchable_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar3_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar3_scale_mqdma">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar3_size">128</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar3_size_mqdma">128</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar3_type">Memory</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar3_type_mqdma">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar4_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar4_64bit_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar4_enabled">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar4_enabled_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar4_index">7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar4_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar4_prefetchable_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar4_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar4_scale_mqdma">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar4_size">128</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar4_size_mqdma">128</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar4_type">Memory</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar4_type_mqdma">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar5_enabled">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar5_enabled_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar5_index">7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar5_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar5_prefetchable_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar5_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar5_scale_mqdma">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar5_size">128</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar5_size_mqdma">128</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar5_type">Memory</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_bar5_type_mqdma">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_base_class_menu">Memory_controller</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_base_class_menu_mqdma">Memory_controller</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_class_code">058000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_class_code_base">05</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_class_code_base_mqdma">05</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_class_code_interface">00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_class_code_interface_mqdma">00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_class_code_mqdma">058000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_class_code_sub">80</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_class_code_sub_mqdma">80</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_device_id">1040</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_expansion_rom_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_expansion_rom_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_expansion_rom_size">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_expansion_rom_type">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_msi_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_msix_enabled_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_pciebar2axibar_0">0x0000000000000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_pciebar2axibar_1">0x0000000000000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_pciebar2axibar_2">0x0000000000000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_pciebar2axibar_3">0x0000000000000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_pciebar2axibar_4">0x0000000000000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_pciebar2axibar_5">0x0000000000000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_rbar_cap_bar0">0x00000000fff0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_rbar_cap_bar1">0x000000000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_rbar_cap_bar2">0x000000000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_rbar_cap_bar3">0x000000000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_rbar_cap_bar4">0x000000000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_rbar_cap_bar5">0x000000000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_rbar_num">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar0_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar0_enabled">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar0_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar0_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar0_size">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar0_type">DMA</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar1_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar1_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar1_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar1_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar1_size">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar1_type">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar2_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar2_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar2_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar2_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar2_size">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar2_type">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar3_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar3_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar3_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar3_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar3_size">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar3_type">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar4_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar4_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar4_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar4_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar4_size">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar4_type">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar5_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar5_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar5_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar5_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar5_size">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sriov_bar5_type">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sub_class_interface_menu">Other_memory_controller</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_sub_class_interface_menu_mqdma">Other_memory_controller</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf2_vendor_id_mqdma">10EE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_Use_Class_Code_Lookup_Assistant_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar0_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar0_64bit_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar0_enabled">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar0_enabled_mqdma">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar0_index">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar0_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar0_prefetchable_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar0_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar0_scale_mqdma">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar0_size">128</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar0_size_mqdma">128</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar0_type">Memory</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar0_type_mqdma">DMA</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar1_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar1_64bit_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar1_enabled">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar1_enabled_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar1_index">7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar1_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar1_prefetchable_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar1_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar1_scale_mqdma">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar1_size">128</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar1_size_mqdma">128</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar1_type">Memory</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar1_type_mqdma">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar2_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar2_64bit_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar2_enabled">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar2_enabled_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar2_index">7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar2_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar2_prefetchable_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar2_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar2_scale_mqdma">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar2_size">128</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar2_size_mqdma">128</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar2_type">Memory</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar2_type_mqdma">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar3_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar3_64bit_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar3_enabled">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar3_enabled_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar3_index">7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar3_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar3_prefetchable_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar3_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar3_scale_mqdma">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar3_size">128</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar3_size_mqdma">128</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar3_type">Memory</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar3_type_mqdma">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar4_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar4_64bit_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar4_enabled">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar4_enabled_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar4_index">7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar4_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar4_prefetchable_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar4_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar4_scale_mqdma">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar4_size">128</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar4_size_mqdma">128</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar4_type">Memory</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar4_type_mqdma">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar5_enabled">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar5_enabled_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar5_index">7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar5_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar5_prefetchable_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar5_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar5_scale_mqdma">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar5_size">128</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar5_size_mqdma">128</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar5_type">Memory</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_bar5_type_mqdma">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_base_class_menu">Memory_controller</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_base_class_menu_mqdma">Memory_controller</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_class_code">058000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_class_code_base">05</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_class_code_base_mqdma">05</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_class_code_interface">00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_class_code_interface_mqdma">00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_class_code_mqdma">058000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_class_code_sub">80</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_class_code_sub_mqdma">80</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_device_id">1039</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_expansion_rom_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_expansion_rom_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_expansion_rom_size">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_expansion_rom_type">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_msi_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_msix_enabled_mqdma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_pciebar2axibar_0">0x0000000000000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_pciebar2axibar_1">0x0000000000000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_pciebar2axibar_2">0x0000000000000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_pciebar2axibar_3">0x0000000000000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_pciebar2axibar_4">0x0000000000000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_pciebar2axibar_5">0x0000000000000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_rbar_cap_bar0">0x00000000fff0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_rbar_cap_bar1">0x000000000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_rbar_cap_bar2">0x000000000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_rbar_cap_bar3">0x000000000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_rbar_cap_bar4">0x000000000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_rbar_cap_bar5">0x000000000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_rbar_num">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar0_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar0_enabled">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar0_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar0_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar0_size">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar0_type">DMA</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar1_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar1_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar1_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar1_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar1_size">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar1_type">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar2_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar2_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar2_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar2_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar2_size">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar2_type">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar3_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar3_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar3_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar3_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar3_size">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar3_type">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar4_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar4_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar4_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar4_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar4_size">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar4_type">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar5_64bit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar5_enabled">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar5_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar5_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar5_size">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sriov_bar5_type">N/A</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sub_class_interface_menu">Other_memory_controller</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_sub_class_interface_menu_mqdma">Other_memory_controller</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf3_vendor_id_mqdma">10EE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pf_swap">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pipe_line_stage">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pipe_sim">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pl_link_cap_max_link_speed">2.5_GT/s</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pl_link_cap_max_link_width">X4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.plltype">CPLL</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.post_synth_sim_en">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.prog_usr_irq_vec_map">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rbar_enable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rcfg_nph_fix_en">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ref_clk_freq">100_MHz</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.replace_uram_with_bram">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.runbit_fix">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rx_detect">Default</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.s_axi_id_width">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.select_quad">GTH_Quad_128</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.set_finite_credit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.shell_bridge">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.silicon_rev">Pre-Production</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.sim_model">NO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.slot_cap_reg">00000040</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.soft_reset_en">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.split_dma">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.split_dma_single_pf">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.sys_reset_polarity">ACTIVE_LOW</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.tandem_enable_rfsoc">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.timeout0_sel">14</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.timeout1_sel">15</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.timeout_mult">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.tl_credits_cd">15</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.tl_credits_ch">15</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.tl_pf_enable_reg">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.tl_tx_mux_strict_priority">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.two_bypass_bar">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.type1_membase_memlimit_enable">Disabled</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.type1_prefetchable_membase_memlimit">Disabled</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_standard_interfaces">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.user_pf_two_axilite_bar_en">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.usplus_es1_seqnum_bypass">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.usr_irq_exdes">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.usrint_expn">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.vcu118_board">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.vcu1525_ddr_ex">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.vdm_en">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.vendor_id">10EE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.versal">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.virtio_exdes">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.virtio_perf_exdes">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.vu9p_board">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.vu9p_tul_ex">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.warm_reboot_sbr_fix">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.xdma_axi_intf_mm">AXI_Memory_Mapped</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.xdma_axilite_slave">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.xdma_dsc_bypass">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.xdma_en">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.xdma_non_incremental_exdes">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.xdma_num_usr_irq">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.xdma_pcie_64bit_en">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.xdma_pcie_prefetchable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.xdma_rnum_chnl">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.xdma_rnum_rids">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.xdma_scale">Kilobytes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.xdma_size">64</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.xdma_st_infinite_desc_exdes">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.xdma_sts_ports">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.xdma_wnum_chnl">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.xdma_wnum_rids">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.xlnx_ref_board">None</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">artix7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7a100tl</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fgg484</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2L</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">E</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEELABORATESCRC">37531336</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">d86a665de0dcbae9</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESPECIALDATA">top_xdma_0_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCL">$Change: 3513466 $</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCRC">c2b7788d</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">355</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">17</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2022.1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
Binary file not shown.
341364
hello_world_dma.cache/ip/2022.1/d/8/d86a665de0dcbae9/top_xdma_0_0_sim_netlist.v
Executable file
341364
hello_world_dma.cache/ip/2022.1/d/8/d86a665de0dcbae9/top_xdma_0_0_sim_netlist.v
Executable file
File diff suppressed because it is too large
Load diff
421422
hello_world_dma.cache/ip/2022.1/d/8/d86a665de0dcbae9/top_xdma_0_0_sim_netlist.vhdl
Executable file
421422
hello_world_dma.cache/ip/2022.1/d/8/d86a665de0dcbae9/top_xdma_0_0_sim_netlist.vhdl
Executable file
File diff suppressed because it is too large
Load diff
97
hello_world_dma.cache/ip/2022.1/d/8/d86a665de0dcbae9/top_xdma_0_0_stub.v
Executable file
97
hello_world_dma.cache/ip/2022.1/d/8/d86a665de0dcbae9/top_xdma_0_0_stub.v
Executable file
|
|
@ -0,0 +1,97 @@
|
|||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
|
||||
// Date : Tue Jun 24 12:01:36 2025
|
||||
// Host : media-wawa running 64-bit NixOS 25.05 (Warbler)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ top_xdma_0_0_stub.v
|
||||
// Design : top_xdma_0_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7a100tlfgg484-2L
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "top_xdma_0_0_core_top,Vivado 2022.1" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(sys_clk, sys_rst_n, user_lnk_up, pci_exp_txp,
|
||||
pci_exp_txn, pci_exp_rxp, pci_exp_rxn, axi_aclk, axi_aresetn, usr_irq_req, usr_irq_ack,
|
||||
msi_enable, msi_vector_width, m_axi_awready, m_axi_wready, m_axi_bid, m_axi_bresp,
|
||||
m_axi_bvalid, m_axi_arready, m_axi_rid, m_axi_rdata, m_axi_rresp, m_axi_rlast, m_axi_rvalid,
|
||||
m_axi_awid, m_axi_awaddr, m_axi_awlen, m_axi_awsize, m_axi_awburst, m_axi_awprot,
|
||||
m_axi_awvalid, m_axi_awlock, m_axi_awcache, m_axi_wdata, m_axi_wstrb, m_axi_wlast,
|
||||
m_axi_wvalid, m_axi_bready, m_axi_arid, m_axi_araddr, m_axi_arlen, m_axi_arsize,
|
||||
m_axi_arburst, m_axi_arprot, m_axi_arvalid, m_axi_arlock, m_axi_arcache, m_axi_rready,
|
||||
m_axil_awaddr, m_axil_awprot, m_axil_awvalid, m_axil_awready, m_axil_wdata, m_axil_wstrb,
|
||||
m_axil_wvalid, m_axil_wready, m_axil_bvalid, m_axil_bresp, m_axil_bready, m_axil_araddr,
|
||||
m_axil_arprot, m_axil_arvalid, m_axil_arready, m_axil_rdata, m_axil_rresp, m_axil_rvalid,
|
||||
m_axil_rready)
|
||||
/* synthesis syn_black_box black_box_pad_pin="sys_clk,sys_rst_n,user_lnk_up,pci_exp_txp[3:0],pci_exp_txn[3:0],pci_exp_rxp[3:0],pci_exp_rxn[3:0],axi_aclk,axi_aresetn,usr_irq_req[0:0],usr_irq_ack[0:0],msi_enable,msi_vector_width[2:0],m_axi_awready,m_axi_wready,m_axi_bid[3:0],m_axi_bresp[1:0],m_axi_bvalid,m_axi_arready,m_axi_rid[3:0],m_axi_rdata[63:0],m_axi_rresp[1:0],m_axi_rlast,m_axi_rvalid,m_axi_awid[3:0],m_axi_awaddr[63:0],m_axi_awlen[7:0],m_axi_awsize[2:0],m_axi_awburst[1:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awlock,m_axi_awcache[3:0],m_axi_wdata[63:0],m_axi_wstrb[7:0],m_axi_wlast,m_axi_wvalid,m_axi_bready,m_axi_arid[3:0],m_axi_araddr[63:0],m_axi_arlen[7:0],m_axi_arsize[2:0],m_axi_arburst[1:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arlock,m_axi_arcache[3:0],m_axi_rready,m_axil_awaddr[31:0],m_axil_awprot[2:0],m_axil_awvalid,m_axil_awready,m_axil_wdata[31:0],m_axil_wstrb[3:0],m_axil_wvalid,m_axil_wready,m_axil_bvalid,m_axil_bresp[1:0],m_axil_bready,m_axil_araddr[31:0],m_axil_arprot[2:0],m_axil_arvalid,m_axil_arready,m_axil_rdata[31:0],m_axil_rresp[1:0],m_axil_rvalid,m_axil_rready" */;
|
||||
input sys_clk;
|
||||
input sys_rst_n;
|
||||
output user_lnk_up;
|
||||
output [3:0]pci_exp_txp;
|
||||
output [3:0]pci_exp_txn;
|
||||
input [3:0]pci_exp_rxp;
|
||||
input [3:0]pci_exp_rxn;
|
||||
output axi_aclk;
|
||||
output axi_aresetn;
|
||||
input [0:0]usr_irq_req;
|
||||
output [0:0]usr_irq_ack;
|
||||
output msi_enable;
|
||||
output [2:0]msi_vector_width;
|
||||
input m_axi_awready;
|
||||
input m_axi_wready;
|
||||
input [3:0]m_axi_bid;
|
||||
input [1:0]m_axi_bresp;
|
||||
input m_axi_bvalid;
|
||||
input m_axi_arready;
|
||||
input [3:0]m_axi_rid;
|
||||
input [63:0]m_axi_rdata;
|
||||
input [1:0]m_axi_rresp;
|
||||
input m_axi_rlast;
|
||||
input m_axi_rvalid;
|
||||
output [3:0]m_axi_awid;
|
||||
output [63:0]m_axi_awaddr;
|
||||
output [7:0]m_axi_awlen;
|
||||
output [2:0]m_axi_awsize;
|
||||
output [1:0]m_axi_awburst;
|
||||
output [2:0]m_axi_awprot;
|
||||
output m_axi_awvalid;
|
||||
output m_axi_awlock;
|
||||
output [3:0]m_axi_awcache;
|
||||
output [63:0]m_axi_wdata;
|
||||
output [7:0]m_axi_wstrb;
|
||||
output m_axi_wlast;
|
||||
output m_axi_wvalid;
|
||||
output m_axi_bready;
|
||||
output [3:0]m_axi_arid;
|
||||
output [63:0]m_axi_araddr;
|
||||
output [7:0]m_axi_arlen;
|
||||
output [2:0]m_axi_arsize;
|
||||
output [1:0]m_axi_arburst;
|
||||
output [2:0]m_axi_arprot;
|
||||
output m_axi_arvalid;
|
||||
output m_axi_arlock;
|
||||
output [3:0]m_axi_arcache;
|
||||
output m_axi_rready;
|
||||
output [31:0]m_axil_awaddr;
|
||||
output [2:0]m_axil_awprot;
|
||||
output m_axil_awvalid;
|
||||
input m_axil_awready;
|
||||
output [31:0]m_axil_wdata;
|
||||
output [3:0]m_axil_wstrb;
|
||||
output m_axil_wvalid;
|
||||
input m_axil_wready;
|
||||
input m_axil_bvalid;
|
||||
input [1:0]m_axil_bresp;
|
||||
output m_axil_bready;
|
||||
output [31:0]m_axil_araddr;
|
||||
output [2:0]m_axil_arprot;
|
||||
output m_axil_arvalid;
|
||||
input m_axil_arready;
|
||||
input [31:0]m_axil_rdata;
|
||||
input [1:0]m_axil_rresp;
|
||||
input m_axil_rvalid;
|
||||
output m_axil_rready;
|
||||
endmodule
|
||||
96
hello_world_dma.cache/ip/2022.1/d/8/d86a665de0dcbae9/top_xdma_0_0_stub.vhdl
Executable file
96
hello_world_dma.cache/ip/2022.1/d/8/d86a665de0dcbae9/top_xdma_0_0_stub.vhdl
Executable file
|
|
@ -0,0 +1,96 @@
|
|||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
|
||||
-- Date : Tue Jun 24 12:01:36 2025
|
||||
-- Host : media-wawa running 64-bit NixOS 25.05 (Warbler)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ top_xdma_0_0_stub.vhdl
|
||||
-- Design : top_xdma_0_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7a100tlfgg484-2L
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
sys_clk : in STD_LOGIC;
|
||||
sys_rst_n : in STD_LOGIC;
|
||||
user_lnk_up : out STD_LOGIC;
|
||||
pci_exp_txp : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
pci_exp_txn : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
pci_exp_rxp : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
pci_exp_rxn : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
axi_aclk : out STD_LOGIC;
|
||||
axi_aresetn : out STD_LOGIC;
|
||||
usr_irq_req : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
usr_irq_ack : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
msi_enable : out STD_LOGIC;
|
||||
msi_vector_width : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
m_axi_awready : in STD_LOGIC;
|
||||
m_axi_wready : in STD_LOGIC;
|
||||
m_axi_bid : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
m_axi_bvalid : in STD_LOGIC;
|
||||
m_axi_arready : in STD_LOGIC;
|
||||
m_axi_rid : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
|
||||
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
m_axi_rlast : in STD_LOGIC;
|
||||
m_axi_rvalid : in STD_LOGIC;
|
||||
m_axi_awid : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
m_axi_awaddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
|
||||
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
m_axi_awvalid : out STD_LOGIC;
|
||||
m_axi_awlock : out STD_LOGIC;
|
||||
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
|
||||
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
m_axi_wlast : out STD_LOGIC;
|
||||
m_axi_wvalid : out STD_LOGIC;
|
||||
m_axi_bready : out STD_LOGIC;
|
||||
m_axi_arid : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
m_axi_araddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
|
||||
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
m_axi_arvalid : out STD_LOGIC;
|
||||
m_axi_arlock : out STD_LOGIC;
|
||||
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
m_axi_rready : out STD_LOGIC;
|
||||
m_axil_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
m_axil_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
m_axil_awvalid : out STD_LOGIC;
|
||||
m_axil_awready : in STD_LOGIC;
|
||||
m_axil_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
m_axil_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
m_axil_wvalid : out STD_LOGIC;
|
||||
m_axil_wready : in STD_LOGIC;
|
||||
m_axil_bvalid : in STD_LOGIC;
|
||||
m_axil_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
m_axil_bready : out STD_LOGIC;
|
||||
m_axil_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
m_axil_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
m_axil_arvalid : out STD_LOGIC;
|
||||
m_axil_arready : in STD_LOGIC;
|
||||
m_axil_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
m_axil_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
m_axil_rvalid : in STD_LOGIC;
|
||||
m_axil_rready : out STD_LOGIC
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "sys_clk,sys_rst_n,user_lnk_up,pci_exp_txp[3:0],pci_exp_txn[3:0],pci_exp_rxp[3:0],pci_exp_rxn[3:0],axi_aclk,axi_aresetn,usr_irq_req[0:0],usr_irq_ack[0:0],msi_enable,msi_vector_width[2:0],m_axi_awready,m_axi_wready,m_axi_bid[3:0],m_axi_bresp[1:0],m_axi_bvalid,m_axi_arready,m_axi_rid[3:0],m_axi_rdata[63:0],m_axi_rresp[1:0],m_axi_rlast,m_axi_rvalid,m_axi_awid[3:0],m_axi_awaddr[63:0],m_axi_awlen[7:0],m_axi_awsize[2:0],m_axi_awburst[1:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awlock,m_axi_awcache[3:0],m_axi_wdata[63:0],m_axi_wstrb[7:0],m_axi_wlast,m_axi_wvalid,m_axi_bready,m_axi_arid[3:0],m_axi_araddr[63:0],m_axi_arlen[7:0],m_axi_arsize[2:0],m_axi_arburst[1:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arlock,m_axi_arcache[3:0],m_axi_rready,m_axil_awaddr[31:0],m_axil_awprot[2:0],m_axil_awvalid,m_axil_awready,m_axil_wdata[31:0],m_axil_wstrb[3:0],m_axil_wvalid,m_axil_wready,m_axil_bvalid,m_axil_bresp[1:0],m_axil_bready,m_axil_araddr[31:0],m_axil_arprot[2:0],m_axil_arvalid,m_axil_arready,m_axil_rdata[31:0],m_axil_rresp[1:0],m_axil_rvalid,m_axil_rready";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "top_xdma_0_0_core_top,Vivado 2022.1";
|
||||
begin
|
||||
end;
|
||||
4
hello_world_dma.cache/wt/project.wpc
Normal file
4
hello_world_dma.cache/wt/project.wpc
Normal file
|
|
@ -0,0 +1,4 @@
|
|||
version:1
|
||||
57656254616c6b5472616e736d697373696f6e417474656d70746564:2
|
||||
6d6f64655f636f756e7465727c4755494d6f6465:4
|
||||
eof:
|
||||
46
hello_world_dma.cache/wt/synthesis.wdf
Normal file
46
hello_world_dma.cache/wt/synthesis.wdf
Normal file
|
|
@ -0,0 +1,46 @@
|
|||
version:1
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:78633761313030746c6667673438342d324c:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:746f705f77726170706572:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67656e65726963:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d766572696c6f675f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e737472736574:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7365755f70726f74656374:64656661756c743a3a6e6f6e65:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d666c617474656e5f686965726172636879:64656661756c743a3a72656275696c74:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67617465645f636c6f636b5f636f6e76657273696f6e:64656661756c743a3a6f6666:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d646972656374697665:64656661756c743a3a64656661756c74:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e6372656d656e74616c5f6d6f6465:64656661756c743a3a64656661756c74:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6c696e74:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d646676:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6466765f73657474696e6773:64656661756c743a3a6e6f6e65:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f6970:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f636f6e73747261696e7473:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f6c63:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6f73:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d62756667:64656661756c743a3a3132:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66616e6f75745f6c696d6974:64656661756c743a3a3130303030:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73687265675f6d696e5f73697a65:64656661756c743a3a33:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d6f6465:64656661756c743a3a64656661756c74:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66736d5f65787472616374696f6e:64656661756c743a3a6175746f:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6b6565705f6571756976616c656e745f726567697374657273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7265736f757263655f73686172696e67:64656661756c743a3a6175746f:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636173636164655f647370:64656661756c743a3a6175746f:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e74726f6c5f7365745f6f70745f7468726573686f6c64:64656661756c743a3a6175746f:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d:64656661756c743a3a2d31:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d:64656661756c743a3a2d31:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f647370:64656661756c743a3a2d31:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d726574696d696e67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f726574696d696e67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f73726c65787472616374:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d64656275675f6c6f67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a323773:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323637312e3539384d42:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:36342e3033314d42:00:00
|
||||
eof:3146637378
|
||||
3
hello_world_dma.cache/wt/synthesis_details.wdf
Normal file
3
hello_world_dma.cache/wt/synthesis_details.wdf
Normal file
|
|
@ -0,0 +1,3 @@
|
|||
version:1
|
||||
73796e746865736973:73796e7468657369735c7573616765:686c735f6970:30:00:00
|
||||
eof:2511430288
|
||||
21
hello_world_dma.cache/wt/webtalk_pa.xml
Normal file
21
hello_world_dma.cache/wt/webtalk_pa.xml
Normal file
|
|
@ -0,0 +1,21 @@
|
|||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<document>
|
||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
<application name="pa" timeStamp="Tue Jun 24 13:34:21 2025">
|
||||
<section name="Project Information" visible="false">
|
||||
<property name="ProjectID" value="e49d70a015124bebbb9a419404306049" type="ProjectID"/>
|
||||
<property name="ProjectIteration" value="10" type="ProjectIteration"/>
|
||||
</section>
|
||||
<section name="PlanAhead Usage" visible="true">
|
||||
<item name="Project Data">
|
||||
<property name="SrcSetCount" value="1" type="SrcSetCount"/>
|
||||
<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
|
||||
<property name="DesignMode" value="RTL" type="DesignMode"/>
|
||||
<property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/>
|
||||
<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
|
||||
</item>
|
||||
</section>
|
||||
</application>
|
||||
</document>
|
||||
52
hello_world_dma.gen/sources_1/bd/top/hdl/top_wrapper.v
Normal file
52
hello_world_dma.gen/sources_1/bd/top/hdl/top_wrapper.v
Normal file
|
|
@ -0,0 +1,52 @@
|
|||
//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
//--------------------------------------------------------------------------------
|
||||
//Tool Version: Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
|
||||
//Date : Tue Jun 24 12:25:34 2025
|
||||
//Host : media-wawa running 64-bit NixOS 25.05 (Warbler)
|
||||
//Command : generate_target top_wrapper.bd
|
||||
//Design : top_wrapper
|
||||
//Purpose : IP block netlist
|
||||
//--------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module top_wrapper
|
||||
(LED_M2,
|
||||
diff_clock_rtl_0_clk_n,
|
||||
diff_clock_rtl_0_clk_p,
|
||||
leds_tri_o,
|
||||
pcie_express_x4_rxn,
|
||||
pcie_express_x4_rxp,
|
||||
pcie_express_x4_txn,
|
||||
pcie_express_x4_txp,
|
||||
reset_rtl_0);
|
||||
output [0:0]LED_M2;
|
||||
input [0:0]diff_clock_rtl_0_clk_n;
|
||||
input [0:0]diff_clock_rtl_0_clk_p;
|
||||
output [1:0]leds_tri_o;
|
||||
input [3:0]pcie_express_x4_rxn;
|
||||
input [3:0]pcie_express_x4_rxp;
|
||||
output [3:0]pcie_express_x4_txn;
|
||||
output [3:0]pcie_express_x4_txp;
|
||||
input reset_rtl_0;
|
||||
|
||||
wire [0:0]LED_M2;
|
||||
wire [0:0]diff_clock_rtl_0_clk_n;
|
||||
wire [0:0]diff_clock_rtl_0_clk_p;
|
||||
wire [1:0]leds_tri_o;
|
||||
wire [3:0]pcie_express_x4_rxn;
|
||||
wire [3:0]pcie_express_x4_rxp;
|
||||
wire [3:0]pcie_express_x4_txn;
|
||||
wire [3:0]pcie_express_x4_txp;
|
||||
wire reset_rtl_0;
|
||||
|
||||
top top_i
|
||||
(.LED_M2(LED_M2),
|
||||
.diff_clock_rtl_0_clk_n(diff_clock_rtl_0_clk_n),
|
||||
.diff_clock_rtl_0_clk_p(diff_clock_rtl_0_clk_p),
|
||||
.leds_tri_o(leds_tri_o),
|
||||
.pcie_express_x4_rxn(pcie_express_x4_rxn),
|
||||
.pcie_express_x4_rxp(pcie_express_x4_rxp),
|
||||
.pcie_express_x4_txn(pcie_express_x4_txn),
|
||||
.pcie_express_x4_txp(pcie_express_x4_txp),
|
||||
.reset_rtl_0(reset_rtl_0));
|
||||
endmodule
|
||||
4108
hello_world_dma.gen/sources_1/bd/top/hw_handoff/top.hwh
Normal file
4108
hello_world_dma.gen/sources_1/bd/top/hw_handoff/top.hwh
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,712 @@
|
|||
// (c) Copyright 1995-2025 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
#include "top_axi_bram_ctrl_0_0_sc.h"
|
||||
|
||||
#include "top_axi_bram_ctrl_0_0.h"
|
||||
|
||||
#include "axi_bram_ctrl.h"
|
||||
|
||||
#include <map>
|
||||
#include <string>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef XILINX_SIMULATOR
|
||||
top_axi_bram_ctrl_0_0::top_axi_bram_ctrl_0_0(const sc_core::sc_module_name& nm) : top_axi_bram_ctrl_0_0_sc(nm), s_axi_aclk("s_axi_aclk"), s_axi_aresetn("s_axi_aresetn"), s_axi_awaddr("s_axi_awaddr"), s_axi_awlen("s_axi_awlen"), s_axi_awsize("s_axi_awsize"), s_axi_awburst("s_axi_awburst"), s_axi_awlock("s_axi_awlock"), s_axi_awcache("s_axi_awcache"), s_axi_awprot("s_axi_awprot"), s_axi_awvalid("s_axi_awvalid"), s_axi_awready("s_axi_awready"), s_axi_wdata("s_axi_wdata"), s_axi_wstrb("s_axi_wstrb"), s_axi_wlast("s_axi_wlast"), s_axi_wvalid("s_axi_wvalid"), s_axi_wready("s_axi_wready"), s_axi_bresp("s_axi_bresp"), s_axi_bvalid("s_axi_bvalid"), s_axi_bready("s_axi_bready"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), bram_rst_a("bram_rst_a"), bram_clk_a("bram_clk_a"), bram_en_a("bram_en_a"), bram_we_a("bram_we_a"), bram_addr_a("bram_addr_a"), bram_wrdata_a("bram_wrdata_a"), bram_rddata_a("bram_rddata_a"), bram_rst_b("bram_rst_b"), bram_clk_b("bram_clk_b"), bram_en_b("bram_en_b"), bram_we_b("bram_we_b"), bram_addr_b("bram_addr_b"), bram_wrdata_b("bram_wrdata_b"), bram_rddata_b("bram_rddata_b")
|
||||
{
|
||||
|
||||
// initialize pins
|
||||
mp_impl->s_axi_aclk(s_axi_aclk);
|
||||
mp_impl->s_axi_aresetn(s_axi_aresetn);
|
||||
mp_impl->bram_rst_a(bram_rst_a);
|
||||
mp_impl->bram_clk_a(bram_clk_a);
|
||||
mp_impl->bram_en_a(bram_en_a);
|
||||
mp_impl->bram_we_a(bram_we_a);
|
||||
mp_impl->bram_addr_a(bram_addr_a);
|
||||
mp_impl->bram_wrdata_a(bram_wrdata_a);
|
||||
mp_impl->bram_rddata_a(bram_rddata_a);
|
||||
mp_impl->bram_rst_b(bram_rst_b);
|
||||
mp_impl->bram_clk_b(bram_clk_b);
|
||||
mp_impl->bram_en_b(bram_en_b);
|
||||
mp_impl->bram_we_b(bram_we_b);
|
||||
mp_impl->bram_addr_b(bram_addr_b);
|
||||
mp_impl->bram_wrdata_b(bram_wrdata_b);
|
||||
mp_impl->bram_rddata_b(bram_rddata_b);
|
||||
|
||||
// initialize transactors
|
||||
mp_S_AXI_transactor = NULL;
|
||||
|
||||
// initialize socket stubs
|
||||
|
||||
}
|
||||
|
||||
void top_axi_bram_ctrl_0_0::before_end_of_elaboration()
|
||||
{
|
||||
// configure 'S_AXI' transactor
|
||||
|
||||
if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("top_axi_bram_ctrl_0_0", "S_AXI_TLM_MODE") != 1)
|
||||
{
|
||||
// Instantiate Socket Stubs
|
||||
|
||||
// 'S_AXI' transactor parameters
|
||||
xsc::common_cpp::properties S_AXI_transactor_param_props;
|
||||
S_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
|
||||
S_AXI_transactor_param_props.addLong("FREQ_HZ", "125000000");
|
||||
S_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "16");
|
||||
S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_QOS", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_REGION", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
|
||||
S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
|
||||
S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "32");
|
||||
S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16");
|
||||
S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "256");
|
||||
S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
|
||||
S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
|
||||
S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
|
||||
S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_RESET", "1");
|
||||
S_AXI_transactor_param_props.addFloat("PHASE", "0.0");
|
||||
S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
|
||||
S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
|
||||
S_AXI_transactor_param_props.addString("CLK_DOMAIN", "top_xdma_0_0_axi_aclk");
|
||||
|
||||
mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<32,16,1,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
|
||||
|
||||
// S_AXI' transactor ports
|
||||
|
||||
mp_S_AXI_transactor->ARADDR(s_axi_araddr);
|
||||
mp_S_AXI_transactor->ARBURST(s_axi_arburst);
|
||||
mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
|
||||
mp_S_AXI_transactor->ARLEN(s_axi_arlen);
|
||||
mp_S_AXI_transactor->ARLOCK(s_axi_arlock);
|
||||
mp_S_AXI_transactor->ARPROT(s_axi_arprot);
|
||||
mp_S_AXI_transactor->ARREADY(s_axi_arready);
|
||||
mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
|
||||
mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
|
||||
mp_S_AXI_transactor->AWADDR(s_axi_awaddr);
|
||||
mp_S_AXI_transactor->AWBURST(s_axi_awburst);
|
||||
mp_S_AXI_transactor->AWCACHE(s_axi_awcache);
|
||||
mp_S_AXI_transactor->AWLEN(s_axi_awlen);
|
||||
mp_S_AXI_transactor->AWLOCK(s_axi_awlock);
|
||||
mp_S_AXI_transactor->AWPROT(s_axi_awprot);
|
||||
mp_S_AXI_transactor->AWREADY(s_axi_awready);
|
||||
mp_S_AXI_transactor->AWSIZE(s_axi_awsize);
|
||||
mp_S_AXI_transactor->AWVALID(s_axi_awvalid);
|
||||
mp_S_AXI_transactor->BREADY(s_axi_bready);
|
||||
mp_S_AXI_transactor->BRESP(s_axi_bresp);
|
||||
mp_S_AXI_transactor->BVALID(s_axi_bvalid);
|
||||
mp_S_AXI_transactor->RDATA(s_axi_rdata);
|
||||
mp_S_AXI_transactor->RLAST(s_axi_rlast);
|
||||
mp_S_AXI_transactor->RREADY(s_axi_rready);
|
||||
mp_S_AXI_transactor->RRESP(s_axi_rresp);
|
||||
mp_S_AXI_transactor->RVALID(s_axi_rvalid);
|
||||
mp_S_AXI_transactor->WDATA(s_axi_wdata);
|
||||
mp_S_AXI_transactor->WLAST(s_axi_wlast);
|
||||
mp_S_AXI_transactor->WREADY(s_axi_wready);
|
||||
mp_S_AXI_transactor->WSTRB(s_axi_wstrb);
|
||||
mp_S_AXI_transactor->WVALID(s_axi_wvalid);
|
||||
mp_S_AXI_transactor->CLK(s_axi_aclk);
|
||||
mp_S_AXI_transactor->RST(s_axi_aresetn);
|
||||
|
||||
// S_AXI' transactor sockets
|
||||
|
||||
mp_impl->target_0_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
|
||||
mp_impl->target_0_wr_socket->bind(*(mp_S_AXI_transactor->wr_socket));
|
||||
}
|
||||
else
|
||||
{
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
#endif // XILINX_SIMULATOR
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef XM_SYSTEMC
|
||||
top_axi_bram_ctrl_0_0::top_axi_bram_ctrl_0_0(const sc_core::sc_module_name& nm) : top_axi_bram_ctrl_0_0_sc(nm), s_axi_aclk("s_axi_aclk"), s_axi_aresetn("s_axi_aresetn"), s_axi_awaddr("s_axi_awaddr"), s_axi_awlen("s_axi_awlen"), s_axi_awsize("s_axi_awsize"), s_axi_awburst("s_axi_awburst"), s_axi_awlock("s_axi_awlock"), s_axi_awcache("s_axi_awcache"), s_axi_awprot("s_axi_awprot"), s_axi_awvalid("s_axi_awvalid"), s_axi_awready("s_axi_awready"), s_axi_wdata("s_axi_wdata"), s_axi_wstrb("s_axi_wstrb"), s_axi_wlast("s_axi_wlast"), s_axi_wvalid("s_axi_wvalid"), s_axi_wready("s_axi_wready"), s_axi_bresp("s_axi_bresp"), s_axi_bvalid("s_axi_bvalid"), s_axi_bready("s_axi_bready"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), bram_rst_a("bram_rst_a"), bram_clk_a("bram_clk_a"), bram_en_a("bram_en_a"), bram_we_a("bram_we_a"), bram_addr_a("bram_addr_a"), bram_wrdata_a("bram_wrdata_a"), bram_rddata_a("bram_rddata_a"), bram_rst_b("bram_rst_b"), bram_clk_b("bram_clk_b"), bram_en_b("bram_en_b"), bram_we_b("bram_we_b"), bram_addr_b("bram_addr_b"), bram_wrdata_b("bram_wrdata_b"), bram_rddata_b("bram_rddata_b")
|
||||
{
|
||||
|
||||
// initialize pins
|
||||
mp_impl->s_axi_aclk(s_axi_aclk);
|
||||
mp_impl->s_axi_aresetn(s_axi_aresetn);
|
||||
mp_impl->bram_rst_a(bram_rst_a);
|
||||
mp_impl->bram_clk_a(bram_clk_a);
|
||||
mp_impl->bram_en_a(bram_en_a);
|
||||
mp_impl->bram_we_a(bram_we_a);
|
||||
mp_impl->bram_addr_a(bram_addr_a);
|
||||
mp_impl->bram_wrdata_a(bram_wrdata_a);
|
||||
mp_impl->bram_rddata_a(bram_rddata_a);
|
||||
mp_impl->bram_rst_b(bram_rst_b);
|
||||
mp_impl->bram_clk_b(bram_clk_b);
|
||||
mp_impl->bram_en_b(bram_en_b);
|
||||
mp_impl->bram_we_b(bram_we_b);
|
||||
mp_impl->bram_addr_b(bram_addr_b);
|
||||
mp_impl->bram_wrdata_b(bram_wrdata_b);
|
||||
mp_impl->bram_rddata_b(bram_rddata_b);
|
||||
|
||||
// initialize transactors
|
||||
mp_S_AXI_transactor = NULL;
|
||||
|
||||
// initialize socket stubs
|
||||
|
||||
}
|
||||
|
||||
void top_axi_bram_ctrl_0_0::before_end_of_elaboration()
|
||||
{
|
||||
// configure 'S_AXI' transactor
|
||||
|
||||
if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("top_axi_bram_ctrl_0_0", "S_AXI_TLM_MODE") != 1)
|
||||
{
|
||||
// Instantiate Socket Stubs
|
||||
|
||||
// 'S_AXI' transactor parameters
|
||||
xsc::common_cpp::properties S_AXI_transactor_param_props;
|
||||
S_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
|
||||
S_AXI_transactor_param_props.addLong("FREQ_HZ", "125000000");
|
||||
S_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "16");
|
||||
S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_QOS", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_REGION", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
|
||||
S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
|
||||
S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "32");
|
||||
S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16");
|
||||
S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "256");
|
||||
S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
|
||||
S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
|
||||
S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
|
||||
S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_RESET", "1");
|
||||
S_AXI_transactor_param_props.addFloat("PHASE", "0.0");
|
||||
S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
|
||||
S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
|
||||
S_AXI_transactor_param_props.addString("CLK_DOMAIN", "top_xdma_0_0_axi_aclk");
|
||||
|
||||
mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<32,16,1,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
|
||||
|
||||
// S_AXI' transactor ports
|
||||
|
||||
mp_S_AXI_transactor->ARADDR(s_axi_araddr);
|
||||
mp_S_AXI_transactor->ARBURST(s_axi_arburst);
|
||||
mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
|
||||
mp_S_AXI_transactor->ARLEN(s_axi_arlen);
|
||||
mp_S_AXI_transactor->ARLOCK(s_axi_arlock);
|
||||
mp_S_AXI_transactor->ARPROT(s_axi_arprot);
|
||||
mp_S_AXI_transactor->ARREADY(s_axi_arready);
|
||||
mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
|
||||
mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
|
||||
mp_S_AXI_transactor->AWADDR(s_axi_awaddr);
|
||||
mp_S_AXI_transactor->AWBURST(s_axi_awburst);
|
||||
mp_S_AXI_transactor->AWCACHE(s_axi_awcache);
|
||||
mp_S_AXI_transactor->AWLEN(s_axi_awlen);
|
||||
mp_S_AXI_transactor->AWLOCK(s_axi_awlock);
|
||||
mp_S_AXI_transactor->AWPROT(s_axi_awprot);
|
||||
mp_S_AXI_transactor->AWREADY(s_axi_awready);
|
||||
mp_S_AXI_transactor->AWSIZE(s_axi_awsize);
|
||||
mp_S_AXI_transactor->AWVALID(s_axi_awvalid);
|
||||
mp_S_AXI_transactor->BREADY(s_axi_bready);
|
||||
mp_S_AXI_transactor->BRESP(s_axi_bresp);
|
||||
mp_S_AXI_transactor->BVALID(s_axi_bvalid);
|
||||
mp_S_AXI_transactor->RDATA(s_axi_rdata);
|
||||
mp_S_AXI_transactor->RLAST(s_axi_rlast);
|
||||
mp_S_AXI_transactor->RREADY(s_axi_rready);
|
||||
mp_S_AXI_transactor->RRESP(s_axi_rresp);
|
||||
mp_S_AXI_transactor->RVALID(s_axi_rvalid);
|
||||
mp_S_AXI_transactor->WDATA(s_axi_wdata);
|
||||
mp_S_AXI_transactor->WLAST(s_axi_wlast);
|
||||
mp_S_AXI_transactor->WREADY(s_axi_wready);
|
||||
mp_S_AXI_transactor->WSTRB(s_axi_wstrb);
|
||||
mp_S_AXI_transactor->WVALID(s_axi_wvalid);
|
||||
mp_S_AXI_transactor->CLK(s_axi_aclk);
|
||||
mp_S_AXI_transactor->RST(s_axi_aresetn);
|
||||
|
||||
// S_AXI' transactor sockets
|
||||
|
||||
mp_impl->target_0_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
|
||||
mp_impl->target_0_wr_socket->bind(*(mp_S_AXI_transactor->wr_socket));
|
||||
}
|
||||
else
|
||||
{
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
#endif // XM_SYSTEMC
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef RIVIERA
|
||||
top_axi_bram_ctrl_0_0::top_axi_bram_ctrl_0_0(const sc_core::sc_module_name& nm) : top_axi_bram_ctrl_0_0_sc(nm), s_axi_aclk("s_axi_aclk"), s_axi_aresetn("s_axi_aresetn"), s_axi_awaddr("s_axi_awaddr"), s_axi_awlen("s_axi_awlen"), s_axi_awsize("s_axi_awsize"), s_axi_awburst("s_axi_awburst"), s_axi_awlock("s_axi_awlock"), s_axi_awcache("s_axi_awcache"), s_axi_awprot("s_axi_awprot"), s_axi_awvalid("s_axi_awvalid"), s_axi_awready("s_axi_awready"), s_axi_wdata("s_axi_wdata"), s_axi_wstrb("s_axi_wstrb"), s_axi_wlast("s_axi_wlast"), s_axi_wvalid("s_axi_wvalid"), s_axi_wready("s_axi_wready"), s_axi_bresp("s_axi_bresp"), s_axi_bvalid("s_axi_bvalid"), s_axi_bready("s_axi_bready"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), bram_rst_a("bram_rst_a"), bram_clk_a("bram_clk_a"), bram_en_a("bram_en_a"), bram_we_a("bram_we_a"), bram_addr_a("bram_addr_a"), bram_wrdata_a("bram_wrdata_a"), bram_rddata_a("bram_rddata_a"), bram_rst_b("bram_rst_b"), bram_clk_b("bram_clk_b"), bram_en_b("bram_en_b"), bram_we_b("bram_we_b"), bram_addr_b("bram_addr_b"), bram_wrdata_b("bram_wrdata_b"), bram_rddata_b("bram_rddata_b")
|
||||
{
|
||||
|
||||
// initialize pins
|
||||
mp_impl->s_axi_aclk(s_axi_aclk);
|
||||
mp_impl->s_axi_aresetn(s_axi_aresetn);
|
||||
mp_impl->bram_rst_a(bram_rst_a);
|
||||
mp_impl->bram_clk_a(bram_clk_a);
|
||||
mp_impl->bram_en_a(bram_en_a);
|
||||
mp_impl->bram_we_a(bram_we_a);
|
||||
mp_impl->bram_addr_a(bram_addr_a);
|
||||
mp_impl->bram_wrdata_a(bram_wrdata_a);
|
||||
mp_impl->bram_rddata_a(bram_rddata_a);
|
||||
mp_impl->bram_rst_b(bram_rst_b);
|
||||
mp_impl->bram_clk_b(bram_clk_b);
|
||||
mp_impl->bram_en_b(bram_en_b);
|
||||
mp_impl->bram_we_b(bram_we_b);
|
||||
mp_impl->bram_addr_b(bram_addr_b);
|
||||
mp_impl->bram_wrdata_b(bram_wrdata_b);
|
||||
mp_impl->bram_rddata_b(bram_rddata_b);
|
||||
|
||||
// initialize transactors
|
||||
mp_S_AXI_transactor = NULL;
|
||||
|
||||
// initialize socket stubs
|
||||
|
||||
}
|
||||
|
||||
void top_axi_bram_ctrl_0_0::before_end_of_elaboration()
|
||||
{
|
||||
// configure 'S_AXI' transactor
|
||||
|
||||
if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("top_axi_bram_ctrl_0_0", "S_AXI_TLM_MODE") != 1)
|
||||
{
|
||||
// Instantiate Socket Stubs
|
||||
|
||||
// 'S_AXI' transactor parameters
|
||||
xsc::common_cpp::properties S_AXI_transactor_param_props;
|
||||
S_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
|
||||
S_AXI_transactor_param_props.addLong("FREQ_HZ", "125000000");
|
||||
S_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "16");
|
||||
S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_QOS", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_REGION", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
|
||||
S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
|
||||
S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "32");
|
||||
S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16");
|
||||
S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "256");
|
||||
S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
|
||||
S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
|
||||
S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
|
||||
S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_RESET", "1");
|
||||
S_AXI_transactor_param_props.addFloat("PHASE", "0.0");
|
||||
S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
|
||||
S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
|
||||
S_AXI_transactor_param_props.addString("CLK_DOMAIN", "top_xdma_0_0_axi_aclk");
|
||||
|
||||
mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<32,16,1,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
|
||||
|
||||
// S_AXI' transactor ports
|
||||
|
||||
mp_S_AXI_transactor->ARADDR(s_axi_araddr);
|
||||
mp_S_AXI_transactor->ARBURST(s_axi_arburst);
|
||||
mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
|
||||
mp_S_AXI_transactor->ARLEN(s_axi_arlen);
|
||||
mp_S_AXI_transactor->ARLOCK(s_axi_arlock);
|
||||
mp_S_AXI_transactor->ARPROT(s_axi_arprot);
|
||||
mp_S_AXI_transactor->ARREADY(s_axi_arready);
|
||||
mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
|
||||
mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
|
||||
mp_S_AXI_transactor->AWADDR(s_axi_awaddr);
|
||||
mp_S_AXI_transactor->AWBURST(s_axi_awburst);
|
||||
mp_S_AXI_transactor->AWCACHE(s_axi_awcache);
|
||||
mp_S_AXI_transactor->AWLEN(s_axi_awlen);
|
||||
mp_S_AXI_transactor->AWLOCK(s_axi_awlock);
|
||||
mp_S_AXI_transactor->AWPROT(s_axi_awprot);
|
||||
mp_S_AXI_transactor->AWREADY(s_axi_awready);
|
||||
mp_S_AXI_transactor->AWSIZE(s_axi_awsize);
|
||||
mp_S_AXI_transactor->AWVALID(s_axi_awvalid);
|
||||
mp_S_AXI_transactor->BREADY(s_axi_bready);
|
||||
mp_S_AXI_transactor->BRESP(s_axi_bresp);
|
||||
mp_S_AXI_transactor->BVALID(s_axi_bvalid);
|
||||
mp_S_AXI_transactor->RDATA(s_axi_rdata);
|
||||
mp_S_AXI_transactor->RLAST(s_axi_rlast);
|
||||
mp_S_AXI_transactor->RREADY(s_axi_rready);
|
||||
mp_S_AXI_transactor->RRESP(s_axi_rresp);
|
||||
mp_S_AXI_transactor->RVALID(s_axi_rvalid);
|
||||
mp_S_AXI_transactor->WDATA(s_axi_wdata);
|
||||
mp_S_AXI_transactor->WLAST(s_axi_wlast);
|
||||
mp_S_AXI_transactor->WREADY(s_axi_wready);
|
||||
mp_S_AXI_transactor->WSTRB(s_axi_wstrb);
|
||||
mp_S_AXI_transactor->WVALID(s_axi_wvalid);
|
||||
mp_S_AXI_transactor->CLK(s_axi_aclk);
|
||||
mp_S_AXI_transactor->RST(s_axi_aresetn);
|
||||
|
||||
// S_AXI' transactor sockets
|
||||
|
||||
mp_impl->target_0_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
|
||||
mp_impl->target_0_wr_socket->bind(*(mp_S_AXI_transactor->wr_socket));
|
||||
}
|
||||
else
|
||||
{
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
#endif // RIVIERA
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef VCSSYSTEMC
|
||||
top_axi_bram_ctrl_0_0::top_axi_bram_ctrl_0_0(const sc_core::sc_module_name& nm) : top_axi_bram_ctrl_0_0_sc(nm), s_axi_aclk("s_axi_aclk"), s_axi_aresetn("s_axi_aresetn"), s_axi_awaddr("s_axi_awaddr"), s_axi_awlen("s_axi_awlen"), s_axi_awsize("s_axi_awsize"), s_axi_awburst("s_axi_awburst"), s_axi_awlock("s_axi_awlock"), s_axi_awcache("s_axi_awcache"), s_axi_awprot("s_axi_awprot"), s_axi_awvalid("s_axi_awvalid"), s_axi_awready("s_axi_awready"), s_axi_wdata("s_axi_wdata"), s_axi_wstrb("s_axi_wstrb"), s_axi_wlast("s_axi_wlast"), s_axi_wvalid("s_axi_wvalid"), s_axi_wready("s_axi_wready"), s_axi_bresp("s_axi_bresp"), s_axi_bvalid("s_axi_bvalid"), s_axi_bready("s_axi_bready"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), bram_rst_a("bram_rst_a"), bram_clk_a("bram_clk_a"), bram_en_a("bram_en_a"), bram_we_a("bram_we_a"), bram_addr_a("bram_addr_a"), bram_wrdata_a("bram_wrdata_a"), bram_rddata_a("bram_rddata_a"), bram_rst_b("bram_rst_b"), bram_clk_b("bram_clk_b"), bram_en_b("bram_en_b"), bram_we_b("bram_we_b"), bram_addr_b("bram_addr_b"), bram_wrdata_b("bram_wrdata_b"), bram_rddata_b("bram_rddata_b")
|
||||
{
|
||||
// initialize pins
|
||||
mp_impl->s_axi_aclk(s_axi_aclk);
|
||||
mp_impl->s_axi_aresetn(s_axi_aresetn);
|
||||
mp_impl->bram_rst_a(bram_rst_a);
|
||||
mp_impl->bram_clk_a(bram_clk_a);
|
||||
mp_impl->bram_en_a(bram_en_a);
|
||||
mp_impl->bram_we_a(bram_we_a);
|
||||
mp_impl->bram_addr_a(bram_addr_a);
|
||||
mp_impl->bram_wrdata_a(bram_wrdata_a);
|
||||
mp_impl->bram_rddata_a(bram_rddata_a);
|
||||
mp_impl->bram_rst_b(bram_rst_b);
|
||||
mp_impl->bram_clk_b(bram_clk_b);
|
||||
mp_impl->bram_en_b(bram_en_b);
|
||||
mp_impl->bram_we_b(bram_we_b);
|
||||
mp_impl->bram_addr_b(bram_addr_b);
|
||||
mp_impl->bram_wrdata_b(bram_wrdata_b);
|
||||
mp_impl->bram_rddata_b(bram_rddata_b);
|
||||
|
||||
// initialize transactors
|
||||
mp_S_AXI_transactor = NULL;
|
||||
|
||||
// Instantiate Socket Stubs
|
||||
|
||||
// configure S_AXI_transactor
|
||||
xsc::common_cpp::properties S_AXI_transactor_param_props;
|
||||
S_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
|
||||
S_AXI_transactor_param_props.addLong("FREQ_HZ", "125000000");
|
||||
S_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "16");
|
||||
S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_QOS", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_REGION", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
|
||||
S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
|
||||
S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "32");
|
||||
S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16");
|
||||
S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "256");
|
||||
S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
|
||||
S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
|
||||
S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
|
||||
S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_RESET", "1");
|
||||
S_AXI_transactor_param_props.addFloat("PHASE", "0.0");
|
||||
S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
|
||||
S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
|
||||
S_AXI_transactor_param_props.addString("CLK_DOMAIN", "top_xdma_0_0_axi_aclk");
|
||||
|
||||
mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<32,16,1,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
|
||||
mp_S_AXI_transactor->ARADDR(s_axi_araddr);
|
||||
mp_S_AXI_transactor->ARBURST(s_axi_arburst);
|
||||
mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
|
||||
mp_S_AXI_transactor->ARLEN(s_axi_arlen);
|
||||
mp_S_AXI_transactor->ARLOCK(s_axi_arlock);
|
||||
mp_S_AXI_transactor->ARPROT(s_axi_arprot);
|
||||
mp_S_AXI_transactor->ARREADY(s_axi_arready);
|
||||
mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
|
||||
mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
|
||||
mp_S_AXI_transactor->AWADDR(s_axi_awaddr);
|
||||
mp_S_AXI_transactor->AWBURST(s_axi_awburst);
|
||||
mp_S_AXI_transactor->AWCACHE(s_axi_awcache);
|
||||
mp_S_AXI_transactor->AWLEN(s_axi_awlen);
|
||||
mp_S_AXI_transactor->AWLOCK(s_axi_awlock);
|
||||
mp_S_AXI_transactor->AWPROT(s_axi_awprot);
|
||||
mp_S_AXI_transactor->AWREADY(s_axi_awready);
|
||||
mp_S_AXI_transactor->AWSIZE(s_axi_awsize);
|
||||
mp_S_AXI_transactor->AWVALID(s_axi_awvalid);
|
||||
mp_S_AXI_transactor->BREADY(s_axi_bready);
|
||||
mp_S_AXI_transactor->BRESP(s_axi_bresp);
|
||||
mp_S_AXI_transactor->BVALID(s_axi_bvalid);
|
||||
mp_S_AXI_transactor->RDATA(s_axi_rdata);
|
||||
mp_S_AXI_transactor->RLAST(s_axi_rlast);
|
||||
mp_S_AXI_transactor->RREADY(s_axi_rready);
|
||||
mp_S_AXI_transactor->RRESP(s_axi_rresp);
|
||||
mp_S_AXI_transactor->RVALID(s_axi_rvalid);
|
||||
mp_S_AXI_transactor->WDATA(s_axi_wdata);
|
||||
mp_S_AXI_transactor->WLAST(s_axi_wlast);
|
||||
mp_S_AXI_transactor->WREADY(s_axi_wready);
|
||||
mp_S_AXI_transactor->WSTRB(s_axi_wstrb);
|
||||
mp_S_AXI_transactor->WVALID(s_axi_wvalid);
|
||||
mp_S_AXI_transactor->CLK(s_axi_aclk);
|
||||
mp_S_AXI_transactor->RST(s_axi_aresetn);
|
||||
|
||||
// initialize transactors stubs
|
||||
S_AXI_transactor_target_wr_socket_stub = nullptr;
|
||||
S_AXI_transactor_target_rd_socket_stub = nullptr;
|
||||
|
||||
}
|
||||
|
||||
void top_axi_bram_ctrl_0_0::before_end_of_elaboration()
|
||||
{
|
||||
// configure 'S_AXI' transactor
|
||||
if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("top_axi_bram_ctrl_0_0", "S_AXI_TLM_MODE") != 1)
|
||||
{
|
||||
mp_impl->target_0_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
|
||||
mp_impl->target_0_wr_socket->bind(*(mp_S_AXI_transactor->wr_socket));
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
S_AXI_transactor_target_wr_socket_stub = new xtlm::xtlm_aximm_target_stub("wr_socket",0);
|
||||
S_AXI_transactor_target_wr_socket_stub->bind(*(mp_S_AXI_transactor->wr_socket));
|
||||
S_AXI_transactor_target_rd_socket_stub = new xtlm::xtlm_aximm_target_stub("rd_socket",0);
|
||||
S_AXI_transactor_target_rd_socket_stub->bind(*(mp_S_AXI_transactor->rd_socket));
|
||||
mp_S_AXI_transactor->disable_transactor();
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
#endif // VCSSYSTEMC
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef MTI_SYSTEMC
|
||||
top_axi_bram_ctrl_0_0::top_axi_bram_ctrl_0_0(const sc_core::sc_module_name& nm) : top_axi_bram_ctrl_0_0_sc(nm), s_axi_aclk("s_axi_aclk"), s_axi_aresetn("s_axi_aresetn"), s_axi_awaddr("s_axi_awaddr"), s_axi_awlen("s_axi_awlen"), s_axi_awsize("s_axi_awsize"), s_axi_awburst("s_axi_awburst"), s_axi_awlock("s_axi_awlock"), s_axi_awcache("s_axi_awcache"), s_axi_awprot("s_axi_awprot"), s_axi_awvalid("s_axi_awvalid"), s_axi_awready("s_axi_awready"), s_axi_wdata("s_axi_wdata"), s_axi_wstrb("s_axi_wstrb"), s_axi_wlast("s_axi_wlast"), s_axi_wvalid("s_axi_wvalid"), s_axi_wready("s_axi_wready"), s_axi_bresp("s_axi_bresp"), s_axi_bvalid("s_axi_bvalid"), s_axi_bready("s_axi_bready"), s_axi_araddr("s_axi_araddr"), s_axi_arlen("s_axi_arlen"), s_axi_arsize("s_axi_arsize"), s_axi_arburst("s_axi_arburst"), s_axi_arlock("s_axi_arlock"), s_axi_arcache("s_axi_arcache"), s_axi_arprot("s_axi_arprot"), s_axi_arvalid("s_axi_arvalid"), s_axi_arready("s_axi_arready"), s_axi_rdata("s_axi_rdata"), s_axi_rresp("s_axi_rresp"), s_axi_rlast("s_axi_rlast"), s_axi_rvalid("s_axi_rvalid"), s_axi_rready("s_axi_rready"), bram_rst_a("bram_rst_a"), bram_clk_a("bram_clk_a"), bram_en_a("bram_en_a"), bram_we_a("bram_we_a"), bram_addr_a("bram_addr_a"), bram_wrdata_a("bram_wrdata_a"), bram_rddata_a("bram_rddata_a"), bram_rst_b("bram_rst_b"), bram_clk_b("bram_clk_b"), bram_en_b("bram_en_b"), bram_we_b("bram_we_b"), bram_addr_b("bram_addr_b"), bram_wrdata_b("bram_wrdata_b"), bram_rddata_b("bram_rddata_b")
|
||||
{
|
||||
// initialize pins
|
||||
mp_impl->s_axi_aclk(s_axi_aclk);
|
||||
mp_impl->s_axi_aresetn(s_axi_aresetn);
|
||||
mp_impl->bram_rst_a(bram_rst_a);
|
||||
mp_impl->bram_clk_a(bram_clk_a);
|
||||
mp_impl->bram_en_a(bram_en_a);
|
||||
mp_impl->bram_we_a(bram_we_a);
|
||||
mp_impl->bram_addr_a(bram_addr_a);
|
||||
mp_impl->bram_wrdata_a(bram_wrdata_a);
|
||||
mp_impl->bram_rddata_a(bram_rddata_a);
|
||||
mp_impl->bram_rst_b(bram_rst_b);
|
||||
mp_impl->bram_clk_b(bram_clk_b);
|
||||
mp_impl->bram_en_b(bram_en_b);
|
||||
mp_impl->bram_we_b(bram_we_b);
|
||||
mp_impl->bram_addr_b(bram_addr_b);
|
||||
mp_impl->bram_wrdata_b(bram_wrdata_b);
|
||||
mp_impl->bram_rddata_b(bram_rddata_b);
|
||||
|
||||
// initialize transactors
|
||||
mp_S_AXI_transactor = NULL;
|
||||
|
||||
// Instantiate Socket Stubs
|
||||
|
||||
// configure S_AXI_transactor
|
||||
xsc::common_cpp::properties S_AXI_transactor_param_props;
|
||||
S_AXI_transactor_param_props.addLong("DATA_WIDTH", "32");
|
||||
S_AXI_transactor_param_props.addLong("FREQ_HZ", "125000000");
|
||||
S_AXI_transactor_param_props.addLong("ID_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("ADDR_WIDTH", "16");
|
||||
S_AXI_transactor_param_props.addLong("AWUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("ARUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("WUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("RUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("BUSER_WIDTH", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_BURST", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_LOCK", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_PROT", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_CACHE", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_QOS", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_REGION", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_WSTRB", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_BRESP", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_RRESP", "1");
|
||||
S_AXI_transactor_param_props.addLong("SUPPORTS_NARROW_BURST", "0");
|
||||
S_AXI_transactor_param_props.addLong("NUM_READ_OUTSTANDING", "32");
|
||||
S_AXI_transactor_param_props.addLong("NUM_WRITE_OUTSTANDING", "16");
|
||||
S_AXI_transactor_param_props.addLong("MAX_BURST_LENGTH", "256");
|
||||
S_AXI_transactor_param_props.addLong("NUM_READ_THREADS", "1");
|
||||
S_AXI_transactor_param_props.addLong("NUM_WRITE_THREADS", "1");
|
||||
S_AXI_transactor_param_props.addLong("RUSER_BITS_PER_BYTE", "0");
|
||||
S_AXI_transactor_param_props.addLong("WUSER_BITS_PER_BYTE", "0");
|
||||
S_AXI_transactor_param_props.addLong("HAS_SIZE", "1");
|
||||
S_AXI_transactor_param_props.addLong("HAS_RESET", "1");
|
||||
S_AXI_transactor_param_props.addFloat("PHASE", "0.0");
|
||||
S_AXI_transactor_param_props.addString("PROTOCOL", "AXI4");
|
||||
S_AXI_transactor_param_props.addString("READ_WRITE_MODE", "READ_WRITE");
|
||||
S_AXI_transactor_param_props.addString("CLK_DOMAIN", "top_xdma_0_0_axi_aclk");
|
||||
|
||||
mp_S_AXI_transactor = new xtlm::xaximm_pin2xtlm_t<32,16,1,1,1,1,1,1>("S_AXI_transactor", S_AXI_transactor_param_props);
|
||||
mp_S_AXI_transactor->ARADDR(s_axi_araddr);
|
||||
mp_S_AXI_transactor->ARBURST(s_axi_arburst);
|
||||
mp_S_AXI_transactor->ARCACHE(s_axi_arcache);
|
||||
mp_S_AXI_transactor->ARLEN(s_axi_arlen);
|
||||
mp_S_AXI_transactor->ARLOCK(s_axi_arlock);
|
||||
mp_S_AXI_transactor->ARPROT(s_axi_arprot);
|
||||
mp_S_AXI_transactor->ARREADY(s_axi_arready);
|
||||
mp_S_AXI_transactor->ARSIZE(s_axi_arsize);
|
||||
mp_S_AXI_transactor->ARVALID(s_axi_arvalid);
|
||||
mp_S_AXI_transactor->AWADDR(s_axi_awaddr);
|
||||
mp_S_AXI_transactor->AWBURST(s_axi_awburst);
|
||||
mp_S_AXI_transactor->AWCACHE(s_axi_awcache);
|
||||
mp_S_AXI_transactor->AWLEN(s_axi_awlen);
|
||||
mp_S_AXI_transactor->AWLOCK(s_axi_awlock);
|
||||
mp_S_AXI_transactor->AWPROT(s_axi_awprot);
|
||||
mp_S_AXI_transactor->AWREADY(s_axi_awready);
|
||||
mp_S_AXI_transactor->AWSIZE(s_axi_awsize);
|
||||
mp_S_AXI_transactor->AWVALID(s_axi_awvalid);
|
||||
mp_S_AXI_transactor->BREADY(s_axi_bready);
|
||||
mp_S_AXI_transactor->BRESP(s_axi_bresp);
|
||||
mp_S_AXI_transactor->BVALID(s_axi_bvalid);
|
||||
mp_S_AXI_transactor->RDATA(s_axi_rdata);
|
||||
mp_S_AXI_transactor->RLAST(s_axi_rlast);
|
||||
mp_S_AXI_transactor->RREADY(s_axi_rready);
|
||||
mp_S_AXI_transactor->RRESP(s_axi_rresp);
|
||||
mp_S_AXI_transactor->RVALID(s_axi_rvalid);
|
||||
mp_S_AXI_transactor->WDATA(s_axi_wdata);
|
||||
mp_S_AXI_transactor->WLAST(s_axi_wlast);
|
||||
mp_S_AXI_transactor->WREADY(s_axi_wready);
|
||||
mp_S_AXI_transactor->WSTRB(s_axi_wstrb);
|
||||
mp_S_AXI_transactor->WVALID(s_axi_wvalid);
|
||||
mp_S_AXI_transactor->CLK(s_axi_aclk);
|
||||
mp_S_AXI_transactor->RST(s_axi_aresetn);
|
||||
|
||||
// initialize transactors stubs
|
||||
S_AXI_transactor_target_wr_socket_stub = nullptr;
|
||||
S_AXI_transactor_target_rd_socket_stub = nullptr;
|
||||
|
||||
}
|
||||
|
||||
void top_axi_bram_ctrl_0_0::before_end_of_elaboration()
|
||||
{
|
||||
// configure 'S_AXI' transactor
|
||||
if (xsc::utils::xsc_sim_manager::getInstanceParameterInt("top_axi_bram_ctrl_0_0", "S_AXI_TLM_MODE") != 1)
|
||||
{
|
||||
mp_impl->target_0_rd_socket->bind(*(mp_S_AXI_transactor->rd_socket));
|
||||
mp_impl->target_0_wr_socket->bind(*(mp_S_AXI_transactor->wr_socket));
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
S_AXI_transactor_target_wr_socket_stub = new xtlm::xtlm_aximm_target_stub("wr_socket",0);
|
||||
S_AXI_transactor_target_wr_socket_stub->bind(*(mp_S_AXI_transactor->wr_socket));
|
||||
S_AXI_transactor_target_rd_socket_stub = new xtlm::xtlm_aximm_target_stub("rd_socket",0);
|
||||
S_AXI_transactor_target_rd_socket_stub->bind(*(mp_S_AXI_transactor->rd_socket));
|
||||
mp_S_AXI_transactor->disable_transactor();
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
#endif // MTI_SYSTEMC
|
||||
|
||||
|
||||
|
||||
|
||||
top_axi_bram_ctrl_0_0::~top_axi_bram_ctrl_0_0()
|
||||
{
|
||||
delete mp_S_AXI_transactor;
|
||||
|
||||
}
|
||||
|
||||
#ifdef MTI_SYSTEMC
|
||||
SC_MODULE_EXPORT(top_axi_bram_ctrl_0_0);
|
||||
#endif
|
||||
|
||||
#ifdef XM_SYSTEMC
|
||||
XMSC_MODULE_EXPORT(top_axi_bram_ctrl_0_0);
|
||||
#endif
|
||||
|
||||
#ifdef RIVIERA
|
||||
SC_MODULE_EXPORT(top_axi_bram_ctrl_0_0);
|
||||
#endif
|
||||
|
||||
|
|
@ -0,0 +1,460 @@
|
|||
#ifndef IP_TOP_AXI_BRAM_CTRL_0_0_H_
|
||||
#define IP_TOP_AXI_BRAM_CTRL_0_0_H_
|
||||
|
||||
// (c) Copyright 1995-2025 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
#ifndef XTLM
|
||||
#include "xtlm.h"
|
||||
#endif
|
||||
#ifndef SYSTEMC_INCLUDED
|
||||
#include <systemc>
|
||||
#endif
|
||||
|
||||
#if defined(_MSC_VER)
|
||||
#define DllExport __declspec(dllexport)
|
||||
#elif defined(__GNUC__)
|
||||
#define DllExport __attribute__ ((visibility("default")))
|
||||
#else
|
||||
#define DllExport
|
||||
#endif
|
||||
|
||||
#include "top_axi_bram_ctrl_0_0_sc.h"
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef XILINX_SIMULATOR
|
||||
class DllExport top_axi_bram_ctrl_0_0 : public top_axi_bram_ctrl_0_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
top_axi_bram_ctrl_0_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~top_axi_bram_ctrl_0_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > s_axi_aclk;
|
||||
sc_core::sc_in< bool > s_axi_aresetn;
|
||||
sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_awaddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||
sc_core::sc_in< bool > s_axi_awlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||
sc_core::sc_in< bool > s_axi_awvalid;
|
||||
sc_core::sc_out< bool > s_axi_awready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||
sc_core::sc_in< bool > s_axi_wlast;
|
||||
sc_core::sc_in< bool > s_axi_wvalid;
|
||||
sc_core::sc_out< bool > s_axi_wready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||
sc_core::sc_out< bool > s_axi_bvalid;
|
||||
sc_core::sc_in< bool > s_axi_bready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_araddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||
sc_core::sc_in< bool > s_axi_arlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||
sc_core::sc_in< bool > s_axi_arvalid;
|
||||
sc_core::sc_out< bool > s_axi_arready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||
sc_core::sc_out< bool > s_axi_rlast;
|
||||
sc_core::sc_out< bool > s_axi_rvalid;
|
||||
sc_core::sc_in< bool > s_axi_rready;
|
||||
sc_core::sc_out< bool > bram_rst_a;
|
||||
sc_core::sc_out< bool > bram_clk_a;
|
||||
sc_core::sc_out< bool > bram_en_a;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > bram_we_a;
|
||||
sc_core::sc_out< sc_dt::sc_bv<16> > bram_addr_a;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > bram_wrdata_a;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > bram_rddata_a;
|
||||
sc_core::sc_out< bool > bram_rst_b;
|
||||
sc_core::sc_out< bool > bram_clk_b;
|
||||
sc_core::sc_out< bool > bram_en_b;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > bram_we_b;
|
||||
sc_core::sc_out< sc_dt::sc_bv<16> > bram_addr_b;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > bram_wrdata_b;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > bram_rddata_b;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,16,1,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||
|
||||
};
|
||||
#endif // XILINX_SIMULATOR
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef XM_SYSTEMC
|
||||
class DllExport top_axi_bram_ctrl_0_0 : public top_axi_bram_ctrl_0_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
top_axi_bram_ctrl_0_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~top_axi_bram_ctrl_0_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > s_axi_aclk;
|
||||
sc_core::sc_in< bool > s_axi_aresetn;
|
||||
sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_awaddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||
sc_core::sc_in< bool > s_axi_awlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||
sc_core::sc_in< bool > s_axi_awvalid;
|
||||
sc_core::sc_out< bool > s_axi_awready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||
sc_core::sc_in< bool > s_axi_wlast;
|
||||
sc_core::sc_in< bool > s_axi_wvalid;
|
||||
sc_core::sc_out< bool > s_axi_wready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||
sc_core::sc_out< bool > s_axi_bvalid;
|
||||
sc_core::sc_in< bool > s_axi_bready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_araddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||
sc_core::sc_in< bool > s_axi_arlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||
sc_core::sc_in< bool > s_axi_arvalid;
|
||||
sc_core::sc_out< bool > s_axi_arready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||
sc_core::sc_out< bool > s_axi_rlast;
|
||||
sc_core::sc_out< bool > s_axi_rvalid;
|
||||
sc_core::sc_in< bool > s_axi_rready;
|
||||
sc_core::sc_out< bool > bram_rst_a;
|
||||
sc_core::sc_out< bool > bram_clk_a;
|
||||
sc_core::sc_out< bool > bram_en_a;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > bram_we_a;
|
||||
sc_core::sc_out< sc_dt::sc_bv<16> > bram_addr_a;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > bram_wrdata_a;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > bram_rddata_a;
|
||||
sc_core::sc_out< bool > bram_rst_b;
|
||||
sc_core::sc_out< bool > bram_clk_b;
|
||||
sc_core::sc_out< bool > bram_en_b;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > bram_we_b;
|
||||
sc_core::sc_out< sc_dt::sc_bv<16> > bram_addr_b;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > bram_wrdata_b;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > bram_rddata_b;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,16,1,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||
|
||||
};
|
||||
#endif // XM_SYSTEMC
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef RIVIERA
|
||||
class DllExport top_axi_bram_ctrl_0_0 : public top_axi_bram_ctrl_0_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
top_axi_bram_ctrl_0_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~top_axi_bram_ctrl_0_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > s_axi_aclk;
|
||||
sc_core::sc_in< bool > s_axi_aresetn;
|
||||
sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_awaddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||
sc_core::sc_in< bool > s_axi_awlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||
sc_core::sc_in< bool > s_axi_awvalid;
|
||||
sc_core::sc_out< bool > s_axi_awready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||
sc_core::sc_in< bool > s_axi_wlast;
|
||||
sc_core::sc_in< bool > s_axi_wvalid;
|
||||
sc_core::sc_out< bool > s_axi_wready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||
sc_core::sc_out< bool > s_axi_bvalid;
|
||||
sc_core::sc_in< bool > s_axi_bready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_araddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||
sc_core::sc_in< bool > s_axi_arlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||
sc_core::sc_in< bool > s_axi_arvalid;
|
||||
sc_core::sc_out< bool > s_axi_arready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||
sc_core::sc_out< bool > s_axi_rlast;
|
||||
sc_core::sc_out< bool > s_axi_rvalid;
|
||||
sc_core::sc_in< bool > s_axi_rready;
|
||||
sc_core::sc_out< bool > bram_rst_a;
|
||||
sc_core::sc_out< bool > bram_clk_a;
|
||||
sc_core::sc_out< bool > bram_en_a;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > bram_we_a;
|
||||
sc_core::sc_out< sc_dt::sc_bv<16> > bram_addr_a;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > bram_wrdata_a;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > bram_rddata_a;
|
||||
sc_core::sc_out< bool > bram_rst_b;
|
||||
sc_core::sc_out< bool > bram_clk_b;
|
||||
sc_core::sc_out< bool > bram_en_b;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > bram_we_b;
|
||||
sc_core::sc_out< sc_dt::sc_bv<16> > bram_addr_b;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > bram_wrdata_b;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > bram_rddata_b;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,16,1,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||
|
||||
};
|
||||
#endif // RIVIERA
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef VCSSYSTEMC
|
||||
#include "utils/xtlm_aximm_target_stub.h"
|
||||
|
||||
class DllExport top_axi_bram_ctrl_0_0 : public top_axi_bram_ctrl_0_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
top_axi_bram_ctrl_0_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~top_axi_bram_ctrl_0_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > s_axi_aclk;
|
||||
sc_core::sc_in< bool > s_axi_aresetn;
|
||||
sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_awaddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||
sc_core::sc_in< bool > s_axi_awlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||
sc_core::sc_in< bool > s_axi_awvalid;
|
||||
sc_core::sc_out< bool > s_axi_awready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||
sc_core::sc_in< bool > s_axi_wlast;
|
||||
sc_core::sc_in< bool > s_axi_wvalid;
|
||||
sc_core::sc_out< bool > s_axi_wready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||
sc_core::sc_out< bool > s_axi_bvalid;
|
||||
sc_core::sc_in< bool > s_axi_bready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_araddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||
sc_core::sc_in< bool > s_axi_arlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||
sc_core::sc_in< bool > s_axi_arvalid;
|
||||
sc_core::sc_out< bool > s_axi_arready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||
sc_core::sc_out< bool > s_axi_rlast;
|
||||
sc_core::sc_out< bool > s_axi_rvalid;
|
||||
sc_core::sc_in< bool > s_axi_rready;
|
||||
sc_core::sc_out< bool > bram_rst_a;
|
||||
sc_core::sc_out< bool > bram_clk_a;
|
||||
sc_core::sc_out< bool > bram_en_a;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > bram_we_a;
|
||||
sc_core::sc_out< sc_dt::sc_bv<16> > bram_addr_a;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > bram_wrdata_a;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > bram_rddata_a;
|
||||
sc_core::sc_out< bool > bram_rst_b;
|
||||
sc_core::sc_out< bool > bram_clk_b;
|
||||
sc_core::sc_out< bool > bram_en_b;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > bram_we_b;
|
||||
sc_core::sc_out< sc_dt::sc_bv<16> > bram_addr_b;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > bram_wrdata_b;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > bram_rddata_b;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,16,1,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||
|
||||
// Transactor stubs
|
||||
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
|
||||
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_wr_socket_stub;
|
||||
|
||||
// Socket stubs
|
||||
|
||||
};
|
||||
#endif // VCSSYSTEMC
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef MTI_SYSTEMC
|
||||
#include "utils/xtlm_aximm_target_stub.h"
|
||||
|
||||
class DllExport top_axi_bram_ctrl_0_0 : public top_axi_bram_ctrl_0_0_sc
|
||||
{
|
||||
public:
|
||||
|
||||
top_axi_bram_ctrl_0_0(const sc_core::sc_module_name& nm);
|
||||
virtual ~top_axi_bram_ctrl_0_0();
|
||||
|
||||
// module pin-to-pin RTL interface
|
||||
|
||||
sc_core::sc_in< bool > s_axi_aclk;
|
||||
sc_core::sc_in< bool > s_axi_aresetn;
|
||||
sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_awaddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
|
||||
sc_core::sc_in< bool > s_axi_awlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
|
||||
sc_core::sc_in< bool > s_axi_awvalid;
|
||||
sc_core::sc_out< bool > s_axi_awready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
|
||||
sc_core::sc_in< bool > s_axi_wlast;
|
||||
sc_core::sc_in< bool > s_axi_wvalid;
|
||||
sc_core::sc_out< bool > s_axi_wready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
|
||||
sc_core::sc_out< bool > s_axi_bvalid;
|
||||
sc_core::sc_in< bool > s_axi_bready;
|
||||
sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_araddr;
|
||||
sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
|
||||
sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
|
||||
sc_core::sc_in< bool > s_axi_arlock;
|
||||
sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
|
||||
sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
|
||||
sc_core::sc_in< bool > s_axi_arvalid;
|
||||
sc_core::sc_out< bool > s_axi_arready;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
|
||||
sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
|
||||
sc_core::sc_out< bool > s_axi_rlast;
|
||||
sc_core::sc_out< bool > s_axi_rvalid;
|
||||
sc_core::sc_in< bool > s_axi_rready;
|
||||
sc_core::sc_out< bool > bram_rst_a;
|
||||
sc_core::sc_out< bool > bram_clk_a;
|
||||
sc_core::sc_out< bool > bram_en_a;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > bram_we_a;
|
||||
sc_core::sc_out< sc_dt::sc_bv<16> > bram_addr_a;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > bram_wrdata_a;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > bram_rddata_a;
|
||||
sc_core::sc_out< bool > bram_rst_b;
|
||||
sc_core::sc_out< bool > bram_clk_b;
|
||||
sc_core::sc_out< bool > bram_en_b;
|
||||
sc_core::sc_out< sc_dt::sc_bv<4> > bram_we_b;
|
||||
sc_core::sc_out< sc_dt::sc_bv<16> > bram_addr_b;
|
||||
sc_core::sc_out< sc_dt::sc_bv<32> > bram_wrdata_b;
|
||||
sc_core::sc_in< sc_dt::sc_bv<32> > bram_rddata_b;
|
||||
|
||||
// Dummy Signals for IP Ports
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
virtual void before_end_of_elaboration();
|
||||
|
||||
private:
|
||||
|
||||
xtlm::xaximm_pin2xtlm_t<32,16,1,1,1,1,1,1>* mp_S_AXI_transactor;
|
||||
|
||||
// Transactor stubs
|
||||
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
|
||||
xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_wr_socket_stub;
|
||||
|
||||
// Socket stubs
|
||||
|
||||
};
|
||||
#endif // MTI_SYSTEMC
|
||||
#endif // IP_TOP_AXI_BRAM_CTRL_0_0_H_
|
||||
|
|
@ -0,0 +1,343 @@
|
|||
-- (c) Copyright 1995-2025 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:axi_bram_ctrl:4.1
|
||||
-- IP Revision: 6
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY axi_bram_ctrl_v4_1_6;
|
||||
USE axi_bram_ctrl_v4_1_6.axi_bram_ctrl;
|
||||
|
||||
ENTITY top_axi_bram_ctrl_0_0 IS
|
||||
PORT (
|
||||
s_axi_aclk : IN STD_LOGIC;
|
||||
s_axi_aresetn : IN STD_LOGIC;
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_awlock : IN STD_LOGIC;
|
||||
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_wlast : IN STD_LOGIC;
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_arlock : IN STD_LOGIC;
|
||||
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rlast : OUT STD_LOGIC;
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
bram_rst_a : OUT STD_LOGIC;
|
||||
bram_clk_a : OUT STD_LOGIC;
|
||||
bram_en_a : OUT STD_LOGIC;
|
||||
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
bram_addr_a : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
bram_rst_b : OUT STD_LOGIC;
|
||||
bram_clk_b : OUT STD_LOGIC;
|
||||
bram_en_b : OUT STD_LOGIC;
|
||||
bram_we_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
bram_addr_b : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
bram_wrdata_b : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
bram_rddata_b : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END top_axi_bram_ctrl_0_0;
|
||||
|
||||
ARCHITECTURE top_axi_bram_ctrl_0_0_arch OF top_axi_bram_ctrl_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF top_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axi_bram_ctrl IS
|
||||
GENERIC (
|
||||
C_BRAM_INST_MODE : STRING;
|
||||
C_MEMORY_DEPTH : INTEGER;
|
||||
C_BRAM_ADDR_WIDTH : INTEGER;
|
||||
C_S_AXI_ADDR_WIDTH : INTEGER;
|
||||
C_S_AXI_DATA_WIDTH : INTEGER;
|
||||
C_S_AXI_ID_WIDTH : INTEGER;
|
||||
C_S_AXI_PROTOCOL : STRING;
|
||||
C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER;
|
||||
C_SINGLE_PORT_BRAM : INTEGER;
|
||||
C_FAMILY : STRING;
|
||||
C_READ_LATENCY : INTEGER;
|
||||
C_RD_CMD_OPTIMIZATION : INTEGER;
|
||||
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
|
||||
C_S_AXI_CTRL_DATA_WIDTH : INTEGER;
|
||||
C_ECC : INTEGER;
|
||||
C_ECC_TYPE : INTEGER;
|
||||
C_FAULT_INJECT : INTEGER;
|
||||
C_ECC_ONOFF_RESET_VALUE : INTEGER
|
||||
);
|
||||
PORT (
|
||||
s_axi_aclk : IN STD_LOGIC;
|
||||
s_axi_aresetn : IN STD_LOGIC;
|
||||
ecc_interrupt : OUT STD_LOGIC;
|
||||
ecc_ue : OUT STD_LOGIC;
|
||||
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_awlock : IN STD_LOGIC;
|
||||
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_wlast : IN STD_LOGIC;
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_arlock : IN STD_LOGIC;
|
||||
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rlast : OUT STD_LOGIC;
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
s_axi_ctrl_awvalid : IN STD_LOGIC;
|
||||
s_axi_ctrl_awready : OUT STD_LOGIC;
|
||||
s_axi_ctrl_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_ctrl_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_ctrl_wvalid : IN STD_LOGIC;
|
||||
s_axi_ctrl_wready : OUT STD_LOGIC;
|
||||
s_axi_ctrl_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_ctrl_bvalid : OUT STD_LOGIC;
|
||||
s_axi_ctrl_bready : IN STD_LOGIC;
|
||||
s_axi_ctrl_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_ctrl_arvalid : IN STD_LOGIC;
|
||||
s_axi_ctrl_arready : OUT STD_LOGIC;
|
||||
s_axi_ctrl_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_ctrl_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_ctrl_rvalid : OUT STD_LOGIC;
|
||||
s_axi_ctrl_rready : IN STD_LOGIC;
|
||||
bram_rst_a : OUT STD_LOGIC;
|
||||
bram_clk_a : OUT STD_LOGIC;
|
||||
bram_en_a : OUT STD_LOGIC;
|
||||
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
bram_addr_a : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
bram_rst_b : OUT STD_LOGIC;
|
||||
bram_clk_b : OUT STD_LOGIC;
|
||||
bram_en_b : OUT STD_LOGIC;
|
||||
bram_we_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
bram_addr_b : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
bram_wrdata_b : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
bram_rddata_b : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT axi_bram_ctrl;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_addr_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_addr_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_clk_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_clk_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_en_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_en_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_rddata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_rddata_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF bram_rst_a: SIGNAL IS "XIL_INTERFACENAME BRAM_PORTA, MASTER_TYPE BRAM_CTRL, MEM_SIZE 65536, MEM_WIDTH 32, MEM_ECC NONE, READ_WRITE_MODE WRITE_ONLY, READ_LATENCY 1";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_rst_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF bram_rst_b: SIGNAL IS "XIL_INTERFACENAME BRAM_PORTB, MASTER_TYPE BRAM_CTRL, MEM_SIZE 65536, MEM_WIDTH 32, MEM_ECC NONE, READ_WRITE_MODE READ_ONLY, READ_LATENCY 1";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_rst_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_we_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_we_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_wrdata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_wrdata_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME CLKIF, ASSOCIATED_BUSIF S_AXI:S_AXI_CTRL, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 125000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN top_xdma_0_0_axi_aclk, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLKIF CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARBURST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 RSTIF RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLEN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARPROT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 125000000, ID_WIDTH 0, ADDR_WIDTH 16, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 32, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 256, PHASE 0.0, CLK_DOMAIN top_xdma_0_0_axi_aclk, NUM_READ_THREADS 1, NUM_WRITE_THREADS" &
|
||||
" 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWBURST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLEN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWPROT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
|
||||
BEGIN
|
||||
U0 : axi_bram_ctrl
|
||||
GENERIC MAP (
|
||||
C_BRAM_INST_MODE => "EXTERNAL",
|
||||
C_MEMORY_DEPTH => 16384,
|
||||
C_BRAM_ADDR_WIDTH => 14,
|
||||
C_S_AXI_ADDR_WIDTH => 16,
|
||||
C_S_AXI_DATA_WIDTH => 32,
|
||||
C_S_AXI_ID_WIDTH => 1,
|
||||
C_S_AXI_PROTOCOL => "AXI4",
|
||||
C_S_AXI_SUPPORTS_NARROW_BURST => 0,
|
||||
C_SINGLE_PORT_BRAM => 0,
|
||||
C_FAMILY => "artix7",
|
||||
C_READ_LATENCY => 1,
|
||||
C_RD_CMD_OPTIMIZATION => 0,
|
||||
C_S_AXI_CTRL_ADDR_WIDTH => 32,
|
||||
C_S_AXI_CTRL_DATA_WIDTH => 32,
|
||||
C_ECC => 0,
|
||||
C_ECC_TYPE => 0,
|
||||
C_FAULT_INJECT => 0,
|
||||
C_ECC_ONOFF_RESET_VALUE => 0
|
||||
)
|
||||
PORT MAP (
|
||||
s_axi_aclk => s_axi_aclk,
|
||||
s_axi_aresetn => s_axi_aresetn,
|
||||
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axi_awaddr => s_axi_awaddr,
|
||||
s_axi_awlen => s_axi_awlen,
|
||||
s_axi_awsize => s_axi_awsize,
|
||||
s_axi_awburst => s_axi_awburst,
|
||||
s_axi_awlock => s_axi_awlock,
|
||||
s_axi_awcache => s_axi_awcache,
|
||||
s_axi_awprot => s_axi_awprot,
|
||||
s_axi_awvalid => s_axi_awvalid,
|
||||
s_axi_awready => s_axi_awready,
|
||||
s_axi_wdata => s_axi_wdata,
|
||||
s_axi_wstrb => s_axi_wstrb,
|
||||
s_axi_wlast => s_axi_wlast,
|
||||
s_axi_wvalid => s_axi_wvalid,
|
||||
s_axi_wready => s_axi_wready,
|
||||
s_axi_bresp => s_axi_bresp,
|
||||
s_axi_bvalid => s_axi_bvalid,
|
||||
s_axi_bready => s_axi_bready,
|
||||
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axi_araddr => s_axi_araddr,
|
||||
s_axi_arlen => s_axi_arlen,
|
||||
s_axi_arsize => s_axi_arsize,
|
||||
s_axi_arburst => s_axi_arburst,
|
||||
s_axi_arlock => s_axi_arlock,
|
||||
s_axi_arcache => s_axi_arcache,
|
||||
s_axi_arprot => s_axi_arprot,
|
||||
s_axi_arvalid => s_axi_arvalid,
|
||||
s_axi_arready => s_axi_arready,
|
||||
s_axi_rdata => s_axi_rdata,
|
||||
s_axi_rresp => s_axi_rresp,
|
||||
s_axi_rlast => s_axi_rlast,
|
||||
s_axi_rvalid => s_axi_rvalid,
|
||||
s_axi_rready => s_axi_rready,
|
||||
s_axi_ctrl_awvalid => '0',
|
||||
s_axi_ctrl_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
s_axi_ctrl_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
s_axi_ctrl_wvalid => '0',
|
||||
s_axi_ctrl_bready => '0',
|
||||
s_axi_ctrl_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
s_axi_ctrl_arvalid => '0',
|
||||
s_axi_ctrl_rready => '0',
|
||||
bram_rst_a => bram_rst_a,
|
||||
bram_clk_a => bram_clk_a,
|
||||
bram_en_a => bram_en_a,
|
||||
bram_we_a => bram_we_a,
|
||||
bram_addr_a => bram_addr_a,
|
||||
bram_wrdata_a => bram_wrdata_a,
|
||||
bram_rddata_a => bram_rddata_a,
|
||||
bram_rst_b => bram_rst_b,
|
||||
bram_clk_b => bram_clk_b,
|
||||
bram_en_b => bram_en_b,
|
||||
bram_we_b => bram_we_b,
|
||||
bram_addr_b => bram_addr_b,
|
||||
bram_wrdata_b => bram_wrdata_b,
|
||||
bram_rddata_b => bram_rddata_b
|
||||
);
|
||||
END top_axi_bram_ctrl_0_0_arch;
|
||||
|
|
@ -0,0 +1,97 @@
|
|||
// (c) Copyright 1995-2025 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
#include "top_axi_bram_ctrl_0_0_sc.h"
|
||||
|
||||
#include "axi_bram_ctrl.h"
|
||||
|
||||
#include <map>
|
||||
#include <string>
|
||||
|
||||
top_axi_bram_ctrl_0_0_sc::top_axi_bram_ctrl_0_0_sc(const sc_core::sc_module_name& nm) : sc_core::sc_module(nm), mp_impl(NULL)
|
||||
{
|
||||
// configure connectivity manager
|
||||
xsc::utils::xsc_sim_manager::addInstance("top_axi_bram_ctrl_0_0", this);
|
||||
|
||||
// initialize module
|
||||
xsc::common_cpp::properties model_param_props;
|
||||
model_param_props.addLong("C_MEMORY_DEPTH", "16384");
|
||||
model_param_props.addLong("C_BRAM_ADDR_WIDTH", "14");
|
||||
model_param_props.addLong("C_S_AXI_ADDR_WIDTH", "16");
|
||||
model_param_props.addLong("C_S_AXI_DATA_WIDTH", "32");
|
||||
model_param_props.addLong("C_S_AXI_ID_WIDTH", "1");
|
||||
model_param_props.addLong("C_S_AXI_SUPPORTS_NARROW_BURST", "0");
|
||||
model_param_props.addLong("C_SINGLE_PORT_BRAM", "0");
|
||||
model_param_props.addLong("C_READ_LATENCY", "1");
|
||||
model_param_props.addLong("C_RD_CMD_OPTIMIZATION", "0");
|
||||
model_param_props.addLong("C_S_AXI_CTRL_ADDR_WIDTH", "32");
|
||||
model_param_props.addLong("C_S_AXI_CTRL_DATA_WIDTH", "32");
|
||||
model_param_props.addLong("C_ECC", "0");
|
||||
model_param_props.addLong("C_ECC_TYPE", "0");
|
||||
model_param_props.addLong("C_FAULT_INJECT", "0");
|
||||
model_param_props.addLong("C_ECC_ONOFF_RESET_VALUE", "0");
|
||||
model_param_props.addString("C_BRAM_INST_MODE", "EXTERNAL");
|
||||
model_param_props.addString("C_S_AXI_PROTOCOL", "AXI4");
|
||||
model_param_props.addString("C_FAMILY", "artix7");
|
||||
model_param_props.addString("COMPONENT_NAME", "top_axi_bram_ctrl_0_0");
|
||||
|
||||
mp_impl = new axi_bram_ctrl("inst", model_param_props);
|
||||
|
||||
// initialize AXI sockets
|
||||
target_0_rd_socket = mp_impl->target_0_rd_socket;
|
||||
target_0_wr_socket = mp_impl->target_0_wr_socket;
|
||||
}
|
||||
|
||||
top_axi_bram_ctrl_0_0_sc::~top_axi_bram_ctrl_0_0_sc()
|
||||
{
|
||||
xsc::utils::xsc_sim_manager::clean();
|
||||
|
||||
delete mp_impl;
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,96 @@
|
|||
#ifndef IP_TOP_AXI_BRAM_CTRL_0_0_SC_H_
|
||||
#define IP_TOP_AXI_BRAM_CTRL_0_0_SC_H_
|
||||
|
||||
// (c) Copyright 1995-2025 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
#ifndef XTLM
|
||||
#include "xtlm.h"
|
||||
#endif
|
||||
#ifndef SYSTEMC_INCLUDED
|
||||
#include <systemc>
|
||||
#endif
|
||||
|
||||
#if defined(_MSC_VER)
|
||||
#define DllExport __declspec(dllexport)
|
||||
#elif defined(__GNUC__)
|
||||
#define DllExport __attribute__ ((visibility("default")))
|
||||
#else
|
||||
#define DllExport
|
||||
#endif
|
||||
|
||||
class axi_bram_ctrl;
|
||||
|
||||
class DllExport top_axi_bram_ctrl_0_0_sc : public sc_core::sc_module
|
||||
{
|
||||
public:
|
||||
|
||||
top_axi_bram_ctrl_0_0_sc(const sc_core::sc_module_name& nm);
|
||||
virtual ~top_axi_bram_ctrl_0_0_sc();
|
||||
|
||||
// module socket-to-socket AXI TLM interfaces
|
||||
|
||||
xtlm::xtlm_aximm_target_socket* target_0_rd_socket;
|
||||
xtlm::xtlm_aximm_target_socket* target_0_wr_socket;
|
||||
|
||||
// module socket-to-socket TLM interfaces
|
||||
|
||||
|
||||
protected:
|
||||
|
||||
axi_bram_ctrl* mp_impl;
|
||||
|
||||
private:
|
||||
|
||||
top_axi_bram_ctrl_0_0_sc(const top_axi_bram_ctrl_0_0_sc&);
|
||||
const top_axi_bram_ctrl_0_0_sc& operator=(const top_axi_bram_ctrl_0_0_sc&);
|
||||
|
||||
};
|
||||
|
||||
#endif // IP_TOP_AXI_BRAM_CTRL_0_0_SC_H_
|
||||
|
|
@ -0,0 +1,173 @@
|
|||
// (c) Copyright 1995-2025 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
//------------------------------------------------------------------------------------
|
||||
// Filename: top_axi_bram_ctrl_0_0_stub.sv
|
||||
// Description: This HDL file is intended to be used with following simulators only:
|
||||
//
|
||||
// Vivado Simulator (XSim)
|
||||
// Cadence Xcelium Simulator
|
||||
//
|
||||
//------------------------------------------------------------------------------------
|
||||
`timescale 1ps/1ps
|
||||
|
||||
`ifdef XILINX_SIMULATOR
|
||||
|
||||
`ifndef XILINX_SIMULATOR_BITASBOOL
|
||||
`define XILINX_SIMULATOR_BITASBOOL
|
||||
typedef bit bit_as_bool;
|
||||
`endif
|
||||
|
||||
(* SC_MODULE_EXPORT *)
|
||||
module top_axi_bram_ctrl_0_0 (
|
||||
input bit_as_bool s_axi_aclk,
|
||||
input bit_as_bool s_axi_aresetn,
|
||||
input bit [15 : 0] s_axi_awaddr,
|
||||
input bit [7 : 0] s_axi_awlen,
|
||||
input bit [2 : 0] s_axi_awsize,
|
||||
input bit [1 : 0] s_axi_awburst,
|
||||
input bit_as_bool s_axi_awlock,
|
||||
input bit [3 : 0] s_axi_awcache,
|
||||
input bit [2 : 0] s_axi_awprot,
|
||||
input bit_as_bool s_axi_awvalid,
|
||||
output bit_as_bool s_axi_awready,
|
||||
input bit [31 : 0] s_axi_wdata,
|
||||
input bit [3 : 0] s_axi_wstrb,
|
||||
input bit_as_bool s_axi_wlast,
|
||||
input bit_as_bool s_axi_wvalid,
|
||||
output bit_as_bool s_axi_wready,
|
||||
output bit [1 : 0] s_axi_bresp,
|
||||
output bit_as_bool s_axi_bvalid,
|
||||
input bit_as_bool s_axi_bready,
|
||||
input bit [15 : 0] s_axi_araddr,
|
||||
input bit [7 : 0] s_axi_arlen,
|
||||
input bit [2 : 0] s_axi_arsize,
|
||||
input bit [1 : 0] s_axi_arburst,
|
||||
input bit_as_bool s_axi_arlock,
|
||||
input bit [3 : 0] s_axi_arcache,
|
||||
input bit [2 : 0] s_axi_arprot,
|
||||
input bit_as_bool s_axi_arvalid,
|
||||
output bit_as_bool s_axi_arready,
|
||||
output bit [31 : 0] s_axi_rdata,
|
||||
output bit [1 : 0] s_axi_rresp,
|
||||
output bit_as_bool s_axi_rlast,
|
||||
output bit_as_bool s_axi_rvalid,
|
||||
input bit_as_bool s_axi_rready,
|
||||
output bit_as_bool bram_rst_a,
|
||||
output bit_as_bool bram_clk_a,
|
||||
output bit_as_bool bram_en_a,
|
||||
output bit [3 : 0] bram_we_a,
|
||||
output bit [15 : 0] bram_addr_a,
|
||||
output bit [31 : 0] bram_wrdata_a,
|
||||
input bit [31 : 0] bram_rddata_a,
|
||||
output bit_as_bool bram_rst_b,
|
||||
output bit_as_bool bram_clk_b,
|
||||
output bit_as_bool bram_en_b,
|
||||
output bit [3 : 0] bram_we_b,
|
||||
output bit [15 : 0] bram_addr_b,
|
||||
output bit [31 : 0] bram_wrdata_b,
|
||||
input bit [31 : 0] bram_rddata_b
|
||||
);
|
||||
endmodule
|
||||
`endif
|
||||
|
||||
`ifdef XCELIUM
|
||||
(* XMSC_MODULE_EXPORT *)
|
||||
module top_axi_bram_ctrl_0_0 (s_axi_aclk,s_axi_aresetn,s_axi_awaddr,s_axi_awlen,s_axi_awsize,s_axi_awburst,s_axi_awlock,s_axi_awcache,s_axi_awprot,s_axi_awvalid,s_axi_awready,s_axi_wdata,s_axi_wstrb,s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bresp,s_axi_bvalid,s_axi_bready,s_axi_araddr,s_axi_arlen,s_axi_arsize,s_axi_arburst,s_axi_arlock,s_axi_arcache,s_axi_arprot,s_axi_arvalid,s_axi_arready,s_axi_rdata,s_axi_rresp,s_axi_rlast,s_axi_rvalid,s_axi_rready,bram_rst_a,bram_clk_a,bram_en_a,bram_we_a,bram_addr_a,bram_wrdata_a,bram_rddata_a,bram_rst_b,bram_clk_b,bram_en_b,bram_we_b,bram_addr_b,bram_wrdata_b,bram_rddata_b)
|
||||
(* integer foreign = "SystemC";
|
||||
*);
|
||||
input bit s_axi_aclk;
|
||||
input bit s_axi_aresetn;
|
||||
input bit [15 : 0] s_axi_awaddr;
|
||||
input bit [7 : 0] s_axi_awlen;
|
||||
input bit [2 : 0] s_axi_awsize;
|
||||
input bit [1 : 0] s_axi_awburst;
|
||||
input bit s_axi_awlock;
|
||||
input bit [3 : 0] s_axi_awcache;
|
||||
input bit [2 : 0] s_axi_awprot;
|
||||
input bit s_axi_awvalid;
|
||||
output wire s_axi_awready;
|
||||
input bit [31 : 0] s_axi_wdata;
|
||||
input bit [3 : 0] s_axi_wstrb;
|
||||
input bit s_axi_wlast;
|
||||
input bit s_axi_wvalid;
|
||||
output wire s_axi_wready;
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
output wire s_axi_bvalid;
|
||||
input bit s_axi_bready;
|
||||
input bit [15 : 0] s_axi_araddr;
|
||||
input bit [7 : 0] s_axi_arlen;
|
||||
input bit [2 : 0] s_axi_arsize;
|
||||
input bit [1 : 0] s_axi_arburst;
|
||||
input bit s_axi_arlock;
|
||||
input bit [3 : 0] s_axi_arcache;
|
||||
input bit [2 : 0] s_axi_arprot;
|
||||
input bit s_axi_arvalid;
|
||||
output wire s_axi_arready;
|
||||
output wire [31 : 0] s_axi_rdata;
|
||||
output wire [1 : 0] s_axi_rresp;
|
||||
output wire s_axi_rlast;
|
||||
output wire s_axi_rvalid;
|
||||
input bit s_axi_rready;
|
||||
output wire bram_rst_a;
|
||||
output wire bram_clk_a;
|
||||
output wire bram_en_a;
|
||||
output wire [3 : 0] bram_we_a;
|
||||
output wire [15 : 0] bram_addr_a;
|
||||
output wire [31 : 0] bram_wrdata_a;
|
||||
input bit [31 : 0] bram_rddata_a;
|
||||
output wire bram_rst_b;
|
||||
output wire bram_clk_b;
|
||||
output wire bram_en_b;
|
||||
output wire [3 : 0] bram_we_b;
|
||||
output wire [15 : 0] bram_addr_b;
|
||||
output wire [31 : 0] bram_wrdata_b;
|
||||
input bit [31 : 0] bram_rddata_b;
|
||||
endmodule
|
||||
`endif
|
||||
|
|
@ -0,0 +1,136 @@
|
|||
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
#ifndef __P2P_XTLM_EXTENSION_HH_
|
||||
#define __P2P_XTLM_EXTENSION_HH_
|
||||
#include "xtlm.h"
|
||||
|
||||
/**
|
||||
* XTLM extension to support peer to peer buffer allocation
|
||||
* Master requests buffer allocation with a base address and size and slave responds with corresponding
|
||||
* mmaped buffer file name
|
||||
*/
|
||||
namespace xsc {
|
||||
namespace extension {
|
||||
enum TYPE {
|
||||
ALLOC_BO,
|
||||
FREE_BO,
|
||||
IMPORT_BO,
|
||||
COPY_BO
|
||||
};
|
||||
|
||||
class P2P_XTLM_extension: public xtlm::xtlm_extension<P2P_XTLM_extension> {
|
||||
|
||||
public:
|
||||
P2P_XTLM_extension() {
|
||||
m_address=0;
|
||||
m_size=0;
|
||||
m_file_name = "";
|
||||
m_resp_valid=false;
|
||||
m_resp=false;
|
||||
m_type=TYPE::ALLOC_BO;
|
||||
m_src_offset = 0;
|
||||
m_dst_offset = 0;
|
||||
}
|
||||
|
||||
~P2P_XTLM_extension(){}
|
||||
xtlm::xtlm_extension_base* clone() const {
|
||||
// Must override pure virtual clone method
|
||||
P2P_XTLM_extension* t = new P2P_XTLM_extension();
|
||||
return t;
|
||||
}
|
||||
// Must override pure virtual copy_from method
|
||||
void copy_from(xtlm::xtlm_extension_base const &ext) {
|
||||
m_address = static_cast<P2P_XTLM_extension const &>(ext).m_address;
|
||||
m_size = static_cast<P2P_XTLM_extension const &>(ext).m_size;
|
||||
m_file_name = static_cast<P2P_XTLM_extension const &>(ext).m_file_name;
|
||||
m_resp_valid = static_cast<P2P_XTLM_extension const &>(ext).m_resp_valid;
|
||||
m_resp = static_cast<P2P_XTLM_extension const &>(ext).m_resp;
|
||||
m_type = static_cast<P2P_XTLM_extension const &>(ext).m_type;
|
||||
m_src_offset = static_cast<P2P_XTLM_extension const &>(ext).m_src_offset;
|
||||
m_dst_offset = static_cast<P2P_XTLM_extension const &>(ext).m_dst_offset;
|
||||
}
|
||||
|
||||
void setAddress(uint64_t address) { m_address = address; }
|
||||
uint64_t getAddress()const { return m_address; }
|
||||
|
||||
void setSize(uint64_t size) { m_size = size; }
|
||||
uint64_t getSize()const { return m_size; }
|
||||
|
||||
void setFileName(std::string file_name) { m_file_name = file_name; }
|
||||
const std::string& getFileName()const { return m_file_name; }
|
||||
|
||||
void setIsResponseValid(bool resp_valid) { m_resp_valid = resp_valid;}
|
||||
bool getIsResponseValid() { return m_resp_valid; }
|
||||
|
||||
void setResponse(bool resp){ m_resp = resp;}
|
||||
bool getResponse() const { return m_resp;}
|
||||
|
||||
void setSrcOffset(uint64_t src_offset) { m_src_offset = src_offset; }
|
||||
uint64_t getSrcOffset() const { return m_src_offset; }
|
||||
|
||||
void setDstOffset(uint64_t dst_offset) { m_dst_offset = dst_offset; }
|
||||
uint64_t getDstOffset() const { return m_dst_offset; }
|
||||
|
||||
void setType(TYPE type) { m_type = type; }
|
||||
TYPE getType() const { return m_type;}
|
||||
|
||||
private :
|
||||
uint64_t m_address;
|
||||
uint64_t m_size;
|
||||
std::string m_file_name;
|
||||
bool m_resp_valid;
|
||||
bool m_resp;
|
||||
uint64_t m_src_offset;
|
||||
uint64_t m_dst_offset;
|
||||
TYPE m_type;
|
||||
};
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
@ -0,0 +1,98 @@
|
|||
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
#include "axi_bram_ctrl.h"
|
||||
|
||||
axi_bram_ctrl::axi_bram_ctrl(const sc_module_name& module_name, xsc::common_cpp::properties& properties) :
|
||||
sc_module(module_name) {
|
||||
//Get Width from property
|
||||
uint64_t data_width=properties.getLongLong("C_S_AXI_DATA_WIDTH");
|
||||
uint64_t dual_port=properties.getLongLong("C_SINGLE_PORT_BRAM");
|
||||
uint64_t ecc=properties.getLongLong("C_ECC");
|
||||
target_0_rd_socket = new xtlm::xtlm_aximm_target_socket("target_0_rd_socket", data_width);
|
||||
target_0_wr_socket = new xtlm::xtlm_aximm_target_socket("target_0_wr_socket", data_width);
|
||||
m_imp=new axi_bram_memory_imp("impl",properties);
|
||||
target_0_rd_socket->bind(*(m_imp->target_0_rd_socket));
|
||||
target_0_wr_socket->bind(*(m_imp->target_0_wr_socket));
|
||||
if(ecc==1)
|
||||
{
|
||||
s_axi_ctrl_target_rd_socket = new xtlm::xtlm_aximm_target_socket("target_1_rd_socket", 32);
|
||||
s_axi_ctrl_target_wr_socket = new xtlm::xtlm_aximm_target_socket("target_1_wr_socket", 32);
|
||||
auto* stubWr = new xtlm::xtlm_aximm_target_stub("ifWrStubskt0", 32);
|
||||
s_axi_ctrl_target_wr_socket->bind(stubWr->target_socket);
|
||||
auto* stubRd = new xtlm::xtlm_aximm_target_stub("ifRdStubskt0", 32);
|
||||
s_axi_ctrl_target_rd_socket->bind(stubRd->target_socket);
|
||||
stubInitSkt.push_back(stubWr);
|
||||
stubInitSkt.push_back(stubRd);
|
||||
}
|
||||
if(dual_port==1)
|
||||
{
|
||||
bram_rst_b(bram_rst_b1);
|
||||
bram_clk_b(bram_clk_b1);
|
||||
bram_en_b(bram_en_b1);
|
||||
bram_we_b(bram_we_b1);
|
||||
bram_addr_b(bram_addr_b1);
|
||||
bram_wrdata_b(bram_wrdata_b1);
|
||||
bram_rddata_b(bram_rddata_b1);
|
||||
}
|
||||
|
||||
SC_THREAD(clock_finder);
|
||||
sensitive<< s_axi_aclk;
|
||||
dont_initialize();
|
||||
|
||||
}
|
||||
axi_bram_ctrl::~axi_bram_ctrl() {
|
||||
delete target_0_rd_socket;
|
||||
delete target_0_wr_socket;
|
||||
delete m_imp;
|
||||
}
|
||||
void axi_bram_ctrl::clock_finder() {
|
||||
sc_time clk1 = sc_time_stamp();
|
||||
wait();
|
||||
sc_time clk2= sc_time_stamp();
|
||||
}
|
||||
|
|
@ -0,0 +1,102 @@
|
|||
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
#ifndef _SIMHBMX_H_
|
||||
#define _SIMHBMX_H_
|
||||
|
||||
#include "xtlm.h"
|
||||
#include <list>
|
||||
|
||||
#include "axi_bram_memory_imp.h"
|
||||
#include "utils/xtlm_aximm_target_stub.h"
|
||||
#include "utils/xsc_stub_port.h"
|
||||
|
||||
class axi_bram_ctrl: public sc_core::sc_module {
|
||||
public:
|
||||
axi_bram_ctrl(const sc_module_name& module_name,xsc::common_cpp::properties&);
|
||||
virtual ~axi_bram_ctrl();
|
||||
SC_HAS_PROCESS(axi_bram_ctrl);
|
||||
//Slave interface used to R/W to HBM Memory
|
||||
xtlm::xtlm_aximm_target_socket* target_0_rd_socket;
|
||||
xtlm::xtlm_aximm_target_socket* target_0_wr_socket;
|
||||
xtlm::xtlm_aximm_target_socket* s_axi_ctrl_target_rd_socket;
|
||||
xtlm::xtlm_aximm_target_socket* s_axi_ctrl_target_wr_socket;
|
||||
std::vector<xtlm::xtlm_aximm_target_stub*> stubInitSkt;
|
||||
void clock_finder();
|
||||
sc_in<bool> s_axi_aclk;
|
||||
sc_in<bool> s_axi_aresetn;
|
||||
xsc::utils::xsc_stub_port ecc_interrupt;
|
||||
xsc::utils::xsc_stub_port ecc_ue;
|
||||
xsc::utils::xsc_stub_port bram_rst_a;
|
||||
xsc::utils::xsc_stub_port bram_clk_a;
|
||||
xsc::utils::xsc_stub_port bram_en_a;
|
||||
xsc::utils::xsc_stub_port bram_we_a;
|
||||
xsc::utils::xsc_stub_port bram_addr_a;
|
||||
xsc::utils::xsc_stub_port bram_wrdata_a;
|
||||
xsc::utils::xsc_stub_port bram_rddata_a;
|
||||
xsc::utils::xsc_stub_port bram_rst_b;
|
||||
xsc::utils::xsc_stub_port bram_clk_b;
|
||||
xsc::utils::xsc_stub_port bram_en_b;
|
||||
xsc::utils::xsc_stub_port bram_we_b;
|
||||
xsc::utils::xsc_stub_port bram_addr_b;
|
||||
xsc::utils::xsc_stub_port bram_wrdata_b;
|
||||
xsc::utils::xsc_stub_port bram_rddata_b;
|
||||
sc_core::sc_signal<bool>bram_rst_b1;
|
||||
sc_core::sc_signal<bool>bram_clk_b1;
|
||||
sc_core::sc_signal<bool>bram_en_b1;
|
||||
sc_core::sc_signal<bool>bram_we_b1;
|
||||
sc_core::sc_signal<bool>bram_addr_b1;
|
||||
sc_core::sc_signal<bool>bram_wrdata_b1;
|
||||
sc_core::sc_signal<bool>bram_rddata_b1;
|
||||
|
||||
|
||||
private :
|
||||
axi_bram_memory_imp* m_imp;
|
||||
};
|
||||
|
||||
#endif /* _SIMHBMX_H_ */
|
||||
|
|
@ -0,0 +1,67 @@
|
|||
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
#include <sys/stat.h>
|
||||
#include "axi_bram_fmodel_base.h"
|
||||
//#define DEBUGMSG
|
||||
|
||||
|
||||
axi_bram_fmodel_base::~ axi_bram_fmodel_base()
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
axi_bram_fmodel_base::axi_bram_fmodel_base(std::string p_module_name,xsc::common_cpp::report_handler* report_handler,uint64_t addr_size): module_name(p_module_name)
|
||||
{
|
||||
}
|
||||
|
||||
void axi_bram_fmodel_base::init_fmodel()
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,97 @@
|
|||
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
#ifndef XTLM_SIMPLE_FMODEL_BASE__H
|
||||
#define XTLM_SIMPLE_FMODEL_BASE__H
|
||||
#include <math.h>
|
||||
#include <iostream>
|
||||
|
||||
#include <string.h> // memcpy
|
||||
#include <stdlib.h> //realloc
|
||||
#include <stdint.h>
|
||||
#include <vector>
|
||||
#include <map> //realloc
|
||||
#include <unistd.h>
|
||||
#include <sys/types.h>
|
||||
#include <sys/stat.h>
|
||||
#include <fcntl.h>
|
||||
#include <sys/mman.h>
|
||||
#include "report_handler.h"
|
||||
|
||||
#define ONE_KB (0x400)
|
||||
#define ONE_MB (ONE_KB * ONE_KB)
|
||||
#define PAGESIZE (ONE_MB)
|
||||
#define ADDRBITS (20)
|
||||
#define N_1MBARRAYS 4096
|
||||
|
||||
class axi_bram_fmodel_base {
|
||||
public:
|
||||
virtual unsigned int writeDevMem(uint64_t offset, void* src,
|
||||
unsigned int size) = 0;
|
||||
virtual unsigned int readDevMem(uint64_t offset, void* dest,
|
||||
unsigned int size) = 0;
|
||||
virtual bool createMMappedBuffer(uint64_t base_address, uint64_t size,
|
||||
std::string& buffer_filename) = 0;
|
||||
virtual bool freePage(uint64_t base_address) = 0;
|
||||
virtual unsigned char* get_page(uint64_t offset, std::string& p2pFileName,
|
||||
uint64_t size = 0) = 0;
|
||||
virtual bool copyBO(uint64_t offset, std::string dst_filename,
|
||||
uint64_t size, uint64_t src_offset, uint64_t dst_offset) = 0;
|
||||
virtual bool importBO(uint64_t offset, std::string dst_filename,
|
||||
uint64_t size) = 0;
|
||||
axi_bram_fmodel_base(std::string p_module_name,
|
||||
xsc::common_cpp::report_handler* report_handler,
|
||||
uint64_t addr_size);
|
||||
virtual ~ axi_bram_fmodel_base();
|
||||
void init_fmodel();
|
||||
virtual void reset_fmodel() = 0;
|
||||
std::string module_name;
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -0,0 +1,443 @@
|
|||
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
#include "axi_bram_fmodel_shared_memory.h"
|
||||
#include <sys/stat.h>
|
||||
#include <sstream>
|
||||
|
||||
std::map<std::string, std::tuple<uint64_t, void*, int> > axi_bram_fmodel_shared_memory::mFileFdMap;
|
||||
|
||||
axi_bram_fmodel_shared_memory::axi_bram_fmodel_shared_memory(
|
||||
std::string p_module_name,
|
||||
xsc::common_cpp::report_handler* report_handler, uint64_t addr_size) : //Mode 0
|
||||
axi_bram_fmodel_base(p_module_name, report_handler, addr_size) {
|
||||
m_report_handler = report_handler;
|
||||
if (m_report_handler->get_verbosity_level()
|
||||
== xsc::common_cpp::VERBOSITY::DEBUG) {
|
||||
std::stringstream m_ss;
|
||||
m_ss.str("");
|
||||
m_ss << module_name << std::endl;
|
||||
XSC_REPORT_INFO((*m_report_handler), "xtlmmemorymodel_shared_memory",
|
||||
m_ss.str().c_str());
|
||||
}
|
||||
}
|
||||
|
||||
void axi_bram_fmodel_shared_memory::reset_fmodel() {
|
||||
auto pageIt = mPageCache.begin();
|
||||
auto pageEnd = mPageCache.end();
|
||||
while (pageIt != pageEnd) {
|
||||
uint64_t offset = (*pageIt).first;
|
||||
|
||||
auto itr = mOffsetFileMap.find(offset);
|
||||
int fd = -1;
|
||||
if (itr != mOffsetFileMap.end()) {
|
||||
std::string sFileName = (*itr).second;
|
||||
auto itr2 = mFileFdMap.find(sFileName);
|
||||
if (itr2 != mFileFdMap.end()) {
|
||||
fd = std::get<0>((*itr2).second);
|
||||
void* pPtr = std::get<1>((*itr2).second);
|
||||
int size = std::get<2>((*itr2).second);
|
||||
munmap(pPtr, size);
|
||||
mFileFdMap.erase(itr2);
|
||||
close(fd);
|
||||
}
|
||||
}
|
||||
pageIt++;
|
||||
}
|
||||
|
||||
}
|
||||
axi_bram_fmodel_shared_memory::~axi_bram_fmodel_shared_memory() {
|
||||
}
|
||||
|
||||
unsigned int axi_bram_fmodel_shared_memory::writeDevMem(uint64_t offset,
|
||||
void* src, unsigned int size) {
|
||||
|
||||
uint64_t written_bytes = 0;
|
||||
uint64_t addr = offset;
|
||||
while (written_bytes < size) {
|
||||
uint64_t src_offset = written_bytes;
|
||||
|
||||
std::string p2pFileName("");
|
||||
unsigned char* page_ptr = get_page(addr, p2pFileName);
|
||||
uint64_t ddrAddress = getBaseDdrAddress(addr);
|
||||
if (!page_ptr) {
|
||||
std::stringstream errMsg;
|
||||
errMsg
|
||||
<< "Kernel attempting to write to memory which was never allocated ("
|
||||
<< std::hex << "0x" << offset << ")" << std::dec;
|
||||
XSC_REPORT_INFO((*m_report_handler),
|
||||
"xtlmsimplememorymodel_shared_memory",
|
||||
errMsg.str().c_str());
|
||||
return 0;
|
||||
}
|
||||
unsigned char* dest_buf_ptr = page_ptr + offset - ddrAddress;
|
||||
unsigned char* src_buf_ptr = (unsigned char*) (src) + src_offset;
|
||||
|
||||
uint64_t remaining_bytes_to_write = size - written_bytes;
|
||||
//memcpy(dest_buf_ptr,src_buf_ptr,buf_size);
|
||||
for (unsigned int i = 0; i < remaining_bytes_to_write; i++) {
|
||||
dest_buf_ptr[i] = src_buf_ptr[i];
|
||||
}
|
||||
|
||||
written_bytes += remaining_bytes_to_write;
|
||||
addr += remaining_bytes_to_write;
|
||||
}
|
||||
|
||||
if (m_report_handler->get_verbosity_level()
|
||||
== xsc::common_cpp::VERBOSITY::DEBUG) {
|
||||
std::stringstream m_ss;
|
||||
m_ss.str("");
|
||||
m_ss << "Write Operation size : " << size << std::endl;
|
||||
for (int i = 0; i < size; i++) {
|
||||
m_ss << std::hex << (unsigned int) (((unsigned char*) src)[i])
|
||||
<< " ";
|
||||
}
|
||||
m_ss << std::endl;
|
||||
m_ss << "Write : " << "Offset --> " << offset << std::endl;
|
||||
XSC_REPORT_INFO((*m_report_handler), "xtlmmemorymodel_shared_memory",
|
||||
m_ss.str().c_str());
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned int axi_bram_fmodel_shared_memory::readDevMem(uint64_t offset,
|
||||
void* dest, unsigned int size) {
|
||||
uint64_t read_bytes = 0;
|
||||
uint64_t addr = offset;
|
||||
while (read_bytes < size) {
|
||||
uint64_t dest_offset = read_bytes;
|
||||
|
||||
std::string p2pFileName("");
|
||||
unsigned char* page_ptr = get_page(addr, p2pFileName);
|
||||
uint64_t ddrAddress = getBaseDdrAddress(addr);
|
||||
|
||||
if (!page_ptr) {
|
||||
if (m_report_handler->get_verbosity_level()
|
||||
== xsc::common_cpp::VERBOSITY::DEBUG) {
|
||||
std::stringstream errMsg;
|
||||
errMsg
|
||||
<< "Kernel attempting to read to memory which was never allocated ("
|
||||
<< std::hex << "0x" << offset << ")" << std::dec;
|
||||
XSC_REPORT_INFO((*m_report_handler),
|
||||
"xtlmsimplememorymodel_shared_memory",
|
||||
errMsg.str().c_str());
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned char* src_buf_ptr = page_ptr + (offset - ddrAddress);
|
||||
unsigned char* dest_buf_ptr = (unsigned char*) (dest) + dest_offset;
|
||||
|
||||
uint64_t remaining_bytes_to_read = size - read_bytes;
|
||||
|
||||
for (uint64_t i = 0; i < remaining_bytes_to_read; i++) {
|
||||
dest_buf_ptr[i] = src_buf_ptr[i];
|
||||
}
|
||||
|
||||
read_bytes += remaining_bytes_to_read;
|
||||
addr += remaining_bytes_to_read;
|
||||
}
|
||||
|
||||
if (m_report_handler->get_verbosity_level()
|
||||
== xsc::common_cpp::VERBOSITY::DEBUG) {
|
||||
std::stringstream m_ss;
|
||||
m_ss.str("");
|
||||
m_ss << "Read Operation size : " << size << std::endl;
|
||||
for (int i = 0; i < size; i++) {
|
||||
m_ss << std::hex << (unsigned int) (((unsigned char*) dest)[i])
|
||||
<< " ";
|
||||
}
|
||||
m_ss << std::endl;
|
||||
m_ss << "Read : " << "Offset --> " << offset << std::endl;
|
||||
XSC_REPORT_INFO((*m_report_handler),
|
||||
"xtlmsimplememorymodel_shared_memory", m_ss.str().c_str());
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned char* axi_bram_fmodel_shared_memory::get_page(uint64_t offset,
|
||||
std::string& p2pFileName, uint64_t size) {
|
||||
auto pageIt = mPageCache.begin();
|
||||
auto pageEnd = mPageCache.end();
|
||||
while (pageIt != pageEnd) {
|
||||
uint64_t startAddress = (*pageIt).first;
|
||||
std::pair<unsigned char*, uint64_t> addressSizePair = (*pageIt).second;
|
||||
unsigned char* pageStartOSAddress = addressSizePair.first;
|
||||
uint64_t pageSize = addressSizePair.second;
|
||||
if (offset >= startAddress && offset < startAddress + pageSize) {
|
||||
return pageStartOSAddress;
|
||||
}
|
||||
pageIt++;
|
||||
}
|
||||
//in partial reconfiguration case, we should read the file which is stored.
|
||||
|
||||
return NULL;
|
||||
|
||||
}
|
||||
|
||||
uint64_t axi_bram_fmodel_shared_memory::getBaseDdrAddress(uint64_t offset) {
|
||||
auto pageIt = mPageCache.begin();
|
||||
auto pageEnd = mPageCache.end();
|
||||
while (pageIt != pageEnd) {
|
||||
uint64_t startAddress = (*pageIt).first;
|
||||
std::pair<unsigned char*, uint64_t> addressSizePair = (*pageIt).second;
|
||||
uint64_t pageSize = addressSizePair.second;
|
||||
if (offset >= startAddress && offset < startAddress + pageSize) {
|
||||
return startAddress;
|
||||
}
|
||||
pageIt++;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
bool axi_bram_fmodel_shared_memory::copyBO(uint64_t offset,
|
||||
std::string dst_filename, uint64_t size, uint64_t src_offset,
|
||||
uint64_t dst_offset) {
|
||||
uint64_t read_bytes = 0;
|
||||
uint64_t addr = offset;
|
||||
std::string p2pFileName("");
|
||||
unsigned char* page_ptr = get_page(addr, p2pFileName);
|
||||
uint64_t ddrAddress = getBaseDdrAddress(addr);
|
||||
unsigned char* src_buf_ptr = (unsigned char*) (page_ptr
|
||||
+ (offset - ddrAddress) + src_offset);
|
||||
auto itr = mFileFdMap.find(dst_filename);
|
||||
if (itr != mFileFdMap.end()) {
|
||||
int dst_fd = std::get<0>((*itr).second);
|
||||
if (lseek(dst_fd, dst_offset, SEEK_CUR) < 0)
|
||||
return false;
|
||||
int bytes_written = write(dst_fd, src_buf_ptr,
|
||||
size/*strlen(src_buf_ptr)*/);
|
||||
if (bytes_written < 0) {
|
||||
std::cout << "Failed to write into file " << dst_fd << std::endl;
|
||||
} else {
|
||||
std::cout << "bytes_written is " << bytes_written
|
||||
<< " is successful " << std::endl;
|
||||
}
|
||||
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
bool axi_bram_fmodel_shared_memory::importBO(uint64_t offset,
|
||||
std::string sFileName, uint64_t size) {
|
||||
int fd = -1;
|
||||
if ((fd = open(sFileName.c_str(), O_CREAT | O_RDWR,
|
||||
S_IRWXU | S_IRGRP | S_IROTH)) == -1) {
|
||||
printf("Error opening file.\n");
|
||||
};
|
||||
if (fd < 0)
|
||||
return false;
|
||||
void* pageStartOSAddressVoid = mmap(0, size,
|
||||
PROT_READ | PROT_WRITE | PROT_EXEC, MAP_SHARED, fd,
|
||||
0/*sysconf(_SC_PAGESIZE)*/);
|
||||
if (ftruncate(fd, size) < 0) {
|
||||
close(fd);
|
||||
munmap(pageStartOSAddressVoid, size);
|
||||
return false;
|
||||
}
|
||||
mFileFdMap[sFileName] = std::make_tuple(fd, pageStartOSAddressVoid, size);
|
||||
mOffsetFileMap[offset] = sFileName;
|
||||
}
|
||||
|
||||
//create a page at offset. Return if already exist
|
||||
std::string axi_bram_fmodel_shared_memory::createPage(uint64_t offset,
|
||||
uint64_t size, bool p2p) {
|
||||
std::string sFileName("");
|
||||
int fd = -1;
|
||||
auto pageIt = mPageCache.begin();
|
||||
auto pageEnd = mPageCache.end();
|
||||
while (pageIt != pageEnd) {
|
||||
uint64_t startAddress = (*pageIt).first;
|
||||
std::pair<unsigned char*, uint64_t> addressSizePair = (*pageIt).second;
|
||||
uint64_t pageSize = addressSizePair.second;
|
||||
if (offset >= startAddress && offset < startAddress + pageSize) {
|
||||
freePage(offset);
|
||||
//new offset is conflicting old addresses
|
||||
//return "";
|
||||
}
|
||||
pageIt++;
|
||||
}
|
||||
|
||||
void* pageStartOSAddressVoid = NULL;
|
||||
// TODO: DDR_BUFFER_ALIGNMENT 0x1000 (4096) this is declared in runtime shim.
|
||||
// below variable is based on it.
|
||||
size_t alignmentForBuffer = 4096; // previously sizeof(double) * 16
|
||||
|
||||
if (!p2p) {
|
||||
if (posix_memalign(&pageStartOSAddressVoid, alignmentForBuffer, size)) {
|
||||
pageStartOSAddressVoid = NULL;
|
||||
}
|
||||
} else {
|
||||
std::stringstream ssFileName;
|
||||
sFileName = get_mem_file_name(offset);
|
||||
ssFileName << sFileName << "_shared";
|
||||
sFileName = ssFileName.str(); //config::getInstance()->getDeviceDirectory() + "/" + ssFileName.str();
|
||||
if ((fd = open(sFileName.c_str(), O_CREAT | O_RDWR,
|
||||
S_IRWXU | S_IRGRP | S_IROTH)) == -1) {
|
||||
printf("Error opening file.\n");
|
||||
}
|
||||
pageStartOSAddressVoid = mmap(0, size,
|
||||
PROT_READ | PROT_WRITE | PROT_EXEC, MAP_SHARED, fd,
|
||||
0/*sysconf(_SC_PAGESIZE)*/);
|
||||
if (fd < 0) {
|
||||
munmap(pageStartOSAddressVoid, size);
|
||||
return sFileName;
|
||||
}
|
||||
|
||||
if (ftruncate(fd, size) < 0) {
|
||||
close(fd);
|
||||
munmap(pageStartOSAddressVoid, size);
|
||||
return sFileName;
|
||||
}
|
||||
}
|
||||
if (!pageStartOSAddressVoid) {
|
||||
close(fd);
|
||||
return sFileName;
|
||||
}
|
||||
|
||||
if (!sFileName.empty()) {
|
||||
mFileFdMap[sFileName] = std::make_tuple(fd, pageStartOSAddressVoid,
|
||||
size);
|
||||
mOffsetFileMap[offset] = sFileName;
|
||||
}
|
||||
|
||||
unsigned char* pageStartOSAddress = (unsigned char*) pageStartOSAddressVoid;
|
||||
mPageCache[offset] = std::make_pair(pageStartOSAddress, size);
|
||||
return sFileName;
|
||||
}
|
||||
//free page at offset. Return if already exist
|
||||
bool axi_bram_fmodel_shared_memory::freePage(uint64_t offset) {
|
||||
bool mMappedBuffer = false;
|
||||
auto itr = mOffsetFileMap.find(offset);
|
||||
int fd = -1;
|
||||
|
||||
if (itr != mOffsetFileMap.end()) {
|
||||
mMappedBuffer = true;
|
||||
std::string sFileName = (*itr).second;
|
||||
auto itr2 = mFileFdMap.find(sFileName);
|
||||
if (itr2 != mFileFdMap.end()) {
|
||||
fd = std::get<0>((*itr2).second);
|
||||
void* pPtr = std::get<1>((*itr2).second);
|
||||
int size = std::get<2>((*itr2).second);
|
||||
munmap(pPtr, size);
|
||||
mFileFdMap.erase(itr2);
|
||||
}
|
||||
}
|
||||
auto pageIt = mPageCache.find(offset);
|
||||
if (pageIt != mPageCache.end()) {
|
||||
std::pair<unsigned char*, uint64_t> addressSizePair = (*pageIt).second;
|
||||
unsigned char* osAddress = addressSizePair.first;
|
||||
uint64_t size = addressSizePair.second;
|
||||
if (osAddress) {
|
||||
if (!mMappedBuffer)
|
||||
free((void *) osAddress);
|
||||
else {
|
||||
munmap(osAddress, size);
|
||||
if (fd != -1) {
|
||||
close(fd);
|
||||
}
|
||||
}
|
||||
}
|
||||
mPageCache.erase(pageIt);
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool axi_bram_fmodel_shared_memory::createMMappedBuffer(
|
||||
uint64_t base_address, uint64_t size, std::string& buffer_filename) {
|
||||
buffer_filename = createPage(base_address, size, true);
|
||||
return true;
|
||||
}
|
||||
|
||||
std::string axi_bram_fmodel_shared_memory::get_mem_file_name(
|
||||
uint64_t pageIdx) //,enum fileType file_type)
|
||||
{
|
||||
std::string file_name;
|
||||
std::string socket_id;
|
||||
std::string pid;
|
||||
std::string deviceName("");
|
||||
std::string user("");
|
||||
if (getenv("EMULATION_SOCKETID")) {
|
||||
socket_id = getenv("EMULATION_SOCKETID");
|
||||
std::size_t foundLast = socket_id.find_last_of("_");
|
||||
std::size_t foundFirst = socket_id.find_first_of("_");
|
||||
if (foundLast != std::string::npos) {
|
||||
pid = socket_id.substr(foundLast + 1);
|
||||
}
|
||||
if (foundFirst != std::string::npos) {
|
||||
deviceName = socket_id.substr(0, foundFirst);
|
||||
}
|
||||
}
|
||||
|
||||
if (getenv("USER") != NULL) {
|
||||
user = getenv("USER");
|
||||
}
|
||||
std::string file_path("");
|
||||
std::string sEmRunDir("");
|
||||
|
||||
if (getenv("EMULATION_RUN_DIR")) {
|
||||
sEmRunDir = getenv("EMULATION_RUN_DIR");
|
||||
} else {
|
||||
sEmRunDir = "/tmp/" + user + "/hw_em/";
|
||||
}
|
||||
|
||||
file_path = sEmRunDir + "/" + module_name + "/";
|
||||
std::stringstream mkdirCommand;
|
||||
mkdirCommand << "mkdir -p " << file_path;
|
||||
;
|
||||
struct stat statBuf;
|
||||
if (stat(file_path.c_str(), &statBuf) == -1) {
|
||||
system(mkdirCommand.str().c_str());
|
||||
}
|
||||
file_name = file_path + module_name + "_" + std::to_string(pageIdx);
|
||||
return file_name;
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,87 @@
|
|||
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
#ifndef axi_bram_FMODEL_SHARED_MEMORY__H
|
||||
#define axi_bram_FMODEL_SHARED_MEMORY__H
|
||||
|
||||
#include "axi_bram_fmodel_base.h"
|
||||
#include "report_handler.h"
|
||||
|
||||
class axi_bram_fmodel_shared_memory: public axi_bram_fmodel_base {
|
||||
public:
|
||||
unsigned int writeDevMem(uint64_t offset, void* src, unsigned int size);
|
||||
unsigned int readDevMem(uint64_t offset, void* dest, unsigned int size);
|
||||
bool createMMappedBuffer(uint64_t base_address, uint64_t size,
|
||||
std::string& buffer_filename);
|
||||
unsigned char* get_page(uint64_t offset, std::string& p2pFileName,
|
||||
uint64_t size = 0);
|
||||
uint64_t getBaseDdrAddress(uint64_t offset); //get the DDR base address of offset
|
||||
bool copyBO(uint64_t offset, std::string dst_filename, uint64_t size,
|
||||
uint64_t src_offset, uint64_t dst_offset);
|
||||
bool importBO(uint64_t offset, std::string dst_filename, uint64_t size);
|
||||
std::string createPage(uint64_t offset, uint64_t size, bool p2p); //create a page of size "size" and add it in mPageCache Map.
|
||||
bool freePage(uint64_t offset); //free page and remove it from mPageCache Map.
|
||||
std::string get_mem_file_name(uint64_t pageIdx);
|
||||
|
||||
public:
|
||||
axi_bram_fmodel_shared_memory(std::string p_module_name,
|
||||
xsc::common_cpp::report_handler* report_handler,
|
||||
uint64_t addr_size);
|
||||
~ axi_bram_fmodel_shared_memory();
|
||||
void reset_fmodel();
|
||||
private:
|
||||
//Paging
|
||||
std::map<uint64_t, std::pair<unsigned char*, uint64_t> > mPageCache; // this map is used to store ddrAddress and OsAddress Mapping.
|
||||
static std::map<std::string, std::tuple<uint64_t, void*, int> > mFileFdMap; //filename and fd map
|
||||
std::map<uint64_t, std::string> mOffsetFileMap; //offset and filename map
|
||||
xsc::common_cpp::report_handler *m_report_handler;
|
||||
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -0,0 +1,408 @@
|
|||
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
#include "axi_bram_memory_imp.h"
|
||||
#include "P2P_XTLM_extension.h"
|
||||
|
||||
#include <sstream>
|
||||
#include <bitset>
|
||||
|
||||
class axi_bram_memory_imp::target_rd_util: public xtlm::xtlm_aximm_target_rd_socket_util {
|
||||
public:
|
||||
target_rd_util(sc_core::sc_module_name p_name,
|
||||
xtlm::aximm::granularity g_hint, int width_p,
|
||||
axi_bram_memory_imp* _parent) :
|
||||
xtlm::xtlm_aximm_target_rd_socket_util(p_name, g_hint, width_p) {
|
||||
this->parent = _parent;
|
||||
}
|
||||
unsigned int transport_dbg_cb(xtlm::aximm_payload& trans) {
|
||||
return parent->transport_dbg(trans);
|
||||
}
|
||||
private:
|
||||
axi_bram_memory_imp* parent;
|
||||
};
|
||||
|
||||
class axi_bram_memory_imp::target_wr_util: public xtlm::xtlm_aximm_target_wr_socket_util {
|
||||
public:
|
||||
target_wr_util(sc_core::sc_module_name p_name,
|
||||
xtlm::aximm::granularity g_hint, int width_p,
|
||||
axi_bram_memory_imp* _parent) :
|
||||
xtlm::xtlm_aximm_target_wr_socket_util(p_name, g_hint, width_p) {
|
||||
this->parent = _parent;
|
||||
}
|
||||
unsigned int transport_dbg_cb(xtlm::aximm_payload& trans) {
|
||||
return parent->transport_dbg(trans);
|
||||
}
|
||||
private:
|
||||
axi_bram_memory_imp* parent;
|
||||
};
|
||||
|
||||
axi_bram_memory_imp::axi_bram_memory_imp(
|
||||
const sc_module_name& module_name,
|
||||
xsc::common_cpp::properties& properties) :
|
||||
sc_module(module_name) {
|
||||
m_data_width = properties.getLongLong("C_S_AXI_DATA_WIDTH");
|
||||
m_mem_addr_width = properties.getLongLong("C_MEMORY_DEPTH");
|
||||
m_mem_addr_width *= m_data_width;
|
||||
|
||||
target_0_rd_socket = new xtlm::xtlm_aximm_target_socket(
|
||||
"saxi_hbmx_imp_rd_socket", m_data_width);
|
||||
target_0_wr_socket = new xtlm::xtlm_aximm_target_socket("saxi_cq_wrie_skt",
|
||||
m_data_width);
|
||||
m_target_0_rd_socket_util = new target_rd_util(
|
||||
"saxi_hbmx_imp_rd_socket_util",
|
||||
xtlm::aximm::granularity::TRANSACTION, m_data_width, this);
|
||||
m_target_0_wr_socket_util = new target_wr_util(
|
||||
"saxi_hbmx_imp_wr_socket_util",
|
||||
xtlm::aximm::granularity::TRANSACTION, m_data_width, this);
|
||||
target_0_rd_socket->bind((m_target_0_rd_socket_util->rd_socket));
|
||||
target_0_wr_socket->bind((m_target_0_wr_socket_util->wr_socket));
|
||||
std::string mod_name = name();
|
||||
m_report_handler = new xsc::common_cpp::report_handler(mod_name);
|
||||
if (!getenv("SDX_USE_SHARED_MEMORY"))
|
||||
m_mem_handler = new axi_bram_ram_fmodel(this->name(),
|
||||
m_report_handler, m_mem_addr_width); //name() returns hierarchical name of ddr systemc module instance
|
||||
else
|
||||
m_mem_handler = new axi_bram_fmodel_shared_memory(this->name(),
|
||||
m_report_handler, m_mem_addr_width); //name() returns hierarchical name of ddr systemc module instance
|
||||
|
||||
//m_mem_handler=new axi_bram_memory_fmodel_base(mod_name,m_report_handler,m_mem_addr_width);
|
||||
|
||||
SC_METHOD(methodProcessTransactionRead);
|
||||
sensitive << m_target_0_rd_socket_util->transaction_available;
|
||||
sensitive << m_target_0_rd_socket_util->data_sampled;
|
||||
dont_initialize();
|
||||
|
||||
//m_report_handler->set_verbosity_level(xsc::common_cpp::VERBOSITY::DEBUG);
|
||||
SC_METHOD(methodProcessTransactionWrite);
|
||||
sensitive << m_target_0_wr_socket_util->transaction_available;
|
||||
sensitive << m_target_0_wr_socket_util->resp_sampled;
|
||||
dont_initialize();
|
||||
}
|
||||
|
||||
axi_bram_memory_imp::~axi_bram_memory_imp() {
|
||||
delete target_0_rd_socket;
|
||||
delete target_0_wr_socket;
|
||||
delete m_target_0_rd_socket_util;
|
||||
delete m_target_0_wr_socket_util;
|
||||
delete m_report_handler;
|
||||
delete m_mem_handler;
|
||||
}
|
||||
|
||||
void axi_bram_memory_imp::methodProcessTransactionRead() {
|
||||
std::stringstream ss;
|
||||
if (m_target_0_rd_socket_util->is_trans_available()) {
|
||||
xtlm::aximm_payload* trans =
|
||||
m_target_0_rd_socket_util->get_transaction();
|
||||
sc_core::sc_time delay = SC_ZERO_TIME;
|
||||
uint64_t max_address = m_mem_addr_width;
|
||||
uint64_t address = trans->get_address() % max_address;
|
||||
uint64_t tranSize = trans->get_data_length();
|
||||
ss.clear();
|
||||
std::string des;
|
||||
if (m_report_handler->get_verbosity_level() == xsc::common_cpp::DEBUG) {
|
||||
trans->get_log(des, 1);
|
||||
ss << name() << ": Received Read Request " << des << std::endl;
|
||||
XSC_REPORT_INFO_VERB((*m_report_handler), "1", ss.str().c_str(),
|
||||
DEBUG);
|
||||
}
|
||||
if ((address + tranSize) > max_address) {
|
||||
ss.clear();
|
||||
ss << name() << ": Invalid Read Request " << std::endl << des
|
||||
<< std::endl;
|
||||
XSC_REPORT_ERROR((*m_report_handler), "1", ss.str().c_str());
|
||||
trans->set_response_status(xtlm::XTLM_ADDRESS_ERROR_RESPONSE);
|
||||
} else {
|
||||
ss.clear();
|
||||
trans->set_response_status(xtlm::XTLM_OK_RESPONSE);
|
||||
unsigned char* data_ptr = trans->get_data_ptr();
|
||||
m_mem_handler->readDevMem(address, data_ptr, tranSize);
|
||||
}
|
||||
m_rd_req_vec.push_back(trans);
|
||||
}
|
||||
if (m_rd_req_vec.empty() == false
|
||||
&& m_target_0_rd_socket_util->is_master_ready()) {
|
||||
ss.clear();
|
||||
xtlm::aximm_payload* trans = m_rd_req_vec.front();
|
||||
if (m_report_handler->get_verbosity_level() == xsc::common_cpp::DEBUG) {
|
||||
std::string des;
|
||||
trans->get_log(des, 1);
|
||||
ss << name() << ": Sending Read Response " << std::endl << des
|
||||
<< std::endl;
|
||||
XSC_REPORT_INFO_VERB((*m_report_handler), "1", ss.str().c_str(),
|
||||
DEBUG);
|
||||
}
|
||||
sc_core::sc_time delay = SC_ZERO_TIME;
|
||||
m_target_0_rd_socket_util->send_data(*trans, delay);
|
||||
m_rd_req_vec.pop_front();
|
||||
}
|
||||
}
|
||||
|
||||
void axi_bram_memory_imp::methodProcessTransactionWrite() {
|
||||
std::stringstream ss;
|
||||
if (m_target_0_wr_socket_util->is_trans_available()) {
|
||||
xtlm::aximm_payload* trans =
|
||||
m_target_0_wr_socket_util->get_transaction();
|
||||
uint64_t max_address = m_mem_addr_width;
|
||||
uint64_t address = trans->get_address() % max_address;
|
||||
uint64_t tranSize = trans->get_data_length();
|
||||
//Check for the address range
|
||||
trans->set_response_status(xtlm::XTLM_OK_RESPONSE);
|
||||
if ((address + tranSize) > max_address) {
|
||||
ss.clear();
|
||||
std::string des;
|
||||
trans->get_log(des, 1);
|
||||
ss << name() << ": Invalid Write Request " << std::endl << des
|
||||
<< std::endl;
|
||||
XSC_REPORT_ERROR((*m_report_handler), "1", ss.str().c_str());
|
||||
trans->set_response_status(xtlm::XTLM_ADDRESS_ERROR_RESPONSE);
|
||||
|
||||
} else {
|
||||
xtlm::xtlm_extension<xsc::extension::P2P_XTLM_extension>* bExt;
|
||||
trans->get_extension(bExt);
|
||||
xsc::extension::P2P_XTLM_extension * ext =
|
||||
dynamic_cast<xsc::extension::P2P_XTLM_extension *>(bExt);
|
||||
if (ext != nullptr) {
|
||||
std::string filename;
|
||||
bool ret = true;
|
||||
if (ext->getType() == xsc::extension::TYPE::ALLOC_BO)
|
||||
ret = m_mem_handler->createMMappedBuffer(
|
||||
address, ext->getSize(), filename);
|
||||
else if (ext->getType() == xsc::extension::TYPE::FREE_BO)
|
||||
ret = m_mem_handler->freePage(address);
|
||||
else if (ext->getType() == xsc::extension::TYPE::IMPORT_BO) {
|
||||
ret = m_mem_handler->importBO(address,
|
||||
ext->getFileName(), ext->getSize());
|
||||
} else if (ext->getType() == xsc::extension::TYPE::COPY_BO) {
|
||||
ret = m_mem_handler->copyBO(address,
|
||||
ext->getFileName(), ext->getSize(),
|
||||
ext->getSrcOffset(), ext->getDstOffset());
|
||||
}
|
||||
ext->setResponse(ret);
|
||||
ext->setFileName(filename);
|
||||
}
|
||||
|
||||
else if (!trans->get_byte_enable_ptr()) {
|
||||
unsigned char* data_ptr = trans->get_data_ptr();
|
||||
if (m_report_handler->get_verbosity_level()
|
||||
== xsc::common_cpp::DEBUG) {
|
||||
ss.clear();
|
||||
std::string des;
|
||||
trans->get_log(des, 1);
|
||||
ss << name() << ": Received Write Request " << std::endl
|
||||
<< des << std::endl;
|
||||
XSC_REPORT_INFO_VERB((*m_report_handler), "1",
|
||||
ss.str().c_str(), DEBUG);
|
||||
}
|
||||
|
||||
m_mem_handler->writeDevMem(address, data_ptr, tranSize);
|
||||
} else {
|
||||
if (m_report_handler->get_verbosity_level()
|
||||
== xsc::common_cpp::DEBUG) {
|
||||
ss.clear();
|
||||
std::string des;
|
||||
trans->get_log(des, 1);
|
||||
ss << name() << ": Received Write Request " << std::endl
|
||||
<< des << std::endl;
|
||||
XSC_REPORT_INFO_VERB((*m_report_handler), "1",
|
||||
ss.str().c_str(), DEBUG);
|
||||
}
|
||||
unsigned char* data_ptr = trans->get_data_ptr();
|
||||
unsigned char* byte_enable_ptr = trans->get_byte_enable_ptr();
|
||||
uint64_t byte_enable_len = trans->get_byte_enable_length();
|
||||
uint32_t index = 0;
|
||||
for (index = 1; index <= tranSize; index++) {
|
||||
bool byteEn = byte_enable_ptr[(index - 1) % byte_enable_len];
|
||||
if (byteEn) {
|
||||
m_mem_handler->writeDevMem(index + address - 1,
|
||||
data_ptr + (index - 1), 1);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
m_wr_resp_vec.push_back(trans);
|
||||
}
|
||||
if (m_wr_resp_vec.empty() == false
|
||||
&& m_target_0_wr_socket_util->is_master_ready()) {
|
||||
std::stringstream msg;
|
||||
sc_core::sc_time delay = SC_ZERO_TIME;
|
||||
xtlm::aximm_payload* trans = m_wr_resp_vec.front();
|
||||
if (m_report_handler->get_verbosity_level() == xsc::common_cpp::DEBUG) {
|
||||
ss.clear();
|
||||
std::string des;
|
||||
trans->get_log(des, 1);
|
||||
ss << name() << ": Sending Write Request " << std::endl << des
|
||||
<< std::endl;
|
||||
XSC_REPORT_INFO_VERB((*m_report_handler), "1", ss.str().c_str(),
|
||||
DEBUG);
|
||||
}
|
||||
m_target_0_wr_socket_util->send_resp(*trans, delay);
|
||||
m_wr_resp_vec.pop_front();
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
unsigned int axi_bram_memory_imp::transport_dbg(xtlm::aximm_payload& trans) {
|
||||
if (trans.get_command() == xtlm::XTLM_READ_COMMAND) {
|
||||
return transport_dbg_rd(trans);
|
||||
} else if (trans.get_command() == xtlm::XTLM_WRITE_COMMAND) {
|
||||
return transport_dbg_wr(trans);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned int axi_bram_memory_imp::transport_dbg_rd(
|
||||
xtlm::aximm_payload& trans) {
|
||||
sc_core::sc_time delay = SC_ZERO_TIME;
|
||||
uint64_t max_address = m_mem_addr_width;
|
||||
uint64_t address = trans.get_address() % max_address;
|
||||
uint64_t tranSize = trans.get_data_length();
|
||||
std::stringstream ss;
|
||||
ss.clear();
|
||||
std::string des;
|
||||
if (m_report_handler->get_verbosity_level() == xsc::common_cpp::DEBUG) {
|
||||
trans.get_log(des, 1);
|
||||
ss << name() << ": Received Debug Read Request " << des << std::endl;
|
||||
XSC_REPORT_INFO_VERB((*m_report_handler), "1", ss.str().c_str(), DEBUG);
|
||||
}
|
||||
if ((address + tranSize) > max_address) {
|
||||
ss.clear();
|
||||
ss << name() << ": Invalid Debug Read Request " << std::endl << des
|
||||
<< std::endl;
|
||||
XSC_REPORT_ERROR((*m_report_handler), "1", ss.str().c_str());
|
||||
trans.set_response_status(xtlm::XTLM_ADDRESS_ERROR_RESPONSE);
|
||||
return 0;
|
||||
} else {
|
||||
ss.clear();
|
||||
trans.set_response_status(xtlm::XTLM_OK_RESPONSE);
|
||||
unsigned char* data_ptr = trans.get_data_ptr();
|
||||
m_mem_handler->readDevMem(address, data_ptr, tranSize);
|
||||
return trans.get_data_length();
|
||||
}
|
||||
}
|
||||
|
||||
unsigned int axi_bram_memory_imp::transport_dbg_wr(
|
||||
xtlm::aximm_payload& trans) {
|
||||
std::stringstream ss;
|
||||
uint64_t max_address = m_mem_addr_width;
|
||||
uint64_t address = trans.get_address() % max_address;
|
||||
uint64_t tranSize = trans.get_data_length();
|
||||
//Check for the address range
|
||||
trans.set_response_status(xtlm::XTLM_OK_RESPONSE);
|
||||
if ((address + tranSize) > max_address) {
|
||||
ss.clear();
|
||||
std::string des;
|
||||
trans.get_log(des, 1);
|
||||
ss << name() << ": Invalid Debug Write Request " << std::endl << des
|
||||
<< std::endl;
|
||||
XSC_REPORT_ERROR((*m_report_handler), "1", ss.str().c_str());
|
||||
trans.set_response_status(xtlm::XTLM_ADDRESS_ERROR_RESPONSE);
|
||||
return 0;
|
||||
}
|
||||
xtlm::xtlm_extension<xsc::extension::P2P_XTLM_extension>* bExt;
|
||||
trans.get_extension(bExt);
|
||||
xsc::extension::P2P_XTLM_extension * ext =
|
||||
dynamic_cast<xsc::extension::P2P_XTLM_extension *>(bExt);
|
||||
if (ext != nullptr) {
|
||||
std::string filename;
|
||||
bool ret = true;
|
||||
if (ext->getType() == xsc::extension::TYPE::ALLOC_BO)
|
||||
ret = m_mem_handler->createMMappedBuffer(address,
|
||||
ext->getSize(), filename);
|
||||
else if (ext->getType() == xsc::extension::TYPE::FREE_BO)
|
||||
ret = m_mem_handler->freePage(address);
|
||||
else if (ext->getType() == xsc::extension::TYPE::IMPORT_BO) {
|
||||
ret = m_mem_handler->importBO(address,
|
||||
ext->getFileName(), ext->getSize());
|
||||
} else if (ext->getType() == xsc::extension::TYPE::COPY_BO) {
|
||||
ret = m_mem_handler->copyBO(address, ext->getFileName(),
|
||||
ext->getSize(), ext->getSrcOffset(), ext->getDstOffset());
|
||||
}
|
||||
ext->setResponse(ret);
|
||||
ext->setFileName(filename);
|
||||
return 0;
|
||||
}
|
||||
|
||||
else if (!trans.get_byte_enable_ptr()) {
|
||||
unsigned char* data_ptr = trans.get_data_ptr();
|
||||
if (m_report_handler->get_verbosity_level() == xsc::common_cpp::DEBUG) {
|
||||
ss.clear();
|
||||
std::string des;
|
||||
trans.get_log(des, 1);
|
||||
ss << name() << ": Received Debug Write Request " << std::endl
|
||||
<< des << std::endl;
|
||||
XSC_REPORT_INFO_VERB((*m_report_handler), "1", ss.str().c_str(),
|
||||
DEBUG);
|
||||
}
|
||||
m_mem_handler->writeDevMem(address, data_ptr, tranSize);
|
||||
return tranSize;
|
||||
} else {
|
||||
if (m_report_handler->get_verbosity_level() == xsc::common_cpp::DEBUG) {
|
||||
ss.clear();
|
||||
std::string des;
|
||||
trans.get_log(des, 1);
|
||||
ss << name() << ": Received Debug Write Request " << std::endl
|
||||
<< des << std::endl;
|
||||
XSC_REPORT_INFO_VERB((*m_report_handler), "1", ss.str().c_str(),
|
||||
DEBUG);
|
||||
}
|
||||
unsigned char* data_ptr = trans.get_data_ptr();
|
||||
unsigned char* byte_enable_ptr = trans.get_byte_enable_ptr();
|
||||
uint64_t byte_enable_len = trans.get_byte_enable_length();
|
||||
uint32_t index = 0;
|
||||
for (index = 1; index <= tranSize; index++) {
|
||||
bool byteEn = byte_enable_ptr[(index - 1) % byte_enable_len];
|
||||
if (byteEn) {
|
||||
m_mem_handler->writeDevMem(index + address - 1,
|
||||
data_ptr + (index - 1), 1);
|
||||
}
|
||||
}
|
||||
return tranSize;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,89 @@
|
|||
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
#ifndef _SIM_HBMX_IMP_H_
|
||||
#define _SIM_HBMX_IMP_H_
|
||||
|
||||
#include "xtlm.h"
|
||||
#include "report_handler.h"
|
||||
#include <list>
|
||||
#include "axi_bram_fmodel_base.h"
|
||||
#include "axi_bram_ram_fmodel.h"
|
||||
#include "axi_bram_fmodel_shared_memory.h"
|
||||
|
||||
class axi_bram_memory_imp: public sc_core::sc_module {
|
||||
public:
|
||||
//Workaround to implement Debug transport
|
||||
class target_rd_util;
|
||||
class target_wr_util;
|
||||
axi_bram_memory_imp(const sc_module_name& module_name,
|
||||
xsc::common_cpp::properties&);
|
||||
virtual ~axi_bram_memory_imp();SC_HAS_PROCESS(axi_bram_memory_imp);
|
||||
//Slave interface used to R/W to HBM Memory
|
||||
xtlm::xtlm_aximm_target_socket* target_0_rd_socket;
|
||||
xtlm::xtlm_aximm_target_socket* target_0_wr_socket;
|
||||
private:
|
||||
target_rd_util* m_target_0_rd_socket_util;
|
||||
target_wr_util* m_target_0_wr_socket_util;
|
||||
uint64_t m_mem_addr_width;
|
||||
uint64_t m_data_width;
|
||||
std::list<xtlm::aximm_payload*> m_rd_req_vec;
|
||||
std::list<xtlm::aximm_payload*> m_wr_req_vec;
|
||||
std::list<xtlm::aximm_payload*> m_wr_data_vec;
|
||||
std::list<xtlm::aximm_payload*> m_wr_resp_vec;
|
||||
void methodProcessTransactionRead();
|
||||
void methodProcessTransactionWrite();
|
||||
xsc::common_cpp::report_handler* m_report_handler;
|
||||
axi_bram_fmodel_base* m_mem_handler;
|
||||
unsigned int transport_dbg(xtlm::aximm_payload&);
|
||||
unsigned int transport_dbg_wr(xtlm::aximm_payload&);
|
||||
unsigned int transport_dbg_rd(xtlm::aximm_payload&);
|
||||
};
|
||||
|
||||
#endif /* _SIM_HBMX_IMP_H_ */
|
||||
|
||||
|
|
@ -0,0 +1,310 @@
|
|||
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
#include "axi_bram_ram_fmodel.h"
|
||||
|
||||
#include <sys/stat.h>
|
||||
#include <sstream>
|
||||
|
||||
axi_bram_ram_fmodel::~axi_bram_ram_fmodel() {
|
||||
for (auto& mem : pageCache) {
|
||||
delete mem.second;
|
||||
}
|
||||
}
|
||||
|
||||
axi_bram_ram_fmodel::axi_bram_ram_fmodel(
|
||||
std::string p_module_name,
|
||||
xsc::common_cpp::report_handler* report_handler, uint64_t addr_size) :
|
||||
axi_bram_fmodel_base(p_module_name, report_handler, addr_size) {
|
||||
std::stringstream msg;
|
||||
msg << p_module_name << " : ";
|
||||
msg << " Initializing " << std::endl;
|
||||
|
||||
module_name = p_module_name;
|
||||
m_report_handler = report_handler;
|
||||
m_mem_addr_width = addr_size;
|
||||
report_handler->report("1", msg.str().c_str(), xsc::common_cpp::INFO,
|
||||
xsc::common_cpp::VERBOSITY::DEBUG);
|
||||
}
|
||||
|
||||
unsigned int axi_bram_ram_fmodel::writeDevMem(uint64_t offset, void* src,
|
||||
unsigned int size) {
|
||||
if (m_report_handler->get_verbosity_level() == xsc::common_cpp::DEBUG) {
|
||||
std::stringstream msg;
|
||||
msg << module_name << " : ";
|
||||
msg << " Writing Memory Address = " << offset << " Size = " << size
|
||||
<< " Data =" << std::endl;
|
||||
uint64_t counter = 0;
|
||||
for (int i = 0; i < size; i++) {
|
||||
msg << (unsigned int) (((unsigned char*) src)[i]) << " ";
|
||||
if (counter <= 16)
|
||||
counter++;
|
||||
else {
|
||||
counter = 0;
|
||||
msg << std::endl;
|
||||
}
|
||||
}
|
||||
msg << std::endl;
|
||||
m_report_handler->report("1", msg.str().c_str(), xsc::common_cpp::INFO,
|
||||
xsc::common_cpp::VERBOSITY::DEBUG);
|
||||
}
|
||||
uint64_t written_bytes = 0;
|
||||
uint64_t addr = offset;
|
||||
while (written_bytes < size) {
|
||||
uint64_t src_offset = written_bytes;
|
||||
std::string sFileName("");
|
||||
unsigned char* page_ptr = get_page(addr, sFileName);
|
||||
uint64_t page_addr = addr & ~(-1 << ADDRBITS);
|
||||
|
||||
unsigned char* dest_buf_ptr = page_ptr + page_addr;
|
||||
unsigned char* src_buf_ptr = (unsigned char*) (src) + src_offset;
|
||||
|
||||
uint64_t remaining_bytes_to_write = size - written_bytes;
|
||||
uint64_t unaligned_bytes_in_addr = (addr & ~(-1 << ADDRBITS));
|
||||
uint64_t bytes_upto_next_alignment = (0x1 << ADDRBITS)
|
||||
- unaligned_bytes_in_addr;
|
||||
|
||||
uint64_t buf_size = 0;
|
||||
if (bytes_upto_next_alignment > remaining_bytes_to_write) {
|
||||
buf_size = remaining_bytes_to_write;
|
||||
} else {
|
||||
buf_size = bytes_upto_next_alignment;
|
||||
}
|
||||
memcpy(dest_buf_ptr, src_buf_ptr, buf_size);
|
||||
written_bytes += buf_size;
|
||||
addr += buf_size;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned int axi_bram_ram_fmodel::readDevMem(uint64_t offset, void* dest,
|
||||
unsigned int size) {
|
||||
uint64_t read_bytes = 0;
|
||||
uint64_t addr = offset;
|
||||
|
||||
while (read_bytes < size) {
|
||||
uint64_t dest_offset = read_bytes;
|
||||
std::string sFileName("");
|
||||
unsigned char* page_ptr = get_page(addr, sFileName);
|
||||
uint64_t page_addr = addr & ~(-1 << ADDRBITS);
|
||||
|
||||
unsigned char* src_buf_ptr = page_ptr + page_addr;
|
||||
unsigned char* dest_buf_ptr = (unsigned char*) (dest) + dest_offset;
|
||||
|
||||
uint64_t remaining_bytes_to_read = size - read_bytes;
|
||||
uint64_t unaligned_bytes_in_addr = (addr & ~(-1 << ADDRBITS));
|
||||
uint64_t bytes_upto_next_alignment = (0x1 << ADDRBITS)
|
||||
- unaligned_bytes_in_addr;
|
||||
|
||||
uint64_t buf_size = 0;
|
||||
if (bytes_upto_next_alignment > remaining_bytes_to_read) {
|
||||
buf_size = remaining_bytes_to_read;
|
||||
} else {
|
||||
buf_size = bytes_upto_next_alignment;
|
||||
}
|
||||
memcpy(dest_buf_ptr, src_buf_ptr, buf_size);
|
||||
read_bytes += buf_size;
|
||||
addr += buf_size;
|
||||
}
|
||||
if (m_report_handler->get_verbosity_level() == xsc::common_cpp::DEBUG) {
|
||||
std::stringstream msg;
|
||||
msg << module_name << " : ";
|
||||
msg << " Reading Memory Address = " << offset << " Size = " << size
|
||||
<< " Data = " << std::endl;
|
||||
uint64_t counter = 0;
|
||||
for (int i = 0; i < size; i++) {
|
||||
msg << (unsigned int) (((unsigned char*) dest)[i]) << " ";
|
||||
if (counter <= 16)
|
||||
counter++;
|
||||
else {
|
||||
counter = 0;
|
||||
msg << std::endl;
|
||||
}
|
||||
}
|
||||
msg << std::endl;
|
||||
m_report_handler->report("1", msg.str().c_str(), xsc::common_cpp::INFO,
|
||||
xsc::common_cpp::VERBOSITY::DEBUG);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
unsigned char* axi_bram_ram_fmodel::get_page(uint64_t offset,
|
||||
std::string& p2pFileName, uint64_t size) {
|
||||
uint64_t page_idx = offset >> ADDRBITS;
|
||||
std::string file_name = get_mem_file_name(page_idx);
|
||||
if (pageCache.size() > N_1MBARRAYS) {
|
||||
std::cerr
|
||||
<< "Out of Memory. DDR model does not support this much of memory\n";
|
||||
exit(1);
|
||||
} else {
|
||||
FILE* pFile = NULL;
|
||||
if (pageCache.find(page_idx) != pageCache.end()) {
|
||||
return pageCache[page_idx];
|
||||
} else {
|
||||
|
||||
if (size != 0) {
|
||||
int fd = -1;
|
||||
p2pFileName = file_name + "_shared";
|
||||
if ((fd = open(p2pFileName.c_str(), O_CREAT | O_RDWR,
|
||||
S_IRWXU | S_IRGRP | S_IROTH)) == -1) {
|
||||
printf("Error opening file.\n");
|
||||
}
|
||||
void* pageStartOSAddressVoid = mmap(0, size,
|
||||
PROT_READ | PROT_WRITE | PROT_EXEC, MAP_SHARED, fd,
|
||||
0/*sysconf(_SC_PAGESIZE)*/);
|
||||
if (fd < 0) {
|
||||
munmap(pageStartOSAddressVoid, size);
|
||||
p2pFileName = "";
|
||||
}
|
||||
|
||||
if (ftruncate(fd, size) < 0) {
|
||||
close(fd);
|
||||
munmap(pageStartOSAddressVoid, size);
|
||||
p2pFileName = "";
|
||||
}
|
||||
if (!p2pFileName.empty()) {
|
||||
unsigned char* pagePtr =
|
||||
(unsigned char*) pageStartOSAddressVoid;
|
||||
while (size > 0) {
|
||||
pageCache[page_idx] = pagePtr;
|
||||
page_idx = page_idx + 1;
|
||||
pagePtr = pagePtr + PAGESIZE;
|
||||
if (size <= PAGESIZE)
|
||||
break;
|
||||
size = size - PAGESIZE;
|
||||
std::cout << "page_idx is " << page_idx << std::endl;
|
||||
std::cout << "size is " << size << std::endl;
|
||||
}
|
||||
return (unsigned char*) pageStartOSAddressVoid;
|
||||
}
|
||||
}
|
||||
|
||||
pageCache[page_idx] = new unsigned char[PAGESIZE];
|
||||
//for(int i = 0; i < ONE_MB;i++){
|
||||
// pageCache[page_idx][i] = 0x0;
|
||||
//}
|
||||
return pageCache[page_idx];
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void axi_bram_ram_fmodel::init_fmodel() {
|
||||
|
||||
}
|
||||
|
||||
bool axi_bram_ram_fmodel::createMMappedBuffer(uint64_t base_address,
|
||||
uint64_t size, std::string& buffer_filename) {
|
||||
return true;
|
||||
}
|
||||
|
||||
bool axi_bram_ram_fmodel::freePage(uint64_t base_address) {
|
||||
return true;
|
||||
}
|
||||
|
||||
bool axi_bram_ram_fmodel::copyBO(uint64_t offset,
|
||||
std::string dst_filename, uint64_t size, uint64_t src_offset,
|
||||
uint64_t dst_offset) {
|
||||
return true;
|
||||
|
||||
}
|
||||
|
||||
bool axi_bram_ram_fmodel::importBO(uint64_t offset,
|
||||
std::string dst_filename, uint64_t size) {
|
||||
return true;
|
||||
}
|
||||
|
||||
std::string axi_bram_ram_fmodel::get_mem_file_name(uint64_t pageIdx) //,enum fileType file_type)
|
||||
{
|
||||
std::string file_name;
|
||||
std::string socket_id;
|
||||
std::string pid;
|
||||
std::string deviceName("");
|
||||
std::string user("");
|
||||
if (getenv("EMULATION_SOCKETID")) {
|
||||
socket_id = getenv("EMULATION_SOCKETID");
|
||||
std::size_t foundLast = socket_id.find_last_of("_");
|
||||
std::size_t foundFirst = socket_id.find_first_of("_");
|
||||
if (foundLast != std::string::npos) {
|
||||
pid = socket_id.substr(foundLast + 1);
|
||||
}
|
||||
if (foundFirst != std::string::npos) {
|
||||
deviceName = socket_id.substr(0, foundFirst);
|
||||
}
|
||||
}
|
||||
|
||||
if (getenv("USER") != NULL) {
|
||||
user = getenv("USER");
|
||||
}
|
||||
std::string file_path("");
|
||||
std::string sEmRunDir("");
|
||||
|
||||
if (getenv("EMULATION_RUN_DIR")) {
|
||||
sEmRunDir = getenv("EMULATION_RUN_DIR");
|
||||
} else {
|
||||
sEmRunDir = "/tmp/" + user + "/hw_em/";
|
||||
}
|
||||
|
||||
file_path = sEmRunDir + "/" + module_name + "/";
|
||||
std::stringstream mkdirCommand;
|
||||
mkdirCommand << "mkdir -p " << file_path;
|
||||
;
|
||||
struct stat statBuf;
|
||||
if (stat(file_path.c_str(), &statBuf) == -1) {
|
||||
system(mkdirCommand.str().c_str());
|
||||
}
|
||||
file_name = file_path + module_name + "_" + std::to_string(pageIdx);
|
||||
if (m_report_handler->get_verbosity_level()
|
||||
== xsc::common_cpp::VERBOSITY::DEBUG) {
|
||||
std::stringstream m_ss;
|
||||
m_ss.str("");
|
||||
m_ss << "ddr fmodel file_name: " << file_name << std::endl;
|
||||
m_report_handler->report("1", m_ss.str().c_str(), xsc::common_cpp::INFO,
|
||||
xsc::common_cpp::VERBOSITY::DEBUG);
|
||||
}
|
||||
return file_name;
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,113 @@
|
|||
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
#ifndef OCL_PLATFORM_H
|
||||
#define OCL_PLATFORM_H
|
||||
#include <math.h>
|
||||
#include <iostream>
|
||||
#include "report_handler.h"
|
||||
#include "axi_bram_fmodel_base.h"
|
||||
|
||||
#include <string.h> // memcpy
|
||||
#include <stdlib.h> //realloc
|
||||
#include <stdint.h>
|
||||
#include <vector>
|
||||
#include <map> //realloc
|
||||
//Uncomment to print the latency calculation log
|
||||
//#define DEBUGMSG
|
||||
|
||||
#define ONE_KB (0x400)
|
||||
#define ONE_MB (ONE_KB * ONE_KB)
|
||||
#define PAGESIZE (ONE_MB)
|
||||
#define ADDRBITS (20)
|
||||
#define N_1MBARRAYS 4096
|
||||
|
||||
//Calculations for Strb
|
||||
//Its Array of 64bit integer
|
||||
#define STRB_SIZE 64
|
||||
#define ONE_KB_STRB (ONE_KB / STRB_SIZE)
|
||||
#define ONE_MB_STRB (ONE_KB_STRB * ONE_KB)
|
||||
|
||||
//using namespace std;
|
||||
|
||||
#define RBC 0
|
||||
#define BRC 1
|
||||
#define RCB 2
|
||||
|
||||
enum fileType {MEM,MEM_STRB};
|
||||
//Models fixed portion of the platform
|
||||
class axi_bram_ram_fmodel:public axi_bram_fmodel_base{
|
||||
public:
|
||||
unsigned int writeDevMem(uint64_t offset, void* src, unsigned int size);
|
||||
unsigned int readDevMem(uint64_t offset, void* dest, unsigned int size);
|
||||
unsigned char* get_page(uint64_t offset, std::string& p2pFileName, uint64_t size = 0);
|
||||
bool createMMappedBuffer(uint64_t base_address,uint64_t size,std::string& buffer_filename);
|
||||
bool freePage(uint64_t base_address);
|
||||
bool copyBO(uint64_t offset, std::string dst_filename, uint64_t size, uint64_t src_offset, uint64_t dst_offset);
|
||||
bool importBO(uint64_t offset, std::string dst_filename,uint64_t size);
|
||||
void reset_fmodel(){};
|
||||
std::string get_mem_file_name(uint64_t pageIdx);
|
||||
|
||||
protected:
|
||||
private:
|
||||
//unsigned char* get_page(uint64_t offset);
|
||||
//Paging
|
||||
std::map<uint64_t,unsigned char*> pageCache;
|
||||
std::map<uint64_t,unsigned char*>::iterator pageCacheItr;
|
||||
std::string module_name;
|
||||
xsc::common_cpp::report_handler* m_report_handler;
|
||||
uint64_t m_mem_addr_width;
|
||||
public:
|
||||
axi_bram_ram_fmodel(std::string p_module_name,xsc::common_cpp::report_handler* report_handler,uint64_t addr_size);
|
||||
~ axi_bram_ram_fmodel();
|
||||
void init_fmodel();
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,350 @@
|
|||
-- (c) Copyright 1995-2025 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:axi_bram_ctrl:4.1
|
||||
-- IP Revision: 6
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY axi_bram_ctrl_v4_1_6;
|
||||
USE axi_bram_ctrl_v4_1_6.axi_bram_ctrl;
|
||||
|
||||
ENTITY top_axi_bram_ctrl_0_0 IS
|
||||
PORT (
|
||||
s_axi_aclk : IN STD_LOGIC;
|
||||
s_axi_aresetn : IN STD_LOGIC;
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_awlock : IN STD_LOGIC;
|
||||
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_wlast : IN STD_LOGIC;
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_arlock : IN STD_LOGIC;
|
||||
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rlast : OUT STD_LOGIC;
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
bram_rst_a : OUT STD_LOGIC;
|
||||
bram_clk_a : OUT STD_LOGIC;
|
||||
bram_en_a : OUT STD_LOGIC;
|
||||
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
bram_addr_a : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
bram_rst_b : OUT STD_LOGIC;
|
||||
bram_clk_b : OUT STD_LOGIC;
|
||||
bram_en_b : OUT STD_LOGIC;
|
||||
bram_we_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
bram_addr_b : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
bram_wrdata_b : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
bram_rddata_b : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END top_axi_bram_ctrl_0_0;
|
||||
|
||||
ARCHITECTURE top_axi_bram_ctrl_0_0_arch OF top_axi_bram_ctrl_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF top_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axi_bram_ctrl IS
|
||||
GENERIC (
|
||||
C_BRAM_INST_MODE : STRING;
|
||||
C_MEMORY_DEPTH : INTEGER;
|
||||
C_BRAM_ADDR_WIDTH : INTEGER;
|
||||
C_S_AXI_ADDR_WIDTH : INTEGER;
|
||||
C_S_AXI_DATA_WIDTH : INTEGER;
|
||||
C_S_AXI_ID_WIDTH : INTEGER;
|
||||
C_S_AXI_PROTOCOL : STRING;
|
||||
C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER;
|
||||
C_SINGLE_PORT_BRAM : INTEGER;
|
||||
C_FAMILY : STRING;
|
||||
C_READ_LATENCY : INTEGER;
|
||||
C_RD_CMD_OPTIMIZATION : INTEGER;
|
||||
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
|
||||
C_S_AXI_CTRL_DATA_WIDTH : INTEGER;
|
||||
C_ECC : INTEGER;
|
||||
C_ECC_TYPE : INTEGER;
|
||||
C_FAULT_INJECT : INTEGER;
|
||||
C_ECC_ONOFF_RESET_VALUE : INTEGER
|
||||
);
|
||||
PORT (
|
||||
s_axi_aclk : IN STD_LOGIC;
|
||||
s_axi_aresetn : IN STD_LOGIC;
|
||||
ecc_interrupt : OUT STD_LOGIC;
|
||||
ecc_ue : OUT STD_LOGIC;
|
||||
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_awlock : IN STD_LOGIC;
|
||||
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_wlast : IN STD_LOGIC;
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_arlock : IN STD_LOGIC;
|
||||
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rlast : OUT STD_LOGIC;
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
s_axi_ctrl_awvalid : IN STD_LOGIC;
|
||||
s_axi_ctrl_awready : OUT STD_LOGIC;
|
||||
s_axi_ctrl_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_ctrl_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_ctrl_wvalid : IN STD_LOGIC;
|
||||
s_axi_ctrl_wready : OUT STD_LOGIC;
|
||||
s_axi_ctrl_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_ctrl_bvalid : OUT STD_LOGIC;
|
||||
s_axi_ctrl_bready : IN STD_LOGIC;
|
||||
s_axi_ctrl_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_ctrl_arvalid : IN STD_LOGIC;
|
||||
s_axi_ctrl_arready : OUT STD_LOGIC;
|
||||
s_axi_ctrl_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_ctrl_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_ctrl_rvalid : OUT STD_LOGIC;
|
||||
s_axi_ctrl_rready : IN STD_LOGIC;
|
||||
bram_rst_a : OUT STD_LOGIC;
|
||||
bram_clk_a : OUT STD_LOGIC;
|
||||
bram_en_a : OUT STD_LOGIC;
|
||||
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
bram_addr_a : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
bram_rst_b : OUT STD_LOGIC;
|
||||
bram_clk_b : OUT STD_LOGIC;
|
||||
bram_en_b : OUT STD_LOGIC;
|
||||
bram_we_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
bram_addr_b : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
bram_wrdata_b : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
bram_rddata_b : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT axi_bram_ctrl;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF top_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "axi_bram_ctrl,Vivado 2022.1";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF top_axi_bram_ctrl_0_0_arch : ARCHITECTURE IS "top_axi_bram_ctrl_0_0,axi_bram_ctrl,{}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF top_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "top_axi_bram_ctrl_0_0,axi_bram_ctrl,{x_ipProduct=Vivado 2022.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_bram_ctrl,x_ipVersion=4.1,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_BRAM_INST_MODE=EXTERNAL,C_MEMORY_DEPTH=16384,C_BRAM_ADDR_WIDTH=14,C_S_AXI_ADDR_WIDTH=16,C_S_AXI_DATA_WIDTH=32,C_S_AXI_ID_WIDTH=1,C_S_AXI_PROTOCOL=AXI4,C_S_AXI_SUPPORTS_NARROW_BURST=0,C_SINGLE_PORT_BRAM=0,C_FAMILY=artix7,C_READ_LATENCY=1,C_RD_CMD_OPTIMIZATION=0,C_S_AXI_CTRL_ADDR_WIDTH=32,C_S_AXI_C" &
|
||||
"TRL_DATA_WIDTH=32,C_ECC=0,C_ECC_TYPE=0,C_FAULT_INJECT=0,C_ECC_ONOFF_RESET_VALUE=0}";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_addr_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_addr_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_clk_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_clk_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_en_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_en_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_rddata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_rddata_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF bram_rst_a: SIGNAL IS "XIL_INTERFACENAME BRAM_PORTA, MASTER_TYPE BRAM_CTRL, MEM_SIZE 65536, MEM_WIDTH 32, MEM_ECC NONE, READ_WRITE_MODE WRITE_ONLY, READ_LATENCY 1";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_rst_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF bram_rst_b: SIGNAL IS "XIL_INTERFACENAME BRAM_PORTB, MASTER_TYPE BRAM_CTRL, MEM_SIZE 65536, MEM_WIDTH 32, MEM_ECC NONE, READ_WRITE_MODE READ_ONLY, READ_LATENCY 1";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_rst_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_we_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_we_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_wrdata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bram_wrdata_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME CLKIF, ASSOCIATED_BUSIF S_AXI:S_AXI_CTRL, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 125000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN top_xdma_0_0_axi_aclk, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLKIF CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARBURST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 RSTIF RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLEN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARPROT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 125000000, ID_WIDTH 0, ADDR_WIDTH 16, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 32, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 256, PHASE 0.0, CLK_DOMAIN top_xdma_0_0_axi_aclk, NUM_READ_THREADS 1, NUM_WRITE_THREADS" &
|
||||
" 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWBURST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLEN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWPROT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WLAST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
|
||||
BEGIN
|
||||
U0 : axi_bram_ctrl
|
||||
GENERIC MAP (
|
||||
C_BRAM_INST_MODE => "EXTERNAL",
|
||||
C_MEMORY_DEPTH => 16384,
|
||||
C_BRAM_ADDR_WIDTH => 14,
|
||||
C_S_AXI_ADDR_WIDTH => 16,
|
||||
C_S_AXI_DATA_WIDTH => 32,
|
||||
C_S_AXI_ID_WIDTH => 1,
|
||||
C_S_AXI_PROTOCOL => "AXI4",
|
||||
C_S_AXI_SUPPORTS_NARROW_BURST => 0,
|
||||
C_SINGLE_PORT_BRAM => 0,
|
||||
C_FAMILY => "artix7",
|
||||
C_READ_LATENCY => 1,
|
||||
C_RD_CMD_OPTIMIZATION => 0,
|
||||
C_S_AXI_CTRL_ADDR_WIDTH => 32,
|
||||
C_S_AXI_CTRL_DATA_WIDTH => 32,
|
||||
C_ECC => 0,
|
||||
C_ECC_TYPE => 0,
|
||||
C_FAULT_INJECT => 0,
|
||||
C_ECC_ONOFF_RESET_VALUE => 0
|
||||
)
|
||||
PORT MAP (
|
||||
s_axi_aclk => s_axi_aclk,
|
||||
s_axi_aresetn => s_axi_aresetn,
|
||||
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axi_awaddr => s_axi_awaddr,
|
||||
s_axi_awlen => s_axi_awlen,
|
||||
s_axi_awsize => s_axi_awsize,
|
||||
s_axi_awburst => s_axi_awburst,
|
||||
s_axi_awlock => s_axi_awlock,
|
||||
s_axi_awcache => s_axi_awcache,
|
||||
s_axi_awprot => s_axi_awprot,
|
||||
s_axi_awvalid => s_axi_awvalid,
|
||||
s_axi_awready => s_axi_awready,
|
||||
s_axi_wdata => s_axi_wdata,
|
||||
s_axi_wstrb => s_axi_wstrb,
|
||||
s_axi_wlast => s_axi_wlast,
|
||||
s_axi_wvalid => s_axi_wvalid,
|
||||
s_axi_wready => s_axi_wready,
|
||||
s_axi_bresp => s_axi_bresp,
|
||||
s_axi_bvalid => s_axi_bvalid,
|
||||
s_axi_bready => s_axi_bready,
|
||||
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axi_araddr => s_axi_araddr,
|
||||
s_axi_arlen => s_axi_arlen,
|
||||
s_axi_arsize => s_axi_arsize,
|
||||
s_axi_arburst => s_axi_arburst,
|
||||
s_axi_arlock => s_axi_arlock,
|
||||
s_axi_arcache => s_axi_arcache,
|
||||
s_axi_arprot => s_axi_arprot,
|
||||
s_axi_arvalid => s_axi_arvalid,
|
||||
s_axi_arready => s_axi_arready,
|
||||
s_axi_rdata => s_axi_rdata,
|
||||
s_axi_rresp => s_axi_rresp,
|
||||
s_axi_rlast => s_axi_rlast,
|
||||
s_axi_rvalid => s_axi_rvalid,
|
||||
s_axi_rready => s_axi_rready,
|
||||
s_axi_ctrl_awvalid => '0',
|
||||
s_axi_ctrl_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
s_axi_ctrl_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
s_axi_ctrl_wvalid => '0',
|
||||
s_axi_ctrl_bready => '0',
|
||||
s_axi_ctrl_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
s_axi_ctrl_arvalid => '0',
|
||||
s_axi_ctrl_rready => '0',
|
||||
bram_rst_a => bram_rst_a,
|
||||
bram_clk_a => bram_clk_a,
|
||||
bram_en_a => bram_en_a,
|
||||
bram_we_a => bram_we_a,
|
||||
bram_addr_a => bram_addr_a,
|
||||
bram_wrdata_a => bram_wrdata_a,
|
||||
bram_rddata_a => bram_rddata_a,
|
||||
bram_rst_b => bram_rst_b,
|
||||
bram_clk_b => bram_clk_b,
|
||||
bram_en_b => bram_en_b,
|
||||
bram_we_b => bram_we_b,
|
||||
bram_addr_b => bram_addr_b,
|
||||
bram_wrdata_b => bram_wrdata_b,
|
||||
bram_rddata_b => bram_rddata_b
|
||||
);
|
||||
END top_axi_bram_ctrl_0_0_arch;
|
||||
Binary file not shown.
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,57 @@
|
|||
# (c) Copyright 2012-2025 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
# DO NOT MODIFY THIS FILE.
|
||||
# #########################################################
|
||||
#
|
||||
# This XDC is used only in OOC mode for synthesis, implementation
|
||||
#
|
||||
# #########################################################
|
||||
|
||||
|
||||
create_clock -period 8 -name s_axi_aclk [get_ports s_axi_aclk]
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,73 @@
|
|||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
|
||||
// Date : Tue Jun 24 11:58:35 2025
|
||||
// Host : media-wawa running 64-bit NixOS 25.05 (Warbler)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_axi_bram_ctrl_0_0/top_axi_bram_ctrl_0_0_stub.v
|
||||
// Design : top_axi_bram_ctrl_0_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7a100tlfgg484-2L
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "axi_bram_ctrl,Vivado 2022.1" *)
|
||||
module top_axi_bram_ctrl_0_0(s_axi_aclk, s_axi_aresetn, s_axi_awaddr,
|
||||
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
|
||||
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wlast, s_axi_wvalid,
|
||||
s_axi_wready, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arlen,
|
||||
s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache, s_axi_arprot, s_axi_arvalid,
|
||||
s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rlast, s_axi_rvalid, s_axi_rready, bram_rst_a,
|
||||
bram_clk_a, bram_en_a, bram_we_a, bram_addr_a, bram_wrdata_a, bram_rddata_a, bram_rst_b,
|
||||
bram_clk_b, bram_en_b, bram_we_b, bram_addr_b, bram_wrdata_b, bram_rddata_b)
|
||||
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awaddr[15:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock,s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[15:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock,s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,bram_rst_a,bram_clk_a,bram_en_a,bram_we_a[3:0],bram_addr_a[15:0],bram_wrdata_a[31:0],bram_rddata_a[31:0],bram_rst_b,bram_clk_b,bram_en_b,bram_we_b[3:0],bram_addr_b[15:0],bram_wrdata_b[31:0],bram_rddata_b[31:0]" */;
|
||||
input s_axi_aclk;
|
||||
input s_axi_aresetn;
|
||||
input [15:0]s_axi_awaddr;
|
||||
input [7:0]s_axi_awlen;
|
||||
input [2:0]s_axi_awsize;
|
||||
input [1:0]s_axi_awburst;
|
||||
input s_axi_awlock;
|
||||
input [3:0]s_axi_awcache;
|
||||
input [2:0]s_axi_awprot;
|
||||
input s_axi_awvalid;
|
||||
output s_axi_awready;
|
||||
input [31:0]s_axi_wdata;
|
||||
input [3:0]s_axi_wstrb;
|
||||
input s_axi_wlast;
|
||||
input s_axi_wvalid;
|
||||
output s_axi_wready;
|
||||
output [1:0]s_axi_bresp;
|
||||
output s_axi_bvalid;
|
||||
input s_axi_bready;
|
||||
input [15:0]s_axi_araddr;
|
||||
input [7:0]s_axi_arlen;
|
||||
input [2:0]s_axi_arsize;
|
||||
input [1:0]s_axi_arburst;
|
||||
input s_axi_arlock;
|
||||
input [3:0]s_axi_arcache;
|
||||
input [2:0]s_axi_arprot;
|
||||
input s_axi_arvalid;
|
||||
output s_axi_arready;
|
||||
output [31:0]s_axi_rdata;
|
||||
output [1:0]s_axi_rresp;
|
||||
output s_axi_rlast;
|
||||
output s_axi_rvalid;
|
||||
input s_axi_rready;
|
||||
output bram_rst_a;
|
||||
output bram_clk_a;
|
||||
output bram_en_a;
|
||||
output [3:0]bram_we_a;
|
||||
output [15:0]bram_addr_a;
|
||||
output [31:0]bram_wrdata_a;
|
||||
input [31:0]bram_rddata_a;
|
||||
output bram_rst_b;
|
||||
output bram_clk_b;
|
||||
output bram_en_b;
|
||||
output [3:0]bram_we_b;
|
||||
output [15:0]bram_addr_b;
|
||||
output [31:0]bram_wrdata_b;
|
||||
input [31:0]bram_rddata_b;
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,76 @@
|
|||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
|
||||
-- Date : Tue Jun 24 11:58:35 2025
|
||||
-- Host : media-wawa running 64-bit NixOS 25.05 (Warbler)
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_axi_bram_ctrl_0_0/top_axi_bram_ctrl_0_0_stub.vhdl
|
||||
-- Design : top_axi_bram_ctrl_0_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7a100tlfgg484-2L
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity top_axi_bram_ctrl_0_0 is
|
||||
Port (
|
||||
s_axi_aclk : in STD_LOGIC;
|
||||
s_axi_aresetn : in STD_LOGIC;
|
||||
s_axi_awaddr : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_awlock : in STD_LOGIC;
|
||||
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_awvalid : in STD_LOGIC;
|
||||
s_axi_awready : out STD_LOGIC;
|
||||
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_wlast : in STD_LOGIC;
|
||||
s_axi_wvalid : in STD_LOGIC;
|
||||
s_axi_wready : out STD_LOGIC;
|
||||
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_bvalid : out STD_LOGIC;
|
||||
s_axi_bready : in STD_LOGIC;
|
||||
s_axi_araddr : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_arlock : in STD_LOGIC;
|
||||
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_arvalid : in STD_LOGIC;
|
||||
s_axi_arready : out STD_LOGIC;
|
||||
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_rlast : out STD_LOGIC;
|
||||
s_axi_rvalid : out STD_LOGIC;
|
||||
s_axi_rready : in STD_LOGIC;
|
||||
bram_rst_a : out STD_LOGIC;
|
||||
bram_clk_a : out STD_LOGIC;
|
||||
bram_en_a : out STD_LOGIC;
|
||||
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
bram_addr_a : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
bram_rddata_a : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
bram_rst_b : out STD_LOGIC;
|
||||
bram_clk_b : out STD_LOGIC;
|
||||
bram_en_b : out STD_LOGIC;
|
||||
bram_we_b : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
bram_addr_b : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
bram_wrdata_b : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 )
|
||||
);
|
||||
|
||||
end top_axi_bram_ctrl_0_0;
|
||||
|
||||
architecture stub of top_axi_bram_ctrl_0_0 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "s_axi_aclk,s_axi_aresetn,s_axi_awaddr[15:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock,s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[15:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock,s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,bram_rst_a,bram_clk_a,bram_en_a,bram_we_a[3:0],bram_addr_a[15:0],bram_wrdata_a[31:0],bram_rddata_a[31:0],bram_rst_b,bram_clk_b,bram_en_b,bram_we_b[3:0],bram_addr_b[15:0],bram_wrdata_b[31:0],bram_rddata_b[31:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "axi_bram_ctrl,Vivado 2022.1";
|
||||
begin
|
||||
end;
|
||||
|
|
@ -0,0 +1,204 @@
|
|||
-- (c) Copyright 1995-2025 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
|
||||
-- IP Revision: 28
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY axi_gpio_v2_0_28;
|
||||
USE axi_gpio_v2_0_28.axi_gpio;
|
||||
|
||||
ENTITY top_axi_gpio_0_0 IS
|
||||
PORT (
|
||||
s_axi_aclk : IN STD_LOGIC;
|
||||
s_axi_aresetn : IN STD_LOGIC;
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
gpio_io_o : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
|
||||
);
|
||||
END top_axi_gpio_0_0;
|
||||
|
||||
ARCHITECTURE top_axi_gpio_0_0_arch OF top_axi_gpio_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF top_axi_gpio_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axi_gpio IS
|
||||
GENERIC (
|
||||
C_FAMILY : STRING;
|
||||
C_S_AXI_ADDR_WIDTH : INTEGER;
|
||||
C_S_AXI_DATA_WIDTH : INTEGER;
|
||||
C_GPIO_WIDTH : INTEGER;
|
||||
C_GPIO2_WIDTH : INTEGER;
|
||||
C_ALL_INPUTS : INTEGER;
|
||||
C_ALL_INPUTS_2 : INTEGER;
|
||||
C_ALL_OUTPUTS : INTEGER;
|
||||
C_ALL_OUTPUTS_2 : INTEGER;
|
||||
C_INTERRUPT_PRESENT : INTEGER;
|
||||
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_IS_DUAL : INTEGER;
|
||||
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
PORT (
|
||||
s_axi_aclk : IN STD_LOGIC;
|
||||
s_axi_aresetn : IN STD_LOGIC;
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
ip2intc_irpt : OUT STD_LOGIC;
|
||||
gpio_io_i : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
gpio_io_o : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
gpio_io_t : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT axi_gpio;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF gpio_io_o: SIGNAL IS "XIL_INTERFACENAME GPIO, BOARD.ASSOCIATED_PARAM GPIO_BOARD_INTERFACE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 125000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN top_xdma_0_0_axi_aclk, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 125000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN top_xdma_0_0_axi_aclk, NUM_READ_THREADS 1, NUM_WRITE_THREADS " &
|
||||
"1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
|
||||
BEGIN
|
||||
U0 : axi_gpio
|
||||
GENERIC MAP (
|
||||
C_FAMILY => "artix7",
|
||||
C_S_AXI_ADDR_WIDTH => 9,
|
||||
C_S_AXI_DATA_WIDTH => 32,
|
||||
C_GPIO_WIDTH => 2,
|
||||
C_GPIO2_WIDTH => 32,
|
||||
C_ALL_INPUTS => 0,
|
||||
C_ALL_INPUTS_2 => 0,
|
||||
C_ALL_OUTPUTS => 1,
|
||||
C_ALL_OUTPUTS_2 => 0,
|
||||
C_INTERRUPT_PRESENT => 0,
|
||||
C_DOUT_DEFAULT => X"00000000",
|
||||
C_TRI_DEFAULT => X"FFFFFFFF",
|
||||
C_IS_DUAL => 0,
|
||||
C_DOUT_DEFAULT_2 => X"00000000",
|
||||
C_TRI_DEFAULT_2 => X"FFFFFFFF"
|
||||
)
|
||||
PORT MAP (
|
||||
s_axi_aclk => s_axi_aclk,
|
||||
s_axi_aresetn => s_axi_aresetn,
|
||||
s_axi_awaddr => s_axi_awaddr,
|
||||
s_axi_awvalid => s_axi_awvalid,
|
||||
s_axi_awready => s_axi_awready,
|
||||
s_axi_wdata => s_axi_wdata,
|
||||
s_axi_wstrb => s_axi_wstrb,
|
||||
s_axi_wvalid => s_axi_wvalid,
|
||||
s_axi_wready => s_axi_wready,
|
||||
s_axi_bresp => s_axi_bresp,
|
||||
s_axi_bvalid => s_axi_bvalid,
|
||||
s_axi_bready => s_axi_bready,
|
||||
s_axi_araddr => s_axi_araddr,
|
||||
s_axi_arvalid => s_axi_arvalid,
|
||||
s_axi_arready => s_axi_arready,
|
||||
s_axi_rdata => s_axi_rdata,
|
||||
s_axi_rresp => s_axi_rresp,
|
||||
s_axi_rvalid => s_axi_rvalid,
|
||||
s_axi_rready => s_axi_rready,
|
||||
gpio_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
|
||||
gpio_io_o => gpio_io_o,
|
||||
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
|
||||
);
|
||||
END top_axi_gpio_0_0_arch;
|
||||
|
|
@ -0,0 +1,210 @@
|
|||
-- (c) Copyright 1995-2025 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
|
||||
-- IP Revision: 28
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY axi_gpio_v2_0_28;
|
||||
USE axi_gpio_v2_0_28.axi_gpio;
|
||||
|
||||
ENTITY top_axi_gpio_0_0 IS
|
||||
PORT (
|
||||
s_axi_aclk : IN STD_LOGIC;
|
||||
s_axi_aresetn : IN STD_LOGIC;
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
gpio_io_o : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
|
||||
);
|
||||
END top_axi_gpio_0_0;
|
||||
|
||||
ARCHITECTURE top_axi_gpio_0_0_arch OF top_axi_gpio_0_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF top_axi_gpio_0_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT axi_gpio IS
|
||||
GENERIC (
|
||||
C_FAMILY : STRING;
|
||||
C_S_AXI_ADDR_WIDTH : INTEGER;
|
||||
C_S_AXI_DATA_WIDTH : INTEGER;
|
||||
C_GPIO_WIDTH : INTEGER;
|
||||
C_GPIO2_WIDTH : INTEGER;
|
||||
C_ALL_INPUTS : INTEGER;
|
||||
C_ALL_INPUTS_2 : INTEGER;
|
||||
C_ALL_OUTPUTS : INTEGER;
|
||||
C_ALL_OUTPUTS_2 : INTEGER;
|
||||
C_INTERRUPT_PRESENT : INTEGER;
|
||||
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_IS_DUAL : INTEGER;
|
||||
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
PORT (
|
||||
s_axi_aclk : IN STD_LOGIC;
|
||||
s_axi_aresetn : IN STD_LOGIC;
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
ip2intc_irpt : OUT STD_LOGIC;
|
||||
gpio_io_i : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
gpio_io_o : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
gpio_io_t : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT axi_gpio;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF top_axi_gpio_0_0_arch: ARCHITECTURE IS "axi_gpio,Vivado 2022.1";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF top_axi_gpio_0_0_arch : ARCHITECTURE IS "top_axi_gpio_0_0,axi_gpio,{}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF top_axi_gpio_0_0_arch: ARCHITECTURE IS "top_axi_gpio_0_0,axi_gpio,{x_ipProduct=Vivado 2022.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=28,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=2,C_GPIO2_WIDTH=32,C_ALL_INPUTS=0,C_ALL_INPUTS_2=0,C_ALL_OUTPUTS=1,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=0,C_DOUT_DEFAULT=0x00000000,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=0,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF gpio_io_o: SIGNAL IS "XIL_INTERFACENAME GPIO, BOARD.ASSOCIATED_PARAM GPIO_BOARD_INTERFACE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 125000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN top_xdma_0_0_axi_aclk, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 125000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN top_xdma_0_0_axi_aclk, NUM_READ_THREADS 1, NUM_WRITE_THREADS " &
|
||||
"1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
|
||||
BEGIN
|
||||
U0 : axi_gpio
|
||||
GENERIC MAP (
|
||||
C_FAMILY => "artix7",
|
||||
C_S_AXI_ADDR_WIDTH => 9,
|
||||
C_S_AXI_DATA_WIDTH => 32,
|
||||
C_GPIO_WIDTH => 2,
|
||||
C_GPIO2_WIDTH => 32,
|
||||
C_ALL_INPUTS => 0,
|
||||
C_ALL_INPUTS_2 => 0,
|
||||
C_ALL_OUTPUTS => 1,
|
||||
C_ALL_OUTPUTS_2 => 0,
|
||||
C_INTERRUPT_PRESENT => 0,
|
||||
C_DOUT_DEFAULT => X"00000000",
|
||||
C_TRI_DEFAULT => X"FFFFFFFF",
|
||||
C_IS_DUAL => 0,
|
||||
C_DOUT_DEFAULT_2 => X"00000000",
|
||||
C_TRI_DEFAULT_2 => X"FFFFFFFF"
|
||||
)
|
||||
PORT MAP (
|
||||
s_axi_aclk => s_axi_aclk,
|
||||
s_axi_aresetn => s_axi_aresetn,
|
||||
s_axi_awaddr => s_axi_awaddr,
|
||||
s_axi_awvalid => s_axi_awvalid,
|
||||
s_axi_awready => s_axi_awready,
|
||||
s_axi_wdata => s_axi_wdata,
|
||||
s_axi_wstrb => s_axi_wstrb,
|
||||
s_axi_wvalid => s_axi_wvalid,
|
||||
s_axi_wready => s_axi_wready,
|
||||
s_axi_bresp => s_axi_bresp,
|
||||
s_axi_bvalid => s_axi_bvalid,
|
||||
s_axi_bready => s_axi_bready,
|
||||
s_axi_araddr => s_axi_araddr,
|
||||
s_axi_arvalid => s_axi_arvalid,
|
||||
s_axi_arready => s_axi_arready,
|
||||
s_axi_rdata => s_axi_rdata,
|
||||
s_axi_rresp => s_axi_rresp,
|
||||
s_axi_rvalid => s_axi_rvalid,
|
||||
s_axi_rready => s_axi_rready,
|
||||
gpio_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
|
||||
gpio_io_o => gpio_io_o,
|
||||
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
|
||||
);
|
||||
END top_axi_gpio_0_0_arch;
|
||||
Binary file not shown.
|
|
@ -0,0 +1,47 @@
|
|||
# (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,2 @@
|
|||
#--------------------Physical Constraints-----------------
|
||||
|
||||
|
|
@ -0,0 +1,62 @@
|
|||
|
||||
################################################################################
|
||||
# (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
################################################################################
|
||||
|
||||
# This XDC is used only for OOC mode of synthesis, implementation
|
||||
# User should update the correct clock period before proceeding further
|
||||
# This constraints file contains default clock frequencies to be used during
|
||||
# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
|
||||
# For best results the frequencies should be modified# to match the target
|
||||
# frequencies.
|
||||
|
||||
|
||||
create_clock -name s_axi_clk -period 10 [get_ports s_axi_aclk]
|
||||
## set_property HD.CLK_SRC BUFGCTRL_X0Y0 [get_ports s_axi_aclk]
|
||||
|
||||
################################################################################
|
||||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,42 @@
|
|||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
|
||||
// Date : Tue Jun 24 11:58:35 2025
|
||||
// Host : media-wawa running 64-bit NixOS 25.05 (Warbler)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_axi_gpio_0_0/top_axi_gpio_0_0_stub.v
|
||||
// Design : top_axi_gpio_0_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7a100tlfgg484-2L
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "axi_gpio,Vivado 2022.1" *)
|
||||
module top_axi_gpio_0_0(s_axi_aclk, s_axi_aresetn, s_axi_awaddr,
|
||||
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
|
||||
s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready,
|
||||
s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, gpio_io_o)
|
||||
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_o[1:0]" */;
|
||||
input s_axi_aclk;
|
||||
input s_axi_aresetn;
|
||||
input [8:0]s_axi_awaddr;
|
||||
input s_axi_awvalid;
|
||||
output s_axi_awready;
|
||||
input [31:0]s_axi_wdata;
|
||||
input [3:0]s_axi_wstrb;
|
||||
input s_axi_wvalid;
|
||||
output s_axi_wready;
|
||||
output [1:0]s_axi_bresp;
|
||||
output s_axi_bvalid;
|
||||
input s_axi_bready;
|
||||
input [8:0]s_axi_araddr;
|
||||
input s_axi_arvalid;
|
||||
output s_axi_arready;
|
||||
output [31:0]s_axi_rdata;
|
||||
output [1:0]s_axi_rresp;
|
||||
output s_axi_rvalid;
|
||||
input s_axi_rready;
|
||||
output [1:0]gpio_io_o;
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
|
||||
-- Date : Tue Jun 24 11:58:35 2025
|
||||
-- Host : media-wawa running 64-bit NixOS 25.05 (Warbler)
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_axi_gpio_0_0/top_axi_gpio_0_0_stub.vhdl
|
||||
-- Design : top_axi_gpio_0_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7a100tlfgg484-2L
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity top_axi_gpio_0_0 is
|
||||
Port (
|
||||
s_axi_aclk : in STD_LOGIC;
|
||||
s_axi_aresetn : in STD_LOGIC;
|
||||
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
|
||||
s_axi_awvalid : in STD_LOGIC;
|
||||
s_axi_awready : out STD_LOGIC;
|
||||
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_wvalid : in STD_LOGIC;
|
||||
s_axi_wready : out STD_LOGIC;
|
||||
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_bvalid : out STD_LOGIC;
|
||||
s_axi_bready : in STD_LOGIC;
|
||||
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
|
||||
s_axi_arvalid : in STD_LOGIC;
|
||||
s_axi_arready : out STD_LOGIC;
|
||||
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_rvalid : out STD_LOGIC;
|
||||
s_axi_rready : in STD_LOGIC;
|
||||
gpio_io_o : out STD_LOGIC_VECTOR ( 1 downto 0 )
|
||||
);
|
||||
|
||||
end top_axi_gpio_0_0;
|
||||
|
||||
architecture stub of top_axi_gpio_0_0 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_o[1:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "axi_gpio,Vivado 2022.1";
|
||||
begin
|
||||
end;
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,43 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Root MajorVersion="0" MinorVersion="40">
|
||||
<CompositeFile CompositeFileTopName="bd_b43a" CanBeSetAsTop="true" CanDisplayChildGraph="true">
|
||||
<Description>Composite Fileset</Description>
|
||||
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1750771510"/>
|
||||
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1750771510"/>
|
||||
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1750771510"/>
|
||||
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1750771510"/>
|
||||
<FileCollection Name="SOURCES" Type="SOURCES">
|
||||
<File Name="synth/bd_b43a.v" Type="Verilog">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SYNTHESIS"/>
|
||||
<UsedIn Val="IMPLEMENTATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="sim/bd_b43a.v" Type="Verilog">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="sim/bd_b43a.protoinst">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="SIMULATION"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="hw_handoff/top_axi_smc_0.hwh" Type="HwHandoff">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
<File Name="synth/top_axi_smc_0.hwdef">
|
||||
<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
|
||||
<Library Name="xil_defaultlib"/>
|
||||
<UsedIn Val="HW_HANDOFF"/>
|
||||
<ProcessingOrder Val="NORMAL"/>
|
||||
</File>
|
||||
</FileCollection>
|
||||
</CompositeFile>
|
||||
</Root>
|
||||
|
|
@ -0,0 +1,301 @@
|
|||
//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
//--------------------------------------------------------------------------------
|
||||
//Command: generate_target bd_b43a_wrapper.bd
|
||||
//Design : bd_b43a_wrapper
|
||||
//Purpose: IP block netlist
|
||||
//--------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module bd_b43a_wrapper
|
||||
(M00_AXI_araddr,
|
||||
M00_AXI_arburst,
|
||||
M00_AXI_arcache,
|
||||
M00_AXI_arlen,
|
||||
M00_AXI_arlock,
|
||||
M00_AXI_arprot,
|
||||
M00_AXI_arqos,
|
||||
M00_AXI_arready,
|
||||
M00_AXI_arsize,
|
||||
M00_AXI_arvalid,
|
||||
M00_AXI_awaddr,
|
||||
M00_AXI_awburst,
|
||||
M00_AXI_awcache,
|
||||
M00_AXI_awlen,
|
||||
M00_AXI_awlock,
|
||||
M00_AXI_awprot,
|
||||
M00_AXI_awqos,
|
||||
M00_AXI_awready,
|
||||
M00_AXI_awsize,
|
||||
M00_AXI_awvalid,
|
||||
M00_AXI_bready,
|
||||
M00_AXI_bresp,
|
||||
M00_AXI_bvalid,
|
||||
M00_AXI_rdata,
|
||||
M00_AXI_rlast,
|
||||
M00_AXI_rready,
|
||||
M00_AXI_rresp,
|
||||
M00_AXI_rvalid,
|
||||
M00_AXI_wdata,
|
||||
M00_AXI_wlast,
|
||||
M00_AXI_wready,
|
||||
M00_AXI_wstrb,
|
||||
M00_AXI_wvalid,
|
||||
S00_AXI_araddr,
|
||||
S00_AXI_arburst,
|
||||
S00_AXI_arcache,
|
||||
S00_AXI_arid,
|
||||
S00_AXI_arlen,
|
||||
S00_AXI_arlock,
|
||||
S00_AXI_arprot,
|
||||
S00_AXI_arqos,
|
||||
S00_AXI_arready,
|
||||
S00_AXI_arsize,
|
||||
S00_AXI_arvalid,
|
||||
S00_AXI_awaddr,
|
||||
S00_AXI_awburst,
|
||||
S00_AXI_awcache,
|
||||
S00_AXI_awid,
|
||||
S00_AXI_awlen,
|
||||
S00_AXI_awlock,
|
||||
S00_AXI_awprot,
|
||||
S00_AXI_awqos,
|
||||
S00_AXI_awready,
|
||||
S00_AXI_awsize,
|
||||
S00_AXI_awvalid,
|
||||
S00_AXI_bid,
|
||||
S00_AXI_bready,
|
||||
S00_AXI_bresp,
|
||||
S00_AXI_bvalid,
|
||||
S00_AXI_rdata,
|
||||
S00_AXI_rid,
|
||||
S00_AXI_rlast,
|
||||
S00_AXI_rready,
|
||||
S00_AXI_rresp,
|
||||
S00_AXI_rvalid,
|
||||
S00_AXI_wdata,
|
||||
S00_AXI_wlast,
|
||||
S00_AXI_wready,
|
||||
S00_AXI_wstrb,
|
||||
S00_AXI_wvalid,
|
||||
aclk,
|
||||
aresetn);
|
||||
output [15:0]M00_AXI_araddr;
|
||||
output [1:0]M00_AXI_arburst;
|
||||
output [3:0]M00_AXI_arcache;
|
||||
output [7:0]M00_AXI_arlen;
|
||||
output [0:0]M00_AXI_arlock;
|
||||
output [2:0]M00_AXI_arprot;
|
||||
output [3:0]M00_AXI_arqos;
|
||||
input M00_AXI_arready;
|
||||
output [2:0]M00_AXI_arsize;
|
||||
output M00_AXI_arvalid;
|
||||
output [15:0]M00_AXI_awaddr;
|
||||
output [1:0]M00_AXI_awburst;
|
||||
output [3:0]M00_AXI_awcache;
|
||||
output [7:0]M00_AXI_awlen;
|
||||
output [0:0]M00_AXI_awlock;
|
||||
output [2:0]M00_AXI_awprot;
|
||||
output [3:0]M00_AXI_awqos;
|
||||
input M00_AXI_awready;
|
||||
output [2:0]M00_AXI_awsize;
|
||||
output M00_AXI_awvalid;
|
||||
output M00_AXI_bready;
|
||||
input [1:0]M00_AXI_bresp;
|
||||
input M00_AXI_bvalid;
|
||||
input [31:0]M00_AXI_rdata;
|
||||
input M00_AXI_rlast;
|
||||
output M00_AXI_rready;
|
||||
input [1:0]M00_AXI_rresp;
|
||||
input M00_AXI_rvalid;
|
||||
output [31:0]M00_AXI_wdata;
|
||||
output M00_AXI_wlast;
|
||||
input M00_AXI_wready;
|
||||
output [3:0]M00_AXI_wstrb;
|
||||
output M00_AXI_wvalid;
|
||||
input [63:0]S00_AXI_araddr;
|
||||
input [1:0]S00_AXI_arburst;
|
||||
input [3:0]S00_AXI_arcache;
|
||||
input [3:0]S00_AXI_arid;
|
||||
input [7:0]S00_AXI_arlen;
|
||||
input [0:0]S00_AXI_arlock;
|
||||
input [2:0]S00_AXI_arprot;
|
||||
input [3:0]S00_AXI_arqos;
|
||||
output S00_AXI_arready;
|
||||
input [2:0]S00_AXI_arsize;
|
||||
input S00_AXI_arvalid;
|
||||
input [63:0]S00_AXI_awaddr;
|
||||
input [1:0]S00_AXI_awburst;
|
||||
input [3:0]S00_AXI_awcache;
|
||||
input [3:0]S00_AXI_awid;
|
||||
input [7:0]S00_AXI_awlen;
|
||||
input [0:0]S00_AXI_awlock;
|
||||
input [2:0]S00_AXI_awprot;
|
||||
input [3:0]S00_AXI_awqos;
|
||||
output S00_AXI_awready;
|
||||
input [2:0]S00_AXI_awsize;
|
||||
input S00_AXI_awvalid;
|
||||
output [3:0]S00_AXI_bid;
|
||||
input S00_AXI_bready;
|
||||
output [1:0]S00_AXI_bresp;
|
||||
output S00_AXI_bvalid;
|
||||
output [63:0]S00_AXI_rdata;
|
||||
output [3:0]S00_AXI_rid;
|
||||
output S00_AXI_rlast;
|
||||
input S00_AXI_rready;
|
||||
output [1:0]S00_AXI_rresp;
|
||||
output S00_AXI_rvalid;
|
||||
input [63:0]S00_AXI_wdata;
|
||||
input S00_AXI_wlast;
|
||||
output S00_AXI_wready;
|
||||
input [7:0]S00_AXI_wstrb;
|
||||
input S00_AXI_wvalid;
|
||||
input aclk;
|
||||
input aresetn;
|
||||
|
||||
wire [15:0]M00_AXI_araddr;
|
||||
wire [1:0]M00_AXI_arburst;
|
||||
wire [3:0]M00_AXI_arcache;
|
||||
wire [7:0]M00_AXI_arlen;
|
||||
wire [0:0]M00_AXI_arlock;
|
||||
wire [2:0]M00_AXI_arprot;
|
||||
wire [3:0]M00_AXI_arqos;
|
||||
wire M00_AXI_arready;
|
||||
wire [2:0]M00_AXI_arsize;
|
||||
wire M00_AXI_arvalid;
|
||||
wire [15:0]M00_AXI_awaddr;
|
||||
wire [1:0]M00_AXI_awburst;
|
||||
wire [3:0]M00_AXI_awcache;
|
||||
wire [7:0]M00_AXI_awlen;
|
||||
wire [0:0]M00_AXI_awlock;
|
||||
wire [2:0]M00_AXI_awprot;
|
||||
wire [3:0]M00_AXI_awqos;
|
||||
wire M00_AXI_awready;
|
||||
wire [2:0]M00_AXI_awsize;
|
||||
wire M00_AXI_awvalid;
|
||||
wire M00_AXI_bready;
|
||||
wire [1:0]M00_AXI_bresp;
|
||||
wire M00_AXI_bvalid;
|
||||
wire [31:0]M00_AXI_rdata;
|
||||
wire M00_AXI_rlast;
|
||||
wire M00_AXI_rready;
|
||||
wire [1:0]M00_AXI_rresp;
|
||||
wire M00_AXI_rvalid;
|
||||
wire [31:0]M00_AXI_wdata;
|
||||
wire M00_AXI_wlast;
|
||||
wire M00_AXI_wready;
|
||||
wire [3:0]M00_AXI_wstrb;
|
||||
wire M00_AXI_wvalid;
|
||||
wire [63:0]S00_AXI_araddr;
|
||||
wire [1:0]S00_AXI_arburst;
|
||||
wire [3:0]S00_AXI_arcache;
|
||||
wire [3:0]S00_AXI_arid;
|
||||
wire [7:0]S00_AXI_arlen;
|
||||
wire [0:0]S00_AXI_arlock;
|
||||
wire [2:0]S00_AXI_arprot;
|
||||
wire [3:0]S00_AXI_arqos;
|
||||
wire S00_AXI_arready;
|
||||
wire [2:0]S00_AXI_arsize;
|
||||
wire S00_AXI_arvalid;
|
||||
wire [63:0]S00_AXI_awaddr;
|
||||
wire [1:0]S00_AXI_awburst;
|
||||
wire [3:0]S00_AXI_awcache;
|
||||
wire [3:0]S00_AXI_awid;
|
||||
wire [7:0]S00_AXI_awlen;
|
||||
wire [0:0]S00_AXI_awlock;
|
||||
wire [2:0]S00_AXI_awprot;
|
||||
wire [3:0]S00_AXI_awqos;
|
||||
wire S00_AXI_awready;
|
||||
wire [2:0]S00_AXI_awsize;
|
||||
wire S00_AXI_awvalid;
|
||||
wire [3:0]S00_AXI_bid;
|
||||
wire S00_AXI_bready;
|
||||
wire [1:0]S00_AXI_bresp;
|
||||
wire S00_AXI_bvalid;
|
||||
wire [63:0]S00_AXI_rdata;
|
||||
wire [3:0]S00_AXI_rid;
|
||||
wire S00_AXI_rlast;
|
||||
wire S00_AXI_rready;
|
||||
wire [1:0]S00_AXI_rresp;
|
||||
wire S00_AXI_rvalid;
|
||||
wire [63:0]S00_AXI_wdata;
|
||||
wire S00_AXI_wlast;
|
||||
wire S00_AXI_wready;
|
||||
wire [7:0]S00_AXI_wstrb;
|
||||
wire S00_AXI_wvalid;
|
||||
wire aclk;
|
||||
wire aresetn;
|
||||
|
||||
bd_b43a bd_b43a_i
|
||||
(.M00_AXI_araddr(M00_AXI_araddr),
|
||||
.M00_AXI_arburst(M00_AXI_arburst),
|
||||
.M00_AXI_arcache(M00_AXI_arcache),
|
||||
.M00_AXI_arlen(M00_AXI_arlen),
|
||||
.M00_AXI_arlock(M00_AXI_arlock),
|
||||
.M00_AXI_arprot(M00_AXI_arprot),
|
||||
.M00_AXI_arqos(M00_AXI_arqos),
|
||||
.M00_AXI_arready(M00_AXI_arready),
|
||||
.M00_AXI_arsize(M00_AXI_arsize),
|
||||
.M00_AXI_arvalid(M00_AXI_arvalid),
|
||||
.M00_AXI_awaddr(M00_AXI_awaddr),
|
||||
.M00_AXI_awburst(M00_AXI_awburst),
|
||||
.M00_AXI_awcache(M00_AXI_awcache),
|
||||
.M00_AXI_awlen(M00_AXI_awlen),
|
||||
.M00_AXI_awlock(M00_AXI_awlock),
|
||||
.M00_AXI_awprot(M00_AXI_awprot),
|
||||
.M00_AXI_awqos(M00_AXI_awqos),
|
||||
.M00_AXI_awready(M00_AXI_awready),
|
||||
.M00_AXI_awsize(M00_AXI_awsize),
|
||||
.M00_AXI_awvalid(M00_AXI_awvalid),
|
||||
.M00_AXI_bready(M00_AXI_bready),
|
||||
.M00_AXI_bresp(M00_AXI_bresp),
|
||||
.M00_AXI_bvalid(M00_AXI_bvalid),
|
||||
.M00_AXI_rdata(M00_AXI_rdata),
|
||||
.M00_AXI_rlast(M00_AXI_rlast),
|
||||
.M00_AXI_rready(M00_AXI_rready),
|
||||
.M00_AXI_rresp(M00_AXI_rresp),
|
||||
.M00_AXI_rvalid(M00_AXI_rvalid),
|
||||
.M00_AXI_wdata(M00_AXI_wdata),
|
||||
.M00_AXI_wlast(M00_AXI_wlast),
|
||||
.M00_AXI_wready(M00_AXI_wready),
|
||||
.M00_AXI_wstrb(M00_AXI_wstrb),
|
||||
.M00_AXI_wvalid(M00_AXI_wvalid),
|
||||
.S00_AXI_araddr(S00_AXI_araddr),
|
||||
.S00_AXI_arburst(S00_AXI_arburst),
|
||||
.S00_AXI_arcache(S00_AXI_arcache),
|
||||
.S00_AXI_arid(S00_AXI_arid),
|
||||
.S00_AXI_arlen(S00_AXI_arlen),
|
||||
.S00_AXI_arlock(S00_AXI_arlock),
|
||||
.S00_AXI_arprot(S00_AXI_arprot),
|
||||
.S00_AXI_arqos(S00_AXI_arqos),
|
||||
.S00_AXI_arready(S00_AXI_arready),
|
||||
.S00_AXI_arsize(S00_AXI_arsize),
|
||||
.S00_AXI_arvalid(S00_AXI_arvalid),
|
||||
.S00_AXI_awaddr(S00_AXI_awaddr),
|
||||
.S00_AXI_awburst(S00_AXI_awburst),
|
||||
.S00_AXI_awcache(S00_AXI_awcache),
|
||||
.S00_AXI_awid(S00_AXI_awid),
|
||||
.S00_AXI_awlen(S00_AXI_awlen),
|
||||
.S00_AXI_awlock(S00_AXI_awlock),
|
||||
.S00_AXI_awprot(S00_AXI_awprot),
|
||||
.S00_AXI_awqos(S00_AXI_awqos),
|
||||
.S00_AXI_awready(S00_AXI_awready),
|
||||
.S00_AXI_awsize(S00_AXI_awsize),
|
||||
.S00_AXI_awvalid(S00_AXI_awvalid),
|
||||
.S00_AXI_bid(S00_AXI_bid),
|
||||
.S00_AXI_bready(S00_AXI_bready),
|
||||
.S00_AXI_bresp(S00_AXI_bresp),
|
||||
.S00_AXI_bvalid(S00_AXI_bvalid),
|
||||
.S00_AXI_rdata(S00_AXI_rdata),
|
||||
.S00_AXI_rid(S00_AXI_rid),
|
||||
.S00_AXI_rlast(S00_AXI_rlast),
|
||||
.S00_AXI_rready(S00_AXI_rready),
|
||||
.S00_AXI_rresp(S00_AXI_rresp),
|
||||
.S00_AXI_rvalid(S00_AXI_rvalid),
|
||||
.S00_AXI_wdata(S00_AXI_wdata),
|
||||
.S00_AXI_wlast(S00_AXI_wlast),
|
||||
.S00_AXI_wready(S00_AXI_wready),
|
||||
.S00_AXI_wstrb(S00_AXI_wstrb),
|
||||
.S00_AXI_wvalid(S00_AXI_wvalid),
|
||||
.aclk(aclk),
|
||||
.aresetn(aresetn));
|
||||
endmodule
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,55 @@
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|
||||
<spirit:displayName>Const Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CONST_WIDTH" spirit:order="3" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CONST_VAL</spirit:name>
|
||||
<spirit:displayName>Const Val</spirit:displayName>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CONST_VAL" spirit:order="4">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:displayName>Constant</xilinx:displayName>
|
||||
<xilinx:coreRevision>7</xilinx:coreRevision>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2022.1</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="ea82c910"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="905deaa3"/>
|
||||
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="0fa77f35"/>
|
||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="f74432fe"/>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
|
|
@ -0,0 +1,73 @@
|
|||
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:xlconstant:1.1
|
||||
// IP Revision: 1
|
||||
|
||||
#ifndef _bd_b43a_one_0_CPP_
|
||||
#define _bd_b43a_one_0_CPP_
|
||||
|
||||
#include "bd_b43a_one_0.h"
|
||||
|
||||
bd_b43a_one_0::bd_b43a_one_0 (sc_core::sc_module_name name) :sc_module(name), mod("mod"), dout("dout") {
|
||||
mod.dout(dout);
|
||||
}
|
||||
#ifdef MTI_SYSTEMC
|
||||
SC_MODULE_EXPORT(bd_b43a_one_0);
|
||||
#endif
|
||||
|
||||
#ifdef XM_SYSTEMC
|
||||
XMSC_MODULE_EXPORT(bd_b43a_one_0);
|
||||
#endif
|
||||
|
||||
#ifdef RIVIERA
|
||||
SC_MODULE_EXPORT(bd_b43a_one_0);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
|
@ -0,0 +1,65 @@
|
|||
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:xlconstant:1.1
|
||||
// IP Revision: 1
|
||||
|
||||
#ifndef _bd_b43a_one_0_H_
|
||||
#define _bd_b43a_one_0_H_
|
||||
|
||||
#include "xlconstant_v1_1_7.h"
|
||||
#include "systemc.h"
|
||||
class bd_b43a_one_0 : public sc_module {
|
||||
public:
|
||||
xlconstant_v1_1_7<1,1> mod;
|
||||
sc_out< sc_bv<1> > dout;
|
||||
bd_b43a_one_0 (sc_core::sc_module_name name);
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,68 @@
|
|||
// (c) Copyright 1995-2025 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:xlconstant:1.1
|
||||
// IP Revision: 7
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_b43a_one_0 (
|
||||
dout
|
||||
);
|
||||
|
||||
output wire [0 : 0] dout;
|
||||
|
||||
xlconstant_v1_1_7_xlconstant #(
|
||||
.CONST_WIDTH(1),
|
||||
.CONST_VAL(1'H1)
|
||||
) inst (
|
||||
.dout(dout)
|
||||
);
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,86 @@
|
|||
// (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
//------------------------------------------------------------------------------------
|
||||
// Filename: xl_Constant_stub.sv
|
||||
// Description: This HDL file is intended to be used with following simulators only:
|
||||
//
|
||||
// Vivado Simulator (XSim)
|
||||
// Cadence Xcelium Simulator
|
||||
// Aldec Riviera-PRO Simulator
|
||||
//
|
||||
//------------------------------------------------------------------------------------
|
||||
`ifdef XILINX_SIMULATOR
|
||||
`ifndef XILINX_SIMULATOR_BITASBOOL
|
||||
`define XILINX_SIMULATOR_BITASBOOL
|
||||
typedef bit bit_as_bool;
|
||||
`endif
|
||||
|
||||
(* SC_MODULE_EXPORT *)
|
||||
module bd_b43a_one_0 (
|
||||
output bit [0 : 0 ] dout
|
||||
);
|
||||
endmodule
|
||||
`endif
|
||||
|
||||
`ifdef XCELIUM
|
||||
(* XMSC_MODULE_EXPORT *)
|
||||
module bd_b43a_one_0 (dout)
|
||||
(* integer foreign = "SystemC";
|
||||
*);
|
||||
output wire [0 : 0 ] dout;
|
||||
endmodule
|
||||
`endif
|
||||
|
||||
`ifdef RIVIERA
|
||||
(* SC_MODULE_EXPORT *)
|
||||
module bd_b43a_one_0 (dout)
|
||||
output wire [0 : 0 ] dout;
|
||||
endmodule
|
||||
`endif
|
||||
|
||||
|
|
@ -0,0 +1,69 @@
|
|||
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:xlconstant:1.1
|
||||
// IP Revision: 1
|
||||
|
||||
#ifndef _xlconstant_v1_1_7_H_
|
||||
#define _xlconstant_v1_1_7_H_
|
||||
|
||||
#include "systemc.h"
|
||||
template<int CONST_WIDTH,int CONST_VAL>
|
||||
SC_MODULE(xlconstant_v1_1_7) {
|
||||
public:
|
||||
sc_out< sc_bv<CONST_WIDTH> > dout;
|
||||
void init() {
|
||||
dout.write(CONST_VAL);
|
||||
}
|
||||
SC_CTOR(xlconstant_v1_1_7) {
|
||||
SC_METHOD(init);
|
||||
}
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,69 @@
|
|||
// (c) Copyright 1995-2025 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:xlconstant:1.1
|
||||
// IP Revision: 7
|
||||
|
||||
(* X_CORE_INFO = "xlconstant_v1_1_7_xlconstant,Vivado 2022.1" *)
|
||||
(* CHECK_LICENSE_TYPE = "bd_b43a_one_0,xlconstant_v1_1_7_xlconstant,{}" *)
|
||||
(* CORE_GENERATION_INFO = "bd_b43a_one_0,xlconstant_v1_1_7_xlconstant,{x_ipProduct=Vivado 2022.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconstant,x_ipVersion=1.1,x_ipCoreRevision=7,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,CONST_WIDTH=1,CONST_VAL=0x1}" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_b43a_one_0 (
|
||||
dout
|
||||
);
|
||||
|
||||
output wire [0 : 0] dout;
|
||||
|
||||
xlconstant_v1_1_7_xlconstant #(
|
||||
.CONST_WIDTH(1),
|
||||
.CONST_VAL(1'H1)
|
||||
) inst (
|
||||
.dout(dout)
|
||||
);
|
||||
endmodule
|
||||
|
|
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7a100tl</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fgg484</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.PHASE" xilinx:valuePermission="bd"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_AUX_RESET_HIGH" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_AUX_RST_WIDTH" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_EXT_RESET_HIGH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
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"boundary": {
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"ports": {
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"aux_reset_in": [ { "direction": "in", "driver_value": "1" } ],
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"mb_debug_sys_rst": [ { "direction": "in", "driver_value": "0" } ],
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"dcm_locked": [ { "direction": "in", "driver_value": "0x1" } ],
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"mb_reset": [ { "direction": "out", "driver_value": "0x0" } ],
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"peripheral_aresetn": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "1" } ]
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},
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"interfaces": {
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"clock": {
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
},
|
||||
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|
||||
"RST": [ { "physical_name": "bus_struct_reset" } ]
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
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||||
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|
||||
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|
||||
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|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "interconnect_aresetn" } ]
|
||||
}
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"mode": "master",
|
||||
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|
||||
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|
||||
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|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"TYPE": [ { "value": "PERIPHERAL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "peripheral_aresetn" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}"/>
|
||||
</xilinx:boundaryDescriptionInfo>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
|
||||
# file: bd_b43a_psr_aclk_0.xdc
|
||||
# (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
set_false_path -to [get_pins -hier *cdc_to*/D]
|
||||
|
|
@ -0,0 +1,908 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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||||
<spirit:vendor>xilinx.com</spirit:vendor>
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<spirit:library>customized_ip</spirit:library>
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||||
<spirit:name>bd_b43a_psr_aclk_0</spirit:name>
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<spirit:version>1.0</spirit:version>
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<spirit:busInterfaces>
|
||||
<spirit:busInterface>
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<spirit:name>clock</spirit:name>
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<spirit:displayName>Clock</spirit:displayName>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
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<spirit:slave/>
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<spirit:portMaps>
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<spirit:portMap>
|
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<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>slowest_sync_clk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
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</spirit:portMaps>
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||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_RESET">mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
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||||
<spirit:displayName>Slowest Sync clock frequency</spirit:displayName>
|
||||
<spirit:description>Slowest Synchronous clock frequency</spirit:description>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLOCK.FREQ_HZ">125000000</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
|
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<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.FREQ_TOLERANCE_HZ">0</spirit:value>
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<spirit:vendorExtensions>
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<xilinx:parameterUsage>none</xilinx:parameterUsage>
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</spirit:vendorExtensions>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>PHASE</spirit:name>
|
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<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.PHASE">0.0</spirit:value>
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<spirit:vendorExtensions>
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<xilinx:parameterInfo>
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<xilinx:parameterUsage>none</xilinx:parameterUsage>
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</spirit:vendorExtensions>
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<spirit:parameter>
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<spirit:name>CLK_DOMAIN</spirit:name>
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<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.CLK_DOMAIN">top_xdma_0_0_axi_aclk</spirit:value>
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<spirit:vendorExtensions>
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</spirit:vendorExtensions>
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<spirit:parameter>
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<spirit:name>ASSOCIATED_BUSIF</spirit:name>
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<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_BUSIF"/>
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<spirit:vendorExtensions>
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<spirit:parameter>
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<spirit:name>ASSOCIATED_PORT</spirit:name>
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<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_PORT"/>
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<spirit:vendorExtensions>
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<spirit:name>INSERT_VIP</spirit:name>
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<spirit:name>ext_reset</spirit:name>
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<spirit:displayName>Ext_Reset</spirit:displayName>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
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<spirit:slave/>
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<spirit:portMaps>
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||||
<spirit:portMap>
|
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<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>ext_reset_in</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
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||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
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|
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<spirit:value spirit:id="BUSIFPARAM_VALUE.EXT_RESET.BOARD.ASSOCIATED_PARAM">RESET_BOARD_INTERFACE</spirit:value>
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<spirit:vendorExtensions>
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<spirit:name>POLARITY</spirit:name>
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<spirit:vendorExtensions>
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<xilinx:parameterInfo>
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<xilinx:parameterUsage>none</xilinx:parameterUsage>
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</xilinx:parameterInfo>
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</spirit:vendorExtensions>
|
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</spirit:parameter>
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||||
<spirit:parameter>
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<spirit:name>INSERT_VIP</spirit:name>
|
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<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.EXT_RESET.INSERT_VIP">0</spirit:value>
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<spirit:vendorExtensions>
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</spirit:vendorExtensions>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:busInterface>
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<spirit:busInterface>
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<spirit:name>aux_reset</spirit:name>
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<spirit:displayName>aux_reset</spirit:displayName>
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||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
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||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
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<spirit:slave/>
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<spirit:portMaps>
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||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
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||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>aux_reset_in</spirit:name>
|
||||
</spirit:physicalPort>
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||||
</spirit:portMap>
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||||
</spirit:portMaps>
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<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
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||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AUX_RESET.POLARITY">ACTIVE_LOW</spirit:value>
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<spirit:vendorExtensions>
|
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<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
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||||
</xilinx:parameterInfo>
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||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.AUX_RESET.INSERT_VIP">0</spirit:value>
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<spirit:vendorExtensions>
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||||
<xilinx:parameterInfo>
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||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
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||||
</xilinx:parameterInfo>
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||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
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||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>dbg_reset</spirit:name>
|
||||
<spirit:displayName>DBG_Reset</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
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||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>mb_debug_sys_rst</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.DBG_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.DBG_RESET.INSERT_VIP">0</spirit:value>
|
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<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
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||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>mb_rst</spirit:name>
|
||||
<spirit:displayName>MB_rst</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>mb_reset</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.MB_RST.POLARITY">ACTIVE_HIGH</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TYPE</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.MB_RST.TYPE">PROCESSOR</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.MB_RST.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>bus_struct_reset</spirit:name>
|
||||
<spirit:displayName>bus_struct_reset</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>bus_struct_reset</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.BUS_STRUCT_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TYPE</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.BUS_STRUCT_RESET.TYPE">INTERCONNECT</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.BUS_STRUCT_RESET.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>interconnect_low_rst</spirit:name>
|
||||
<spirit:displayName>interconnect_low_rst</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>interconnect_aresetn</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.INTERCONNECT_LOW_RST.POLARITY">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TYPE</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.INTERCONNECT_LOW_RST.TYPE">INTERCONNECT</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.INTERCONNECT_LOW_RST.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>peripheral_high_rst</spirit:name>
|
||||
<spirit:displayName>peripheral_high_rst</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>peripheral_reset</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.PERIPHERAL_HIGH_RST.POLARITY">ACTIVE_HIGH</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TYPE</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.PERIPHERAL_HIGH_RST.TYPE">PERIPHERAL</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.PERIPHERAL_HIGH_RST.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
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|
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||||
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|
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||||
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|
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|
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|
||||
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|
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|
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|
||||
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||||
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|
||||
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||||
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|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_PERP_ARESETN" spirit:minimum="1" spirit:maximum="31" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
</spirit:modelParameters>
|
||||
</spirit:model>
|
||||
<spirit:choices>
|
||||
<spirit:choice>
|
||||
<spirit:name>choice_list_ac75ef1e</spirit:name>
|
||||
<spirit:enumeration>Custom</spirit:enumeration>
|
||||
</spirit:choice>
|
||||
</spirit:choices>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsynthesis_xilinx_com_ip_lib_cdc_1_0__ref_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>../../../../../ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>lib_cdc_v1_0_2</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:subCoreRef>
|
||||
<xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="lib_cdc" xilinx:version="1.0" xilinx:isGenerated="true" xilinx:checksum="726cb4eb">
|
||||
<xilinx:mode xilinx:name="copy_mode"/>
|
||||
</xilinx:componentRef>
|
||||
</xilinx:subCoreRef>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsynthesis_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>../../../../../ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>proc_sys_reset_v5_0_13</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>bd_b43a_psr_aclk_0.xdc</spirit:name>
|
||||
<spirit:userFileType>xdc</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>synth/bd_b43a_psr_aclk_0.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlbehavioralsimulation_xilinx_com_ip_lib_cdc_1_0__ref_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>../../../../../ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
|
||||
<spirit:logicalName>lib_cdc_v1_0_2</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:subCoreRef>
|
||||
<xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="lib_cdc" xilinx:version="1.0" xilinx:isGenerated="true" xilinx:checksum="726cb4eb">
|
||||
<xilinx:mode xilinx:name="copy_mode"/>
|
||||
</xilinx:componentRef>
|
||||
</xilinx:subCoreRef>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlbehavioralsimulation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>../../../../../ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
|
||||
<spirit:logicalName>proc_sys_reset_v5_0_13</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>sim/bd_b43a_psr_aclk_0.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_implementation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>bd_b43a_psr_aclk_0_board.xdc</spirit:name>
|
||||
<spirit:userFileType>xdc</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_board</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>Processor Reset System</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_NUM_PERP_ARESETN</spirit:name>
|
||||
<spirit:displayName>No. of Peripheral Reset (Active Low)</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_PERP_ARESETN" spirit:order="1800" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_NUM_INTERCONNECT_ARESETN</spirit:name>
|
||||
<spirit:displayName>No. of Interconnect Reset (Active Low)</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_INTERCONNECT_ARESETN" spirit:order="1700" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_NUM_PERP_RST</spirit:name>
|
||||
<spirit:displayName>No. of Peripheral Reset (Active High)</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_PERP_RST" spirit:order="1600" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_NUM_BUS_RST</spirit:name>
|
||||
<spirit:displayName>No. of Bus Reset (Active High)</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_BUS_RST" spirit:order="1500" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_AUX_RESET_HIGH</spirit:name>
|
||||
<spirit:displayName>Aux Reset High</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_AUX_RESET_HIGH" spirit:order="1400" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_EXT_RESET_HIGH</spirit:name>
|
||||
<spirit:displayName>Ext Reset High</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_EXT_RESET_HIGH" spirit:order="1300" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_AUX_RST_WIDTH</spirit:name>
|
||||
<spirit:displayName>Aux Rst Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_AUX_RST_WIDTH" spirit:order="1200" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_EXT_RST_WIDTH</spirit:name>
|
||||
<spirit:displayName>Ext Rst Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_EXT_RST_WIDTH" spirit:order="1100" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">bd_b43a_psr_aclk_0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>USE_BOARD_FLOW</spirit:name>
|
||||
<spirit:displayName>Generate Board based IO Constraints</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_BOARD_FLOW" spirit:order="2">false</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>RESET_BOARD_INTERFACE</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RESET_BOARD_INTERFACE" spirit:choiceRef="choice_list_ac75ef1e" spirit:order="3">Custom</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:displayName>Processor System Reset</xilinx:displayName>
|
||||
<xilinx:coreRevision>13</xilinx:coreRevision>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AUX_RESET.POLARITY" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BUS_STRUCT_RESET.POLARITY" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BUS_STRUCT_RESET.TYPE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_PORT" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_RESET" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.DBG_RESET.POLARITY" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.EXT_RESET.BOARD.ASSOCIATED_PARAM" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.EXT_RESET.POLARITY" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.INTERCONNECT_LOW_RST.POLARITY" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.INTERCONNECT_LOW_RST.TYPE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.MB_RST.POLARITY" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.MB_RST.TYPE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.PERIPHERAL_HIGH_RST.POLARITY" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.PERIPHERAL_HIGH_RST.TYPE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.PERIPHERAL_LOW_RST.POLARITY" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.PERIPHERAL_LOW_RST.TYPE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_AUX_RESET_HIGH" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_AUX_RST_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_EXT_RESET_HIGH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2022.1</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="26169568"/>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="af82d8e6"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="f2ac9635"/>
|
||||
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="404de108"/>
|
||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="8319b917"/>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
#--------------------Physical Constraints-----------------
|
||||
|
||||
|
|
@ -0,0 +1,147 @@
|
|||
-- (c) Copyright 1995-2025 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
|
||||
-- IP Revision: 13
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY proc_sys_reset_v5_0_13;
|
||||
USE proc_sys_reset_v5_0_13.proc_sys_reset;
|
||||
|
||||
ENTITY bd_b43a_psr_aclk_0 IS
|
||||
PORT (
|
||||
slowest_sync_clk : IN STD_LOGIC;
|
||||
ext_reset_in : IN STD_LOGIC;
|
||||
aux_reset_in : IN STD_LOGIC;
|
||||
mb_debug_sys_rst : IN STD_LOGIC;
|
||||
dcm_locked : IN STD_LOGIC;
|
||||
mb_reset : OUT STD_LOGIC;
|
||||
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END bd_b43a_psr_aclk_0;
|
||||
|
||||
ARCHITECTURE bd_b43a_psr_aclk_0_arch OF bd_b43a_psr_aclk_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF bd_b43a_psr_aclk_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT proc_sys_reset IS
|
||||
GENERIC (
|
||||
C_FAMILY : STRING;
|
||||
C_EXT_RST_WIDTH : INTEGER;
|
||||
C_AUX_RST_WIDTH : INTEGER;
|
||||
C_EXT_RESET_HIGH : STD_LOGIC;
|
||||
C_AUX_RESET_HIGH : STD_LOGIC;
|
||||
C_NUM_BUS_RST : INTEGER;
|
||||
C_NUM_PERP_RST : INTEGER;
|
||||
C_NUM_INTERCONNECT_ARESETN : INTEGER;
|
||||
C_NUM_PERP_ARESETN : INTEGER
|
||||
);
|
||||
PORT (
|
||||
slowest_sync_clk : IN STD_LOGIC;
|
||||
ext_reset_in : IN STD_LOGIC;
|
||||
aux_reset_in : IN STD_LOGIC;
|
||||
mb_debug_sys_rst : IN STD_LOGIC;
|
||||
dcm_locked : IN STD_LOGIC;
|
||||
mb_reset : OUT STD_LOGIC;
|
||||
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT proc_sys_reset;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF aux_reset_in: SIGNAL IS "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF bus_struct_reset: SIGNAL IS "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF ext_reset_in: SIGNAL IS "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF interconnect_aresetn: SIGNAL IS "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF mb_debug_sys_rst: SIGNAL IS "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF mb_reset: SIGNAL IS "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_aresetn: SIGNAL IS "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_reset: SIGNAL IS "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF slowest_sync_clk: SIGNAL IS "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 125000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN top_xdma_0_0_axi_aclk, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
|
||||
BEGIN
|
||||
U0 : proc_sys_reset
|
||||
GENERIC MAP (
|
||||
C_FAMILY => "artix7",
|
||||
C_EXT_RST_WIDTH => 4,
|
||||
C_AUX_RST_WIDTH => 1,
|
||||
C_EXT_RESET_HIGH => '0',
|
||||
C_AUX_RESET_HIGH => '0',
|
||||
C_NUM_BUS_RST => 1,
|
||||
C_NUM_PERP_RST => 1,
|
||||
C_NUM_INTERCONNECT_ARESETN => 1,
|
||||
C_NUM_PERP_ARESETN => 1
|
||||
)
|
||||
PORT MAP (
|
||||
slowest_sync_clk => slowest_sync_clk,
|
||||
ext_reset_in => ext_reset_in,
|
||||
aux_reset_in => aux_reset_in,
|
||||
mb_debug_sys_rst => mb_debug_sys_rst,
|
||||
dcm_locked => dcm_locked,
|
||||
mb_reset => mb_reset,
|
||||
bus_struct_reset => bus_struct_reset,
|
||||
peripheral_reset => peripheral_reset,
|
||||
interconnect_aresetn => interconnect_aresetn,
|
||||
peripheral_aresetn => peripheral_aresetn
|
||||
);
|
||||
END bd_b43a_psr_aclk_0_arch;
|
||||
|
|
@ -0,0 +1,153 @@
|
|||
-- (c) Copyright 1995-2025 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
|
||||
-- IP Revision: 13
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY proc_sys_reset_v5_0_13;
|
||||
USE proc_sys_reset_v5_0_13.proc_sys_reset;
|
||||
|
||||
ENTITY bd_b43a_psr_aclk_0 IS
|
||||
PORT (
|
||||
slowest_sync_clk : IN STD_LOGIC;
|
||||
ext_reset_in : IN STD_LOGIC;
|
||||
aux_reset_in : IN STD_LOGIC;
|
||||
mb_debug_sys_rst : IN STD_LOGIC;
|
||||
dcm_locked : IN STD_LOGIC;
|
||||
mb_reset : OUT STD_LOGIC;
|
||||
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END bd_b43a_psr_aclk_0;
|
||||
|
||||
ARCHITECTURE bd_b43a_psr_aclk_0_arch OF bd_b43a_psr_aclk_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF bd_b43a_psr_aclk_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT proc_sys_reset IS
|
||||
GENERIC (
|
||||
C_FAMILY : STRING;
|
||||
C_EXT_RST_WIDTH : INTEGER;
|
||||
C_AUX_RST_WIDTH : INTEGER;
|
||||
C_EXT_RESET_HIGH : STD_LOGIC;
|
||||
C_AUX_RESET_HIGH : STD_LOGIC;
|
||||
C_NUM_BUS_RST : INTEGER;
|
||||
C_NUM_PERP_RST : INTEGER;
|
||||
C_NUM_INTERCONNECT_ARESETN : INTEGER;
|
||||
C_NUM_PERP_ARESETN : INTEGER
|
||||
);
|
||||
PORT (
|
||||
slowest_sync_clk : IN STD_LOGIC;
|
||||
ext_reset_in : IN STD_LOGIC;
|
||||
aux_reset_in : IN STD_LOGIC;
|
||||
mb_debug_sys_rst : IN STD_LOGIC;
|
||||
dcm_locked : IN STD_LOGIC;
|
||||
mb_reset : OUT STD_LOGIC;
|
||||
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT proc_sys_reset;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF bd_b43a_psr_aclk_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2022.1";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF bd_b43a_psr_aclk_0_arch : ARCHITECTURE IS "bd_b43a_psr_aclk_0,proc_sys_reset,{}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF bd_b43a_psr_aclk_0_arch: ARCHITECTURE IS "bd_b43a_psr_aclk_0,proc_sys_reset,{x_ipProduct=Vivado 2022.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=13,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=1,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF aux_reset_in: SIGNAL IS "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF bus_struct_reset: SIGNAL IS "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF ext_reset_in: SIGNAL IS "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF interconnect_aresetn: SIGNAL IS "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF mb_debug_sys_rst: SIGNAL IS "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF mb_reset: SIGNAL IS "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_aresetn: SIGNAL IS "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_reset: SIGNAL IS "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF slowest_sync_clk: SIGNAL IS "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 125000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN top_xdma_0_0_axi_aclk, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
|
||||
BEGIN
|
||||
U0 : proc_sys_reset
|
||||
GENERIC MAP (
|
||||
C_FAMILY => "artix7",
|
||||
C_EXT_RST_WIDTH => 4,
|
||||
C_AUX_RST_WIDTH => 1,
|
||||
C_EXT_RESET_HIGH => '0',
|
||||
C_AUX_RESET_HIGH => '0',
|
||||
C_NUM_BUS_RST => 1,
|
||||
C_NUM_PERP_RST => 1,
|
||||
C_NUM_INTERCONNECT_ARESETN => 1,
|
||||
C_NUM_PERP_ARESETN => 1
|
||||
)
|
||||
PORT MAP (
|
||||
slowest_sync_clk => slowest_sync_clk,
|
||||
ext_reset_in => ext_reset_in,
|
||||
aux_reset_in => aux_reset_in,
|
||||
mb_debug_sys_rst => mb_debug_sys_rst,
|
||||
dcm_locked => dcm_locked,
|
||||
mb_reset => mb_reset,
|
||||
bus_struct_reset => bus_struct_reset,
|
||||
peripheral_reset => peripheral_reset,
|
||||
interconnect_aresetn => interconnect_aresetn,
|
||||
peripheral_aresetn => peripheral_aresetn
|
||||
);
|
||||
END bd_b43a_psr_aclk_0_arch;
|
||||
|
|
@ -0,0 +1,353 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>xci</spirit:library>
|
||||
<spirit:name>unknown</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>bd_b43a_sbn_0</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="sc_node" spirit:version="1.0"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK.ASSOCIATED_PORT"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK.CLK_DOMAIN">top_xdma_0_0_axi_aclk</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK.FREQ_HZ">125000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ARESETN.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_ARB.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_ARB.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_ARB.HAS_TKEEP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_ARB.HAS_TLAST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_ARB.HAS_TREADY">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_ARB.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_ARB.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_ARB.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_ARB.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_ARB.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_ARB.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_ARB.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_ARB.TUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_SC_ACLK.ASSOCIATED_PORT"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_SC_ACLK.CLK_DOMAIN">top_xdma_0_0_axi_aclk</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_SC_ACLK.FREQ_HZ">125000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_SC_ACLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_SC_ACLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_SC_ACLK.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_SC_ACLKEN.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_SC_ARESETN.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_ARB.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_ARB.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_ARB.HAS_TKEEP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_ARB.HAS_TLAST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_ARB.HAS_TREADY">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_ARB.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_ARB.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_ARB.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_ARB.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_ARB.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_ARB.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_ARB.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_ARB.TUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_SC_ACLKEN.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ACLKEN_CONVERSION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ACLK_RELATIONSHIP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDR_WIDTH">64</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ARBITER_MODE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CHANNEL">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DISABLE_IP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_PIPELINING">0x01</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">artix7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FIFO_IP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FIFO_OUTPUT_REG">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FIFO_SIZE">5</spirit:configurableElementValue>
|
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|
||||
"port_maps": {
|
||||
"INFO": [ { "physical_name": "s_sc_info" } ],
|
||||
"PAYLD": [ { "physical_name": "s_sc_payld" } ],
|
||||
"RECV": [ { "physical_name": "s_sc_recv" } ],
|
||||
"REQ": [ { "physical_name": "s_sc_req" } ],
|
||||
"SEND": [ { "physical_name": "s_sc_send" } ]
|
||||
}
|
||||
},
|
||||
"M_SC": {
|
||||
"vlnv": "xilinx.com:interface:sc:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:sc_rtl:1.0",
|
||||
"mode": "master",
|
||||
"port_maps": {
|
||||
"INFO": [ { "physical_name": "m_sc_info" } ],
|
||||
"PAYLD": [ { "physical_name": "m_sc_payld" } ],
|
||||
"RECV": [ { "physical_name": "m_sc_recv" } ],
|
||||
"REQ": [ { "physical_name": "m_sc_req" } ],
|
||||
"SEND": [ { "physical_name": "m_sc_send" } ]
|
||||
}
|
||||
},
|
||||
"aclk": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXIS_ARB:M_AXIS_ARB:S_SC", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s_sc_aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_CLKEN": [ { "value": "s_sc_aclken", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "125000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "top_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_sc_aclk" } ]
|
||||
}
|
||||
},
|
||||
"aresetn": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s_sc_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"m_sc_aclk": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_SC", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "m_sc_aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_CLKEN": [ { "value": "m_sc_aclken", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "125000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "top_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "m_sc_aclk" } ]
|
||||
}
|
||||
},
|
||||
"m_sc_aresetn": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "m_sc_aresetn" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}"/>
|
||||
</xilinx:boundaryDescriptionInfo>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,52 @@
|
|||
################################################################################
|
||||
# (c) Copyright 2013 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
################################################################################
|
||||
|
||||
create_clock -period 100.0 -name s_sc_aclk [get_ports s_sc_aclk]
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,160 @@
|
|||
// (c) Copyright 1995-2025 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:sc_node:1.0
|
||||
// IP Revision: 14
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_b43a_sbn_0 (
|
||||
s_sc_aclk,
|
||||
s_sc_aresetn,
|
||||
s_sc_req,
|
||||
s_sc_info,
|
||||
s_sc_send,
|
||||
s_sc_recv,
|
||||
s_sc_payld,
|
||||
m_sc_aclk,
|
||||
m_sc_aresetn,
|
||||
m_sc_recv,
|
||||
m_sc_send,
|
||||
m_sc_req,
|
||||
m_sc_info,
|
||||
m_sc_payld
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXIS_ARB:M_AXIS_ARB:S_SC, ASSOCIATED_RESET s_sc_aresetn, ASSOCIATED_CLKEN s_sc_aclken, FREQ_HZ 125000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN top_xdma_0_0_axi_aclk, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire s_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn RST" *)
|
||||
input wire s_sc_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC REQ" *)
|
||||
input wire [0 : 0] s_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC INFO" *)
|
||||
input wire [0 : 0] s_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC SEND" *)
|
||||
input wire [0 : 0] s_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC RECV" *)
|
||||
output wire [0 : 0] s_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC PAYLD" *)
|
||||
input wire [4 : 0] s_sc_payld;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aclk, ASSOCIATED_BUSIF M_SC, ASSOCIATED_RESET m_sc_aresetn, ASSOCIATED_CLKEN m_sc_aclken, FREQ_HZ 125000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN top_xdma_0_0_axi_aclk, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 m_sc_aclk CLK" *)
|
||||
input wire m_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 m_sc_aresetn RST" *)
|
||||
input wire m_sc_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC RECV" *)
|
||||
input wire [0 : 0] m_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC SEND" *)
|
||||
output wire [0 : 0] m_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC REQ" *)
|
||||
output wire [0 : 0] m_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC INFO" *)
|
||||
output wire [0 : 0] m_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC PAYLD" *)
|
||||
output wire [4 : 0] m_sc_payld;
|
||||
|
||||
sc_node_v1_0_14_top #(
|
||||
.C_FAMILY("artix7"),
|
||||
.C_FIFO_IP(0),
|
||||
.C_DISABLE_IP(0),
|
||||
.C_FIFO_SIZE(5),
|
||||
.C_FIFO_TYPE(0),
|
||||
.C_FIFO_OUTPUT_REG(1),
|
||||
.C_ENABLE_PIPELINING(8'H01),
|
||||
.C_SYNCHRONIZATION_STAGES(3),
|
||||
.C_NUM_SI(1),
|
||||
.C_NUM_MI(1),
|
||||
.C_CHANNEL(4),
|
||||
.C_PAYLD_WIDTH(5),
|
||||
.C_S_NUM_BYTES_ARRAY(32'H00000004),
|
||||
.C_M_NUM_BYTES_ARRAY(32'H00000008),
|
||||
.C_PRIORITY_ARB_ARRAY(1'B0),
|
||||
.C_USER_BITS_PER_BYTE(0),
|
||||
.C_ARBITER_MODE(1),
|
||||
.C_SC_ROUTE_WIDTH(1),
|
||||
.C_ID_WIDTH(1),
|
||||
.C_ADDR_WIDTH(64),
|
||||
.C_USER_WIDTH(0),
|
||||
.C_MAX_PAYLD_BYTES(8),
|
||||
.C_S_PIPELINE(0),
|
||||
.C_M_PIPELINE(0),
|
||||
.C_M_SEND_PIPELINE(0),
|
||||
.C_S_LATENCY(0),
|
||||
.C_NUM_OUTSTANDING(16),
|
||||
.C_ACLK_RELATIONSHIP(1),
|
||||
.C_ACLKEN_CONVERSION(0)
|
||||
) inst (
|
||||
.s_sc_aclk(s_sc_aclk),
|
||||
.s_sc_aclken(1'H1),
|
||||
.s_sc_aresetn(s_sc_aresetn),
|
||||
.s_sc_req(s_sc_req),
|
||||
.s_sc_info(s_sc_info),
|
||||
.s_sc_send(s_sc_send),
|
||||
.s_sc_recv(s_sc_recv),
|
||||
.s_sc_payld(s_sc_payld),
|
||||
.m_sc_aclk(m_sc_aclk),
|
||||
.m_sc_aclken(1'H1),
|
||||
.m_sc_aresetn(m_sc_aresetn),
|
||||
.m_sc_recv(m_sc_recv),
|
||||
.m_sc_send(m_sc_send),
|
||||
.m_sc_req(m_sc_req),
|
||||
.m_sc_info(m_sc_info),
|
||||
.m_sc_payld(m_sc_payld),
|
||||
.m_axis_arb_tvalid(),
|
||||
.m_axis_arb_tready(1'H1),
|
||||
.m_axis_arb_tdata(),
|
||||
.s_axis_arb_tvalid(1'H0),
|
||||
.s_axis_arb_tready(),
|
||||
.s_axis_arb_tdata(16'B0)
|
||||
);
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,162 @@
|
|||
// (c) Copyright 1995-2025 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:sc_node:1.0
|
||||
// IP Revision: 14
|
||||
|
||||
(* X_CORE_INFO = "sc_node_v1_0_14_top,Vivado 2022.1" *)
|
||||
(* CHECK_LICENSE_TYPE = "bd_b43a_sbn_0,sc_node_v1_0_14_top,{}" *)
|
||||
(* CORE_GENERATION_INFO = "bd_b43a_sbn_0,sc_node_v1_0_14_top,{x_ipProduct=Vivado 2022.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=sc_node,x_ipVersion=1.0,x_ipCoreRevision=14,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_FIFO_IP=0,C_DISABLE_IP=0,C_FIFO_SIZE=5,C_FIFO_TYPE=0,C_FIFO_OUTPUT_REG=1,C_ENABLE_PIPELINING=0x01,C_SYNCHRONIZATION_STAGES=3,C_NUM_SI=1,C_NUM_MI=1,C_CHANNEL=4,C_PAYLD_WIDTH=5,C_S_NUM_BYTES_ARRAY=0x00000004,C_M_NUM_BYTES_ARRAY=0x00000008,C_PRIORITY_ARB_ARRAY=0b0,C_USER_BITS_PER_BYTE=0,C_A\
|
||||
RBITER_MODE=1,C_SC_ROUTE_WIDTH=1,C_ID_WIDTH=1,C_ADDR_WIDTH=64,C_USER_WIDTH=0,C_MAX_PAYLD_BYTES=8,C_S_PIPELINE=0,C_M_PIPELINE=0,C_M_SEND_PIPELINE=0,C_S_LATENCY=0,C_NUM_OUTSTANDING=16,C_ACLK_RELATIONSHIP=1,C_ACLKEN_CONVERSION=0}" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_b43a_sbn_0 (
|
||||
s_sc_aclk,
|
||||
s_sc_aresetn,
|
||||
s_sc_req,
|
||||
s_sc_info,
|
||||
s_sc_send,
|
||||
s_sc_recv,
|
||||
s_sc_payld,
|
||||
m_sc_aclk,
|
||||
m_sc_aresetn,
|
||||
m_sc_recv,
|
||||
m_sc_send,
|
||||
m_sc_req,
|
||||
m_sc_info,
|
||||
m_sc_payld
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF S_AXIS_ARB:M_AXIS_ARB:S_SC, ASSOCIATED_RESET s_sc_aresetn, ASSOCIATED_CLKEN s_sc_aclken, FREQ_HZ 125000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN top_xdma_0_0_axi_aclk, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire s_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn RST" *)
|
||||
input wire s_sc_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC REQ" *)
|
||||
input wire [0 : 0] s_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC INFO" *)
|
||||
input wire [0 : 0] s_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC SEND" *)
|
||||
input wire [0 : 0] s_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC RECV" *)
|
||||
output wire [0 : 0] s_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC PAYLD" *)
|
||||
input wire [4 : 0] s_sc_payld;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aclk, ASSOCIATED_BUSIF M_SC, ASSOCIATED_RESET m_sc_aresetn, ASSOCIATED_CLKEN m_sc_aclken, FREQ_HZ 125000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN top_xdma_0_0_axi_aclk, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 m_sc_aclk CLK" *)
|
||||
input wire m_sc_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_sc_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 m_sc_aresetn RST" *)
|
||||
input wire m_sc_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC RECV" *)
|
||||
input wire [0 : 0] m_sc_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC SEND" *)
|
||||
output wire [0 : 0] m_sc_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC REQ" *)
|
||||
output wire [0 : 0] m_sc_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC INFO" *)
|
||||
output wire [0 : 0] m_sc_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC PAYLD" *)
|
||||
output wire [4 : 0] m_sc_payld;
|
||||
|
||||
sc_node_v1_0_14_top #(
|
||||
.C_FAMILY("artix7"),
|
||||
.C_FIFO_IP(0),
|
||||
.C_DISABLE_IP(0),
|
||||
.C_FIFO_SIZE(5),
|
||||
.C_FIFO_TYPE(0),
|
||||
.C_FIFO_OUTPUT_REG(1),
|
||||
.C_ENABLE_PIPELINING(8'H01),
|
||||
.C_SYNCHRONIZATION_STAGES(3),
|
||||
.C_NUM_SI(1),
|
||||
.C_NUM_MI(1),
|
||||
.C_CHANNEL(4),
|
||||
.C_PAYLD_WIDTH(5),
|
||||
.C_S_NUM_BYTES_ARRAY(32'H00000004),
|
||||
.C_M_NUM_BYTES_ARRAY(32'H00000008),
|
||||
.C_PRIORITY_ARB_ARRAY(1'B0),
|
||||
.C_USER_BITS_PER_BYTE(0),
|
||||
.C_ARBITER_MODE(1),
|
||||
.C_SC_ROUTE_WIDTH(1),
|
||||
.C_ID_WIDTH(1),
|
||||
.C_ADDR_WIDTH(64),
|
||||
.C_USER_WIDTH(0),
|
||||
.C_MAX_PAYLD_BYTES(8),
|
||||
.C_S_PIPELINE(0),
|
||||
.C_M_PIPELINE(0),
|
||||
.C_M_SEND_PIPELINE(0),
|
||||
.C_S_LATENCY(0),
|
||||
.C_NUM_OUTSTANDING(16),
|
||||
.C_ACLK_RELATIONSHIP(1),
|
||||
.C_ACLKEN_CONVERSION(0)
|
||||
) inst (
|
||||
.s_sc_aclk(s_sc_aclk),
|
||||
.s_sc_aclken(1'H1),
|
||||
.s_sc_aresetn(s_sc_aresetn),
|
||||
.s_sc_req(s_sc_req),
|
||||
.s_sc_info(s_sc_info),
|
||||
.s_sc_send(s_sc_send),
|
||||
.s_sc_recv(s_sc_recv),
|
||||
.s_sc_payld(s_sc_payld),
|
||||
.m_sc_aclk(m_sc_aclk),
|
||||
.m_sc_aclken(1'H1),
|
||||
.m_sc_aresetn(m_sc_aresetn),
|
||||
.m_sc_recv(m_sc_recv),
|
||||
.m_sc_send(m_sc_send),
|
||||
.m_sc_req(m_sc_req),
|
||||
.m_sc_info(m_sc_info),
|
||||
.m_sc_payld(m_sc_payld),
|
||||
.m_axis_arb_tvalid(),
|
||||
.m_axis_arb_tready(1'H1),
|
||||
.m_axis_arb_tdata(),
|
||||
.s_axis_arb_tvalid(1'H0),
|
||||
.s_axis_arb_tready(),
|
||||
.s_axis_arb_tdata(16'B0)
|
||||
);
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,395 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>xci</spirit:library>
|
||||
<spirit:name>unknown</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>bd_b43a_m00s2a_0</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="sc_sc2axi" spirit:version="1.0"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK.ASSOCIATED_PORT"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK.CLK_DOMAIN">top_xdma_0_0_axi_aclk</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK.FREQ_HZ">125000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH">1024</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH">1024</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH">1024</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN">top_xdma_0_0_axi_aclk</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ">125000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH">256</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL">AXI4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH">1024</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH">1024</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_RDATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WDATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MSC_ROUTE_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SC_ADDR_WIDTH">64</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SC_ARUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SC_AWUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SC_BUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SC_ID_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SC_RDATA_WIDTH">64</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SC_RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SC_WDATA_WIDTH">64</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SC_WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SSC_ROUTE_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_ADDR_WIDTH">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_ID_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_RDATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_WDATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">bd_b43a_m00s2a_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MSC_ROUTE_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SC_ADDR_WIDTH">64</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SC_ARUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SC_AWUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SC_BUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SC_ID_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SC_RDATA_WIDTH">64</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SC_RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SC_WDATA_WIDTH">64</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SC_WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SSC_ROUTE_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">artix7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7a100tl</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fgg484</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2L</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">E</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../../../../ipshared</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2022.1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:componentInstanceExtensions>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ACLK.ASSOCIATED_PORT" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ACLK.ASSOCIATED_RESET" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ACLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ACLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ACLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.ACLK.PHASE" xilinx:valuePermission="bd"/>
|
||||
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|
||||
"MAX_BURST_LENGTH": [ { "value": "256", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "top_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ARADDR": [ { "physical_name": "m_axi_araddr" } ],
|
||||
"ARCACHE": [ { "physical_name": "m_axi_arcache" } ],
|
||||
"ARID": [ { "physical_name": "m_axi_arid" } ],
|
||||
"ARLEN": [ { "physical_name": "m_axi_arlen" } ],
|
||||
"ARLOCK": [ { "physical_name": "m_axi_arlock" } ],
|
||||
"ARPROT": [ { "physical_name": "m_axi_arprot" } ],
|
||||
"ARQOS": [ { "physical_name": "m_axi_arqos" } ],
|
||||
"ARREADY": [ { "physical_name": "m_axi_arready" } ],
|
||||
"ARUSER": [ { "physical_name": "m_axi_aruser" } ],
|
||||
"ARVALID": [ { "physical_name": "m_axi_arvalid" } ],
|
||||
"AWADDR": [ { "physical_name": "m_axi_awaddr" } ],
|
||||
"AWCACHE": [ { "physical_name": "m_axi_awcache" } ],
|
||||
"AWID": [ { "physical_name": "m_axi_awid" } ],
|
||||
"AWLEN": [ { "physical_name": "m_axi_awlen" } ],
|
||||
"AWLOCK": [ { "physical_name": "m_axi_awlock" } ],
|
||||
"AWPROT": [ { "physical_name": "m_axi_awprot" } ],
|
||||
"AWQOS": [ { "physical_name": "m_axi_awqos" } ],
|
||||
"AWREADY": [ { "physical_name": "m_axi_awready" } ],
|
||||
"AWUSER": [ { "physical_name": "m_axi_awuser" } ],
|
||||
"AWVALID": [ { "physical_name": "m_axi_awvalid" } ],
|
||||
"BID": [ { "physical_name": "m_axi_bid" } ],
|
||||
"BREADY": [ { "physical_name": "m_axi_bready" } ],
|
||||
"BRESP": [ { "physical_name": "m_axi_bresp" } ],
|
||||
"BUSER": [ { "physical_name": "m_axi_buser" } ],
|
||||
"BVALID": [ { "physical_name": "m_axi_bvalid" } ],
|
||||
"RDATA": [ { "physical_name": "m_axi_rdata" } ],
|
||||
"RID": [ { "physical_name": "m_axi_rid" } ],
|
||||
"RLAST": [ { "physical_name": "m_axi_rlast" } ],
|
||||
"RREADY": [ { "physical_name": "m_axi_rready" } ],
|
||||
"RRESP": [ { "physical_name": "m_axi_rresp" } ],
|
||||
"RUSER": [ { "physical_name": "m_axi_ruser" } ],
|
||||
"RVALID": [ { "physical_name": "m_axi_rvalid" } ],
|
||||
"WDATA": [ { "physical_name": "m_axi_wdata" } ],
|
||||
"WLAST": [ { "physical_name": "m_axi_wlast" } ],
|
||||
"WREADY": [ { "physical_name": "m_axi_wready" } ],
|
||||
"WSTRB": [ { "physical_name": "m_axi_wstrb" } ],
|
||||
"WUSER": [ { "physical_name": "m_axi_wuser" } ],
|
||||
"WVALID": [ { "physical_name": "m_axi_wvalid" } ]
|
||||
}
|
||||
},
|
||||
"aclk": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXI:S_AW_SC:S_AR_SC:S_W_SC:M_R_SC:M_W_SC", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "125000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "top_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}"/>
|
||||
</xilinx:boundaryDescriptionInfo>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,51 @@
|
|||
################################################################################
|
||||
# (c) Copyright 2015 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
################################################################################
|
||||
#
|
||||
# Port aclk is never used.
|
||||
#
|
||||
|
|
@ -0,0 +1,342 @@
|
|||
// (c) Copyright 1995-2025 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:sc_sc2axi:1.0
|
||||
// IP Revision: 8
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module bd_b43a_m00s2a_0 (
|
||||
aclk,
|
||||
m_sc_r_req,
|
||||
m_sc_r_info,
|
||||
m_sc_r_send,
|
||||
m_sc_r_recv,
|
||||
m_sc_r_payld,
|
||||
m_sc_b_req,
|
||||
m_sc_b_info,
|
||||
m_sc_b_send,
|
||||
m_sc_b_recv,
|
||||
m_sc_b_payld,
|
||||
s_sc_ar_req,
|
||||
s_sc_ar_info,
|
||||
s_sc_ar_send,
|
||||
s_sc_ar_recv,
|
||||
s_sc_ar_payld,
|
||||
s_sc_aw_req,
|
||||
s_sc_aw_info,
|
||||
s_sc_aw_send,
|
||||
s_sc_aw_recv,
|
||||
s_sc_aw_payld,
|
||||
s_sc_w_req,
|
||||
s_sc_w_info,
|
||||
s_sc_w_send,
|
||||
s_sc_w_recv,
|
||||
s_sc_w_payld,
|
||||
m_axi_awid,
|
||||
m_axi_awaddr,
|
||||
m_axi_awlen,
|
||||
m_axi_awlock,
|
||||
m_axi_awcache,
|
||||
m_axi_awprot,
|
||||
m_axi_awqos,
|
||||
m_axi_awuser,
|
||||
m_axi_awvalid,
|
||||
m_axi_awready,
|
||||
m_axi_wdata,
|
||||
m_axi_wstrb,
|
||||
m_axi_wlast,
|
||||
m_axi_wuser,
|
||||
m_axi_wvalid,
|
||||
m_axi_wready,
|
||||
m_axi_bid,
|
||||
m_axi_bresp,
|
||||
m_axi_buser,
|
||||
m_axi_bvalid,
|
||||
m_axi_bready,
|
||||
m_axi_arid,
|
||||
m_axi_araddr,
|
||||
m_axi_arlen,
|
||||
m_axi_arlock,
|
||||
m_axi_arcache,
|
||||
m_axi_arprot,
|
||||
m_axi_arqos,
|
||||
m_axi_aruser,
|
||||
m_axi_arvalid,
|
||||
m_axi_arready,
|
||||
m_axi_rid,
|
||||
m_axi_rdata,
|
||||
m_axi_rresp,
|
||||
m_axi_rlast,
|
||||
m_axi_ruser,
|
||||
m_axi_rvalid,
|
||||
m_axi_rready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF M_AXI:S_AW_SC:S_AR_SC:S_W_SC:M_R_SC:M_W_SC, FREQ_HZ 125000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN top_xdma_0_0_axi_aclk, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_R REQ" *)
|
||||
output wire m_sc_r_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_R INFO" *)
|
||||
output wire [0 : 0] m_sc_r_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_R SEND" *)
|
||||
output wire m_sc_r_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_R RECV" *)
|
||||
input wire m_sc_r_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_R PAYLD" *)
|
||||
output wire [82 : 0] m_sc_r_payld;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_B REQ" *)
|
||||
output wire m_sc_b_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_B INFO" *)
|
||||
output wire [0 : 0] m_sc_b_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_B SEND" *)
|
||||
output wire m_sc_b_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_B RECV" *)
|
||||
input wire m_sc_b_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 M_SC_B PAYLD" *)
|
||||
output wire [4 : 0] m_sc_b_payld;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_AR REQ" *)
|
||||
input wire s_sc_ar_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_AR INFO" *)
|
||||
input wire [0 : 0] s_sc_ar_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_AR SEND" *)
|
||||
input wire s_sc_ar_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_AR RECV" *)
|
||||
output wire s_sc_ar_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_AR PAYLD" *)
|
||||
input wire [169 : 0] s_sc_ar_payld;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_AW REQ" *)
|
||||
input wire s_sc_aw_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_AW INFO" *)
|
||||
input wire [0 : 0] s_sc_aw_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_AW SEND" *)
|
||||
input wire s_sc_aw_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_AW RECV" *)
|
||||
output wire s_sc_aw_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_AW PAYLD" *)
|
||||
input wire [169 : 0] s_sc_aw_payld;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_W REQ" *)
|
||||
input wire s_sc_w_req;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_W INFO" *)
|
||||
input wire [0 : 0] s_sc_w_info;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_W SEND" *)
|
||||
input wire s_sc_w_send;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_W RECV" *)
|
||||
output wire s_sc_w_recv;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:sc:1.0 S_SC_W PAYLD" *)
|
||||
input wire [87 : 0] s_sc_w_payld;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *)
|
||||
output wire [0 : 0] m_axi_awid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
|
||||
output wire [15 : 0] m_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
|
||||
output wire [7 : 0] m_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
|
||||
output wire [0 : 0] m_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
|
||||
output wire [3 : 0] m_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
|
||||
output wire [2 : 0] m_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
|
||||
output wire [3 : 0] m_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWUSER" *)
|
||||
output wire [1023 : 0] m_axi_awuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
|
||||
output wire m_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
|
||||
input wire m_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
|
||||
output wire [31 : 0] m_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
|
||||
output wire [3 : 0] m_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
|
||||
output wire m_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WUSER" *)
|
||||
output wire [1023 : 0] m_axi_wuser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
|
||||
output wire m_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
|
||||
input wire m_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BID" *)
|
||||
input wire [0 : 0] m_axi_bid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
|
||||
input wire [1 : 0] m_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BUSER" *)
|
||||
input wire [1023 : 0] m_axi_buser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
|
||||
input wire m_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
|
||||
output wire m_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARID" *)
|
||||
output wire [0 : 0] m_axi_arid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
|
||||
output wire [15 : 0] m_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
|
||||
output wire [7 : 0] m_axi_arlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
|
||||
output wire [0 : 0] m_axi_arlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
|
||||
output wire [3 : 0] m_axi_arcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
|
||||
output wire [2 : 0] m_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
|
||||
output wire [3 : 0] m_axi_arqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARUSER" *)
|
||||
output wire [1023 : 0] m_axi_aruser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
|
||||
output wire m_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
|
||||
input wire m_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RID" *)
|
||||
input wire [0 : 0] m_axi_rid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
|
||||
input wire [31 : 0] m_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
|
||||
input wire [1 : 0] m_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
|
||||
input wire m_axi_rlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RUSER" *)
|
||||
input wire [1023 : 0] m_axi_ruser;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
|
||||
input wire m_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 125000000, ID_WIDTH 1, ADDR_WIDTH 16, AWUSER_WIDTH 1024, ARUSER_WIDTH 1024, WUSER_WIDTH 1024, RUSER_WIDTH 1024, BUSER_WIDTH 1024, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.0, CLK_DOMAIN top_xdma_0_0_axi_aclk, NUM_READ_THREADS 1, NUM_\
|
||||
WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
|
||||
output wire m_axi_rready;
|
||||
|
||||
sc_sc2axi_v1_0_8_top #(
|
||||
.C_AXI_ADDR_WIDTH(16),
|
||||
.C_AXI_ID_WIDTH(1),
|
||||
.C_AXI_RDATA_WIDTH(32),
|
||||
.C_AXI_WDATA_WIDTH(32),
|
||||
.C_SC_ADDR_WIDTH(64),
|
||||
.C_SC_ID_WIDTH(1),
|
||||
.C_SC_RDATA_WIDTH(64),
|
||||
.C_SC_WDATA_WIDTH(64),
|
||||
.C_SC_RUSER_BITS_PER_BYTE(0),
|
||||
.C_SC_WUSER_BITS_PER_BYTE(0),
|
||||
.C_SC_ARUSER_WIDTH(0),
|
||||
.C_SC_AWUSER_WIDTH(0),
|
||||
.C_SC_BUSER_WIDTH(0),
|
||||
.C_MSC_ROUTE_WIDTH(1),
|
||||
.C_SSC_ROUTE_WIDTH(1),
|
||||
.C_AWPAYLD_WIDTH(170),
|
||||
.C_ARPAYLD_WIDTH(170),
|
||||
.C_WPAYLD_WIDTH(88),
|
||||
.C_RPAYLD_WIDTH(83),
|
||||
.C_BPAYLD_WIDTH(5)
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.m_sc_r_req(m_sc_r_req),
|
||||
.m_sc_r_info(m_sc_r_info),
|
||||
.m_sc_r_send(m_sc_r_send),
|
||||
.m_sc_r_recv(m_sc_r_recv),
|
||||
.m_sc_r_payld(m_sc_r_payld),
|
||||
.m_sc_b_req(m_sc_b_req),
|
||||
.m_sc_b_info(m_sc_b_info),
|
||||
.m_sc_b_send(m_sc_b_send),
|
||||
.m_sc_b_recv(m_sc_b_recv),
|
||||
.m_sc_b_payld(m_sc_b_payld),
|
||||
.s_sc_ar_req(s_sc_ar_req),
|
||||
.s_sc_ar_info(s_sc_ar_info),
|
||||
.s_sc_ar_send(s_sc_ar_send),
|
||||
.s_sc_ar_recv(s_sc_ar_recv),
|
||||
.s_sc_ar_payld(s_sc_ar_payld),
|
||||
.s_sc_aw_req(s_sc_aw_req),
|
||||
.s_sc_aw_info(s_sc_aw_info),
|
||||
.s_sc_aw_send(s_sc_aw_send),
|
||||
.s_sc_aw_recv(s_sc_aw_recv),
|
||||
.s_sc_aw_payld(s_sc_aw_payld),
|
||||
.s_sc_w_req(s_sc_w_req),
|
||||
.s_sc_w_info(s_sc_w_info),
|
||||
.s_sc_w_send(s_sc_w_send),
|
||||
.s_sc_w_recv(s_sc_w_recv),
|
||||
.s_sc_w_payld(s_sc_w_payld),
|
||||
.m_axi_awid(m_axi_awid),
|
||||
.m_axi_awaddr(m_axi_awaddr),
|
||||
.m_axi_awlen(m_axi_awlen),
|
||||
.m_axi_awlock(m_axi_awlock),
|
||||
.m_axi_awcache(m_axi_awcache),
|
||||
.m_axi_awprot(m_axi_awprot),
|
||||
.m_axi_awqos(m_axi_awqos),
|
||||
.m_axi_awuser(m_axi_awuser),
|
||||
.m_axi_awvalid(m_axi_awvalid),
|
||||
.m_axi_awready(m_axi_awready),
|
||||
.m_axi_wdata(m_axi_wdata),
|
||||
.m_axi_wstrb(m_axi_wstrb),
|
||||
.m_axi_wlast(m_axi_wlast),
|
||||
.m_axi_wuser(m_axi_wuser),
|
||||
.m_axi_wvalid(m_axi_wvalid),
|
||||
.m_axi_wready(m_axi_wready),
|
||||
.m_axi_bid(m_axi_bid),
|
||||
.m_axi_bresp(m_axi_bresp),
|
||||
.m_axi_buser(m_axi_buser),
|
||||
.m_axi_bvalid(m_axi_bvalid),
|
||||
.m_axi_bready(m_axi_bready),
|
||||
.m_axi_arid(m_axi_arid),
|
||||
.m_axi_araddr(m_axi_araddr),
|
||||
.m_axi_arlen(m_axi_arlen),
|
||||
.m_axi_arlock(m_axi_arlock),
|
||||
.m_axi_arcache(m_axi_arcache),
|
||||
.m_axi_arprot(m_axi_arprot),
|
||||
.m_axi_arqos(m_axi_arqos),
|
||||
.m_axi_aruser(m_axi_aruser),
|
||||
.m_axi_arvalid(m_axi_arvalid),
|
||||
.m_axi_arready(m_axi_arready),
|
||||
.m_axi_rid(m_axi_rid),
|
||||
.m_axi_rdata(m_axi_rdata),
|
||||
.m_axi_rresp(m_axi_rresp),
|
||||
.m_axi_rlast(m_axi_rlast),
|
||||
.m_axi_ruser(m_axi_ruser),
|
||||
.m_axi_rvalid(m_axi_rvalid),
|
||||
.m_axi_rready(m_axi_rready)
|
||||
);
|
||||
endmodule
|
||||
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Add a link
Reference in a new issue