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Nicholas Orlowsky 2025-06-24 15:24:21 -04:00
commit ba46ab8dc4
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0
hello_world_dma.runs/synth_1/.Vivado_Synthesis.queue.rst Normal file
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58
hello_world_dma.runs/synth_1/.Xil/top_wrapper_propImpl.xdc Normal file
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set_property SRC_FILE_INFO {cfile:/home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/constrs_1/new/early.xdc rfile:../../../hello_world_dma.srcs/constrs_1/new/early.xdc id:1 order:EARLY} [current_design]
set_property SRC_FILE_INFO {cfile:/home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/constrs_1/new/normal.xdc rfile:../../../hello_world_dma.srcs/constrs_1/new/normal.xdc id:2} [current_design]
set_property src_info {type:XDC file:1 line:4 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC GTPE2_CHANNEL_X0Y7 [get_cells {top_i/xdma_0/inst/top_xdma_0_0_pcie2_to_pcie3_wrapper_i/pcie2_ip_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/gtp_channel.gtpe2_channel_i}]
set_property src_info {type:XDC file:1 line:5 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN A10 [get_ports {pcie_mgt_rxn[0]}]
set_property src_info {type:XDC file:1 line:6 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN B10 [get_ports {pcie_mgt_rxp[0]}]
set_property src_info {type:XDC file:1 line:7 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN A6 [get_ports {pcie_mgt_txn[0]}]
set_property src_info {type:XDC file:1 line:8 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN B6 [get_ports {pcie_mgt_txp[0]}]
set_property src_info {type:XDC file:1 line:11 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC GTPE2_CHANNEL_X0Y6 [get_cells {top_i/xdma_0/inst/top_xdma_0_0_pcie2_to_pcie3_wrapper_i/pcie2_ip_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtp_channel.gtpe2_channel_i}]
set_property src_info {type:XDC file:1 line:12 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN A8 [get_ports {pcie_mgt_rxn[1]}]
set_property src_info {type:XDC file:1 line:13 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN B8 [get_ports {pcie_mgt_rxp[1]}]
set_property src_info {type:XDC file:1 line:14 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN A4 [get_ports {pcie_mgt_txn[1]}]
set_property src_info {type:XDC file:1 line:15 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN B4 [get_ports {pcie_mgt_txp[1]}]
set_property src_info {type:XDC file:1 line:18 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC GTPE2_CHANNEL_X0Y5 [get_cells {top_i/xdma_0/inst/top_xdma_0_0_pcie2_to_pcie3_wrapper_i/pcie2_ip_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/gtp_channel.gtpe2_channel_i}]
set_property src_info {type:XDC file:1 line:19 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN C11 [get_ports {pcie_mgt_rxn[2]}]
set_property src_info {type:XDC file:1 line:20 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN D11 [get_ports {pcie_mgt_rxp[2]}]
set_property src_info {type:XDC file:1 line:21 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN C5 [get_ports {pcie_mgt_txn[2]}]
set_property src_info {type:XDC file:1 line:22 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN D5 [get_ports {pcie_mgt_txp[2]}]
set_property src_info {type:XDC file:1 line:25 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC GTPE2_CHANNEL_X0Y4 [get_cells {top_i/xdma_0/inst/top_xdma_0_0_pcie2_to_pcie3_wrapper_i/pcie2_ip_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/gtp_channel.gtpe2_channel_i}]
set_property src_info {type:XDC file:1 line:26 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN C9 [get_ports {pcie_mgt_rxn[3]}]
set_property src_info {type:XDC file:1 line:27 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN D9 [get_ports {pcie_mgt_rxp[3]}]
set_property src_info {type:XDC file:1 line:28 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN C7 [get_ports {pcie_mgt_txn[3]}]
set_property src_info {type:XDC file:1 line:29 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN D7 [get_ports {pcie_mgt_txp[3]}]
set_property src_info {type:XDC file:1 line:32 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN F6 [get_ports {diff_clock_rtl_0_clk_p[0]}]
set_property src_info {type:XDC file:1 line:33 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN E6 [get_ports {diff_clock_rtl_0_clk_n[0]}]
set_property src_info {type:XDC file:1 line:36 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN G1 [get_ports {pcie_clkreq_l}]
set_property src_info {type:XDC file:1 line:37 export:INPUT save:INPUT read:READ} [current_design]
set_property IOSTANDARD LVCMOS33 [get_ports {pcie_clkreq_l}]
set_property src_info {type:XDC file:1 line:38 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN J1 [get_ports reset_rtl_0]
set_property src_info {type:XDC file:2 line:1 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN G4 [get_ports {leds_tri_o[1]}]
set_property src_info {type:XDC file:2 line:6 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN H4 [get_ports {leds_tri_o[0]}]
set_property src_info {type:XDC file:2 line:11 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN M1 [get_ports {LED_M2[0]}]

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hello_world_dma.runs/synth_1/.vivado.begin.rst Normal file
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<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command="vivado" Owner="nickorlow" Host="media-wawa" Pid="417074" HostCore="12" HostMemory="16324096">
</Process>
</ProcessHandle>

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hello_world_dma.runs/synth_1/.vivado.end.rst Normal file
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hello_world_dma.runs/synth_1/ISEWrap.js Executable file
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//
// Vivado(TM)
// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved.
//
// GLOBAL VARIABLES
var ISEShell = new ActiveXObject( "WScript.Shell" );
var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
var ISERunDir = "";
var ISELogFile = "runme.log";
var ISELogFileStr = null;
var ISELogEcho = true;
var ISEOldVersionWSH = false;
// BOOTSTRAP
ISEInit();
//
// ISE FUNCTIONS
//
function ISEInit() {
// 1. RUN DIR setup
var ISEScrFP = WScript.ScriptFullName;
var ISEScrN = WScript.ScriptName;
ISERunDir =
ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
// 2. LOG file setup
ISELogFileStr = ISEOpenFile( ISELogFile );
// 3. LOG echo?
var ISEScriptArgs = WScript.Arguments;
for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
if ( ISEScriptArgs(loopi) == "-quiet" ) {
ISELogEcho = false;
break;
}
}
// 4. WSH version check
var ISEOptimalVersionWSH = 5.6;
var ISECurrentVersionWSH = WScript.Version;
if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
ISEStdErr( "" );
ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
ISEOptimalVersionWSH + " or higher. Downloads" );
ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
ISEStdErr( "" );
ISEOldVersionWSH = true;
}
}
function ISEStep( ISEProg, ISEArgs ) {
// CHECK for a STOP FILE
if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
ISEStdErr( "" );
ISEStdErr( "*** Halting run - EA reset detected ***" );
ISEStdErr( "" );
WScript.Quit( 1 );
}
// WRITE STEP HEADER to LOG
ISEStdOut( "" );
ISEStdOut( "*** Running " + ISEProg );
ISEStdOut( " with args " + ISEArgs );
ISEStdOut( "" );
// LAUNCH!
var ISEExitCode = ISEExec( ISEProg, ISEArgs );
if ( ISEExitCode != 0 ) {
WScript.Quit( ISEExitCode );
}
}
function ISEExec( ISEProg, ISEArgs ) {
var ISEStep = ISEProg;
if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
ISEProg += ".bat";
}
var ISECmdLine = ISEProg + " " + ISEArgs;
var ISEExitCode = 1;
if ( ISEOldVersionWSH ) { // WSH 5.1
// BEGIN file creation
ISETouchFile( ISEStep, "begin" );
// LAUNCH!
ISELogFileStr.Close();
ISECmdLine =
"%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
ISELogFileStr = ISEOpenFile( ISELogFile );
} else { // WSH 5.6
// LAUNCH!
ISEShell.CurrentDirectory = ISERunDir;
// Redirect STDERR to STDOUT
ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
var ISEProcess = ISEShell.Exec( ISECmdLine );
// BEGIN file creation
var wbemFlagReturnImmediately = 0x10;
var wbemFlagForwardOnly = 0x20;
var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
var NOC = 0;
var NOLP = 0;
var TPM = 0;
var cpuInfos = new Enumerator(processor);
for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
var cpuInfo = cpuInfos.item();
NOC += cpuInfo.NumberOfCores;
NOLP += cpuInfo.NumberOfLogicalProcessors;
}
var csInfos = new Enumerator(computerSystem);
for(;!csInfos.atEnd(); csInfos.moveNext()) {
var csInfo = csInfos.item();
TPM += csInfo.TotalPhysicalMemory;
}
var ISEHOSTCORE = NOLP
var ISEMEMTOTAL = TPM
var ISENetwork = WScript.CreateObject( "WScript.Network" );
var ISEHost = ISENetwork.ComputerName;
var ISEUser = ISENetwork.UserName;
var ISEPid = ISEProcess.ProcessID;
var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
"\" Owner=\"" + ISEUser +
"\" Host=\"" + ISEHost +
"\" Pid=\"" + ISEPid +
"\" HostCore=\"" + ISEHOSTCORE +
"\" HostMemory=\"" + ISEMEMTOTAL +
"\">" );
ISEBeginFile.WriteLine( " </Process>" );
ISEBeginFile.WriteLine( "</ProcessHandle>" );
ISEBeginFile.Close();
var ISEOutStr = ISEProcess.StdOut;
var ISEErrStr = ISEProcess.StdErr;
// WAIT for ISEStep to finish
while ( ISEProcess.Status == 0 ) {
// dump stdout then stderr - feels a little arbitrary
while ( !ISEOutStr.AtEndOfStream ) {
ISEStdOut( ISEOutStr.ReadLine() );
}
WScript.Sleep( 100 );
}
ISEExitCode = ISEProcess.ExitCode;
}
ISELogFileStr.Close();
// END/ERROR file creation
if ( ISEExitCode != 0 ) {
ISETouchFile( ISEStep, "error" );
} else {
ISETouchFile( ISEStep, "end" );
}
return ISEExitCode;
}
//
// UTILITIES
//
function ISEStdOut( ISELine ) {
ISELogFileStr.WriteLine( ISELine );
if ( ISELogEcho ) {
WScript.StdOut.WriteLine( ISELine );
}
}
function ISEStdErr( ISELine ) {
ISELogFileStr.WriteLine( ISELine );
if ( ISELogEcho ) {
WScript.StdErr.WriteLine( ISELine );
}
}
function ISETouchFile( ISERoot, ISEStatus ) {
var ISETFile =
ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
ISETFile.Close();
}
function ISEOpenFile( ISEFilename ) {
// This function has been updated to deal with a problem seen in CR #870871.
// In that case the user runs a script that runs impl_1, and then turns around
// and runs impl_1 -to_step write_bitstream. That second run takes place in
// the same directory, which means we may hit some of the same files, and in
// particular, we will open the runme.log file. Even though this script closes
// the file (now), we see cases where a subsequent attempt to open the file
// fails. Perhaps the OS is slow to release the lock, or the disk comes into
// play? In any case, we try to work around this by first waiting if the file
// is already there for an arbitrary 5 seconds. Then we use a try-catch block
// and try to open the file 10 times with a one second delay after each attempt.
// Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
// If there is an unrecognized exception when trying to open the file, we output
// an error message and write details to an exception.log file.
var ISEFullPath = ISERunDir + "/" + ISEFilename;
if (ISEFileSys.FileExists(ISEFullPath)) {
// File is already there. This could be a problem. Wait in case it is still in use.
WScript.Sleep(5000);
}
var i;
for (i = 0; i < 10; ++i) {
try {
return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
} catch (exception) {
var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
if (error_code == 52) { // 52 is bad file name or number.
// Wait a second and try again.
WScript.Sleep(1000);
continue;
} else {
WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
var exceptionFilePath = ISERunDir + "/exception.log";
if (!ISEFileSys.FileExists(exceptionFilePath)) {
WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
exceptionFile.WriteLine("\tException name: " + exception.name);
exceptionFile.WriteLine("\tException error code: " + error_code);
exceptionFile.WriteLine("\tException message: " + exception.message);
exceptionFile.Close();
}
throw exception;
}
}
}
// If we reached this point, we failed to open the file after 10 attempts.
// We need to error out.
WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
WScript.Quit(1);
}

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hello_world_dma.runs/synth_1/ISEWrap.sh Executable file
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#!/bin/sh
#
# Vivado(TM)
# ISEWrap.sh: Vivado Runs Script for UNIX
# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
#
cmd_exists()
{
command -v "$1" >/dev/null 2>&1
}
HD_LOG=$1
shift
# CHECK for a STOP FILE
if [ -f .stop.rst ]
then
echo "" >> $HD_LOG
echo "*** Halting run - EA reset detected ***" >> $HD_LOG
echo "" >> $HD_LOG
exit 1
fi
ISE_STEP=$1
shift
# WRITE STEP HEADER to LOG
echo "" >> $HD_LOG
echo "*** Running $ISE_STEP" >> $HD_LOG
echo " with args $@" >> $HD_LOG
echo "" >> $HD_LOG
# LAUNCH!
$ISE_STEP "$@" >> $HD_LOG 2>&1 &
# BEGIN file creation
ISE_PID=$!
HostNameFile=/proc/sys/kernel/hostname
if cmd_exists hostname
then
ISE_HOST=$(hostname)
elif cmd_exists uname
then
ISE_HOST=$(uname -n)
elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ]
then
ISE_HOST=$(cat $HostNameFile)
elif [ X != X$HOSTNAME ]
then
ISE_HOST=$HOSTNAME #bash
else
ISE_HOST=$HOST #csh
fi
ISE_USER=$USER
ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
ISE_BEGINFILE=.$ISE_STEP.begin.rst
/bin/touch $ISE_BEGINFILE
echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
echo " </Process>" >> $ISE_BEGINFILE
echo "</ProcessHandle>" >> $ISE_BEGINFILE
# WAIT for ISEStep to finish
wait $ISE_PID
# END/ERROR file creation
RETVAL=$?
if [ $RETVAL -eq 0 ]
then
/bin/touch .$ISE_STEP.end.rst
else
/bin/touch .$ISE_STEP.error.rst
fi
exit $RETVAL

0
hello_world_dma.runs/synth_1/__synthesis_is_complete__ Normal file
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hello_world_dma.runs/synth_1/dont_touch.xdc Normal file
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# This file is automatically generated.
# It contains project source information necessary for synthesis and implementation.
# XDC: new/early.xdc
# XDC: new/normal.xdc
# Block Designs: bd/top/top.bd
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==top || ORIG_REF_NAME==top} -quiet] -quiet
# IP: bd/top/ip/top_xdma_0_0/top_xdma_0_0.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==top_xdma_0_0 || ORIG_REF_NAME==top_xdma_0_0} -quiet] -quiet
# IP: bd/top/ip/top_axi_bram_ctrl_0_0/top_axi_bram_ctrl_0_0.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==top_axi_bram_ctrl_0_0 || ORIG_REF_NAME==top_axi_bram_ctrl_0_0} -quiet] -quiet
# IP: bd/top/ip/top_blk_mem_gen_0_0/top_blk_mem_gen_0_0.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==top_blk_mem_gen_0_0 || ORIG_REF_NAME==top_blk_mem_gen_0_0} -quiet] -quiet
# IP: bd/top/ip/top_util_vector_logic_0_0/top_util_vector_logic_0_0.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==top_util_vector_logic_0_0 || ORIG_REF_NAME==top_util_vector_logic_0_0} -quiet] -quiet
# IP: bd/top/ip/top_axi_gpio_0_0/top_axi_gpio_0_0.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==top_axi_gpio_0_0 || ORIG_REF_NAME==top_axi_gpio_0_0} -quiet] -quiet
# IP: bd/top/ip/top_util_ds_buf_0/top_util_ds_buf_0.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==top_util_ds_buf_0 || ORIG_REF_NAME==top_util_ds_buf_0} -quiet] -quiet
# IP: bd/top/ip/top_axi_smc_0/top_axi_smc_0.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==top_axi_smc_0 || ORIG_REF_NAME==top_axi_smc_0} -quiet] -quiet
# IP: bd/top/ip/top_xdma_0_axi_periph_0/top_xdma_0_axi_periph_0.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==top_xdma_0_axi_periph_0 || ORIG_REF_NAME==top_xdma_0_axi_periph_0} -quiet] -quiet
# XDC: /home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/top_ooc.xdc

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hello_world_dma.runs/synth_1/gen_run.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="synth_1" LaunchPart="xc7a100tlfgg484-2L" LaunchTime="1750771529" LaunchIncrCheckpoint="$PSRCDIR/utils_1/imports/synth_1/top_wrapper.dcp">
<File Type="VDS-TIMINGSUMMARY" Name="top_wrapper_timing_summary_synth.rpt"/>
<File Type="RDS-DCP" Name="top_wrapper.dcp"/>
<File Type="RDS-UTIL-PB" Name="top_wrapper_utilization_synth.pb"/>
<File Type="RDS-UTIL" Name="top_wrapper_utilization_synth.rpt"/>
<File Type="RDS-PROPCONSTRS" Name="top_wrapper_drc_synth.rpt"/>
<File Type="RDS-RDS" Name="top_wrapper.vds"/>
<File Type="REPORTS-TCL" Name="top_wrapper_reports.tcl"/>
<File Type="VDS-TIMING-PB" Name="top_wrapper_timing_summary_synth.pb"/>
<File Type="PA-TCL" Name="top_wrapper.tcl"/>
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/bd/top/top.bd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PGENDIR/sources_1/bd/top/hdl/top_wrapper.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="top_wrapper"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<File Path="$PSRCDIR/constrs_1/new/early.xdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="ProcessingOrder" Val="EARLY"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/constrs_1/new/normal.xdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
<Filter Type="Utils"/>
<File Path="$PSRCDIR/utils_1/imports/synth_1/top_wrapper.dcp">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedInSteps" Val="synth_1"/>
<Attr Name="AutoDcp" Val="1"/>
</FileInfo>
</File>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<BlockFileSet Type="BlockSrcs" Name="top_util_ds_buf_0"/>
<BlockFileSet Type="BlockSrcs" Name="top_axi_gpio_0_0"/>
<BlockFileSet Type="BlockSrcs" Name="top_util_vector_logic_0_0"/>
<BlockFileSet Type="BlockSrcs" Name="top_blk_mem_gen_0_0"/>
<BlockFileSet Type="BlockSrcs" Name="top_axi_bram_ctrl_0_0"/>
<BlockFileSet Type="BlockSrcs" Name="top_xdma_0_0"/>
</GenRun>

9
hello_world_dma.runs/synth_1/htr.txt Normal file
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#
# Vivado(TM)
# htr.txt: a Vivado-generated description of how-to-repeat the
# the basic steps of a run. Note that runme.bat/sh needs
# to be invoked for Vivado to track run status.
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
#
vivado -log top_wrapper.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source top_wrapper.tcl

57
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version:1
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5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3135333234333232323333333430663361393430363839383033373839353562:506172656e742050412070726f6a656374204944:00
eof:1916727104

40
hello_world_dma.runs/synth_1/rundef.js Normal file
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@ -0,0 +1,40 @@
//
// Vivado(TM)
// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
//
echo "This script was generated under a different operating system."
echo "Please update the PATH variable below, before executing this script"
exit
var WshShell = new ActiveXObject( "WScript.Shell" );
var ProcEnv = WshShell.Environment( "Process" );
var PathVal = ProcEnv("PATH");
if ( PathVal.length == 0 ) {
PathVal = "/home/nickorlow/vivado/inst_22.01/Vivado/2022.1/ids_lite/ISE/bin/lin64;/home/nickorlow/vivado/inst_22.01/Vivado/2022.1/bin;";
} else {
PathVal = "/home/nickorlow/vivado/inst_22.01/Vivado/2022.1/ids_lite/ISE/bin/lin64;/home/nickorlow/vivado/inst_22.01/Vivado/2022.1/bin;" + PathVal;
}
ProcEnv("PATH") = PathVal;
var RDScrFP = WScript.ScriptFullName;
var RDScrN = WScript.ScriptName;
var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
eval( EAInclude(ISEJScriptLib) );
ISEStep( "vivado",
"-log top_wrapper.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source top_wrapper.tcl" );
function EAInclude( EAInclFilename ) {
var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
var EAIFContents = EAInclFile.ReadAll();
EAInclFile.Close();
return EAIFContents;
}

11
hello_world_dma.runs/synth_1/runme.bat Normal file
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@ -0,0 +1,11 @@
@echo off
rem Vivado (TM)
rem runme.bat: a Vivado-generated Script
rem Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
set HD_SDIR=%~dp0
cd /d "%HD_SDIR%"
set PATH=%SYSTEMROOT%\system32;%PATH%
cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*

322
hello_world_dma.runs/synth_1/runme.log Normal file
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*** Running vivado
with args -log top_wrapper.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source top_wrapper.tcl
****** Vivado v2022.1 (64-bit)
**** SW Build 3526262 on Mon Apr 18 15:47:01 MDT 2022
**** IP Build 3524634 on Mon Apr 18 20:55:01 MDT 2022
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
source top_wrapper.tcl -notrace
create_project: Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 2607.566 ; gain = 5.961 ; free physical = 1450 ; free virtual = 4871
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/nickorlow/vivado/inst_22.01/Vivado/2022.1/data/ip'.
Command: read_checkpoint -auto_incremental -incremental /home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/utils_1/imports/synth_1/top_wrapper.dcp
INFO: [Vivado 12-5825] Read reference checkpoint from /home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/utils_1/imports/synth_1/top_wrapper.dcp for incremental synthesis
INFO: [Vivado 12-7989] Please ensure there are no constraint changes
Command: synth_design -top top_wrapper -part xc7a100tlfgg484-2L
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100tl'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100tl'
INFO: [Device 21-403] Loading part xc7a100tlfgg484-2L
INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run
INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 417254
WARNING: [Synth 8-9501] generate block is allowed only inside loop and conditional generate in SystemVerilog mode [/home/nickorlow/vivado/inst_22.01/Vivado/2022.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:4023]
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2607.566 ; gain = 0.000 ; free physical = 158 ; free virtual = 3085
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'top_wrapper' [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/hdl/top_wrapper.v:12]
INFO: [Synth 8-6157] synthesizing module 'top' [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/synth/top.v:144]
INFO: [Synth 8-6157] synthesizing module 'top_axi_bram_ctrl_0_0' [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.runs/synth_1/.Xil/Vivado-417119-media-wawa/realtime/top_axi_bram_ctrl_0_0_stub.v:5]
INFO: [Synth 8-6155] done synthesizing module 'top_axi_bram_ctrl_0_0' (0#1) [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.runs/synth_1/.Xil/Vivado-417119-media-wawa/realtime/top_axi_bram_ctrl_0_0_stub.v:5]
INFO: [Synth 8-6157] synthesizing module 'top_axi_gpio_0_0' [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.runs/synth_1/.Xil/Vivado-417119-media-wawa/realtime/top_axi_gpio_0_0_stub.v:5]
INFO: [Synth 8-6155] done synthesizing module 'top_axi_gpio_0_0' (0#1) [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.runs/synth_1/.Xil/Vivado-417119-media-wawa/realtime/top_axi_gpio_0_0_stub.v:5]
INFO: [Synth 8-6157] synthesizing module 'top_axi_smc_0' [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.runs/synth_1/.Xil/Vivado-417119-media-wawa/realtime/top_axi_smc_0_stub.v:5]
INFO: [Synth 8-6155] done synthesizing module 'top_axi_smc_0' (0#1) [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.runs/synth_1/.Xil/Vivado-417119-media-wawa/realtime/top_axi_smc_0_stub.v:5]
WARNING: [Synth 8-7071] port 'M00_AXI_awqos' of module 'top_axi_smc_0' is unconnected for instance 'axi_smc' [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/synth/top.v:371]
WARNING: [Synth 8-7071] port 'M00_AXI_arqos' of module 'top_axi_smc_0' is unconnected for instance 'axi_smc' [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/synth/top.v:371]
WARNING: [Synth 8-7023] instance 'axi_smc' of module 'top_axi_smc_0' has 72 connections declared, but only 70 given [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/synth/top.v:371]
INFO: [Synth 8-6157] synthesizing module 'top_blk_mem_gen_0_0' [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.runs/synth_1/.Xil/Vivado-417119-media-wawa/realtime/top_blk_mem_gen_0_0_stub.v:5]
INFO: [Synth 8-6155] done synthesizing module 'top_blk_mem_gen_0_0' (0#1) [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.runs/synth_1/.Xil/Vivado-417119-media-wawa/realtime/top_blk_mem_gen_0_0_stub.v:5]
INFO: [Synth 8-6157] synthesizing module 'top_util_ds_buf_0' [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.runs/synth_1/.Xil/Vivado-417119-media-wawa/realtime/top_util_ds_buf_0_stub.v:5]
INFO: [Synth 8-6155] done synthesizing module 'top_util_ds_buf_0' (0#1) [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.runs/synth_1/.Xil/Vivado-417119-media-wawa/realtime/top_util_ds_buf_0_stub.v:5]
WARNING: [Synth 8-7071] port 'IBUF_DS_ODIV2' of module 'top_util_ds_buf_0' is unconnected for instance 'util_ds_buf' [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/synth/top.v:457]
WARNING: [Synth 8-7023] instance 'util_ds_buf' of module 'top_util_ds_buf_0' has 4 connections declared, but only 3 given [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/synth/top.v:457]
INFO: [Synth 8-6157] synthesizing module 'top_util_vector_logic_0_0' [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.runs/synth_1/.Xil/Vivado-417119-media-wawa/realtime/top_util_vector_logic_0_0_stub.v:5]
INFO: [Synth 8-6155] done synthesizing module 'top_util_vector_logic_0_0' (0#1) [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.runs/synth_1/.Xil/Vivado-417119-media-wawa/realtime/top_util_vector_logic_0_0_stub.v:5]
INFO: [Synth 8-6157] synthesizing module 'top_xdma_0_0' [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.runs/synth_1/.Xil/Vivado-417119-media-wawa/realtime/top_xdma_0_0_stub.v:5]
INFO: [Synth 8-6155] done synthesizing module 'top_xdma_0_0' (0#1) [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.runs/synth_1/.Xil/Vivado-417119-media-wawa/realtime/top_xdma_0_0_stub.v:5]
WARNING: [Synth 8-7071] port 'usr_irq_ack' of module 'top_xdma_0_0' is unconnected for instance 'xdma_0' [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/synth/top.v:464]
WARNING: [Synth 8-7071] port 'msi_enable' of module 'top_xdma_0_0' is unconnected for instance 'xdma_0' [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/synth/top.v:464]
WARNING: [Synth 8-7071] port 'msi_vector_width' of module 'top_xdma_0_0' is unconnected for instance 'xdma_0' [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/synth/top.v:464]
WARNING: [Synth 8-7071] port 'm_axil_awprot' of module 'top_xdma_0_0' is unconnected for instance 'xdma_0' [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/synth/top.v:464]
WARNING: [Synth 8-7071] port 'm_axil_arprot' of module 'top_xdma_0_0' is unconnected for instance 'xdma_0' [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/synth/top.v:464]
WARNING: [Synth 8-7023] instance 'xdma_0' of module 'top_xdma_0_0' has 67 connections declared, but only 62 given [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/synth/top.v:464]
INFO: [Synth 8-6157] synthesizing module 'top_xdma_0_axi_periph_0' [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/synth/top.v:570]
INFO: [Synth 8-6157] synthesizing module 's00_couplers_imp_110C0LX' [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/synth/top.v:12]
INFO: [Synth 8-6155] done synthesizing module 's00_couplers_imp_110C0LX' (0#1) [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/synth/top.v:12]
INFO: [Synth 8-6155] done synthesizing module 'top_xdma_0_axi_periph_0' (0#1) [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/synth/top.v:570]
INFO: [Synth 8-6155] done synthesizing module 'top' (0#1) [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/synth/top.v:144]
INFO: [Synth 8-6155] done synthesizing module 'top_wrapper' (0#1) [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/hdl/top_wrapper.v:12]
WARNING: [Synth 8-7129] Port M_ACLK in module s00_couplers_imp_110C0LX is either unconnected or has no load
WARNING: [Synth 8-7129] Port M_ARESETN in module s00_couplers_imp_110C0LX is either unconnected or has no load
WARNING: [Synth 8-7129] Port S_ACLK in module s00_couplers_imp_110C0LX is either unconnected or has no load
WARNING: [Synth 8-7129] Port S_ARESETN in module s00_couplers_imp_110C0LX is either unconnected or has no load
WARNING: [Synth 8-7129] Port ACLK in module top_xdma_0_axi_periph_0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ARESETN in module top_xdma_0_axi_periph_0 is either unconnected or has no load
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2607.566 ; gain = 0.000 ; free physical = 1139 ; free virtual = 4028
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2607.566 ; gain = 0.000 ; free physical = 1139 ; free virtual = 4028
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2607.566 ; gain = 0.000 ; free physical = 1139 ; free virtual = 4028
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2607.566 ; gain = 0.000 ; free physical = 1139 ; free virtual = 4028
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_xdma_0_0/top_xdma_0_0/top_xdma_0_0_in_context.xdc] for cell 'top_i/xdma_0'
Finished Parsing XDC File [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_xdma_0_0/top_xdma_0_0/top_xdma_0_0_in_context.xdc] for cell 'top_i/xdma_0'
Parsing XDC File [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_axi_bram_ctrl_0_0/top_axi_bram_ctrl_0_0/top_axi_bram_ctrl_0_0_in_context.xdc] for cell 'top_i/axi_bram_ctrl_0'
Finished Parsing XDC File [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_axi_bram_ctrl_0_0/top_axi_bram_ctrl_0_0/top_axi_bram_ctrl_0_0_in_context.xdc] for cell 'top_i/axi_bram_ctrl_0'
Parsing XDC File [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_blk_mem_gen_0_0/top_blk_mem_gen_0_0/top_blk_mem_gen_0_0_in_context.xdc] for cell 'top_i/blk_mem_gen_0'
Finished Parsing XDC File [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_blk_mem_gen_0_0/top_blk_mem_gen_0_0/top_blk_mem_gen_0_0_in_context.xdc] for cell 'top_i/blk_mem_gen_0'
Parsing XDC File [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_util_vector_logic_0_0/top_util_vector_logic_0_0/top_util_vector_logic_0_0_in_context.xdc] for cell 'top_i/util_vector_logic_0'
Finished Parsing XDC File [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_util_vector_logic_0_0/top_util_vector_logic_0_0/top_util_vector_logic_0_0_in_context.xdc] for cell 'top_i/util_vector_logic_0'
Parsing XDC File [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_axi_gpio_0_0/top_axi_gpio_0_0/top_axi_gpio_0_0_in_context.xdc] for cell 'top_i/axi_gpio_0'
Finished Parsing XDC File [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_axi_gpio_0_0/top_axi_gpio_0_0/top_axi_gpio_0_0_in_context.xdc] for cell 'top_i/axi_gpio_0'
Parsing XDC File [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_util_ds_buf_0/top_util_ds_buf_0/top_util_ds_buf_0_in_context.xdc] for cell 'top_i/util_ds_buf'
Finished Parsing XDC File [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_util_ds_buf_0/top_util_ds_buf_0/top_util_ds_buf_0_in_context.xdc] for cell 'top_i/util_ds_buf'
Parsing XDC File [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_axi_smc_0/top_axi_smc_0/top_axi_smc_0_in_context.xdc] for cell 'top_i/axi_smc'
Finished Parsing XDC File [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_axi_smc_0/top_axi_smc_0/top_axi_smc_0_in_context.xdc] for cell 'top_i/axi_smc'
Parsing XDC File [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/constrs_1/new/early.xdc]
WARNING: [Vivado 12-584] No ports matched 'pcie_mgt_rxn[0]'. [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/constrs_1/new/early.xdc:5]
WARNING: [Vivado 12-584] No ports matched 'pcie_mgt_rxp[0]'. [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/constrs_1/new/early.xdc:6]
WARNING: [Vivado 12-584] No ports matched 'pcie_mgt_txn[0]'. [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/constrs_1/new/early.xdc:7]
WARNING: [Vivado 12-584] No ports matched 'pcie_mgt_txp[0]'. [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/constrs_1/new/early.xdc:8]
WARNING: [Vivado 12-584] No ports matched 'pcie_mgt_rxn[1]'. [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/constrs_1/new/early.xdc:12]
WARNING: [Vivado 12-584] No ports matched 'pcie_mgt_rxp[1]'. [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/constrs_1/new/early.xdc:13]
WARNING: [Vivado 12-584] No ports matched 'pcie_mgt_txn[1]'. [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/constrs_1/new/early.xdc:14]
WARNING: [Vivado 12-584] No ports matched 'pcie_mgt_txp[1]'. [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/constrs_1/new/early.xdc:15]
WARNING: [Vivado 12-584] No ports matched 'pcie_mgt_rxn[2]'. [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/constrs_1/new/early.xdc:19]
WARNING: [Vivado 12-584] No ports matched 'pcie_mgt_rxp[2]'. [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/constrs_1/new/early.xdc:20]
WARNING: [Vivado 12-584] No ports matched 'pcie_mgt_txn[2]'. [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/constrs_1/new/early.xdc:21]
WARNING: [Vivado 12-584] No ports matched 'pcie_mgt_txp[2]'. [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/constrs_1/new/early.xdc:22]
WARNING: [Vivado 12-584] No ports matched 'pcie_mgt_rxn[3]'. [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/constrs_1/new/early.xdc:26]
WARNING: [Vivado 12-584] No ports matched 'pcie_mgt_rxp[3]'. [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/constrs_1/new/early.xdc:27]
WARNING: [Vivado 12-584] No ports matched 'pcie_mgt_txn[3]'. [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/constrs_1/new/early.xdc:28]
WARNING: [Vivado 12-584] No ports matched 'pcie_mgt_txp[3]'. [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/constrs_1/new/early.xdc:29]
WARNING: [Vivado 12-584] No ports matched 'pcie_clkreq_l'. [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/constrs_1/new/early.xdc:36]
WARNING: [Vivado 12-584] No ports matched 'pcie_clkreq_l'. [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/constrs_1/new/early.xdc:37]
Finished Parsing XDC File [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/constrs_1/new/early.xdc]
WARNING: [Project 1-498] One or more constraints failed evaluation while reading constraint file [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/constrs_1/new/early.xdc] and the design contains unresolved black boxes. These constraints will be read post-synthesis (as long as their source constraint file is marked as used_in_implementation) and should be applied correctly then. You should review the constraints listed in the file [.Xil/top_wrapper_propImpl.xdc] and check the run log file to verify that these constraints were correctly applied.
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/constrs_1/new/early.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_wrapper_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/top_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Parsing XDC File [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/constrs_1/new/normal.xdc]
Finished Parsing XDC File [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/constrs_1/new/normal.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/constrs_1/new/normal.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_wrapper_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/top_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Parsing XDC File [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.runs/synth_1/dont_touch.xdc]
Finished Parsing XDC File [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.runs/synth_1/dont_touch.xdc]
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2671.598 ; gain = 0.000 ; free physical = 1135 ; free virtual = 4024
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2671.598 ; gain = 0.000 ; free physical = 1135 ; free virtual = 4024
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'top_i/axi_gpio_0' at clock pin 's_axi_aclk' is different from the actual clock period '8.000', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'top_i/blk_mem_gen_0' at clock pin 'clka' is different from the actual clock period '8.000', this can lead to different synthesis results.
INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run
INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
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Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2671.598 ; gain = 64.031 ; free physical = 1174 ; free virtual = 4063
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Start Loading Part and Timing Information
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Loading part: xc7a100tlfgg484-2L
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Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2671.598 ; gain = 64.031 ; free physical = 1174 ; free virtual = 4063
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Start Applying 'set_property' XDC Constraints
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Applied set_property IO_BUFFER_TYPE = NONE for diff_clock_rtl_0_clk_n[0]. (constraint file /home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_util_ds_buf_0/top_util_ds_buf_0/top_util_ds_buf_0_in_context.xdc, line 3).
Applied set_property CLOCK_BUFFER_TYPE = NONE for diff_clock_rtl_0_clk_n[0]. (constraint file /home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_util_ds_buf_0/top_util_ds_buf_0/top_util_ds_buf_0_in_context.xdc, line 4).
Applied set_property IO_BUFFER_TYPE = NONE for diff_clock_rtl_0_clk_p[0]. (constraint file /home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_util_ds_buf_0/top_util_ds_buf_0/top_util_ds_buf_0_in_context.xdc, line 5).
Applied set_property CLOCK_BUFFER_TYPE = NONE for diff_clock_rtl_0_clk_p[0]. (constraint file /home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_util_ds_buf_0/top_util_ds_buf_0/top_util_ds_buf_0_in_context.xdc, line 6).
Applied set_property KEEP_HIERARCHY = SOFT for top_i. (constraint file auto generated constraint).
Applied set_property KEEP_HIERARCHY = SOFT for top_i/xdma_0. (constraint file auto generated constraint).
Applied set_property KEEP_HIERARCHY = SOFT for top_i/axi_bram_ctrl_0. (constraint file auto generated constraint).
Applied set_property KEEP_HIERARCHY = SOFT for top_i/blk_mem_gen_0. (constraint file auto generated constraint).
Applied set_property KEEP_HIERARCHY = SOFT for top_i/util_vector_logic_0. (constraint file auto generated constraint).
Applied set_property KEEP_HIERARCHY = SOFT for top_i/axi_gpio_0. (constraint file auto generated constraint).
Applied set_property KEEP_HIERARCHY = SOFT for top_i/util_ds_buf. (constraint file auto generated constraint).
Applied set_property KEEP_HIERARCHY = SOFT for top_i/axi_smc. (constraint file auto generated constraint).
Applied set_property KEEP_HIERARCHY = SOFT for top_i/xdma_0_axi_periph. (constraint file auto generated constraint).
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2671.598 ; gain = 64.031 ; free physical = 1174 ; free virtual = 4063
---------------------------------------------------------------------------------
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Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2671.598 ; gain = 64.031 ; free physical = 1174 ; free virtual = 4064
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Start RTL Component Statistics
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Detailed RTL Component Info :
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Finished RTL Component Statistics
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Start Part Resource Summary
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Part Resources:
DSPs: 240 (col length:80)
BRAMs: 270 (col length: RAMB18 80 RAMB36 40)
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Finished Part Resource Summary
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Start Cross Boundary and Area Optimization
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WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
WARNING: [Synth 8-7129] Port ACLK in module top_xdma_0_axi_periph_0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ARESETN in module top_xdma_0_axi_periph_0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port M00_ACLK in module top_xdma_0_axi_periph_0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port M00_ARESETN in module top_xdma_0_axi_periph_0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port S00_ACLK in module top_xdma_0_axi_periph_0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port S00_ARESETN in module top_xdma_0_axi_periph_0 is either unconnected or has no load
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:14 ; elapsed = 00:00:16 . Memory (MB): peak = 2671.598 ; gain = 64.031 ; free physical = 1173 ; free virtual = 4067
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Start Applying XDC Timing Constraints
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Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 2671.598 ; gain = 64.031 ; free physical = 1100 ; free virtual = 3994
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Start Timing Optimization
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Finished Timing Optimization : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 2671.598 ; gain = 64.031 ; free physical = 1100 ; free virtual = 3994
---------------------------------------------------------------------------------
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Start Technology Mapping
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Finished Technology Mapping : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 2671.598 ; gain = 64.031 ; free physical = 1076 ; free virtual = 3971
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Start IO Insertion
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Start Flattening Before IO Insertion
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Finished Flattening Before IO Insertion
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Start Final Netlist Cleanup
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Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
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Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2671.598 ; gain = 64.031 ; free physical = 1091 ; free virtual = 3986
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
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Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2671.598 ; gain = 64.031 ; free physical = 1091 ; free virtual = 3986
---------------------------------------------------------------------------------
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Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
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Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2671.598 ; gain = 64.031 ; free physical = 1091 ; free virtual = 3986
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
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Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2671.598 ; gain = 64.031 ; free physical = 1091 ; free virtual = 3986
---------------------------------------------------------------------------------
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Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2671.598 ; gain = 64.031 ; free physical = 1091 ; free virtual = 3986
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2671.598 ; gain = 64.031 ; free physical = 1091 ; free virtual = 3986
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+------+--------------------------+----------+
| |BlackBox name |Instances |
+------+--------------------------+----------+
|1 |top_axi_bram_ctrl_0_0 | 1|
|2 |top_axi_gpio_0_0 | 1|
|3 |top_axi_smc_0 | 1|
|4 |top_blk_mem_gen_0_0 | 1|
|5 |top_util_ds_buf_0 | 1|
|6 |top_util_vector_logic_0_0 | 1|
|7 |top_xdma_0_0 | 1|
+------+--------------------------+----------+
Report Cell Usage:
+------+------------------------+------+
| |Cell |Count |
+------+------------------------+------+
|1 |top_axi_bram_ctrl_0 | 1|
|2 |top_axi_gpio_0 | 1|
|3 |top_axi_smc | 1|
|4 |top_blk_mem_gen_0 | 1|
|5 |top_util_ds_buf | 1|
|6 |top_util_vector_logic_0 | 1|
|7 |top_xdma_0 | 1|
|8 |IBUF | 9|
|9 |OBUF | 11|
+------+------------------------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2671.598 ; gain = 64.031 ; free physical = 1091 ; free virtual = 3986
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 7 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2671.598 ; gain = 0.000 ; free physical = 1134 ; free virtual = 4028
Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2671.598 ; gain = 64.031 ; free physical = 1134 ; free virtual = 4028
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2671.598 ; gain = 0.000 ; free physical = 1227 ; free virtual = 4122
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2671.598 ; gain = 0.000 ; free physical = 1170 ; free virtual = 4065
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Synth Design complete, checksum: f7656efe
INFO: [Common 17-83] Releasing license: Synthesis
45 Infos, 46 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:30 . Memory (MB): peak = 2671.598 ; gain = 64.031 ; free physical = 1347 ; free virtual = 4242
INFO: [Common 17-1381] The checkpoint '/home/nickorlow/vivado/hello_world_dma/hello_world_dma.runs/synth_1/top_wrapper.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file top_wrapper_utilization_synth.rpt -pb top_wrapper_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Tue Jun 24 13:26:14 2025...

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hello_world_dma.runs/synth_1/runme.sh Executable file
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@ -0,0 +1,39 @@
#!/bin/sh
#
# Vivado(TM)
# runme.sh: a Vivado-generated Runs Script for UNIX
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
#
if [ -z "$PATH" ]; then
PATH=/home/nickorlow/vivado/inst_22.01/Vivado/2022.1/ids_lite/ISE/bin/lin64:/home/nickorlow/vivado/inst_22.01/Vivado/2022.1/bin
else
PATH=/home/nickorlow/vivado/inst_22.01/Vivado/2022.1/ids_lite/ISE/bin/lin64:/home/nickorlow/vivado/inst_22.01/Vivado/2022.1/bin:$PATH
fi
export PATH
if [ -z "$LD_LIBRARY_PATH" ]; then
LD_LIBRARY_PATH=
else
LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
fi
export LD_LIBRARY_PATH
HD_PWD='/home/nickorlow/vivado/hello_world_dma/hello_world_dma.runs/synth_1'
cd "$HD_PWD"
HD_LOG=runme.log
/bin/touch $HD_LOG
ISEStep="./ISEWrap.sh"
EAStep()
{
$ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
if [ $? -ne 0 ]
then
exit
fi
}
EAStep vivado -log top_wrapper.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source top_wrapper.tcl

BIN
hello_world_dma.runs/synth_1/top_wrapper.dcp Normal file
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162
hello_world_dma.runs/synth_1/top_wrapper.tcl Normal file
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#
# Synthesis run script generated by Vivado
#
set TIME_start [clock seconds]
namespace eval ::optrace {
variable script "/home/nickorlow/vivado/hello_world_dma/hello_world_dma.runs/synth_1/top_wrapper.tcl"
variable category "vivado_synth"
}
# Try to connect to running dispatch if we haven't done so already.
# This code assumes that the Tcl interpreter is not using threads,
# since the ::dispatch::connected variable isn't mutex protected.
if {![info exists ::dispatch::connected]} {
namespace eval ::dispatch {
variable connected false
if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} {
set result "true"
if {[catch {
if {[lsearch -exact [package names] DispatchTcl] < 0} {
set result [load librdi_cd_clienttcl[info sharedlibextension]]
}
if {$result eq "false"} {
puts "WARNING: Could not load dispatch client library"
}
set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ]
if { $connect_id eq "" } {
puts "WARNING: Could not initialize dispatch client"
} else {
puts "INFO: Dispatch client connection id - $connect_id"
set connected true
}
} catch_res]} {
puts "WARNING: failed to connect to dispatch server - $catch_res"
}
}
}
}
if {$::dispatch::connected} {
# Remove the dummy proc if it exists.
if { [expr {[llength [info procs ::OPTRACE]] > 0}] } {
rename ::OPTRACE ""
}
proc ::OPTRACE { task action {tags {} } } {
::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category
}
# dispatch is generic. We specifically want to attach logging.
::vitis_log::connect_client
} else {
# Add dummy proc if it doesn't exist.
if { [expr {[llength [info procs ::OPTRACE]] == 0}] } {
proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} {
# Do nothing
}
}
}
proc create_report { reportName command } {
set status "."
append status $reportName ".fail"
if { [file exists $status] } {
eval file delete [glob $status]
}
send_msg_id runtcl-4 info "Executing : $command"
set retval [eval catch { $command } msg]
if { $retval != 0 } {
set fp [open $status w]
close $fp
send_msg_id runtcl-5 warning "$msg"
}
}
OPTRACE "synth_1" START { ROLLUP_AUTO }
set_param xicom.use_bs_reader 1
set_param chipscope.maxJobs 1
OPTRACE "Creating in-memory project" START { }
create_project -in_memory -part xc7a100tlfgg484-2L
set_param project.singleFileAddWarning.threshold 0
set_param project.compositeFile.enableAutoGeneration 0
set_param synth.vivado.isSynthRun true
set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
set_property webtalk.parent_dir /home/nickorlow/vivado/hello_world_dma/hello_world_dma.cache/wt [current_project]
set_property parent.project_path /home/nickorlow/vivado/hello_world_dma/hello_world_dma.xpr [current_project]
set_property XPM_LIBRARIES {XPM_CDC XPM_FIFO XPM_MEMORY} [current_project]
set_property default_lib xil_defaultlib [current_project]
set_property target_language Verilog [current_project]
set_property ip_output_repo /home/nickorlow/vivado/hello_world_dma/hello_world_dma.cache/ip [current_project]
set_property ip_cache_permissions {read write} [current_project]
OPTRACE "Creating in-memory project" END { }
OPTRACE "Adding files" START { }
read_verilog -library xil_defaultlib /home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/hdl/top_wrapper.v
add_files /home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/sources_1/bd/top/top.bd
set_property used_in_implementation false [get_files -all /home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_xdma_0_0/ip_4/pcie2_fifo_generator_tgt_brdg.xdc]
set_property used_in_implementation false [get_files -all /home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_xdma_0_0/ip_3/pcie2_fifo_generator_dma_cpl.xdc]
set_property used_in_implementation false [get_files -all /home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_xdma_0_0/ip_2/xdma_v4_1_17_blk_mem_64_noreg_be_ooc.xdc]
set_property used_in_implementation false [get_files -all /home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_xdma_0_0/ip_1/xdma_v4_1_17_blk_mem_64_reg_be_ooc.xdc]
set_property used_in_implementation false [get_files -all /home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_xdma_0_0/ip_0/source/top_xdma_0_0_pcie2_ip-PCIE_X0Y0.xdc]
set_property used_in_implementation false [get_files -all /home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_xdma_0_0/ip_0/synth/top_xdma_0_0_pcie2_ip_ooc.xdc]
set_property used_in_implementation false [get_files -all /home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_xdma_0_0/top_xdma_0_0_board.xdc]
set_property used_in_implementation false [get_files -all /home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_xdma_0_0/source/top_xdma_0_0_pcie3_7vx_ip.xdc]
set_property used_in_implementation false [get_files -all /home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_xdma_0_0/synth/top_xdma_0_0_ooc.xdc]
set_property used_in_implementation false [get_files -all /home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_axi_bram_ctrl_0_0/top_axi_bram_ctrl_0_0_ooc.xdc]
set_property used_in_implementation false [get_files -all /home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_blk_mem_gen_0_0/top_blk_mem_gen_0_0_ooc.xdc]
set_property used_in_implementation false [get_files -all /home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_axi_gpio_0_0/top_axi_gpio_0_0_board.xdc]
set_property used_in_implementation false [get_files -all /home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_axi_gpio_0_0/top_axi_gpio_0_0_ooc.xdc]
set_property used_in_implementation false [get_files -all /home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_axi_gpio_0_0/top_axi_gpio_0_0.xdc]
set_property used_in_implementation false [get_files -all /home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_util_ds_buf_0/top_util_ds_buf_0_board.xdc]
set_property used_in_implementation false [get_files -all /home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_util_ds_buf_0/top_util_ds_buf_0_ooc.xdc]
set_property used_in_implementation false [get_files -all /home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_axi_smc_0/bd_0/ip/ip_1/bd_b43a_psr_aclk_0_board.xdc]
set_property used_in_implementation false [get_files -all /home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_axi_smc_0/bd_0/ip/ip_1/bd_b43a_psr_aclk_0.xdc]
set_property used_in_implementation false [get_files -all /home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_axi_smc_0/bd_0/ip/ip_5/bd_b43a_s00a2s_0_ooc.xdc]
set_property used_in_implementation false [get_files -all /home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_axi_smc_0/bd_0/ip/ip_6/bd_b43a_sarn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all /home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_axi_smc_0/bd_0/ip/ip_7/bd_b43a_srn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all /home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_axi_smc_0/bd_0/ip/ip_8/bd_b43a_sawn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all /home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_axi_smc_0/bd_0/ip/ip_9/bd_b43a_swn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all /home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_axi_smc_0/bd_0/ip/ip_10/bd_b43a_sbn_0_ooc.xdc]
set_property used_in_implementation false [get_files -all /home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_axi_smc_0/bd_0/ip/ip_11/bd_b43a_m00s2a_0_ooc.xdc]
set_property used_in_implementation false [get_files -all /home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_axi_smc_0/ooc.xdc]
set_property used_in_implementation false [get_files -all /home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/top_ooc.xdc]
OPTRACE "Adding files" END { }
# Mark all dcp files as not used in implementation to prevent them from being
# stitched into the results of this synthesis run. Any black boxes in the
# design are intentionally left as such for best results. Dcp files will be
# stitched into the design at a later time, either when this synthesis run is
# opened, or when it is stitched into a dependent implementation run.
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
set_property used_in_implementation false $dcp
}
read_xdc /home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/constrs_1/new/early.xdc
set_property used_in_implementation false [get_files /home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/constrs_1/new/early.xdc]
set_property processing_order EARLY [get_files /home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/constrs_1/new/early.xdc]
read_xdc /home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/constrs_1/new/normal.xdc
set_property used_in_implementation false [get_files /home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/constrs_1/new/normal.xdc]
read_xdc dont_touch.xdc
set_property used_in_implementation false [get_files dont_touch.xdc]
set_param ips.enableIPCacheLiteLoad 1
read_checkpoint -auto_incremental -incremental /home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/utils_1/imports/synth_1/top_wrapper.dcp
close [open __synthesis_is_running__ w]
OPTRACE "synth_design" START { }
synth_design -top top_wrapper -part xc7a100tlfgg484-2L
OPTRACE "synth_design" END { }
if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } {
send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING"
}
OPTRACE "write_checkpoint" START { CHECKPOINT }
# disable binary constraint mode for synth run checkpoints
set_param constraints.enableBinaryConstraints false
write_checkpoint -force -noxdef top_wrapper.dcp
OPTRACE "write_checkpoint" END { }
OPTRACE "synth reports" START { REPORT }
create_report "synth_1_synth_report_utilization_0" "report_utilization -file top_wrapper_utilization_synth.rpt -pb top_wrapper_utilization_synth.pb"
OPTRACE "synth reports" END { }
file delete __synthesis_is_running__
close [open __synthesis_is_complete__ w]
OPTRACE "synth_1" END { }

324
hello_world_dma.runs/synth_1/top_wrapper.vds Normal file
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#-----------------------------------------------------------
# Vivado v2022.1 (64-bit)
# SW Build 3526262 on Mon Apr 18 15:47:01 MDT 2022
# IP Build 3524634 on Mon Apr 18 20:55:01 MDT 2022
# Start of session at: Tue Jun 24 13:25:33 2025
# Process ID: 417119
# Current directory: /home/nickorlow/vivado/hello_world_dma/hello_world_dma.runs/synth_1
# Command line: vivado -log top_wrapper.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source top_wrapper.tcl
# Log file: /home/nickorlow/vivado/hello_world_dma/hello_world_dma.runs/synth_1/top_wrapper.vds
# Journal file: /home/nickorlow/vivado/hello_world_dma/hello_world_dma.runs/synth_1/vivado.jou
# Running On: media-wawa, OS: Linux, CPU Frequency: 2722.617 MHz, CPU Physical cores: 12, Host memory: 16715 MB
#-----------------------------------------------------------
source top_wrapper.tcl -notrace
create_project: Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 2607.566 ; gain = 5.961 ; free physical = 1450 ; free virtual = 4871
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/nickorlow/vivado/inst_22.01/Vivado/2022.1/data/ip'.
Command: read_checkpoint -auto_incremental -incremental /home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/utils_1/imports/synth_1/top_wrapper.dcp
INFO: [Vivado 12-5825] Read reference checkpoint from /home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/utils_1/imports/synth_1/top_wrapper.dcp for incremental synthesis
INFO: [Vivado 12-7989] Please ensure there are no constraint changes
Command: synth_design -top top_wrapper -part xc7a100tlfgg484-2L
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100tl'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100tl'
INFO: [Device 21-403] Loading part xc7a100tlfgg484-2L
INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run
INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 417254
WARNING: [Synth 8-9501] generate block is allowed only inside loop and conditional generate in SystemVerilog mode [/home/nickorlow/vivado/inst_22.01/Vivado/2022.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:4023]
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2607.566 ; gain = 0.000 ; free physical = 158 ; free virtual = 3085
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'top_wrapper' [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/hdl/top_wrapper.v:12]
INFO: [Synth 8-6157] synthesizing module 'top' [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/synth/top.v:144]
INFO: [Synth 8-6157] synthesizing module 'top_axi_bram_ctrl_0_0' [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.runs/synth_1/.Xil/Vivado-417119-media-wawa/realtime/top_axi_bram_ctrl_0_0_stub.v:5]
INFO: [Synth 8-6155] done synthesizing module 'top_axi_bram_ctrl_0_0' (0#1) [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.runs/synth_1/.Xil/Vivado-417119-media-wawa/realtime/top_axi_bram_ctrl_0_0_stub.v:5]
INFO: [Synth 8-6157] synthesizing module 'top_axi_gpio_0_0' [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.runs/synth_1/.Xil/Vivado-417119-media-wawa/realtime/top_axi_gpio_0_0_stub.v:5]
INFO: [Synth 8-6155] done synthesizing module 'top_axi_gpio_0_0' (0#1) [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.runs/synth_1/.Xil/Vivado-417119-media-wawa/realtime/top_axi_gpio_0_0_stub.v:5]
INFO: [Synth 8-6157] synthesizing module 'top_axi_smc_0' [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.runs/synth_1/.Xil/Vivado-417119-media-wawa/realtime/top_axi_smc_0_stub.v:5]
INFO: [Synth 8-6155] done synthesizing module 'top_axi_smc_0' (0#1) [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.runs/synth_1/.Xil/Vivado-417119-media-wawa/realtime/top_axi_smc_0_stub.v:5]
WARNING: [Synth 8-7071] port 'M00_AXI_awqos' of module 'top_axi_smc_0' is unconnected for instance 'axi_smc' [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/synth/top.v:371]
WARNING: [Synth 8-7071] port 'M00_AXI_arqos' of module 'top_axi_smc_0' is unconnected for instance 'axi_smc' [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/synth/top.v:371]
WARNING: [Synth 8-7023] instance 'axi_smc' of module 'top_axi_smc_0' has 72 connections declared, but only 70 given [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/synth/top.v:371]
INFO: [Synth 8-6157] synthesizing module 'top_blk_mem_gen_0_0' [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.runs/synth_1/.Xil/Vivado-417119-media-wawa/realtime/top_blk_mem_gen_0_0_stub.v:5]
INFO: [Synth 8-6155] done synthesizing module 'top_blk_mem_gen_0_0' (0#1) [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.runs/synth_1/.Xil/Vivado-417119-media-wawa/realtime/top_blk_mem_gen_0_0_stub.v:5]
INFO: [Synth 8-6157] synthesizing module 'top_util_ds_buf_0' [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.runs/synth_1/.Xil/Vivado-417119-media-wawa/realtime/top_util_ds_buf_0_stub.v:5]
INFO: [Synth 8-6155] done synthesizing module 'top_util_ds_buf_0' (0#1) [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.runs/synth_1/.Xil/Vivado-417119-media-wawa/realtime/top_util_ds_buf_0_stub.v:5]
WARNING: [Synth 8-7071] port 'IBUF_DS_ODIV2' of module 'top_util_ds_buf_0' is unconnected for instance 'util_ds_buf' [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/synth/top.v:457]
WARNING: [Synth 8-7023] instance 'util_ds_buf' of module 'top_util_ds_buf_0' has 4 connections declared, but only 3 given [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/synth/top.v:457]
INFO: [Synth 8-6157] synthesizing module 'top_util_vector_logic_0_0' [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.runs/synth_1/.Xil/Vivado-417119-media-wawa/realtime/top_util_vector_logic_0_0_stub.v:5]
INFO: [Synth 8-6155] done synthesizing module 'top_util_vector_logic_0_0' (0#1) [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.runs/synth_1/.Xil/Vivado-417119-media-wawa/realtime/top_util_vector_logic_0_0_stub.v:5]
INFO: [Synth 8-6157] synthesizing module 'top_xdma_0_0' [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.runs/synth_1/.Xil/Vivado-417119-media-wawa/realtime/top_xdma_0_0_stub.v:5]
INFO: [Synth 8-6155] done synthesizing module 'top_xdma_0_0' (0#1) [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.runs/synth_1/.Xil/Vivado-417119-media-wawa/realtime/top_xdma_0_0_stub.v:5]
WARNING: [Synth 8-7071] port 'usr_irq_ack' of module 'top_xdma_0_0' is unconnected for instance 'xdma_0' [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/synth/top.v:464]
WARNING: [Synth 8-7071] port 'msi_enable' of module 'top_xdma_0_0' is unconnected for instance 'xdma_0' [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/synth/top.v:464]
WARNING: [Synth 8-7071] port 'msi_vector_width' of module 'top_xdma_0_0' is unconnected for instance 'xdma_0' [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/synth/top.v:464]
WARNING: [Synth 8-7071] port 'm_axil_awprot' of module 'top_xdma_0_0' is unconnected for instance 'xdma_0' [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/synth/top.v:464]
WARNING: [Synth 8-7071] port 'm_axil_arprot' of module 'top_xdma_0_0' is unconnected for instance 'xdma_0' [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/synth/top.v:464]
WARNING: [Synth 8-7023] instance 'xdma_0' of module 'top_xdma_0_0' has 67 connections declared, but only 62 given [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/synth/top.v:464]
INFO: [Synth 8-6157] synthesizing module 'top_xdma_0_axi_periph_0' [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/synth/top.v:570]
INFO: [Synth 8-6157] synthesizing module 's00_couplers_imp_110C0LX' [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/synth/top.v:12]
INFO: [Synth 8-6155] done synthesizing module 's00_couplers_imp_110C0LX' (0#1) [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/synth/top.v:12]
INFO: [Synth 8-6155] done synthesizing module 'top_xdma_0_axi_periph_0' (0#1) [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/synth/top.v:570]
INFO: [Synth 8-6155] done synthesizing module 'top' (0#1) [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/synth/top.v:144]
INFO: [Synth 8-6155] done synthesizing module 'top_wrapper' (0#1) [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/hdl/top_wrapper.v:12]
WARNING: [Synth 8-7129] Port M_ACLK in module s00_couplers_imp_110C0LX is either unconnected or has no load
WARNING: [Synth 8-7129] Port M_ARESETN in module s00_couplers_imp_110C0LX is either unconnected or has no load
WARNING: [Synth 8-7129] Port S_ACLK in module s00_couplers_imp_110C0LX is either unconnected or has no load
WARNING: [Synth 8-7129] Port S_ARESETN in module s00_couplers_imp_110C0LX is either unconnected or has no load
WARNING: [Synth 8-7129] Port ACLK in module top_xdma_0_axi_periph_0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ARESETN in module top_xdma_0_axi_periph_0 is either unconnected or has no load
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2607.566 ; gain = 0.000 ; free physical = 1139 ; free virtual = 4028
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2607.566 ; gain = 0.000 ; free physical = 1139 ; free virtual = 4028
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2607.566 ; gain = 0.000 ; free physical = 1139 ; free virtual = 4028
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2607.566 ; gain = 0.000 ; free physical = 1139 ; free virtual = 4028
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_xdma_0_0/top_xdma_0_0/top_xdma_0_0_in_context.xdc] for cell 'top_i/xdma_0'
Finished Parsing XDC File [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_xdma_0_0/top_xdma_0_0/top_xdma_0_0_in_context.xdc] for cell 'top_i/xdma_0'
Parsing XDC File [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_axi_bram_ctrl_0_0/top_axi_bram_ctrl_0_0/top_axi_bram_ctrl_0_0_in_context.xdc] for cell 'top_i/axi_bram_ctrl_0'
Finished Parsing XDC File [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_axi_bram_ctrl_0_0/top_axi_bram_ctrl_0_0/top_axi_bram_ctrl_0_0_in_context.xdc] for cell 'top_i/axi_bram_ctrl_0'
Parsing XDC File [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_blk_mem_gen_0_0/top_blk_mem_gen_0_0/top_blk_mem_gen_0_0_in_context.xdc] for cell 'top_i/blk_mem_gen_0'
Finished Parsing XDC File [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_blk_mem_gen_0_0/top_blk_mem_gen_0_0/top_blk_mem_gen_0_0_in_context.xdc] for cell 'top_i/blk_mem_gen_0'
Parsing XDC File [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_util_vector_logic_0_0/top_util_vector_logic_0_0/top_util_vector_logic_0_0_in_context.xdc] for cell 'top_i/util_vector_logic_0'
Finished Parsing XDC File [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_util_vector_logic_0_0/top_util_vector_logic_0_0/top_util_vector_logic_0_0_in_context.xdc] for cell 'top_i/util_vector_logic_0'
Parsing XDC File [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_axi_gpio_0_0/top_axi_gpio_0_0/top_axi_gpio_0_0_in_context.xdc] for cell 'top_i/axi_gpio_0'
Finished Parsing XDC File [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_axi_gpio_0_0/top_axi_gpio_0_0/top_axi_gpio_0_0_in_context.xdc] for cell 'top_i/axi_gpio_0'
Parsing XDC File [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_util_ds_buf_0/top_util_ds_buf_0/top_util_ds_buf_0_in_context.xdc] for cell 'top_i/util_ds_buf'
Finished Parsing XDC File [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_util_ds_buf_0/top_util_ds_buf_0/top_util_ds_buf_0_in_context.xdc] for cell 'top_i/util_ds_buf'
Parsing XDC File [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_axi_smc_0/top_axi_smc_0/top_axi_smc_0_in_context.xdc] for cell 'top_i/axi_smc'
Finished Parsing XDC File [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_axi_smc_0/top_axi_smc_0/top_axi_smc_0_in_context.xdc] for cell 'top_i/axi_smc'
Parsing XDC File [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/constrs_1/new/early.xdc]
WARNING: [Vivado 12-584] No ports matched 'pcie_mgt_rxn[0]'. [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/constrs_1/new/early.xdc:5]
WARNING: [Vivado 12-584] No ports matched 'pcie_mgt_rxp[0]'. [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/constrs_1/new/early.xdc:6]
WARNING: [Vivado 12-584] No ports matched 'pcie_mgt_txn[0]'. [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/constrs_1/new/early.xdc:7]
WARNING: [Vivado 12-584] No ports matched 'pcie_mgt_txp[0]'. [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/constrs_1/new/early.xdc:8]
WARNING: [Vivado 12-584] No ports matched 'pcie_mgt_rxn[1]'. [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/constrs_1/new/early.xdc:12]
WARNING: [Vivado 12-584] No ports matched 'pcie_mgt_rxp[1]'. [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/constrs_1/new/early.xdc:13]
WARNING: [Vivado 12-584] No ports matched 'pcie_mgt_txn[1]'. [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/constrs_1/new/early.xdc:14]
WARNING: [Vivado 12-584] No ports matched 'pcie_mgt_txp[1]'. [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/constrs_1/new/early.xdc:15]
WARNING: [Vivado 12-584] No ports matched 'pcie_mgt_rxn[2]'. [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/constrs_1/new/early.xdc:19]
WARNING: [Vivado 12-584] No ports matched 'pcie_mgt_rxp[2]'. [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/constrs_1/new/early.xdc:20]
WARNING: [Vivado 12-584] No ports matched 'pcie_mgt_txn[2]'. [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/constrs_1/new/early.xdc:21]
WARNING: [Vivado 12-584] No ports matched 'pcie_mgt_txp[2]'. [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/constrs_1/new/early.xdc:22]
WARNING: [Vivado 12-584] No ports matched 'pcie_mgt_rxn[3]'. [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/constrs_1/new/early.xdc:26]
WARNING: [Vivado 12-584] No ports matched 'pcie_mgt_rxp[3]'. [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/constrs_1/new/early.xdc:27]
WARNING: [Vivado 12-584] No ports matched 'pcie_mgt_txn[3]'. [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/constrs_1/new/early.xdc:28]
WARNING: [Vivado 12-584] No ports matched 'pcie_mgt_txp[3]'. [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/constrs_1/new/early.xdc:29]
WARNING: [Vivado 12-584] No ports matched 'pcie_clkreq_l'. [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/constrs_1/new/early.xdc:36]
WARNING: [Vivado 12-584] No ports matched 'pcie_clkreq_l'. [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/constrs_1/new/early.xdc:37]
Finished Parsing XDC File [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/constrs_1/new/early.xdc]
WARNING: [Project 1-498] One or more constraints failed evaluation while reading constraint file [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/constrs_1/new/early.xdc] and the design contains unresolved black boxes. These constraints will be read post-synthesis (as long as their source constraint file is marked as used_in_implementation) and should be applied correctly then. You should review the constraints listed in the file [.Xil/top_wrapper_propImpl.xdc] and check the run log file to verify that these constraints were correctly applied.
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/constrs_1/new/early.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_wrapper_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/top_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Parsing XDC File [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/constrs_1/new/normal.xdc]
Finished Parsing XDC File [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/constrs_1/new/normal.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.srcs/constrs_1/new/normal.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_wrapper_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/top_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Parsing XDC File [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.runs/synth_1/dont_touch.xdc]
Finished Parsing XDC File [/home/nickorlow/vivado/hello_world_dma/hello_world_dma.runs/synth_1/dont_touch.xdc]
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2671.598 ; gain = 0.000 ; free physical = 1135 ; free virtual = 4024
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2671.598 ; gain = 0.000 ; free physical = 1135 ; free virtual = 4024
WARNING: [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'top_i/axi_gpio_0' at clock pin 's_axi_aclk' is different from the actual clock period '8.000', this can lead to different synthesis results.
WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'top_i/blk_mem_gen_0' at clock pin 'clka' is different from the actual clock period '8.000', this can lead to different synthesis results.
INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run
INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2671.598 ; gain = 64.031 ; free physical = 1174 ; free virtual = 4063
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Start Loading Part and Timing Information
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Loading part: xc7a100tlfgg484-2L
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Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2671.598 ; gain = 64.031 ; free physical = 1174 ; free virtual = 4063
---------------------------------------------------------------------------------
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Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
Applied set_property IO_BUFFER_TYPE = NONE for diff_clock_rtl_0_clk_n[0]. (constraint file /home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_util_ds_buf_0/top_util_ds_buf_0/top_util_ds_buf_0_in_context.xdc, line 3).
Applied set_property CLOCK_BUFFER_TYPE = NONE for diff_clock_rtl_0_clk_n[0]. (constraint file /home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_util_ds_buf_0/top_util_ds_buf_0/top_util_ds_buf_0_in_context.xdc, line 4).
Applied set_property IO_BUFFER_TYPE = NONE for diff_clock_rtl_0_clk_p[0]. (constraint file /home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_util_ds_buf_0/top_util_ds_buf_0/top_util_ds_buf_0_in_context.xdc, line 5).
Applied set_property CLOCK_BUFFER_TYPE = NONE for diff_clock_rtl_0_clk_p[0]. (constraint file /home/nickorlow/vivado/hello_world_dma/hello_world_dma.gen/sources_1/bd/top/ip/top_util_ds_buf_0/top_util_ds_buf_0/top_util_ds_buf_0_in_context.xdc, line 6).
Applied set_property KEEP_HIERARCHY = SOFT for top_i. (constraint file auto generated constraint).
Applied set_property KEEP_HIERARCHY = SOFT for top_i/xdma_0. (constraint file auto generated constraint).
Applied set_property KEEP_HIERARCHY = SOFT for top_i/axi_bram_ctrl_0. (constraint file auto generated constraint).
Applied set_property KEEP_HIERARCHY = SOFT for top_i/blk_mem_gen_0. (constraint file auto generated constraint).
Applied set_property KEEP_HIERARCHY = SOFT for top_i/util_vector_logic_0. (constraint file auto generated constraint).
Applied set_property KEEP_HIERARCHY = SOFT for top_i/axi_gpio_0. (constraint file auto generated constraint).
Applied set_property KEEP_HIERARCHY = SOFT for top_i/util_ds_buf. (constraint file auto generated constraint).
Applied set_property KEEP_HIERARCHY = SOFT for top_i/axi_smc. (constraint file auto generated constraint).
Applied set_property KEEP_HIERARCHY = SOFT for top_i/xdma_0_axi_periph. (constraint file auto generated constraint).
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2671.598 ; gain = 64.031 ; free physical = 1174 ; free virtual = 4063
---------------------------------------------------------------------------------
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Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2671.598 ; gain = 64.031 ; free physical = 1174 ; free virtual = 4064
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Start RTL Component Statistics
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Detailed RTL Component Info :
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Finished RTL Component Statistics
---------------------------------------------------------------------------------
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Start Part Resource Summary
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Part Resources:
DSPs: 240 (col length:80)
BRAMs: 270 (col length: RAMB18 80 RAMB36 40)
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Finished Part Resource Summary
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Start Cross Boundary and Area Optimization
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WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
WARNING: [Synth 8-7129] Port ACLK in module top_xdma_0_axi_periph_0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ARESETN in module top_xdma_0_axi_periph_0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port M00_ACLK in module top_xdma_0_axi_periph_0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port M00_ARESETN in module top_xdma_0_axi_periph_0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port S00_ACLK in module top_xdma_0_axi_periph_0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port S00_ARESETN in module top_xdma_0_axi_periph_0 is either unconnected or has no load
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:14 ; elapsed = 00:00:16 . Memory (MB): peak = 2671.598 ; gain = 64.031 ; free physical = 1173 ; free virtual = 4067
---------------------------------------------------------------------------------
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Start Applying XDC Timing Constraints
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Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 2671.598 ; gain = 64.031 ; free physical = 1100 ; free virtual = 3994
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Start Timing Optimization
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Finished Timing Optimization : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 2671.598 ; gain = 64.031 ; free physical = 1100 ; free virtual = 3994
---------------------------------------------------------------------------------
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Start Technology Mapping
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Finished Technology Mapping : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 2671.598 ; gain = 64.031 ; free physical = 1076 ; free virtual = 3971
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Start IO Insertion
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Start Flattening Before IO Insertion
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Finished Flattening Before IO Insertion
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Start Final Netlist Cleanup
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Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
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Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2671.598 ; gain = 64.031 ; free physical = 1091 ; free virtual = 3986
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2671.598 ; gain = 64.031 ; free physical = 1091 ; free virtual = 3986
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2671.598 ; gain = 64.031 ; free physical = 1091 ; free virtual = 3986
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2671.598 ; gain = 64.031 ; free physical = 1091 ; free virtual = 3986
---------------------------------------------------------------------------------
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Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2671.598 ; gain = 64.031 ; free physical = 1091 ; free virtual = 3986
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2671.598 ; gain = 64.031 ; free physical = 1091 ; free virtual = 3986
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+------+--------------------------+----------+
| |BlackBox name |Instances |
+------+--------------------------+----------+
|1 |top_axi_bram_ctrl_0_0 | 1|
|2 |top_axi_gpio_0_0 | 1|
|3 |top_axi_smc_0 | 1|
|4 |top_blk_mem_gen_0_0 | 1|
|5 |top_util_ds_buf_0 | 1|
|6 |top_util_vector_logic_0_0 | 1|
|7 |top_xdma_0_0 | 1|
+------+--------------------------+----------+
Report Cell Usage:
+------+------------------------+------+
| |Cell |Count |
+------+------------------------+------+
|1 |top_axi_bram_ctrl_0 | 1|
|2 |top_axi_gpio_0 | 1|
|3 |top_axi_smc | 1|
|4 |top_blk_mem_gen_0 | 1|
|5 |top_util_ds_buf | 1|
|6 |top_util_vector_logic_0 | 1|
|7 |top_xdma_0 | 1|
|8 |IBUF | 9|
|9 |OBUF | 11|
+------+------------------------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2671.598 ; gain = 64.031 ; free physical = 1091 ; free virtual = 3986
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 7 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2671.598 ; gain = 0.000 ; free physical = 1134 ; free virtual = 4028
Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2671.598 ; gain = 64.031 ; free physical = 1134 ; free virtual = 4028
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2671.598 ; gain = 0.000 ; free physical = 1227 ; free virtual = 4122
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2671.598 ; gain = 0.000 ; free physical = 1170 ; free virtual = 4065
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Synth Design complete, checksum: f7656efe
INFO: [Common 17-83] Releasing license: Synthesis
45 Infos, 46 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:30 . Memory (MB): peak = 2671.598 ; gain = 64.031 ; free physical = 1347 ; free virtual = 4242
INFO: [Common 17-1381] The checkpoint '/home/nickorlow/vivado/hello_world_dma/hello_world_dma.runs/synth_1/top_wrapper.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file top_wrapper_utilization_synth.rpt -pb top_wrapper_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Tue Jun 24 13:26:14 2025...

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Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
| Date : Tue Jun 24 13:26:14 2025
| Host : media-wawa running 64-bit NixOS 25.05 (Warbler)
| Command : report_utilization -file top_wrapper_utilization_synth.rpt -pb top_wrapper_utilization_synth.pb
| Design : top_wrapper
| Device : xc7a100tlfgg484-2L
| Speed File : -2L
| Design State : Synthesized
-----------------------------------------------------------------------------------------------------------------
Utilization Design Information
Table of Contents
-----------------
1. Slice Logic
1.1 Summary of Registers by Type
2. Memory
3. DSP
4. IO and GT Specific
5. Clocking
6. Specific Feature
7. Primitives
8. Black Boxes
9. Instantiated Netlists
1. Slice Logic
--------------
+-------------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------------------+------+-------+------------+-----------+-------+
| Slice LUTs* | 0 | 0 | 0 | 63400 | 0.00 |
| LUT as Logic | 0 | 0 | 0 | 63400 | 0.00 |
| LUT as Memory | 0 | 0 | 0 | 19000 | 0.00 |
| Slice Registers | 0 | 0 | 0 | 126800 | 0.00 |
| Register as Flip Flop | 0 | 0 | 0 | 126800 | 0.00 |
| Register as Latch | 0 | 0 | 0 | 126800 | 0.00 |
| F7 Muxes | 0 | 0 | 0 | 31700 | 0.00 |
| F8 Muxes | 0 | 0 | 0 | 15850 | 0.00 |
+-------------------------+------+-------+------------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
1.1 Summary of Registers by Type
--------------------------------
+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0 | _ | - | - |
| 0 | _ | - | Set |
| 0 | _ | - | Reset |
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 0 | Yes | - | Set |
| 0 | Yes | - | Reset |
| 0 | Yes | Set | - |
| 0 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
2. Memory
---------
+----------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------+------+-------+------------+-----------+-------+
| Block RAM Tile | 0 | 0 | 0 | 135 | 0.00 |
| RAMB36/FIFO* | 0 | 0 | 0 | 135 | 0.00 |
| RAMB18 | 0 | 0 | 0 | 270 | 0.00 |
+----------------+------+-------+------------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
3. DSP
------
+-----------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------+------+-------+------------+-----------+-------+
| DSPs | 0 | 0 | 0 | 240 | 0.00 |
+-----------+------+-------+------------+-----------+-------+
4. IO and GT Specific
---------------------
+-----------------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------------------------+------+-------+------------+-----------+-------+
| Bonded IOB | 20 | 0 | 0 | 285 | 7.02 |
| Bonded IPADs | 0 | 0 | 0 | 14 | 0.00 |
| Bonded OPADs | 0 | 0 | 0 | 8 | 0.00 |
| PHY_CONTROL | 0 | 0 | 0 | 6 | 0.00 |
| PHASER_REF | 0 | 0 | 0 | 6 | 0.00 |
| OUT_FIFO | 0 | 0 | 0 | 24 | 0.00 |
| IN_FIFO | 0 | 0 | 0 | 24 | 0.00 |
| IDELAYCTRL | 0 | 0 | 0 | 6 | 0.00 |
| IBUFDS | 0 | 0 | 0 | 274 | 0.00 |
| GTPE2_CHANNEL | 0 | 0 | 0 | 4 | 0.00 |
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 24 | 0.00 |
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 24 | 0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 300 | 0.00 |
| IBUFDS_GTE2 | 0 | 0 | 0 | 2 | 0.00 |
| ILOGIC | 0 | 0 | 0 | 285 | 0.00 |
| OLOGIC | 0 | 0 | 0 | 285 | 0.00 |
+-----------------------------+------+-------+------------+-----------+-------+
5. Clocking
-----------
+------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+------------+------+-------+------------+-----------+-------+
| BUFGCTRL | 0 | 0 | 0 | 32 | 0.00 |
| BUFIO | 0 | 0 | 0 | 24 | 0.00 |
| MMCME2_ADV | 0 | 0 | 0 | 6 | 0.00 |
| PLLE2_ADV | 0 | 0 | 0 | 6 | 0.00 |
| BUFMRCE | 0 | 0 | 0 | 12 | 0.00 |
| BUFHCE | 0 | 0 | 0 | 96 | 0.00 |
| BUFR | 0 | 0 | 0 | 24 | 0.00 |
+------------+------+-------+------------+-----------+-------+
6. Specific Feature
-------------------
+-------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------+------+-------+------------+-----------+-------+
| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 |
| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 |
| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 |
| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 |
| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 |
| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 |
| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 |
| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 |
| XADC | 0 | 0 | 0 | 1 | 0.00 |
+-------------+------+-------+------------+-----------+-------+
7. Primitives
-------------
+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| OBUF | 11 | IO |
| IBUF | 9 | IO |
+----------+------+---------------------+
8. Black Boxes
--------------
+---------------------------+------+
| Ref Name | Used |
+---------------------------+------+
| top_xdma_0_0 | 1 |
| top_util_vector_logic_0_0 | 1 |
| top_util_ds_buf_0 | 1 |
| top_blk_mem_gen_0_0 | 1 |
| top_axi_smc_0 | 1 |
| top_axi_gpio_0_0 | 1 |
| top_axi_bram_ctrl_0_0 | 1 |
+---------------------------+------+
9. Instantiated Netlists
------------------------
+----------+------+
| Ref Name | Used |
+----------+------+

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#-----------------------------------------------------------
# Vivado v2022.1 (64-bit)
# SW Build 3526262 on Mon Apr 18 15:47:01 MDT 2022
# IP Build 3524634 on Mon Apr 18 20:55:01 MDT 2022
# Start of session at: Tue Jun 24 13:25:33 2025
# Process ID: 417119
# Current directory: /home/nickorlow/vivado/hello_world_dma/hello_world_dma.runs/synth_1
# Command line: vivado -log top_wrapper.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source top_wrapper.tcl
# Log file: /home/nickorlow/vivado/hello_world_dma/hello_world_dma.runs/synth_1/top_wrapper.vds
# Journal file: /home/nickorlow/vivado/hello_world_dma/hello_world_dma.runs/synth_1/vivado.jou
# Running On: media-wawa, OS: Linux, CPU Frequency: 2722.617 MHz, CPU Physical cores: 12, Host memory: 16715 MB
#-----------------------------------------------------------
source top_wrapper.tcl -notrace

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