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848 changed files with 3642008 additions and 0 deletions
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<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>ipcache</spirit:library>
|
||||
<spirit:name>8704c60805dd810f</spirit:name>
|
||||
<spirit:version>0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>top_util_ds_buf_0</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="util_ds_buf" spirit:version="2.2"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_IN_D.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.IBUF_DS_ODIV2.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.IBUF_OUT.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BOARD_PARAMETER"> </spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_BUFGCE_DIV">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_BUFG_GT_SYNC">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_BUF_TYPE">IBUFDSGTE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_OBUFDS_GTE5_ADV">"00"</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_REFCLK_ICNTL_TX">"00000"</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SIZE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">top_util_ds_buf_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FREQ_HZ">156250000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">artix7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7a100tl</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fgg484</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2L</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">E</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">8704c60805dd810f</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCL">$Change: 3513466 $</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCRC">ea2a5533</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">167</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">27</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2022.1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
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|
|||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
|
||||
// Date : Tue Jun 24 11:58:34 2025
|
||||
// Host : media-wawa running 64-bit NixOS 25.05 (Warbler)
|
||||
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ top_util_ds_buf_0_sim_netlist.v
|
||||
// Design : top_util_ds_buf_0
|
||||
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
||||
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
// Device : xc7a100tlfgg484-2L
|
||||
// --------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
(* CHECK_LICENSE_TYPE = "top_util_ds_buf_0,util_ds_buf,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "util_ds_buf,Vivado 2022.1" *)
|
||||
(* NotValidForBitStream *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
|
||||
(IBUF_DS_P,
|
||||
IBUF_DS_N,
|
||||
IBUF_OUT,
|
||||
IBUF_DS_ODIV2);
|
||||
(* x_interface_info = "xilinx.com:interface:diff_clock:1.0 CLK_IN_D CLK_P" *) (* x_interface_parameter = "XIL_INTERFACENAME CLK_IN_D, BOARD.ASSOCIATED_PARAM DIFF_CLK_IN_BOARD_INTERFACE, CAN_DEBUG false, FREQ_HZ 100000000" *) input [0:0]IBUF_DS_P;
|
||||
(* x_interface_info = "xilinx.com:interface:diff_clock:1.0 CLK_IN_D CLK_N" *) input [0:0]IBUF_DS_N;
|
||||
(* x_interface_info = "xilinx.com:signal:clock:1.0 IBUF_OUT CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME IBUF_OUT, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN top_util_ds_buf_0_IBUF_OUT, INSERT_VIP 0" *) output [0:0]IBUF_OUT;
|
||||
(* x_interface_info = "xilinx.com:signal:clock:1.0 IBUF_DS_ODIV2 CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME IBUF_DS_ODIV2, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN top_util_ds_buf_0_IBUF_DS_ODIV2, INSERT_VIP 0" *) output [0:0]IBUF_DS_ODIV2;
|
||||
|
||||
(* IBUF_LOW_PWR *) wire [0:0]IBUF_DS_N;
|
||||
wire [0:0]IBUF_DS_ODIV2;
|
||||
(* IBUF_LOW_PWR *) wire [0:0]IBUF_DS_P;
|
||||
wire [0:0]IBUF_OUT;
|
||||
wire [0:0]NLW_U0_BUFGCE_O_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_BUFG_FABRIC_O_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_BUFG_GT_O_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_BUFG_O_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_BUFG_PS_O_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_BUFHCE_O_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_BUFH_O_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_IBUFDS_GTME5_O_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_IBUFDS_GTME5_ODIV2_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_IBUFDS_GTM_O_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_IBUFDS_GTM_ODIV2_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_IOBUF_DS_N_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_IOBUF_DS_P_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_IOBUF_IO_IO_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_IOBUF_IO_O_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_MBUFG_GT_O1_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_MBUFG_GT_O2_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_MBUFG_GT_O3_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_MBUFG_GT_O4_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_MBUFG_PS_O1_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_MBUFG_PS_O2_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_MBUFG_PS_O3_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_MBUFG_PS_O4_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_OBUFDS_GTE3_ADV_O_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_OBUFDS_GTE3_ADV_OB_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_OBUFDS_GTE3_O_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_OBUFDS_GTE3_OB_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_OBUFDS_GTE4_ADV_O_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_OBUFDS_GTE4_ADV_OB_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_OBUFDS_GTE4_O_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_OBUFDS_GTE4_OB_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_OBUFDS_GTE5_ADV_O_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_OBUFDS_GTE5_ADV_OB_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_OBUFDS_GTE5_O_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_OBUFDS_GTE5_OB_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_OBUFDS_GTME5_ADV_O_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_OBUFDS_GTME5_ADV_OB_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_OBUFDS_GTME5_O_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_OBUFDS_GTME5_OB_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_OBUFDS_GTM_ADV_O_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_OBUFDS_GTM_ADV_OB_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_OBUFDS_GTM_O_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_OBUFDS_GTM_OB_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_OBUF_DS_N_UNCONNECTED;
|
||||
wire [0:0]NLW_U0_OBUF_DS_P_UNCONNECTED;
|
||||
|
||||
(* C_BUFGCE_DIV = "1" *)
|
||||
(* C_BUFG_GT_SYNC = "0" *)
|
||||
(* C_BUF_TYPE = "ibufdsgte2" *)
|
||||
(* C_MODE = "PERFORMANCE" *)
|
||||
(* C_OBUFDS_GTE5_ADV = "2'b00" *)
|
||||
(* C_REFCLK_ICNTL_TX = "5'b00000" *)
|
||||
(* C_SIM_DEVICE = "VERSAL_AI_CORE_ES1" *)
|
||||
(* C_SIZE = "1" *)
|
||||
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_util_ds_buf U0
|
||||
(.BUFGCE_CE(1'b0),
|
||||
.BUFGCE_CLR(1'b0),
|
||||
.BUFGCE_I(1'b0),
|
||||
.BUFGCE_O(NLW_U0_BUFGCE_O_UNCONNECTED[0]),
|
||||
.BUFG_FABRIC_I(1'b0),
|
||||
.BUFG_FABRIC_O(NLW_U0_BUFG_FABRIC_O_UNCONNECTED[0]),
|
||||
.BUFG_GT_CE(1'b1),
|
||||
.BUFG_GT_CEMASK(1'b0),
|
||||
.BUFG_GT_CLR(1'b0),
|
||||
.BUFG_GT_CLRMASK(1'b0),
|
||||
.BUFG_GT_DIV({1'b0,1'b0,1'b0}),
|
||||
.BUFG_GT_I(1'b0),
|
||||
.BUFG_GT_O(NLW_U0_BUFG_GT_O_UNCONNECTED[0]),
|
||||
.BUFG_I(1'b0),
|
||||
.BUFG_O(NLW_U0_BUFG_O_UNCONNECTED[0]),
|
||||
.BUFG_PS_I(1'b0),
|
||||
.BUFG_PS_O(NLW_U0_BUFG_PS_O_UNCONNECTED[0]),
|
||||
.BUFHCE_CE(1'b0),
|
||||
.BUFHCE_I(1'b0),
|
||||
.BUFHCE_O(NLW_U0_BUFHCE_O_UNCONNECTED[0]),
|
||||
.BUFH_I(1'b0),
|
||||
.BUFH_O(NLW_U0_BUFH_O_UNCONNECTED[0]),
|
||||
.IBUFDS_GTME5_CEB(1'b0),
|
||||
.IBUFDS_GTME5_I(1'b0),
|
||||
.IBUFDS_GTME5_IB(1'b0),
|
||||
.IBUFDS_GTME5_O(NLW_U0_IBUFDS_GTME5_O_UNCONNECTED[0]),
|
||||
.IBUFDS_GTME5_ODIV2(NLW_U0_IBUFDS_GTME5_ODIV2_UNCONNECTED[0]),
|
||||
.IBUFDS_GTM_CEB(1'b0),
|
||||
.IBUFDS_GTM_I(1'b0),
|
||||
.IBUFDS_GTM_IB(1'b0),
|
||||
.IBUFDS_GTM_O(NLW_U0_IBUFDS_GTM_O_UNCONNECTED[0]),
|
||||
.IBUFDS_GTM_ODIV2(NLW_U0_IBUFDS_GTM_ODIV2_UNCONNECTED[0]),
|
||||
.IBUF_DS_CEB(1'b0),
|
||||
.IBUF_DS_N(IBUF_DS_N),
|
||||
.IBUF_DS_ODIV2(IBUF_DS_ODIV2),
|
||||
.IBUF_DS_P(IBUF_DS_P),
|
||||
.IBUF_OUT(IBUF_OUT),
|
||||
.IOBUF_DS_N(NLW_U0_IOBUF_DS_N_UNCONNECTED[0]),
|
||||
.IOBUF_DS_P(NLW_U0_IOBUF_DS_P_UNCONNECTED[0]),
|
||||
.IOBUF_IO_I(1'b0),
|
||||
.IOBUF_IO_IO(NLW_U0_IOBUF_IO_IO_UNCONNECTED[0]),
|
||||
.IOBUF_IO_O(NLW_U0_IOBUF_IO_O_UNCONNECTED[0]),
|
||||
.IOBUF_IO_T(1'b0),
|
||||
.MBUFG_GT_CE(1'b1),
|
||||
.MBUFG_GT_CEMASK(1'b0),
|
||||
.MBUFG_GT_CLR(1'b0),
|
||||
.MBUFG_GT_CLRB_LEAF(1'b1),
|
||||
.MBUFG_GT_CLRMASK(1'b0),
|
||||
.MBUFG_GT_DIV({1'b0,1'b0,1'b0}),
|
||||
.MBUFG_GT_I(1'b0),
|
||||
.MBUFG_GT_O1(NLW_U0_MBUFG_GT_O1_UNCONNECTED[0]),
|
||||
.MBUFG_GT_O2(NLW_U0_MBUFG_GT_O2_UNCONNECTED[0]),
|
||||
.MBUFG_GT_O3(NLW_U0_MBUFG_GT_O3_UNCONNECTED[0]),
|
||||
.MBUFG_GT_O4(NLW_U0_MBUFG_GT_O4_UNCONNECTED[0]),
|
||||
.MBUFG_PS_CLRB_LEAF(1'b1),
|
||||
.MBUFG_PS_I(1'b0),
|
||||
.MBUFG_PS_O1(NLW_U0_MBUFG_PS_O1_UNCONNECTED[0]),
|
||||
.MBUFG_PS_O2(NLW_U0_MBUFG_PS_O2_UNCONNECTED[0]),
|
||||
.MBUFG_PS_O3(NLW_U0_MBUFG_PS_O3_UNCONNECTED[0]),
|
||||
.MBUFG_PS_O4(NLW_U0_MBUFG_PS_O4_UNCONNECTED[0]),
|
||||
.OBUFDS_GTE3_ADV_CEB(1'b0),
|
||||
.OBUFDS_GTE3_ADV_I({1'b0,1'b0,1'b0,1'b0}),
|
||||
.OBUFDS_GTE3_ADV_O(NLW_U0_OBUFDS_GTE3_ADV_O_UNCONNECTED[0]),
|
||||
.OBUFDS_GTE3_ADV_OB(NLW_U0_OBUFDS_GTE3_ADV_OB_UNCONNECTED[0]),
|
||||
.OBUFDS_GTE3_CEB(1'b0),
|
||||
.OBUFDS_GTE3_I(1'b0),
|
||||
.OBUFDS_GTE3_O(NLW_U0_OBUFDS_GTE3_O_UNCONNECTED[0]),
|
||||
.OBUFDS_GTE3_OB(NLW_U0_OBUFDS_GTE3_OB_UNCONNECTED[0]),
|
||||
.OBUFDS_GTE4_ADV_CEB(1'b0),
|
||||
.OBUFDS_GTE4_ADV_I({1'b0,1'b0,1'b0,1'b0}),
|
||||
.OBUFDS_GTE4_ADV_O(NLW_U0_OBUFDS_GTE4_ADV_O_UNCONNECTED[0]),
|
||||
.OBUFDS_GTE4_ADV_OB(NLW_U0_OBUFDS_GTE4_ADV_OB_UNCONNECTED[0]),
|
||||
.OBUFDS_GTE4_CEB(1'b0),
|
||||
.OBUFDS_GTE4_I(1'b0),
|
||||
.OBUFDS_GTE4_O(NLW_U0_OBUFDS_GTE4_O_UNCONNECTED[0]),
|
||||
.OBUFDS_GTE4_OB(NLW_U0_OBUFDS_GTE4_OB_UNCONNECTED[0]),
|
||||
.OBUFDS_GTE5_ADV_CEB(1'b0),
|
||||
.OBUFDS_GTE5_ADV_I({1'b0,1'b0,1'b0,1'b0}),
|
||||
.OBUFDS_GTE5_ADV_O(NLW_U0_OBUFDS_GTE5_ADV_O_UNCONNECTED[0]),
|
||||
.OBUFDS_GTE5_ADV_OB(NLW_U0_OBUFDS_GTE5_ADV_OB_UNCONNECTED[0]),
|
||||
.OBUFDS_GTE5_ADV_RXRECCLKSEL({1'b0,1'b0}),
|
||||
.OBUFDS_GTE5_CEB(1'b0),
|
||||
.OBUFDS_GTE5_I(1'b0),
|
||||
.OBUFDS_GTE5_O(NLW_U0_OBUFDS_GTE5_O_UNCONNECTED[0]),
|
||||
.OBUFDS_GTE5_OB(NLW_U0_OBUFDS_GTE5_OB_UNCONNECTED[0]),
|
||||
.OBUFDS_GTME5_ADV_CEB(1'b0),
|
||||
.OBUFDS_GTME5_ADV_I({1'b0,1'b0,1'b0,1'b0}),
|
||||
.OBUFDS_GTME5_ADV_O(NLW_U0_OBUFDS_GTME5_ADV_O_UNCONNECTED[0]),
|
||||
.OBUFDS_GTME5_ADV_OB(NLW_U0_OBUFDS_GTME5_ADV_OB_UNCONNECTED[0]),
|
||||
.OBUFDS_GTME5_ADV_RXRECCLKSEL({1'b0,1'b0}),
|
||||
.OBUFDS_GTME5_CEB(1'b0),
|
||||
.OBUFDS_GTME5_I(1'b0),
|
||||
.OBUFDS_GTME5_O(NLW_U0_OBUFDS_GTME5_O_UNCONNECTED[0]),
|
||||
.OBUFDS_GTME5_OB(NLW_U0_OBUFDS_GTME5_OB_UNCONNECTED[0]),
|
||||
.OBUFDS_GTM_ADV_CEB(1'b0),
|
||||
.OBUFDS_GTM_ADV_I({1'b0,1'b0,1'b0,1'b0}),
|
||||
.OBUFDS_GTM_ADV_O(NLW_U0_OBUFDS_GTM_ADV_O_UNCONNECTED[0]),
|
||||
.OBUFDS_GTM_ADV_OB(NLW_U0_OBUFDS_GTM_ADV_OB_UNCONNECTED[0]),
|
||||
.OBUFDS_GTM_CEB(1'b0),
|
||||
.OBUFDS_GTM_I(1'b0),
|
||||
.OBUFDS_GTM_O(NLW_U0_OBUFDS_GTM_O_UNCONNECTED[0]),
|
||||
.OBUFDS_GTM_OB(NLW_U0_OBUFDS_GTM_OB_UNCONNECTED[0]),
|
||||
.OBUF_DS_N(NLW_U0_OBUF_DS_N_UNCONNECTED[0]),
|
||||
.OBUF_DS_P(NLW_U0_OBUF_DS_P_UNCONNECTED[0]),
|
||||
.OBUF_IN(1'b0),
|
||||
.RXRECCLK_SEL_GTE3_ADV({1'b0,1'b0}),
|
||||
.RXRECCLK_SEL_GTE4_ADV({1'b0,1'b0}));
|
||||
endmodule
|
||||
|
||||
(* C_BUFGCE_DIV = "1" *) (* C_BUFG_GT_SYNC = "0" *) (* C_BUF_TYPE = "ibufdsgte2" *)
|
||||
(* C_MODE = "PERFORMANCE" *) (* C_OBUFDS_GTE5_ADV = "2'b00" *) (* C_REFCLK_ICNTL_TX = "5'b00000" *)
|
||||
(* C_SIM_DEVICE = "VERSAL_AI_CORE_ES1" *) (* C_SIZE = "1" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_util_ds_buf
|
||||
(IBUF_DS_P,
|
||||
IBUF_DS_N,
|
||||
IBUF_OUT,
|
||||
IBUF_DS_ODIV2,
|
||||
IBUF_DS_CEB,
|
||||
OBUF_IN,
|
||||
OBUF_DS_P,
|
||||
OBUF_DS_N,
|
||||
IOBUF_DS_P,
|
||||
IOBUF_DS_N,
|
||||
IOBUF_IO_T,
|
||||
IOBUF_IO_I,
|
||||
IOBUF_IO_O,
|
||||
IOBUF_IO_IO,
|
||||
BUFG_I,
|
||||
BUFG_O,
|
||||
BUFGCE_I,
|
||||
BUFGCE_CE,
|
||||
BUFGCE_O,
|
||||
BUFGCE_CLR,
|
||||
BUFH_I,
|
||||
BUFH_O,
|
||||
BUFHCE_I,
|
||||
BUFHCE_CE,
|
||||
BUFHCE_O,
|
||||
BUFG_FABRIC_I,
|
||||
BUFG_FABRIC_O,
|
||||
OBUFDS_GTE5_CEB,
|
||||
OBUFDS_GTE5_I,
|
||||
OBUFDS_GTE5_O,
|
||||
OBUFDS_GTE5_OB,
|
||||
OBUFDS_GTE5_ADV_CEB,
|
||||
OBUFDS_GTE5_ADV_I,
|
||||
OBUFDS_GTE5_ADV_O,
|
||||
OBUFDS_GTE5_ADV_OB,
|
||||
OBUFDS_GTE5_ADV_RXRECCLKSEL,
|
||||
OBUFDS_GTE3_CEB,
|
||||
OBUFDS_GTE3_I,
|
||||
OBUFDS_GTE3_O,
|
||||
OBUFDS_GTE3_OB,
|
||||
OBUFDS_GTE3_ADV_CEB,
|
||||
OBUFDS_GTE3_ADV_I,
|
||||
OBUFDS_GTE3_ADV_O,
|
||||
OBUFDS_GTE3_ADV_OB,
|
||||
RXRECCLK_SEL_GTE3_ADV,
|
||||
OBUFDS_GTE4_CEB,
|
||||
OBUFDS_GTE4_I,
|
||||
OBUFDS_GTE4_O,
|
||||
OBUFDS_GTE4_OB,
|
||||
OBUFDS_GTE4_ADV_CEB,
|
||||
OBUFDS_GTE4_ADV_I,
|
||||
OBUFDS_GTE4_ADV_O,
|
||||
OBUFDS_GTE4_ADV_OB,
|
||||
RXRECCLK_SEL_GTE4_ADV,
|
||||
IBUFDS_GTM_O,
|
||||
IBUFDS_GTM_ODIV2,
|
||||
IBUFDS_GTM_CEB,
|
||||
IBUFDS_GTM_I,
|
||||
IBUFDS_GTM_IB,
|
||||
OBUFDS_GTM_O,
|
||||
OBUFDS_GTM_OB,
|
||||
OBUFDS_GTM_CEB,
|
||||
OBUFDS_GTM_I,
|
||||
OBUFDS_GTM_ADV_CEB,
|
||||
OBUFDS_GTM_ADV_I,
|
||||
OBUFDS_GTM_ADV_O,
|
||||
OBUFDS_GTM_ADV_OB,
|
||||
IBUFDS_GTME5_O,
|
||||
IBUFDS_GTME5_ODIV2,
|
||||
IBUFDS_GTME5_CEB,
|
||||
IBUFDS_GTME5_I,
|
||||
IBUFDS_GTME5_IB,
|
||||
OBUFDS_GTME5_CEB,
|
||||
OBUFDS_GTME5_I,
|
||||
OBUFDS_GTME5_O,
|
||||
OBUFDS_GTME5_OB,
|
||||
OBUFDS_GTME5_ADV_CEB,
|
||||
OBUFDS_GTME5_ADV_I,
|
||||
OBUFDS_GTME5_ADV_O,
|
||||
OBUFDS_GTME5_ADV_OB,
|
||||
OBUFDS_GTME5_ADV_RXRECCLKSEL,
|
||||
BUFG_GT_I,
|
||||
BUFG_GT_CE,
|
||||
BUFG_GT_CEMASK,
|
||||
BUFG_GT_CLR,
|
||||
BUFG_GT_CLRMASK,
|
||||
BUFG_GT_DIV,
|
||||
BUFG_GT_O,
|
||||
BUFG_PS_I,
|
||||
BUFG_PS_O,
|
||||
MBUFG_GT_I,
|
||||
MBUFG_GT_CE,
|
||||
MBUFG_GT_CEMASK,
|
||||
MBUFG_GT_CLR,
|
||||
MBUFG_GT_CLRB_LEAF,
|
||||
MBUFG_GT_CLRMASK,
|
||||
MBUFG_GT_DIV,
|
||||
MBUFG_GT_O1,
|
||||
MBUFG_GT_O2,
|
||||
MBUFG_GT_O3,
|
||||
MBUFG_GT_O4,
|
||||
MBUFG_PS_I,
|
||||
MBUFG_PS_CLRB_LEAF,
|
||||
MBUFG_PS_O1,
|
||||
MBUFG_PS_O2,
|
||||
MBUFG_PS_O3,
|
||||
MBUFG_PS_O4);
|
||||
input [0:0]IBUF_DS_P;
|
||||
input [0:0]IBUF_DS_N;
|
||||
output [0:0]IBUF_OUT;
|
||||
output [0:0]IBUF_DS_ODIV2;
|
||||
input [0:0]IBUF_DS_CEB;
|
||||
input [0:0]OBUF_IN;
|
||||
output [0:0]OBUF_DS_P;
|
||||
output [0:0]OBUF_DS_N;
|
||||
inout [0:0]IOBUF_DS_P;
|
||||
inout [0:0]IOBUF_DS_N;
|
||||
input [0:0]IOBUF_IO_T;
|
||||
input [0:0]IOBUF_IO_I;
|
||||
output [0:0]IOBUF_IO_O;
|
||||
inout [0:0]IOBUF_IO_IO;
|
||||
input [0:0]BUFG_I;
|
||||
output [0:0]BUFG_O;
|
||||
input [0:0]BUFGCE_I;
|
||||
input [0:0]BUFGCE_CE;
|
||||
output [0:0]BUFGCE_O;
|
||||
input [0:0]BUFGCE_CLR;
|
||||
input [0:0]BUFH_I;
|
||||
output [0:0]BUFH_O;
|
||||
input [0:0]BUFHCE_I;
|
||||
input [0:0]BUFHCE_CE;
|
||||
output [0:0]BUFHCE_O;
|
||||
input [0:0]BUFG_FABRIC_I;
|
||||
output [0:0]BUFG_FABRIC_O;
|
||||
input [0:0]OBUFDS_GTE5_CEB;
|
||||
input [0:0]OBUFDS_GTE5_I;
|
||||
output [0:0]OBUFDS_GTE5_O;
|
||||
output [0:0]OBUFDS_GTE5_OB;
|
||||
input [0:0]OBUFDS_GTE5_ADV_CEB;
|
||||
input [3:0]OBUFDS_GTE5_ADV_I;
|
||||
output [0:0]OBUFDS_GTE5_ADV_O;
|
||||
output [0:0]OBUFDS_GTE5_ADV_OB;
|
||||
input [1:0]OBUFDS_GTE5_ADV_RXRECCLKSEL;
|
||||
input [0:0]OBUFDS_GTE3_CEB;
|
||||
input [0:0]OBUFDS_GTE3_I;
|
||||
output [0:0]OBUFDS_GTE3_O;
|
||||
output [0:0]OBUFDS_GTE3_OB;
|
||||
input [0:0]OBUFDS_GTE3_ADV_CEB;
|
||||
input [3:0]OBUFDS_GTE3_ADV_I;
|
||||
output [0:0]OBUFDS_GTE3_ADV_O;
|
||||
output [0:0]OBUFDS_GTE3_ADV_OB;
|
||||
input [1:0]RXRECCLK_SEL_GTE3_ADV;
|
||||
input [0:0]OBUFDS_GTE4_CEB;
|
||||
input [0:0]OBUFDS_GTE4_I;
|
||||
output [0:0]OBUFDS_GTE4_O;
|
||||
output [0:0]OBUFDS_GTE4_OB;
|
||||
input [0:0]OBUFDS_GTE4_ADV_CEB;
|
||||
input [3:0]OBUFDS_GTE4_ADV_I;
|
||||
output [0:0]OBUFDS_GTE4_ADV_O;
|
||||
output [0:0]OBUFDS_GTE4_ADV_OB;
|
||||
input [1:0]RXRECCLK_SEL_GTE4_ADV;
|
||||
output [0:0]IBUFDS_GTM_O;
|
||||
output [0:0]IBUFDS_GTM_ODIV2;
|
||||
input [0:0]IBUFDS_GTM_CEB;
|
||||
input [0:0]IBUFDS_GTM_I;
|
||||
input [0:0]IBUFDS_GTM_IB;
|
||||
output [0:0]OBUFDS_GTM_O;
|
||||
output [0:0]OBUFDS_GTM_OB;
|
||||
input [0:0]OBUFDS_GTM_CEB;
|
||||
input [0:0]OBUFDS_GTM_I;
|
||||
input [0:0]OBUFDS_GTM_ADV_CEB;
|
||||
input [3:0]OBUFDS_GTM_ADV_I;
|
||||
output [0:0]OBUFDS_GTM_ADV_O;
|
||||
output [0:0]OBUFDS_GTM_ADV_OB;
|
||||
output [0:0]IBUFDS_GTME5_O;
|
||||
output [0:0]IBUFDS_GTME5_ODIV2;
|
||||
input [0:0]IBUFDS_GTME5_CEB;
|
||||
input [0:0]IBUFDS_GTME5_I;
|
||||
input [0:0]IBUFDS_GTME5_IB;
|
||||
input [0:0]OBUFDS_GTME5_CEB;
|
||||
input [0:0]OBUFDS_GTME5_I;
|
||||
output [0:0]OBUFDS_GTME5_O;
|
||||
output [0:0]OBUFDS_GTME5_OB;
|
||||
input [0:0]OBUFDS_GTME5_ADV_CEB;
|
||||
input [3:0]OBUFDS_GTME5_ADV_I;
|
||||
output [0:0]OBUFDS_GTME5_ADV_O;
|
||||
output [0:0]OBUFDS_GTME5_ADV_OB;
|
||||
input [1:0]OBUFDS_GTME5_ADV_RXRECCLKSEL;
|
||||
input [0:0]BUFG_GT_I;
|
||||
input [0:0]BUFG_GT_CE;
|
||||
input [0:0]BUFG_GT_CEMASK;
|
||||
input [0:0]BUFG_GT_CLR;
|
||||
input [0:0]BUFG_GT_CLRMASK;
|
||||
input [2:0]BUFG_GT_DIV;
|
||||
output [0:0]BUFG_GT_O;
|
||||
input [0:0]BUFG_PS_I;
|
||||
output [0:0]BUFG_PS_O;
|
||||
input [0:0]MBUFG_GT_I;
|
||||
input [0:0]MBUFG_GT_CE;
|
||||
input [0:0]MBUFG_GT_CEMASK;
|
||||
input [0:0]MBUFG_GT_CLR;
|
||||
input [0:0]MBUFG_GT_CLRB_LEAF;
|
||||
input [0:0]MBUFG_GT_CLRMASK;
|
||||
input [2:0]MBUFG_GT_DIV;
|
||||
output [0:0]MBUFG_GT_O1;
|
||||
output [0:0]MBUFG_GT_O2;
|
||||
output [0:0]MBUFG_GT_O3;
|
||||
output [0:0]MBUFG_GT_O4;
|
||||
input [0:0]MBUFG_PS_I;
|
||||
input [0:0]MBUFG_PS_CLRB_LEAF;
|
||||
output [0:0]MBUFG_PS_O1;
|
||||
output [0:0]MBUFG_PS_O2;
|
||||
output [0:0]MBUFG_PS_O3;
|
||||
output [0:0]MBUFG_PS_O4;
|
||||
|
||||
wire \<const0> ;
|
||||
wire [0:0]IBUF_DS_N;
|
||||
wire [0:0]IBUF_DS_ODIV2;
|
||||
wire [0:0]IBUF_DS_P;
|
||||
wire [0:0]IBUF_OUT;
|
||||
wire \USE_IBUFDS_GTE2.IBUF_OUT_N ;
|
||||
wire \USE_IBUFDS_GTE2.IBUF_OUT_P ;
|
||||
|
||||
assign BUFGCE_O[0] = IOBUF_DS_P[0];
|
||||
assign BUFG_FABRIC_O[0] = IOBUF_DS_P[0];
|
||||
assign BUFG_GT_O[0] = IOBUF_DS_P[0];
|
||||
assign BUFG_O[0] = IOBUF_DS_P[0];
|
||||
assign BUFG_PS_O[0] = IOBUF_DS_P[0];
|
||||
assign BUFHCE_O[0] = IOBUF_DS_P[0];
|
||||
assign BUFH_O[0] = IOBUF_DS_P[0];
|
||||
assign IBUFDS_GTME5_O[0] = IOBUF_DS_P[0];
|
||||
assign IBUFDS_GTME5_ODIV2[0] = IOBUF_DS_P[0];
|
||||
assign IBUFDS_GTM_O[0] = IOBUF_DS_P[0];
|
||||
assign IBUFDS_GTM_ODIV2[0] = IOBUF_DS_P[0];
|
||||
assign IOBUF_IO_O[0] = IOBUF_DS_P[0];
|
||||
assign MBUFG_GT_O1[0] = IOBUF_DS_P[0];
|
||||
assign MBUFG_GT_O2[0] = IOBUF_DS_P[0];
|
||||
assign MBUFG_GT_O3[0] = IOBUF_DS_P[0];
|
||||
assign MBUFG_GT_O4[0] = IOBUF_DS_P[0];
|
||||
assign MBUFG_PS_O1[0] = IOBUF_DS_P[0];
|
||||
assign MBUFG_PS_O2[0] = IOBUF_DS_P[0];
|
||||
assign MBUFG_PS_O3[0] = IOBUF_DS_P[0];
|
||||
assign MBUFG_PS_O4[0] = IOBUF_DS_P[0];
|
||||
assign OBUFDS_GTE3_ADV_O[0] = IOBUF_DS_P[0];
|
||||
assign OBUFDS_GTE3_ADV_OB[0] = IOBUF_DS_P[0];
|
||||
assign OBUFDS_GTE3_O[0] = IOBUF_DS_P[0];
|
||||
assign OBUFDS_GTE3_OB[0] = IOBUF_DS_P[0];
|
||||
assign OBUFDS_GTE4_ADV_O[0] = IOBUF_DS_P[0];
|
||||
assign OBUFDS_GTE4_ADV_OB[0] = IOBUF_DS_P[0];
|
||||
assign OBUFDS_GTE4_O[0] = IOBUF_DS_P[0];
|
||||
assign OBUFDS_GTE4_OB[0] = IOBUF_DS_P[0];
|
||||
assign OBUFDS_GTE5_ADV_O[0] = IOBUF_DS_P[0];
|
||||
assign OBUFDS_GTE5_ADV_OB[0] = IOBUF_DS_P[0];
|
||||
assign OBUFDS_GTE5_O[0] = IOBUF_DS_P[0];
|
||||
assign OBUFDS_GTE5_OB[0] = IOBUF_DS_P[0];
|
||||
assign OBUFDS_GTME5_ADV_O[0] = IOBUF_DS_P[0];
|
||||
assign OBUFDS_GTME5_ADV_OB[0] = IOBUF_DS_P[0];
|
||||
assign OBUFDS_GTME5_O[0] = IOBUF_DS_P[0];
|
||||
assign OBUFDS_GTME5_OB[0] = IOBUF_DS_P[0];
|
||||
assign OBUFDS_GTM_ADV_O[0] = IOBUF_DS_P[0];
|
||||
assign OBUFDS_GTM_ADV_OB[0] = IOBUF_DS_P[0];
|
||||
assign OBUFDS_GTM_O[0] = IOBUF_DS_P[0];
|
||||
assign OBUFDS_GTM_OB[0] = IOBUF_DS_P[0];
|
||||
assign OBUF_DS_N[0] = IOBUF_DS_P[0];
|
||||
assign OBUF_DS_P[0] = IOBUF_DS_P[0];
|
||||
xVIA IOBUF_DS_N_0via (IOBUF_DS_N[0], IOBUF_DS_P[0]);
|
||||
GND GND
|
||||
(.G(IOBUF_DS_P[0]));
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
IBUFDS_GTE2 #(
|
||||
.CLKCM_CFG("TRUE"),
|
||||
.CLKRCV_TRST("TRUE"),
|
||||
.CLKSWING_CFG(2'b11))
|
||||
\USE_IBUFDS_GTE2.GEN_IBUFDS_GTE2[0].IBUFDS_GTE2_I
|
||||
(.CEB(IOBUF_DS_P[0]),
|
||||
.I(\USE_IBUFDS_GTE2.IBUF_OUT_P ),
|
||||
.IB(\USE_IBUFDS_GTE2.IBUF_OUT_N ),
|
||||
.O(IBUF_OUT),
|
||||
.ODIV2(IBUF_DS_ODIV2));
|
||||
(* CAPACITANCE = "DONT_CARE" *)
|
||||
(* IBUF_DELAY_VALUE = "0" *)
|
||||
(* IFD_DELAY_VALUE = "AUTO" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
IBUF #(
|
||||
.IOSTANDARD("DEFAULT"))
|
||||
\USE_IBUFDS_GTE2.GEN_IBUFDS_GTE2[0].IBUF_N_I
|
||||
(.I(IBUF_DS_N),
|
||||
.O(\USE_IBUFDS_GTE2.IBUF_OUT_N ));
|
||||
(* CAPACITANCE = "DONT_CARE" *)
|
||||
(* IBUF_DELAY_VALUE = "0" *)
|
||||
(* IFD_DELAY_VALUE = "AUTO" *)
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
IBUF #(
|
||||
.IOSTANDARD("DEFAULT"))
|
||||
\USE_IBUFDS_GTE2.GEN_IBUFDS_GTE2[0].IBUF_P_I
|
||||
(.I(IBUF_DS_P),
|
||||
.O(\USE_IBUFDS_GTE2.IBUF_OUT_P ));
|
||||
endmodule
|
||||
module xVIA(.a(w),.b(w));
|
||||
inout w;
|
||||
endmodule
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
parameter GRES_WIDTH = 10000;
|
||||
parameter GRES_START = 10000;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
wire GRESTORE;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
reg GRESTORE_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
assign (strong1, weak0) GRESTORE = GRESTORE_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GRESTORE_int = 1'b0;
|
||||
#(GRES_START);
|
||||
GRESTORE_int = 1'b1;
|
||||
#(GRES_WIDTH);
|
||||
GRESTORE_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
|
|
@ -0,0 +1,444 @@
|
|||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
|
||||
-- Date : Tue Jun 24 11:58:34 2025
|
||||
-- Host : media-wawa running 64-bit NixOS 25.05 (Warbler)
|
||||
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ top_util_ds_buf_0_sim_netlist.vhdl
|
||||
-- Design : top_util_ds_buf_0
|
||||
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
|
||||
-- synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
-- Device : xc7a100tlfgg484-2L
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_util_ds_buf is
|
||||
port (
|
||||
IBUF_DS_P : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
IBUF_DS_N : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
IBUF_OUT : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
IBUF_DS_ODIV2 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
IBUF_DS_CEB : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUF_IN : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUF_DS_P : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUF_DS_N : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
IOBUF_DS_P : inout STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
IOBUF_DS_N : inout STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
IOBUF_IO_T : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
IOBUF_IO_I : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
IOBUF_IO_O : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
IOBUF_IO_IO : inout STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
BUFG_I : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
BUFG_O : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
BUFGCE_I : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
BUFGCE_CE : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
BUFGCE_O : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
BUFGCE_CLR : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
BUFH_I : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
BUFH_O : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
BUFHCE_I : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
BUFHCE_CE : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
BUFHCE_O : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
BUFG_FABRIC_I : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
BUFG_FABRIC_O : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTE5_CEB : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTE5_I : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTE5_O : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTE5_OB : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTE5_ADV_CEB : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTE5_ADV_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
OBUFDS_GTE5_ADV_O : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTE5_ADV_OB : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTE5_ADV_RXRECCLKSEL : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
OBUFDS_GTE3_CEB : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTE3_I : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTE3_O : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTE3_OB : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTE3_ADV_CEB : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTE3_ADV_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
OBUFDS_GTE3_ADV_O : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTE3_ADV_OB : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
RXRECCLK_SEL_GTE3_ADV : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
OBUFDS_GTE4_CEB : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTE4_I : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTE4_O : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTE4_OB : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTE4_ADV_CEB : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTE4_ADV_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
OBUFDS_GTE4_ADV_O : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTE4_ADV_OB : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
RXRECCLK_SEL_GTE4_ADV : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
IBUFDS_GTM_O : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
IBUFDS_GTM_ODIV2 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
IBUFDS_GTM_CEB : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
IBUFDS_GTM_I : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
IBUFDS_GTM_IB : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTM_O : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTM_OB : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTM_CEB : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTM_I : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTM_ADV_CEB : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTM_ADV_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
OBUFDS_GTM_ADV_O : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTM_ADV_OB : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
IBUFDS_GTME5_O : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
IBUFDS_GTME5_ODIV2 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
IBUFDS_GTME5_CEB : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
IBUFDS_GTME5_I : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
IBUFDS_GTME5_IB : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTME5_CEB : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTME5_I : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTME5_O : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTME5_OB : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTME5_ADV_CEB : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTME5_ADV_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
OBUFDS_GTME5_ADV_O : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTME5_ADV_OB : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
OBUFDS_GTME5_ADV_RXRECCLKSEL : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
BUFG_GT_I : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
BUFG_GT_CE : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
BUFG_GT_CEMASK : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
BUFG_GT_CLR : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
BUFG_GT_CLRMASK : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
BUFG_GT_DIV : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
BUFG_GT_O : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
BUFG_PS_I : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
BUFG_PS_O : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
MBUFG_GT_I : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
MBUFG_GT_CE : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
MBUFG_GT_CEMASK : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
MBUFG_GT_CLR : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
MBUFG_GT_CLRB_LEAF : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
MBUFG_GT_CLRMASK : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
MBUFG_GT_DIV : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
MBUFG_GT_O1 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
MBUFG_GT_O2 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
MBUFG_GT_O3 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
MBUFG_GT_O4 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
MBUFG_PS_I : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
MBUFG_PS_CLRB_LEAF : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
MBUFG_PS_O1 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
MBUFG_PS_O2 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
MBUFG_PS_O3 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
MBUFG_PS_O4 : out STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
);
|
||||
attribute C_BUFGCE_DIV : integer;
|
||||
attribute C_BUFGCE_DIV of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_util_ds_buf : entity is 1;
|
||||
attribute C_BUFG_GT_SYNC : integer;
|
||||
attribute C_BUFG_GT_SYNC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_util_ds_buf : entity is 0;
|
||||
attribute C_BUF_TYPE : string;
|
||||
attribute C_BUF_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_util_ds_buf : entity is "ibufdsgte2";
|
||||
attribute C_MODE : string;
|
||||
attribute C_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_util_ds_buf : entity is "PERFORMANCE";
|
||||
attribute C_OBUFDS_GTE5_ADV : string;
|
||||
attribute C_OBUFDS_GTE5_ADV of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_util_ds_buf : entity is "2'b00";
|
||||
attribute C_REFCLK_ICNTL_TX : string;
|
||||
attribute C_REFCLK_ICNTL_TX of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_util_ds_buf : entity is "5'b00000";
|
||||
attribute C_SIM_DEVICE : string;
|
||||
attribute C_SIM_DEVICE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_util_ds_buf : entity is "VERSAL_AI_CORE_ES1";
|
||||
attribute C_SIZE : integer;
|
||||
attribute C_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_util_ds_buf : entity is 1;
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_util_ds_buf;
|
||||
|
||||
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_util_ds_buf is
|
||||
signal \<const0>\ : STD_LOGIC;
|
||||
signal \USE_IBUFDS_GTE2.IBUF_OUT_N\ : STD_LOGIC;
|
||||
signal \USE_IBUFDS_GTE2.IBUF_OUT_P\ : STD_LOGIC;
|
||||
attribute box_type : string;
|
||||
attribute box_type of \USE_IBUFDS_GTE2.GEN_IBUFDS_GTE2[0].IBUFDS_GTE2_I\ : label is "PRIMITIVE";
|
||||
attribute CAPACITANCE : string;
|
||||
attribute CAPACITANCE of \USE_IBUFDS_GTE2.GEN_IBUFDS_GTE2[0].IBUF_N_I\ : label is "DONT_CARE";
|
||||
attribute IBUF_DELAY_VALUE : string;
|
||||
attribute IBUF_DELAY_VALUE of \USE_IBUFDS_GTE2.GEN_IBUFDS_GTE2[0].IBUF_N_I\ : label is "0";
|
||||
attribute IFD_DELAY_VALUE : string;
|
||||
attribute IFD_DELAY_VALUE of \USE_IBUFDS_GTE2.GEN_IBUFDS_GTE2[0].IBUF_N_I\ : label is "AUTO";
|
||||
attribute box_type of \USE_IBUFDS_GTE2.GEN_IBUFDS_GTE2[0].IBUF_N_I\ : label is "PRIMITIVE";
|
||||
attribute CAPACITANCE of \USE_IBUFDS_GTE2.GEN_IBUFDS_GTE2[0].IBUF_P_I\ : label is "DONT_CARE";
|
||||
attribute IBUF_DELAY_VALUE of \USE_IBUFDS_GTE2.GEN_IBUFDS_GTE2[0].IBUF_P_I\ : label is "0";
|
||||
attribute IFD_DELAY_VALUE of \USE_IBUFDS_GTE2.GEN_IBUFDS_GTE2[0].IBUF_P_I\ : label is "AUTO";
|
||||
attribute box_type of \USE_IBUFDS_GTE2.GEN_IBUFDS_GTE2[0].IBUF_P_I\ : label is "PRIMITIVE";
|
||||
begin
|
||||
BUFGCE_O(0) <= \<const0>\;
|
||||
BUFG_FABRIC_O(0) <= \<const0>\;
|
||||
BUFG_GT_O(0) <= \<const0>\;
|
||||
BUFG_O(0) <= \<const0>\;
|
||||
BUFG_PS_O(0) <= \<const0>\;
|
||||
BUFHCE_O(0) <= \<const0>\;
|
||||
BUFH_O(0) <= \<const0>\;
|
||||
IBUFDS_GTME5_O(0) <= \<const0>\;
|
||||
IBUFDS_GTME5_ODIV2(0) <= \<const0>\;
|
||||
IBUFDS_GTM_O(0) <= \<const0>\;
|
||||
IBUFDS_GTM_ODIV2(0) <= \<const0>\;
|
||||
IOBUF_DS_N(0) <= \<const0>\;
|
||||
IOBUF_DS_P(0) <= \<const0>\;
|
||||
IOBUF_IO_O(0) <= \<const0>\;
|
||||
MBUFG_GT_O1(0) <= \<const0>\;
|
||||
MBUFG_GT_O2(0) <= \<const0>\;
|
||||
MBUFG_GT_O3(0) <= \<const0>\;
|
||||
MBUFG_GT_O4(0) <= \<const0>\;
|
||||
MBUFG_PS_O1(0) <= \<const0>\;
|
||||
MBUFG_PS_O2(0) <= \<const0>\;
|
||||
MBUFG_PS_O3(0) <= \<const0>\;
|
||||
MBUFG_PS_O4(0) <= \<const0>\;
|
||||
OBUFDS_GTE3_ADV_O(0) <= \<const0>\;
|
||||
OBUFDS_GTE3_ADV_OB(0) <= \<const0>\;
|
||||
OBUFDS_GTE3_O(0) <= \<const0>\;
|
||||
OBUFDS_GTE3_OB(0) <= \<const0>\;
|
||||
OBUFDS_GTE4_ADV_O(0) <= \<const0>\;
|
||||
OBUFDS_GTE4_ADV_OB(0) <= \<const0>\;
|
||||
OBUFDS_GTE4_O(0) <= \<const0>\;
|
||||
OBUFDS_GTE4_OB(0) <= \<const0>\;
|
||||
OBUFDS_GTE5_ADV_O(0) <= \<const0>\;
|
||||
OBUFDS_GTE5_ADV_OB(0) <= \<const0>\;
|
||||
OBUFDS_GTE5_O(0) <= \<const0>\;
|
||||
OBUFDS_GTE5_OB(0) <= \<const0>\;
|
||||
OBUFDS_GTME5_ADV_O(0) <= \<const0>\;
|
||||
OBUFDS_GTME5_ADV_OB(0) <= \<const0>\;
|
||||
OBUFDS_GTME5_O(0) <= \<const0>\;
|
||||
OBUFDS_GTME5_OB(0) <= \<const0>\;
|
||||
OBUFDS_GTM_ADV_O(0) <= \<const0>\;
|
||||
OBUFDS_GTM_ADV_OB(0) <= \<const0>\;
|
||||
OBUFDS_GTM_O(0) <= \<const0>\;
|
||||
OBUFDS_GTM_OB(0) <= \<const0>\;
|
||||
OBUF_DS_N(0) <= \<const0>\;
|
||||
OBUF_DS_P(0) <= \<const0>\;
|
||||
GND: unisim.vcomponents.GND
|
||||
port map (
|
||||
G => \<const0>\
|
||||
);
|
||||
\USE_IBUFDS_GTE2.GEN_IBUFDS_GTE2[0].IBUFDS_GTE2_I\: unisim.vcomponents.IBUFDS_GTE2
|
||||
generic map(
|
||||
CLKCM_CFG => true,
|
||||
CLKRCV_TRST => true,
|
||||
CLKSWING_CFG => B"11"
|
||||
)
|
||||
port map (
|
||||
CEB => \<const0>\,
|
||||
I => \USE_IBUFDS_GTE2.IBUF_OUT_P\,
|
||||
IB => \USE_IBUFDS_GTE2.IBUF_OUT_N\,
|
||||
O => IBUF_OUT(0),
|
||||
ODIV2 => IBUF_DS_ODIV2(0)
|
||||
);
|
||||
\USE_IBUFDS_GTE2.GEN_IBUFDS_GTE2[0].IBUF_N_I\: unisim.vcomponents.IBUF
|
||||
generic map(
|
||||
IOSTANDARD => "DEFAULT"
|
||||
)
|
||||
port map (
|
||||
I => IBUF_DS_N(0),
|
||||
O => \USE_IBUFDS_GTE2.IBUF_OUT_N\
|
||||
);
|
||||
\USE_IBUFDS_GTE2.GEN_IBUFDS_GTE2[0].IBUF_P_I\: unisim.vcomponents.IBUF
|
||||
generic map(
|
||||
IOSTANDARD => "DEFAULT"
|
||||
)
|
||||
port map (
|
||||
I => IBUF_DS_P(0),
|
||||
O => \USE_IBUFDS_GTE2.IBUF_OUT_P\
|
||||
);
|
||||
end STRUCTURE;
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
port (
|
||||
IBUF_DS_P : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
IBUF_DS_N : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
IBUF_OUT : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
IBUF_DS_ODIV2 : out STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
);
|
||||
attribute NotValidForBitStream : boolean;
|
||||
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
|
||||
attribute CHECK_LICENSE_TYPE : string;
|
||||
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "top_util_ds_buf_0,util_ds_buf,{}";
|
||||
attribute downgradeipidentifiedwarnings : string;
|
||||
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "util_ds_buf,Vivado 2022.1";
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
signal NLW_U0_BUFGCE_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_BUFG_FABRIC_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_BUFG_GT_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_BUFG_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_BUFG_PS_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_BUFHCE_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_BUFH_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_IBUFDS_GTME5_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_IBUFDS_GTME5_ODIV2_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_IBUFDS_GTM_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_IBUFDS_GTM_ODIV2_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_IOBUF_DS_N_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_IOBUF_DS_P_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_IOBUF_IO_IO_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_IOBUF_IO_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_MBUFG_GT_O1_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_MBUFG_GT_O2_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_MBUFG_GT_O3_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_MBUFG_GT_O4_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_MBUFG_PS_O1_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_MBUFG_PS_O2_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_MBUFG_PS_O3_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_MBUFG_PS_O4_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_OBUFDS_GTE3_ADV_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_OBUFDS_GTE3_ADV_OB_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_OBUFDS_GTE3_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_OBUFDS_GTE3_OB_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_OBUFDS_GTE4_ADV_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_OBUFDS_GTE4_ADV_OB_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_OBUFDS_GTE4_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_OBUFDS_GTE4_OB_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_OBUFDS_GTE5_ADV_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_OBUFDS_GTE5_ADV_OB_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_OBUFDS_GTE5_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_OBUFDS_GTE5_OB_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_OBUFDS_GTME5_ADV_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_OBUFDS_GTME5_ADV_OB_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_OBUFDS_GTME5_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_OBUFDS_GTME5_OB_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_OBUFDS_GTM_ADV_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_OBUFDS_GTM_ADV_OB_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_OBUFDS_GTM_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_OBUFDS_GTM_OB_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_OBUF_DS_N_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
signal NLW_U0_OBUF_DS_P_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
attribute C_BUFGCE_DIV : integer;
|
||||
attribute C_BUFGCE_DIV of U0 : label is 1;
|
||||
attribute C_BUFG_GT_SYNC : integer;
|
||||
attribute C_BUFG_GT_SYNC of U0 : label is 0;
|
||||
attribute C_BUF_TYPE : string;
|
||||
attribute C_BUF_TYPE of U0 : label is "ibufdsgte2";
|
||||
attribute C_MODE : string;
|
||||
attribute C_MODE of U0 : label is "PERFORMANCE";
|
||||
attribute C_OBUFDS_GTE5_ADV : string;
|
||||
attribute C_OBUFDS_GTE5_ADV of U0 : label is "2'b00";
|
||||
attribute C_REFCLK_ICNTL_TX : string;
|
||||
attribute C_REFCLK_ICNTL_TX of U0 : label is "5'b00000";
|
||||
attribute C_SIM_DEVICE : string;
|
||||
attribute C_SIM_DEVICE of U0 : label is "VERSAL_AI_CORE_ES1";
|
||||
attribute C_SIZE : integer;
|
||||
attribute C_SIZE of U0 : label is 1;
|
||||
attribute x_interface_info : string;
|
||||
attribute x_interface_info of IBUF_DS_N : signal is "xilinx.com:interface:diff_clock:1.0 CLK_IN_D CLK_N";
|
||||
attribute x_interface_info of IBUF_DS_ODIV2 : signal is "xilinx.com:signal:clock:1.0 IBUF_DS_ODIV2 CLK";
|
||||
attribute x_interface_parameter : string;
|
||||
attribute x_interface_parameter of IBUF_DS_ODIV2 : signal is "XIL_INTERFACENAME IBUF_DS_ODIV2, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN top_util_ds_buf_0_IBUF_DS_ODIV2, INSERT_VIP 0";
|
||||
attribute x_interface_info of IBUF_DS_P : signal is "xilinx.com:interface:diff_clock:1.0 CLK_IN_D CLK_P";
|
||||
attribute x_interface_parameter of IBUF_DS_P : signal is "XIL_INTERFACENAME CLK_IN_D, BOARD.ASSOCIATED_PARAM DIFF_CLK_IN_BOARD_INTERFACE, CAN_DEBUG false, FREQ_HZ 100000000";
|
||||
attribute x_interface_info of IBUF_OUT : signal is "xilinx.com:signal:clock:1.0 IBUF_OUT CLK";
|
||||
attribute x_interface_parameter of IBUF_OUT : signal is "XIL_INTERFACENAME IBUF_OUT, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN top_util_ds_buf_0_IBUF_OUT, INSERT_VIP 0";
|
||||
begin
|
||||
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_util_ds_buf
|
||||
port map (
|
||||
BUFGCE_CE(0) => '0',
|
||||
BUFGCE_CLR(0) => '0',
|
||||
BUFGCE_I(0) => '0',
|
||||
BUFGCE_O(0) => NLW_U0_BUFGCE_O_UNCONNECTED(0),
|
||||
BUFG_FABRIC_I(0) => '0',
|
||||
BUFG_FABRIC_O(0) => NLW_U0_BUFG_FABRIC_O_UNCONNECTED(0),
|
||||
BUFG_GT_CE(0) => '1',
|
||||
BUFG_GT_CEMASK(0) => '0',
|
||||
BUFG_GT_CLR(0) => '0',
|
||||
BUFG_GT_CLRMASK(0) => '0',
|
||||
BUFG_GT_DIV(2 downto 0) => B"000",
|
||||
BUFG_GT_I(0) => '0',
|
||||
BUFG_GT_O(0) => NLW_U0_BUFG_GT_O_UNCONNECTED(0),
|
||||
BUFG_I(0) => '0',
|
||||
BUFG_O(0) => NLW_U0_BUFG_O_UNCONNECTED(0),
|
||||
BUFG_PS_I(0) => '0',
|
||||
BUFG_PS_O(0) => NLW_U0_BUFG_PS_O_UNCONNECTED(0),
|
||||
BUFHCE_CE(0) => '0',
|
||||
BUFHCE_I(0) => '0',
|
||||
BUFHCE_O(0) => NLW_U0_BUFHCE_O_UNCONNECTED(0),
|
||||
BUFH_I(0) => '0',
|
||||
BUFH_O(0) => NLW_U0_BUFH_O_UNCONNECTED(0),
|
||||
IBUFDS_GTME5_CEB(0) => '0',
|
||||
IBUFDS_GTME5_I(0) => '0',
|
||||
IBUFDS_GTME5_IB(0) => '0',
|
||||
IBUFDS_GTME5_O(0) => NLW_U0_IBUFDS_GTME5_O_UNCONNECTED(0),
|
||||
IBUFDS_GTME5_ODIV2(0) => NLW_U0_IBUFDS_GTME5_ODIV2_UNCONNECTED(0),
|
||||
IBUFDS_GTM_CEB(0) => '0',
|
||||
IBUFDS_GTM_I(0) => '0',
|
||||
IBUFDS_GTM_IB(0) => '0',
|
||||
IBUFDS_GTM_O(0) => NLW_U0_IBUFDS_GTM_O_UNCONNECTED(0),
|
||||
IBUFDS_GTM_ODIV2(0) => NLW_U0_IBUFDS_GTM_ODIV2_UNCONNECTED(0),
|
||||
IBUF_DS_CEB(0) => '0',
|
||||
IBUF_DS_N(0) => IBUF_DS_N(0),
|
||||
IBUF_DS_ODIV2(0) => IBUF_DS_ODIV2(0),
|
||||
IBUF_DS_P(0) => IBUF_DS_P(0),
|
||||
IBUF_OUT(0) => IBUF_OUT(0),
|
||||
IOBUF_DS_N(0) => NLW_U0_IOBUF_DS_N_UNCONNECTED(0),
|
||||
IOBUF_DS_P(0) => NLW_U0_IOBUF_DS_P_UNCONNECTED(0),
|
||||
IOBUF_IO_I(0) => '0',
|
||||
IOBUF_IO_IO(0) => NLW_U0_IOBUF_IO_IO_UNCONNECTED(0),
|
||||
IOBUF_IO_O(0) => NLW_U0_IOBUF_IO_O_UNCONNECTED(0),
|
||||
IOBUF_IO_T(0) => '0',
|
||||
MBUFG_GT_CE(0) => '1',
|
||||
MBUFG_GT_CEMASK(0) => '0',
|
||||
MBUFG_GT_CLR(0) => '0',
|
||||
MBUFG_GT_CLRB_LEAF(0) => '1',
|
||||
MBUFG_GT_CLRMASK(0) => '0',
|
||||
MBUFG_GT_DIV(2 downto 0) => B"000",
|
||||
MBUFG_GT_I(0) => '0',
|
||||
MBUFG_GT_O1(0) => NLW_U0_MBUFG_GT_O1_UNCONNECTED(0),
|
||||
MBUFG_GT_O2(0) => NLW_U0_MBUFG_GT_O2_UNCONNECTED(0),
|
||||
MBUFG_GT_O3(0) => NLW_U0_MBUFG_GT_O3_UNCONNECTED(0),
|
||||
MBUFG_GT_O4(0) => NLW_U0_MBUFG_GT_O4_UNCONNECTED(0),
|
||||
MBUFG_PS_CLRB_LEAF(0) => '1',
|
||||
MBUFG_PS_I(0) => '0',
|
||||
MBUFG_PS_O1(0) => NLW_U0_MBUFG_PS_O1_UNCONNECTED(0),
|
||||
MBUFG_PS_O2(0) => NLW_U0_MBUFG_PS_O2_UNCONNECTED(0),
|
||||
MBUFG_PS_O3(0) => NLW_U0_MBUFG_PS_O3_UNCONNECTED(0),
|
||||
MBUFG_PS_O4(0) => NLW_U0_MBUFG_PS_O4_UNCONNECTED(0),
|
||||
OBUFDS_GTE3_ADV_CEB(0) => '0',
|
||||
OBUFDS_GTE3_ADV_I(3 downto 0) => B"0000",
|
||||
OBUFDS_GTE3_ADV_O(0) => NLW_U0_OBUFDS_GTE3_ADV_O_UNCONNECTED(0),
|
||||
OBUFDS_GTE3_ADV_OB(0) => NLW_U0_OBUFDS_GTE3_ADV_OB_UNCONNECTED(0),
|
||||
OBUFDS_GTE3_CEB(0) => '0',
|
||||
OBUFDS_GTE3_I(0) => '0',
|
||||
OBUFDS_GTE3_O(0) => NLW_U0_OBUFDS_GTE3_O_UNCONNECTED(0),
|
||||
OBUFDS_GTE3_OB(0) => NLW_U0_OBUFDS_GTE3_OB_UNCONNECTED(0),
|
||||
OBUFDS_GTE4_ADV_CEB(0) => '0',
|
||||
OBUFDS_GTE4_ADV_I(3 downto 0) => B"0000",
|
||||
OBUFDS_GTE4_ADV_O(0) => NLW_U0_OBUFDS_GTE4_ADV_O_UNCONNECTED(0),
|
||||
OBUFDS_GTE4_ADV_OB(0) => NLW_U0_OBUFDS_GTE4_ADV_OB_UNCONNECTED(0),
|
||||
OBUFDS_GTE4_CEB(0) => '0',
|
||||
OBUFDS_GTE4_I(0) => '0',
|
||||
OBUFDS_GTE4_O(0) => NLW_U0_OBUFDS_GTE4_O_UNCONNECTED(0),
|
||||
OBUFDS_GTE4_OB(0) => NLW_U0_OBUFDS_GTE4_OB_UNCONNECTED(0),
|
||||
OBUFDS_GTE5_ADV_CEB(0) => '0',
|
||||
OBUFDS_GTE5_ADV_I(3 downto 0) => B"0000",
|
||||
OBUFDS_GTE5_ADV_O(0) => NLW_U0_OBUFDS_GTE5_ADV_O_UNCONNECTED(0),
|
||||
OBUFDS_GTE5_ADV_OB(0) => NLW_U0_OBUFDS_GTE5_ADV_OB_UNCONNECTED(0),
|
||||
OBUFDS_GTE5_ADV_RXRECCLKSEL(1 downto 0) => B"00",
|
||||
OBUFDS_GTE5_CEB(0) => '0',
|
||||
OBUFDS_GTE5_I(0) => '0',
|
||||
OBUFDS_GTE5_O(0) => NLW_U0_OBUFDS_GTE5_O_UNCONNECTED(0),
|
||||
OBUFDS_GTE5_OB(0) => NLW_U0_OBUFDS_GTE5_OB_UNCONNECTED(0),
|
||||
OBUFDS_GTME5_ADV_CEB(0) => '0',
|
||||
OBUFDS_GTME5_ADV_I(3 downto 0) => B"0000",
|
||||
OBUFDS_GTME5_ADV_O(0) => NLW_U0_OBUFDS_GTME5_ADV_O_UNCONNECTED(0),
|
||||
OBUFDS_GTME5_ADV_OB(0) => NLW_U0_OBUFDS_GTME5_ADV_OB_UNCONNECTED(0),
|
||||
OBUFDS_GTME5_ADV_RXRECCLKSEL(1 downto 0) => B"00",
|
||||
OBUFDS_GTME5_CEB(0) => '0',
|
||||
OBUFDS_GTME5_I(0) => '0',
|
||||
OBUFDS_GTME5_O(0) => NLW_U0_OBUFDS_GTME5_O_UNCONNECTED(0),
|
||||
OBUFDS_GTME5_OB(0) => NLW_U0_OBUFDS_GTME5_OB_UNCONNECTED(0),
|
||||
OBUFDS_GTM_ADV_CEB(0) => '0',
|
||||
OBUFDS_GTM_ADV_I(3 downto 0) => B"0000",
|
||||
OBUFDS_GTM_ADV_O(0) => NLW_U0_OBUFDS_GTM_ADV_O_UNCONNECTED(0),
|
||||
OBUFDS_GTM_ADV_OB(0) => NLW_U0_OBUFDS_GTM_ADV_OB_UNCONNECTED(0),
|
||||
OBUFDS_GTM_CEB(0) => '0',
|
||||
OBUFDS_GTM_I(0) => '0',
|
||||
OBUFDS_GTM_O(0) => NLW_U0_OBUFDS_GTM_O_UNCONNECTED(0),
|
||||
OBUFDS_GTM_OB(0) => NLW_U0_OBUFDS_GTM_OB_UNCONNECTED(0),
|
||||
OBUF_DS_N(0) => NLW_U0_OBUF_DS_N_UNCONNECTED(0),
|
||||
OBUF_DS_P(0) => NLW_U0_OBUF_DS_P_UNCONNECTED(0),
|
||||
OBUF_IN(0) => '0',
|
||||
RXRECCLK_SEL_GTE3_ADV(1 downto 0) => B"00",
|
||||
RXRECCLK_SEL_GTE4_ADV(1 downto 0) => B"00"
|
||||
);
|
||||
end STRUCTURE;
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
|
||||
// Date : Tue Jun 24 11:58:34 2025
|
||||
// Host : media-wawa running 64-bit NixOS 25.05 (Warbler)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ top_util_ds_buf_0_stub.v
|
||||
// Design : top_util_ds_buf_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7a100tlfgg484-2L
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "util_ds_buf,Vivado 2022.1" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(IBUF_DS_P, IBUF_DS_N, IBUF_OUT, IBUF_DS_ODIV2)
|
||||
/* synthesis syn_black_box black_box_pad_pin="IBUF_DS_P[0:0],IBUF_DS_N[0:0],IBUF_OUT[0:0],IBUF_DS_ODIV2[0:0]" */;
|
||||
input [0:0]IBUF_DS_P;
|
||||
input [0:0]IBUF_DS_N;
|
||||
output [0:0]IBUF_OUT;
|
||||
output [0:0]IBUF_DS_ODIV2;
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
|
||||
-- Date : Tue Jun 24 11:58:34 2025
|
||||
-- Host : media-wawa running 64-bit NixOS 25.05 (Warbler)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ top_util_ds_buf_0_stub.vhdl
|
||||
-- Design : top_util_ds_buf_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7a100tlfgg484-2L
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
IBUF_DS_P : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
IBUF_DS_N : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
IBUF_OUT : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
IBUF_DS_ODIV2 : out STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "IBUF_DS_P[0:0],IBUF_DS_N[0:0],IBUF_OUT[0:0],IBUF_DS_ODIV2[0:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "util_ds_buf,Vivado 2022.1";
|
||||
begin
|
||||
end;
|
||||
Loading…
Add table
Add a link
Reference in a new issue