nickorlow/pcie_blinker
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it's an adder now

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Nicholas Orlowsky 2025-06-28 08:41:37 -04:00
parent ba46ab8dc4
commit 8616605746
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GPG key ID: A9F3BA4C0AA7A70B
376 changed files with 1693682 additions and 476560 deletions
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2
hello_world_dma.srcs/constrs_1/new/early.xdc
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@ -15,7 +15,6 @@ set_property PACKAGE_PIN A4 [get_ports {pcie_mgt_txn[1]}]
set_property PACKAGE_PIN B4 [get_ports {pcie_mgt_txp[1]}]
# PCIe lane 2
set_property LOC GTPE2_CHANNEL_X0Y5 [get_cells {top_i/xdma_0/inst/top_xdma_0_0_pcie2_to_pcie3_wrapper_i/pcie2_ip_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/gtp_channel.gtpe2_channel_i}]
set_property PACKAGE_PIN C11 [get_ports {pcie_mgt_rxn[2]}]
set_property PACKAGE_PIN D11 [get_ports {pcie_mgt_rxp[2]}]
set_property PACKAGE_PIN C5 [get_ports {pcie_mgt_txn[2]}]
@ -41,3 +40,4 @@ set_property IOSTANDARD LVCMOS33 [get_ports reset_rtl_0]

21
hello_world_dma.srcs/constrs_1/new/normal.xdc
View file

@ -1,12 +1,12 @@
set_property PACKAGE_PIN G4 [get_ports {leds_tri_o[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {leds_tri_o[1]}]
set_property PULLUP true [get_ports {leds_tri_o[1]}]
set_property DRIVE 8 [get_ports {leds_tri_o[1]}]
set_property PACKAGE_PIN G4 [get_ports {leds[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {leds[1]}]
set_property PULLUP true [get_ports {leds[1]}]
set_property DRIVE 8 [get_ports {leds[1]}]
set_property PACKAGE_PIN H4 [get_ports {leds_tri_o[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {leds_tri_o[0]}]
set_property PULLUP true [get_ports {leds_tri_o[0]}]
set_property DRIVE 8 [get_ports {leds_tri_o[0]}]
set_property PACKAGE_PIN H4 [get_ports {leds[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {leds[0]}]
set_property PULLUP true [get_ports {leds[0]}]
set_property DRIVE 8 [get_ports {leds[0]}]
set_property PACKAGE_PIN M1 [get_ports {LED_M2[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED_M2[0]}]
@ -16,4 +16,7 @@ set_property DRIVE 8 [get_ports {LED_M2[0]}]
set_property BITSTREAM.CONFIG.CONFIGRATE 16 [current_design]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
connect_debug_port u_ila_0/probe1 [get_nets [list {top_i/c_addsub_0_S[0]} {top_i/c_addsub_0_S[1]} {top_i/c_addsub_0_S[2]} {top_i/c_addsub_0_S[3]} {top_i/c_addsub_0_S[4]} {top_i/c_addsub_0_S[5]} {top_i/c_addsub_0_S[6]} {top_i/c_addsub_0_S[7]} {top_i/c_addsub_0_S[8]} {top_i/c_addsub_0_S[9]} {top_i/c_addsub_0_S[10]} {top_i/c_addsub_0_S[11]} {top_i/c_addsub_0_S[12]} {top_i/c_addsub_0_S[13]} {top_i/c_addsub_0_S[14]} {top_i/c_addsub_0_S[15]} {top_i/c_addsub_0_S[16]} {top_i/c_addsub_0_S[17]} {top_i/c_addsub_0_S[18]} {top_i/c_addsub_0_S[19]} {top_i/c_addsub_0_S[20]} {top_i/c_addsub_0_S[21]} {top_i/c_addsub_0_S[22]} {top_i/c_addsub_0_S[23]} {top_i/c_addsub_0_S[24]} {top_i/c_addsub_0_S[25]} {top_i/c_addsub_0_S[26]} {top_i/c_addsub_0_S[27]} {top_i/c_addsub_0_S[28]} {top_i/c_addsub_0_S[29]} {top_i/c_addsub_0_S[30]} {top_i/c_addsub_0_S[31]}]]