it's an adder now
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ba46ab8dc4
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8616605746
376 changed files with 1693682 additions and 476560 deletions
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@ -15,7 +15,6 @@ set_property PACKAGE_PIN A4 [get_ports {pcie_mgt_txn[1]}]
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set_property PACKAGE_PIN B4 [get_ports {pcie_mgt_txp[1]}]
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# PCIe lane 2
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set_property LOC GTPE2_CHANNEL_X0Y5 [get_cells {top_i/xdma_0/inst/top_xdma_0_0_pcie2_to_pcie3_wrapper_i/pcie2_ip_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/gtp_channel.gtpe2_channel_i}]
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set_property PACKAGE_PIN C11 [get_ports {pcie_mgt_rxn[2]}]
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set_property PACKAGE_PIN D11 [get_ports {pcie_mgt_rxp[2]}]
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set_property PACKAGE_PIN C5 [get_ports {pcie_mgt_txn[2]}]
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@ -41,3 +40,4 @@ set_property IOSTANDARD LVCMOS33 [get_ports reset_rtl_0]
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@ -1,12 +1,12 @@
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set_property PACKAGE_PIN G4 [get_ports {leds_tri_o[1]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {leds_tri_o[1]}]
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set_property PULLUP true [get_ports {leds_tri_o[1]}]
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set_property DRIVE 8 [get_ports {leds_tri_o[1]}]
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set_property PACKAGE_PIN G4 [get_ports {leds[1]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {leds[1]}]
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set_property PULLUP true [get_ports {leds[1]}]
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set_property DRIVE 8 [get_ports {leds[1]}]
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set_property PACKAGE_PIN H4 [get_ports {leds_tri_o[0]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {leds_tri_o[0]}]
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set_property PULLUP true [get_ports {leds_tri_o[0]}]
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set_property DRIVE 8 [get_ports {leds_tri_o[0]}]
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set_property PACKAGE_PIN H4 [get_ports {leds[0]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {leds[0]}]
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set_property PULLUP true [get_ports {leds[0]}]
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set_property DRIVE 8 [get_ports {leds[0]}]
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set_property PACKAGE_PIN M1 [get_ports {LED_M2[0]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {LED_M2[0]}]
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@ -16,4 +16,7 @@ set_property DRIVE 8 [get_ports {LED_M2[0]}]
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set_property BITSTREAM.CONFIG.CONFIGRATE 16 [current_design]
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
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set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
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set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
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connect_debug_port u_ila_0/probe1 [get_nets [list {top_i/c_addsub_0_S[0]} {top_i/c_addsub_0_S[1]} {top_i/c_addsub_0_S[2]} {top_i/c_addsub_0_S[3]} {top_i/c_addsub_0_S[4]} {top_i/c_addsub_0_S[5]} {top_i/c_addsub_0_S[6]} {top_i/c_addsub_0_S[7]} {top_i/c_addsub_0_S[8]} {top_i/c_addsub_0_S[9]} {top_i/c_addsub_0_S[10]} {top_i/c_addsub_0_S[11]} {top_i/c_addsub_0_S[12]} {top_i/c_addsub_0_S[13]} {top_i/c_addsub_0_S[14]} {top_i/c_addsub_0_S[15]} {top_i/c_addsub_0_S[16]} {top_i/c_addsub_0_S[17]} {top_i/c_addsub_0_S[18]} {top_i/c_addsub_0_S[19]} {top_i/c_addsub_0_S[20]} {top_i/c_addsub_0_S[21]} {top_i/c_addsub_0_S[22]} {top_i/c_addsub_0_S[23]} {top_i/c_addsub_0_S[24]} {top_i/c_addsub_0_S[25]} {top_i/c_addsub_0_S[26]} {top_i/c_addsub_0_S[27]} {top_i/c_addsub_0_S[28]} {top_i/c_addsub_0_S[29]} {top_i/c_addsub_0_S[30]} {top_i/c_addsub_0_S[31]}]]
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@ -256,37 +256,37 @@
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"mode": "slave",
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"memory_map_ref": "S_AXI",
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"parameters": {
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"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
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"PROTOCOL": [ { "value": "AXI4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
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"FREQ_HZ": [ { "value": "125000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
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"ID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
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"ADDR_WIDTH": [ { "value": "16", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
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"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
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"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
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"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
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"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
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"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
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"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
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"HAS_BURST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
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"HAS_LOCK": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
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"HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
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"HAS_CACHE": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
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"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
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"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
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"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
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"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
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"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
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"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
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"NUM_READ_OUTSTANDING": [ { "value": "32", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
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"NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
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"MAX_BURST_LENGTH": [ { "value": "256", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
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"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
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"CLK_DOMAIN": [ { "value": "top_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
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"NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
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"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
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"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
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"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
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"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
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"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
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"PROTOCOL": [ { "value": "AXI4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
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"FREQ_HZ": [ { "value": "125000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
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"ID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
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"ADDR_WIDTH": [ { "value": "16", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
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"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
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"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
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"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
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"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
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"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
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"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
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"HAS_BURST": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
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"HAS_LOCK": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
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"HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
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"HAS_CACHE": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
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"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
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"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
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"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
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"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
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"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
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"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
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"NUM_READ_OUTSTANDING": [ { "value": "32", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
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"NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
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"MAX_BURST_LENGTH": [ { "value": "256", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
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"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_static_object": false } ],
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"CLK_DOMAIN": [ { "value": "top_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
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"NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
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"NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
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"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
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"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
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"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
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},
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"port_maps": {
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"ARADDR": [ { "physical_name": "s_axi_araddr" } ],
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@ -328,11 +328,11 @@
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"mode": "master",
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"parameters": {
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"MASTER_TYPE": [ { "value": "BRAM_CTRL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
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"MEM_SIZE": [ { "value": "65536", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"MEM_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"MEM_ECC": [ { "value": "NONE", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
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"READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
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"READ_LATENCY": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
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"MEM_SIZE": [ { "value": "65536", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
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"MEM_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
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"MEM_ECC": [ { "value": "NONE", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
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"READ_WRITE_MODE": [ { "value": "WRITE_ONLY", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
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"READ_LATENCY": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ]
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},
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"port_maps": {
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"ADDR": [ { "physical_name": "bram_addr_a" } ],
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"mode": "master",
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"parameters": {
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"MASTER_TYPE": [ { "value": "BRAM_CTRL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
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"MEM_SIZE": [ { "value": "65536", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"MEM_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"MEM_ECC": [ { "value": "NONE", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
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"READ_WRITE_MODE": [ { "value": "READ_ONLY", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
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"READ_LATENCY": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
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"MEM_SIZE": [ { "value": "65536", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
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"MEM_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"MEM_ECC": [ { "value": "NONE", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_ONLY", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"READ_LATENCY": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ADDR": [ { "physical_name": "bram_addr_b" } ],
|
||||
|
|
@ -372,7 +372,7 @@
|
|||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s_axi_aresetn" } ]
|
||||
|
|
@ -386,11 +386,11 @@
|
|||
"ASSOCIATED_BUSIF": [ { "value": "S_AXI:S_AXI_CTRL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "125000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "top_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "top_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axi_aclk" } ]
|
||||
|
|
|
|||
|
|
@ -29,9 +29,9 @@
|
|||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
|
||||
|
|
@ -119,17 +119,17 @@
|
|||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.ASSOCIATED_PORT" xilinx:valuePermission="bd"/>
|
||||
|
|
@ -193,10 +193,10 @@
|
|||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "2", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "top_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
|
|
|
|||
|
|
@ -0,0 +1,445 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>xci</spirit:library>
|
||||
<spirit:name>unknown</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>top_axi_gpio_1_0</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="axi_gpio" spirit:version="2.0"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.IP2INTC_IRQ.PortWidth">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH">9</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN">top_xdma_0_0_axi_aclk</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">125000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.ASSOCIATED_PORT"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.CLK_DOMAIN">top_xdma_0_0_axi_aclk</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.FREQ_HZ">125000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ARESETN.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ALL_INPUTS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ALL_INPUTS_2">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ALL_OUTPUTS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ALL_OUTPUTS_2">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_DEFAULT">0x00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_DEFAULT_2">0x00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">artix7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_GPIO2_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_GPIO_WIDTH">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERRUPT_PRESENT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IS_DUAL">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TRI_DEFAULT">0xFFFFFFFF</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TRI_DEFAULT_2">0xFFFFFFFF</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_ALL_INPUTS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_ALL_INPUTS_2">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_ALL_OUTPUTS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_ALL_OUTPUTS_2">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_DOUT_DEFAULT">0x00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_DOUT_DEFAULT_2">0x00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GPIO2_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GPIO_WIDTH">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_INTERRUPT_PRESENT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_IS_DUAL">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_TRI_DEFAULT">0xFFFFFFFF</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_TRI_DEFAULT_2">0xFFFFFFFF</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">top_axi_gpio_1_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPIO2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPIO_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">artix7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7a100tl</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fgg484</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2L</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">E</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">28</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../../../hello_world_dma.gen/sources_1/bd/top/ip/top_axi_gpio_1_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2022.1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:componentInstanceExtensions>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="ip_propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.ASSOCIATED_PORT" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_ALL_INPUTS" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_ALL_OUTPUTS" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_GPIO_WIDTH" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
<xilinx:boundaryDescriptionInfo>
|
||||
<xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{
|
||||
"schema": "xilinx.com:schema:json_boundary:1.0",
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"s_axi_aclk": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_aresetn": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"s_axi_awaddr": [ { "direction": "in", "size_left": "8", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_awready": [ { "direction": "out" } ],
|
||||
"s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_wvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_wready": [ { "direction": "out" } ],
|
||||
"s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_bvalid": [ { "direction": "out" } ],
|
||||
"s_axi_bready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_araddr": [ { "direction": "in", "size_left": "8", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_arready": [ { "direction": "out" } ],
|
||||
"s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_rvalid": [ { "direction": "out" } ],
|
||||
"s_axi_rready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"gpio_io_i": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"memory_map_ref": "S_AXI",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "125000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "9", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "2", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "top_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"ARADDR": [ { "physical_name": "s_axi_araddr" } ],
|
||||
"ARREADY": [ { "physical_name": "s_axi_arready" } ],
|
||||
"ARVALID": [ { "physical_name": "s_axi_arvalid" } ],
|
||||
"AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
|
||||
"AWREADY": [ { "physical_name": "s_axi_awready" } ],
|
||||
"AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
|
||||
"BREADY": [ { "physical_name": "s_axi_bready" } ],
|
||||
"BRESP": [ { "physical_name": "s_axi_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "s_axi_bvalid" } ],
|
||||
"RDATA": [ { "physical_name": "s_axi_rdata" } ],
|
||||
"RREADY": [ { "physical_name": "s_axi_rready" } ],
|
||||
"RRESP": [ { "physical_name": "s_axi_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "s_axi_rvalid" } ],
|
||||
"WDATA": [ { "physical_name": "s_axi_wdata" } ],
|
||||
"WREADY": [ { "physical_name": "s_axi_wready" } ],
|
||||
"WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
|
||||
"WVALID": [ { "physical_name": "s_axi_wvalid" } ]
|
||||
}
|
||||
},
|
||||
"S_AXI_ACLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXI", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "125000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "top_xdma_0_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axi_aclk" } ]
|
||||
}
|
||||
},
|
||||
"S_AXI_ARESETN": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s_axi_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"GPIO": {
|
||||
"vlnv": "xilinx.com:interface:gpio:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:gpio_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"BOARD.ASSOCIATED_PARAM": [ { "value": "GPIO_BOARD_INTERFACE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TRI_I": [ { "physical_name": "gpio_io_i" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"S_AXI": {
|
||||
"display_name": "S_AXI_MEM",
|
||||
"description": "Memory Map for S_AXI",
|
||||
"address_blocks": {
|
||||
"Reg": {
|
||||
"base_address": "0",
|
||||
"range": "4096",
|
||||
"display_name": "Reg",
|
||||
"description": "Register Block",
|
||||
"usage": "register",
|
||||
"access": "read-write",
|
||||
"registers": {
|
||||
"GPIO_DATA": {
|
||||
"address_offset": "0x0",
|
||||
"size": 2,
|
||||
"display_name": "Channel_1_GPIO_DATA",
|
||||
"description": "Channel-1 AXI GPIO Data register",
|
||||
"is_volatile": true,
|
||||
"access": "read-write",
|
||||
"reset_value": "0x0",
|
||||
"fields": {
|
||||
"Channel_1_GPIO_DATA": {
|
||||
"bit_offset": 0,
|
||||
"bit_width": 2,
|
||||
"display_name": "Channel_1_GPIO_DATA",
|
||||
"description": "AXI GPIO Data Register.\nFor each I/O bit programmed as input\n R - Reads value on the input pin.\n W - No effect.\nFor each I/O bit programmed as output\n R - Reads value on GPIO_O pins\n W - Writes value to the corresponding AXI GPIO \n data register bit and output pin\n",
|
||||
"is_volatile": true,
|
||||
"access": "read-write"
|
||||
}
|
||||
}
|
||||
},
|
||||
"GPIO_TRI": {
|
||||
"address_offset": "0x4",
|
||||
"size": 2,
|
||||
"display_name": "Channel_1_GPIO_TRI",
|
||||
"description": "Channel-1 AXI GPIO 3-State Control register",
|
||||
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|
||||
"LAYERED_METADATA": [ { "value": "xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value data} bitwidth {attribs {resolve_type generated dependency bitwidth format long minimum {} maximum {}} value 2} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} integer {signed {attribs {resolve_type generated dependency signed format bool minimum {} maximum {}} value FALSE}}}} DATA_WIDTH 2}", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"DATA": [ { "physical_name": "A" } ]
|
||||
}
|
||||
},
|
||||
"clk_intf": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "s_intf:c_out_intf:sinit_intf:sset_intf:bypass_intf:c_in_intf:add_intf:b_intf:a_intf", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "SCLR", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"ASSOCIATED_CLKEN": [ { "value": "CE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"sclr_intf": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"ce_intf": {
|
||||
"vlnv": "xilinx.com:signal:clockenable:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ]
|
||||
}
|
||||
},
|
||||
"b_intf": {
|
||||
"vlnv": "xilinx.com:signal:data:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:data_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"LAYERED_METADATA": [ { "value": "undef", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"add_intf": {
|
||||
"vlnv": "xilinx.com:signal:data:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:data_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"c_in_intf": {
|
||||
"vlnv": "xilinx.com:signal:data:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:data_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"bypass_intf": {
|
||||
"vlnv": "xilinx.com:signal:data:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:data_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"sset_intf": {
|
||||
"vlnv": "xilinx.com:signal:data:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:data_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"sinit_intf": {
|
||||
"vlnv": "xilinx.com:signal:data:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:data_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"c_out_intf": {
|
||||
"vlnv": "xilinx.com:signal:data:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:data_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"s_intf": {
|
||||
"vlnv": "xilinx.com:signal:data:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:data_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"LAYERED_METADATA": [ { "value": "xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value data} bitwidth {attribs {resolve_type generated dependency bitwidth format long minimum {} maximum {}} value 2} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} integer {signed {attribs {resolve_type generated dependency signed format bool minimum {} maximum {}} value FALSE}}}} DATA_WIDTH 2}", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"DATA": [ { "physical_name": "S" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}"/>
|
||||
</xilinx:boundaryDescriptionInfo>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
3749
hello_world_dma.srcs/sources_1/bd/top/ip/top_xbar_0/top_xbar_0.xci
Normal file
3749
hello_world_dma.srcs/sources_1/bd/top/ip/top_xbar_0/top_xbar_0.xci
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -665,7 +665,7 @@
|
|||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PARITY_CHECK">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PARITY_GEN">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PARITY_PROP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PCIEBAR2AXIBAR_0">0x0000000000000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PCIEBAR2AXIBAR_0">0x0000000040000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PCIEBAR2AXIBAR_1">0x0000000000000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PCIEBAR2AXIBAR_2">0x0000000000000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PCIEBAR2AXIBAR_3">0x0000000000000000</spirit:configurableElementValue>
|
||||
|
|
@ -1370,7 +1370,7 @@
|
|||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pciebar2axibar_4">0x0000000000000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pciebar2axibar_5">0x0000000000000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pciebar2axibar_6">0x0000000000000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pciebar2axibar_axil_master">0x00000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pciebar2axibar_axil_master">0x40000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pciebar2axibar_axist_bypass">0x0000000000000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pciebar2axibar_xdma">0x0000000000000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.performance">false</spirit:configurableElementValue>
|
||||
|
|
@ -2082,7 +2082,7 @@
|
|||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.SYS_CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.SYS_CLK.ASSOCIATED_PORT" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.SYS_CLK.ASSOCIATED_RESET" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.SYS_CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.SYS_CLK.CLK_DOMAIN" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.SYS_CLK.FREQ_HZ" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.SYS_CLK.FREQ_TOLERANCE_HZ" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.SYS_CLK.PHASE" xilinx:valuePermission="bd"/>
|
||||
|
|
@ -2153,6 +2153,7 @@
|
|||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.axilite_master_en" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.axisten_freq" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.cfg_mgmt_if" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pciebar2axibar_axil_master" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_device_id" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_msix_cap_pba_bir" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.pf0_msix_cap_table_bir" xilinx:valueSource="user"/>
|
||||
|
|
@ -2244,7 +2245,7 @@
|
|||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "top_util_ds_buf_0_IBUF_OUT", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "top_util_ds_buf_0_IBUF_OUT", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
|
|
|
|||
|
|
@ -268,7 +268,7 @@
|
|||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M63_HAS_REGSLICE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M63_ISSUANCE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M63_SECURE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_MI">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_MI">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_SI">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCHK_MAX_RD_BURSTS">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCHK_MAX_WR_BURSTS">2</spirit:configurableElementValue>
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
{
|
||||
"design": {
|
||||
"design_info": {
|
||||
"boundary_crc": "0xDCADD24011654157",
|
||||
"boundary_crc": "0xE6D6E116F7F37665",
|
||||
"device": "xc7a100tlfgg484-2L",
|
||||
"gen_directory": "../../../../hello_world_dma.gen/sources_1/bd/top",
|
||||
"name": "top",
|
||||
|
|
@ -15,12 +15,17 @@
|
|||
"axi_bram_ctrl_0": "",
|
||||
"blk_mem_gen_0": "",
|
||||
"util_vector_logic_0": "",
|
||||
"axi_gpio_0": "",
|
||||
"util_ds_buf": "",
|
||||
"axi_smc": "",
|
||||
"xdma_0_axi_periph": {
|
||||
"s00_couplers": {}
|
||||
}
|
||||
"xbar": "",
|
||||
"s00_couplers": {},
|
||||
"m00_couplers": {},
|
||||
"m01_couplers": {}
|
||||
},
|
||||
"axi_gpio_1": "",
|
||||
"axi_gpio_0": "",
|
||||
"c_addsub_0": ""
|
||||
},
|
||||
"interface_ports": {
|
||||
"pcie_express_x4": {
|
||||
|
|
@ -41,11 +46,6 @@
|
|||
"value": "100000000"
|
||||
}
|
||||
}
|
||||
},
|
||||
"leds": {
|
||||
"mode": "Master",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:gpio:1.0",
|
||||
"vlnv": "xilinx.com:interface:gpio_rtl:1.0"
|
||||
}
|
||||
},
|
||||
"ports": {
|
||||
|
|
@ -76,6 +76,17 @@
|
|||
"value_src": "ip_prop"
|
||||
}
|
||||
}
|
||||
},
|
||||
"leds": {
|
||||
"direction": "O",
|
||||
"left": "1",
|
||||
"right": "0",
|
||||
"parameters": {
|
||||
"LAYERED_METADATA": {
|
||||
"value": "xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value data} bitwidth {attribs {resolve_type generated dependency bitwidth format long minimum {} maximum {}} value 2} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} integer {signed {attribs {resolve_type generated dependency signed format bool minimum {} maximum {}} value FALSE}}}} DATA_WIDTH 2}",
|
||||
"value_src": "ip_prop"
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"components": {
|
||||
|
|
@ -106,6 +117,9 @@
|
|||
"cfg_mgmt_if": {
|
||||
"value": "false"
|
||||
},
|
||||
"pciebar2axibar_axil_master": {
|
||||
"value": "0x40000000"
|
||||
},
|
||||
"pf0_device_id": {
|
||||
"value": "7014"
|
||||
},
|
||||
|
|
@ -211,20 +225,6 @@
|
|||
}
|
||||
}
|
||||
},
|
||||
"axi_gpio_0": {
|
||||
"vlnv": "xilinx.com:ip:axi_gpio:2.0",
|
||||
"xci_name": "top_axi_gpio_0_0",
|
||||
"xci_path": "ip/top_axi_gpio_0_0/top_axi_gpio_0_0.xci",
|
||||
"inst_hier_path": "axi_gpio_0",
|
||||
"parameters": {
|
||||
"C_ALL_OUTPUTS": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_GPIO_WIDTH": {
|
||||
"value": "2"
|
||||
}
|
||||
}
|
||||
},
|
||||
"util_ds_buf": {
|
||||
"vlnv": "xilinx.com:ip:util_ds_buf:2.2",
|
||||
"xci_name": "top_util_ds_buf_0",
|
||||
|
|
@ -303,7 +303,7 @@
|
|||
"xci_name": "top_xdma_0_axi_periph_0",
|
||||
"parameters": {
|
||||
"NUM_MI": {
|
||||
"value": "1"
|
||||
"value": "2"
|
||||
}
|
||||
},
|
||||
"interface_ports": {
|
||||
|
|
@ -316,6 +316,11 @@
|
|||
"mode": "Master",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
|
||||
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
||||
},
|
||||
"M01_AXI": {
|
||||
"mode": "Master",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
|
||||
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
||||
}
|
||||
},
|
||||
"ports": {
|
||||
|
|
@ -363,9 +368,52 @@
|
|||
"M00_ARESETN": {
|
||||
"type": "rst",
|
||||
"direction": "I"
|
||||
},
|
||||
"M01_ACLK": {
|
||||
"type": "clk",
|
||||
"direction": "I",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": {
|
||||
"value": "M01_AXI"
|
||||
},
|
||||
"ASSOCIATED_RESET": {
|
||||
"value": "M01_ARESETN"
|
||||
}
|
||||
}
|
||||
},
|
||||
"M01_ARESETN": {
|
||||
"type": "rst",
|
||||
"direction": "I"
|
||||
}
|
||||
},
|
||||
"components": {
|
||||
"xbar": {
|
||||
"vlnv": "xilinx.com:ip:axi_crossbar:2.1",
|
||||
"xci_name": "top_xbar_0",
|
||||
"xci_path": "ip/top_xbar_0/top_xbar_0.xci",
|
||||
"inst_hier_path": "xdma_0_axi_periph/xbar",
|
||||
"parameters": {
|
||||
"NUM_MI": {
|
||||
"value": "2"
|
||||
},
|
||||
"NUM_SI": {
|
||||
"value": "1"
|
||||
},
|
||||
"STRATEGY": {
|
||||
"value": "0"
|
||||
}
|
||||
},
|
||||
"interface_ports": {
|
||||
"S00_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "Slave",
|
||||
"bridges": [
|
||||
"M00_AXI",
|
||||
"M01_AXI"
|
||||
]
|
||||
}
|
||||
}
|
||||
},
|
||||
"s00_couplers": {
|
||||
"interface_ports": {
|
||||
"M_AXI": {
|
||||
|
|
@ -421,13 +469,149 @@
|
|||
]
|
||||
}
|
||||
}
|
||||
},
|
||||
"m00_couplers": {
|
||||
"interface_ports": {
|
||||
"M_AXI": {
|
||||
"mode": "Master",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
|
||||
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
||||
},
|
||||
"S_AXI": {
|
||||
"mode": "Slave",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
|
||||
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
||||
}
|
||||
},
|
||||
"ports": {
|
||||
"M_ACLK": {
|
||||
"type": "clk",
|
||||
"direction": "I",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": {
|
||||
"value": "M_AXI"
|
||||
},
|
||||
"ASSOCIATED_RESET": {
|
||||
"value": "M_ARESETN"
|
||||
}
|
||||
}
|
||||
},
|
||||
"M_ARESETN": {
|
||||
"type": "rst",
|
||||
"direction": "I"
|
||||
},
|
||||
"S_ACLK": {
|
||||
"type": "clk",
|
||||
"direction": "I",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": {
|
||||
"value": "S_AXI"
|
||||
},
|
||||
"ASSOCIATED_RESET": {
|
||||
"value": "S_ARESETN"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S_ARESETN": {
|
||||
"type": "rst",
|
||||
"direction": "I"
|
||||
}
|
||||
},
|
||||
"interface_nets": {
|
||||
"m00_couplers_to_m00_couplers": {
|
||||
"interface_ports": [
|
||||
"S_AXI",
|
||||
"M_AXI"
|
||||
]
|
||||
}
|
||||
}
|
||||
},
|
||||
"m01_couplers": {
|
||||
"interface_ports": {
|
||||
"M_AXI": {
|
||||
"mode": "Master",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
|
||||
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
||||
},
|
||||
"S_AXI": {
|
||||
"mode": "Slave",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
|
||||
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
||||
}
|
||||
},
|
||||
"ports": {
|
||||
"M_ACLK": {
|
||||
"type": "clk",
|
||||
"direction": "I",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": {
|
||||
"value": "M_AXI"
|
||||
},
|
||||
"ASSOCIATED_RESET": {
|
||||
"value": "M_ARESETN"
|
||||
}
|
||||
}
|
||||
},
|
||||
"M_ARESETN": {
|
||||
"type": "rst",
|
||||
"direction": "I"
|
||||
},
|
||||
"S_ACLK": {
|
||||
"type": "clk",
|
||||
"direction": "I",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": {
|
||||
"value": "S_AXI"
|
||||
},
|
||||
"ASSOCIATED_RESET": {
|
||||
"value": "S_ARESETN"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S_ARESETN": {
|
||||
"type": "rst",
|
||||
"direction": "I"
|
||||
}
|
||||
},
|
||||
"interface_nets": {
|
||||
"m01_couplers_to_m01_couplers": {
|
||||
"interface_ports": [
|
||||
"S_AXI",
|
||||
"M_AXI"
|
||||
]
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"interface_nets": {
|
||||
"s00_couplers_to_xdma_0_axi_periph": {
|
||||
"m00_couplers_to_xdma_0_axi_periph": {
|
||||
"interface_ports": [
|
||||
"M00_AXI",
|
||||
"s00_couplers/M_AXI"
|
||||
"m00_couplers/M_AXI"
|
||||
]
|
||||
},
|
||||
"m01_couplers_to_xdma_0_axi_periph": {
|
||||
"interface_ports": [
|
||||
"M01_AXI",
|
||||
"m01_couplers/M_AXI"
|
||||
]
|
||||
},
|
||||
"s00_couplers_to_xbar": {
|
||||
"interface_ports": [
|
||||
"s00_couplers/M_AXI",
|
||||
"xbar/S00_AXI"
|
||||
]
|
||||
},
|
||||
"xbar_to_m00_couplers": {
|
||||
"interface_ports": [
|
||||
"xbar/M00_AXI",
|
||||
"m00_couplers/S_AXI"
|
||||
]
|
||||
},
|
||||
"xbar_to_m01_couplers": {
|
||||
"interface_ports": [
|
||||
"xbar/M01_AXI",
|
||||
"m01_couplers/S_AXI"
|
||||
]
|
||||
},
|
||||
"xdma_0_axi_periph_to_s00_couplers": {
|
||||
|
|
@ -438,31 +622,94 @@
|
|||
}
|
||||
},
|
||||
"nets": {
|
||||
"S00_ACLK_1": {
|
||||
"ports": [
|
||||
"S00_ACLK",
|
||||
"s00_couplers/S_ACLK"
|
||||
]
|
||||
},
|
||||
"S00_ARESETN_1": {
|
||||
"ports": [
|
||||
"S00_ARESETN",
|
||||
"s00_couplers/S_ARESETN"
|
||||
]
|
||||
},
|
||||
"xdma_0_axi_periph_ACLK_net": {
|
||||
"ports": [
|
||||
"M00_ACLK",
|
||||
"s00_couplers/M_ACLK"
|
||||
"ACLK",
|
||||
"xbar/aclk",
|
||||
"s00_couplers/S_ACLK",
|
||||
"s00_couplers/M_ACLK",
|
||||
"m00_couplers/M_ACLK",
|
||||
"m01_couplers/M_ACLK",
|
||||
"m00_couplers/S_ACLK",
|
||||
"m01_couplers/S_ACLK"
|
||||
]
|
||||
},
|
||||
"xdma_0_axi_periph_ARESETN_net": {
|
||||
"ports": [
|
||||
"M00_ARESETN",
|
||||
"s00_couplers/M_ARESETN"
|
||||
"ARESETN",
|
||||
"xbar/aresetn",
|
||||
"s00_couplers/S_ARESETN",
|
||||
"s00_couplers/M_ARESETN",
|
||||
"m00_couplers/M_ARESETN",
|
||||
"m01_couplers/M_ARESETN",
|
||||
"m00_couplers/S_ARESETN",
|
||||
"m01_couplers/S_ARESETN"
|
||||
]
|
||||
}
|
||||
}
|
||||
},
|
||||
"axi_gpio_1": {
|
||||
"vlnv": "xilinx.com:ip:axi_gpio:2.0",
|
||||
"xci_name": "top_axi_gpio_1_0",
|
||||
"xci_path": "ip/top_axi_gpio_1_0/top_axi_gpio_1_0.xci",
|
||||
"inst_hier_path": "axi_gpio_1",
|
||||
"parameters": {
|
||||
"C_ALL_INPUTS": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_GPIO_WIDTH": {
|
||||
"value": "2"
|
||||
}
|
||||
}
|
||||
},
|
||||
"axi_gpio_0": {
|
||||
"vlnv": "xilinx.com:ip:axi_gpio:2.0",
|
||||
"xci_name": "top_axi_gpio_0_0",
|
||||
"xci_path": "ip/top_axi_gpio_0_0/top_axi_gpio_0_0.xci",
|
||||
"inst_hier_path": "axi_gpio_0",
|
||||
"parameters": {
|
||||
"C_ALL_OUTPUTS": {
|
||||
"value": "1"
|
||||
},
|
||||
"C_GPIO_WIDTH": {
|
||||
"value": "2"
|
||||
}
|
||||
}
|
||||
},
|
||||
"c_addsub_0": {
|
||||
"vlnv": "xilinx.com:ip:c_addsub:12.0",
|
||||
"xci_name": "top_c_addsub_0_0",
|
||||
"xci_path": "ip/top_c_addsub_0_0/top_c_addsub_0_0.xci",
|
||||
"inst_hier_path": "c_addsub_0",
|
||||
"parameters": {
|
||||
"A_Type": {
|
||||
"value": "Unsigned"
|
||||
},
|
||||
"A_Width": {
|
||||
"value": "2"
|
||||
},
|
||||
"B_Constant": {
|
||||
"value": "true"
|
||||
},
|
||||
"B_Type": {
|
||||
"value": "Unsigned"
|
||||
},
|
||||
"B_Value": {
|
||||
"value": "01"
|
||||
},
|
||||
"B_Width": {
|
||||
"value": "2"
|
||||
},
|
||||
"CE": {
|
||||
"value": "false"
|
||||
},
|
||||
"Latency": {
|
||||
"value": "0"
|
||||
},
|
||||
"Out_Width": {
|
||||
"value": "2"
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"interface_nets": {
|
||||
|
|
@ -478,12 +725,6 @@
|
|||
"axi_bram_ctrl_0/BRAM_PORTB"
|
||||
]
|
||||
},
|
||||
"axi_gpio_0_GPIO": {
|
||||
"interface_ports": [
|
||||
"leds",
|
||||
"axi_gpio_0/GPIO"
|
||||
]
|
||||
},
|
||||
"axi_smc_M00_AXI": {
|
||||
"interface_ports": [
|
||||
"axi_smc/M00_AXI",
|
||||
|
|
@ -511,6 +752,12 @@
|
|||
"xdma_0_axi_periph_M00_AXI": {
|
||||
"interface_ports": [
|
||||
"xdma_0_axi_periph/M00_AXI",
|
||||
"axi_gpio_1/S_AXI"
|
||||
]
|
||||
},
|
||||
"xdma_0_axi_periph_M01_AXI": {
|
||||
"interface_ports": [
|
||||
"xdma_0_axi_periph/M01_AXI",
|
||||
"axi_gpio_0/S_AXI"
|
||||
]
|
||||
},
|
||||
|
|
@ -522,6 +769,19 @@
|
|||
}
|
||||
},
|
||||
"nets": {
|
||||
"axi_gpio_0_gpio_io_o": {
|
||||
"ports": [
|
||||
"axi_gpio_0/gpio_io_o",
|
||||
"leds",
|
||||
"c_addsub_0/A"
|
||||
]
|
||||
},
|
||||
"c_addsub_0_S": {
|
||||
"ports": [
|
||||
"c_addsub_0/S",
|
||||
"axi_gpio_1/gpio_io_i"
|
||||
]
|
||||
},
|
||||
"reset_rtl_0_1": {
|
||||
"ports": [
|
||||
"reset_rtl_0",
|
||||
|
|
@ -546,9 +806,11 @@
|
|||
"axi_smc/aclk",
|
||||
"axi_bram_ctrl_0/s_axi_aclk",
|
||||
"xdma_0_axi_periph/S00_ACLK",
|
||||
"axi_gpio_0/s_axi_aclk",
|
||||
"xdma_0_axi_periph/M00_ACLK",
|
||||
"xdma_0_axi_periph/ACLK"
|
||||
"xdma_0_axi_periph/ACLK",
|
||||
"axi_gpio_1/s_axi_aclk",
|
||||
"axi_gpio_0/s_axi_aclk",
|
||||
"xdma_0_axi_periph/M01_ACLK"
|
||||
]
|
||||
},
|
||||
"xdma_0_axi_aresetn": {
|
||||
|
|
@ -557,9 +819,11 @@
|
|||
"axi_bram_ctrl_0/s_axi_aresetn",
|
||||
"axi_smc/aresetn",
|
||||
"xdma_0_axi_periph/S00_ARESETN",
|
||||
"axi_gpio_0/s_axi_aresetn",
|
||||
"xdma_0_axi_periph/M00_ARESETN",
|
||||
"xdma_0_axi_periph/ARESETN"
|
||||
"xdma_0_axi_periph/ARESETN",
|
||||
"axi_gpio_1/s_axi_aresetn",
|
||||
"axi_gpio_0/s_axi_aresetn",
|
||||
"xdma_0_axi_periph/M01_ARESETN"
|
||||
]
|
||||
},
|
||||
"xdma_0_user_lnk_up": {
|
||||
|
|
@ -586,7 +850,12 @@
|
|||
"SEG_axi_gpio_0_Reg": {
|
||||
"address_block": "/axi_gpio_0/S_AXI/Reg",
|
||||
"offset": "0x40000000",
|
||||
"range": "32K"
|
||||
"range": "64K"
|
||||
},
|
||||
"SEG_axi_gpio_1_Reg": {
|
||||
"address_block": "/axi_gpio_1/S_AXI/Reg",
|
||||
"offset": "0x40010000",
|
||||
"range": "64K"
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -21,24 +21,15 @@
|
|||
<key id="VT" for="node" attr.name="vert_type" attr.type="string"/>
|
||||
<graph id="G" edgedefault="undirected" parse.nodeids="canonical" parse.edgeids="canonical" parse.order="nodesfirst">
|
||||
<node id="n0">
|
||||
<data key="BA">0x40000000</data>
|
||||
<data key="BP">C_BASEADDR</data>
|
||||
<data key="HA">0x40007FFF</data>
|
||||
<data key="HP">C_HIGHADDR</data>
|
||||
<data key="MA">M_AXI_LITE</data>
|
||||
<data key="MX">/xdma_0</data>
|
||||
<data key="MI">M_AXI_LITE</data>
|
||||
<data key="MS">SEG_axi_gpio_0_Reg</data>
|
||||
<data key="MV">xilinx.com:ip:xdma:4.1</data>
|
||||
<data key="TM">both</data>
|
||||
<data key="SX">/axi_gpio_0</data>
|
||||
<data key="SI">S_AXI</data>
|
||||
<data key="SS">Reg</data>
|
||||
<data key="SV">xilinx.com:ip:axi_gpio:2.0</data>
|
||||
<data key="TU">register</data>
|
||||
<data key="VT">AC</data>
|
||||
<data key="VH">2</data>
|
||||
<data key="VM">top</data>
|
||||
<data key="VT">VR</data>
|
||||
</node>
|
||||
<node id="n1">
|
||||
<data key="VM">top</data>
|
||||
<data key="VT">BC</data>
|
||||
</node>
|
||||
<node id="n2">
|
||||
<data key="BA">0x0000000000000000</data>
|
||||
<data key="BP">C_S_AXI_BASEADDR</data>
|
||||
<data key="HA">0x000000000000FFFF</data>
|
||||
|
|
@ -56,26 +47,56 @@
|
|||
<data key="TU">memory</data>
|
||||
<data key="VT">AC</data>
|
||||
</node>
|
||||
<node id="n2">
|
||||
<data key="VM">top</data>
|
||||
<data key="VT">BC</data>
|
||||
</node>
|
||||
<node id="n3">
|
||||
<data key="VH">2</data>
|
||||
<data key="VM">top</data>
|
||||
<data key="VT">VR</data>
|
||||
<data key="BA">0x40010000</data>
|
||||
<data key="BP">C_BASEADDR</data>
|
||||
<data key="HA">0x4001FFFF</data>
|
||||
<data key="HP">C_HIGHADDR</data>
|
||||
<data key="MA">M_AXI_LITE</data>
|
||||
<data key="MX">/xdma_0</data>
|
||||
<data key="MI">M_AXI_LITE</data>
|
||||
<data key="MS">SEG_axi_gpio_1_Reg</data>
|
||||
<data key="MV">xilinx.com:ip:xdma:4.1</data>
|
||||
<data key="TM">both</data>
|
||||
<data key="SX">/axi_gpio_1</data>
|
||||
<data key="SI">S_AXI</data>
|
||||
<data key="SS">Reg</data>
|
||||
<data key="SV">xilinx.com:ip:axi_gpio:2.0</data>
|
||||
<data key="TU">register</data>
|
||||
<data key="VT">AC</data>
|
||||
</node>
|
||||
<node id="n4">
|
||||
<data key="TU">active</data>
|
||||
<data key="VH">2</data>
|
||||
<data key="VT">PM</data>
|
||||
</node>
|
||||
<edge id="e0" source="n2" target="n3"/>
|
||||
<edge id="e1" source="n3" target="n4"/>
|
||||
<edge id="e2" source="n1" target="n4">
|
||||
<node id="n5">
|
||||
<data key="BA">0x40000000</data>
|
||||
<data key="BP">C_BASEADDR</data>
|
||||
<data key="HA">0x4000FFFF</data>
|
||||
<data key="HP">C_HIGHADDR</data>
|
||||
<data key="MA">M_AXI_LITE</data>
|
||||
<data key="MX">/xdma_0</data>
|
||||
<data key="MI">M_AXI_LITE</data>
|
||||
<data key="MS">SEG_axi_gpio_0_Reg</data>
|
||||
<data key="MV">xilinx.com:ip:xdma:4.1</data>
|
||||
<data key="TM">both</data>
|
||||
<data key="SX">/axi_gpio_0</data>
|
||||
<data key="SI">S_AXI</data>
|
||||
<data key="SS">Reg</data>
|
||||
<data key="SV">xilinx.com:ip:axi_gpio:2.0</data>
|
||||
<data key="TU">register</data>
|
||||
<data key="VT">AC</data>
|
||||
</node>
|
||||
<edge id="e0" source="n1" target="n0"/>
|
||||
<edge id="e1" source="n0" target="n4"/>
|
||||
<edge id="e2" source="n2" target="n4">
|
||||
<data key="EH">2</data>
|
||||
</edge>
|
||||
<edge id="e3" source="n0" target="n4">
|
||||
<edge id="e3" source="n5" target="n4">
|
||||
<data key="EH">2</data>
|
||||
</edge>
|
||||
<edge id="e4" source="n3" target="n4">
|
||||
<data key="EH">2</data>
|
||||
</edge>
|
||||
</graph>
|
||||
|
|
|
|||
|
|
@ -1,45 +1,49 @@
|
|||
{
|
||||
"ActiveEmotionalView":"Default View",
|
||||
"Default View_ScaleFactor":"1.44304",
|
||||
"Default View_TopLeft":"-270,-580",
|
||||
"Default View_ScaleFactor":"1.22",
|
||||
"Default View_TopLeft":"-546,-620",
|
||||
"ExpandedHierarchyInLayout":"",
|
||||
"guistr":"# # String gsaved with Nlview 7.0r4 2019-12-20 bk=1.5203 VDI=41 GEI=36 GUI=JA:10.0 TLS
|
||||
# -string -flagsOSRD
|
||||
preplace port pcie_express_x4 -pg 1 -lvl 4 -x 1120 -y -30 -defaultsOSRD
|
||||
preplace port diff_clock_rtl_0 -pg 1 -lvl 0 -x -10 -y -140 -defaultsOSRD
|
||||
preplace port leds -pg 1 -lvl 4 -x 1120 -y -60 -defaultsOSRD
|
||||
preplace port port-id_reset_rtl_0 -pg 1 -lvl 0 -x -10 -y 50 -defaultsOSRD
|
||||
preplace portBus LED_M2 -pg 1 -lvl 4 -x 1120 -y 150 -defaultsOSRD
|
||||
preplace inst xdma_0 -pg 1 -lvl 1 -x 180 -y 50 -defaultsOSRD
|
||||
preplace inst axi_bram_ctrl_0 -pg 1 -lvl 3 -x 910 -y -140 -defaultsOSRD
|
||||
preplace inst blk_mem_gen_0 -pg 1 -lvl 3 -x 910 -y 40 -defaultsOSRD
|
||||
preplace inst util_vector_logic_0 -pg 1 -lvl 3 -x 910 -y 150 -defaultsOSRD
|
||||
preplace inst axi_gpio_0 -pg 1 -lvl 2 -x 550 -y -120 -defaultsOSRD
|
||||
preplace inst util_ds_buf -pg 1 -lvl 1 -x 180 -y -140 -defaultsOSRD
|
||||
preplace inst axi_smc -pg 1 -lvl 2 -x 550 -y -280 -defaultsOSRD
|
||||
preplace inst xdma_0_axi_periph -pg 1 -lvl 2 -x 550 -y -460 -defaultsOSRD
|
||||
preplace port pcie_express_x4 -pg 1 -lvl 5 -x 1280 -y -30 -defaultsOSRD
|
||||
preplace port diff_clock_rtl_0 -pg 1 -lvl 0 -x -190 -y -140 -defaultsOSRD
|
||||
preplace port port-id_reset_rtl_0 -pg 1 -lvl 0 -x -190 -y 50 -defaultsOSRD
|
||||
preplace portBus LED_M2 -pg 1 -lvl 5 -x 1280 -y 150 -defaultsOSRD
|
||||
preplace portBus leds -pg 1 -lvl 5 -x 1280 -y -570 -defaultsOSRD
|
||||
preplace inst xdma_0 -pg 1 -lvl 1 -x 10 -y 50 -defaultsOSRD
|
||||
preplace inst axi_bram_ctrl_0 -pg 1 -lvl 3 -x 910 -y -120 -defaultsOSRD
|
||||
preplace inst blk_mem_gen_0 -pg 1 -lvl 3 -x 910 -y 60 -defaultsOSRD
|
||||
preplace inst util_vector_logic_0 -pg 1 -lvl 3 -x 910 -y 170 -defaultsOSRD
|
||||
preplace inst util_ds_buf -pg 1 -lvl 1 -x 10 -y -140 -defaultsOSRD
|
||||
preplace inst axi_smc -pg 1 -lvl 2 -x 380 -y -240 -defaultsOSRD
|
||||
preplace inst xdma_0_axi_periph -pg 1 -lvl 2 -x 380 -y -460 -defaultsOSRD
|
||||
preplace inst axi_gpio_1 -pg 1 -lvl 3 -x 910 -y -520 -defaultsOSRD
|
||||
preplace inst axi_gpio_0 -pg 1 -lvl 3 -x 910 -y -360 -defaultsOSRD
|
||||
preplace inst c_addsub_0 -pg 1 -lvl 4 -x 1170 -y -230 -defaultsOSRD
|
||||
preplace netloc axi_gpio_0_gpio_io_o 1 3 2 1070 -570 N
|
||||
preplace netloc reset_rtl_0_1 1 0 1 NJ 50
|
||||
preplace netloc util_ds_buf_IBUF_OUT 1 0 2 10 190 350J
|
||||
preplace netloc util_vector_logic_0_Res 1 3 1 N 150
|
||||
preplace netloc xdma_0_axi_aclk 1 1 2 380 -30 710
|
||||
preplace netloc xdma_0_axi_aresetn 1 1 2 390 -20 730
|
||||
preplace netloc xdma_0_user_lnk_up 1 1 2 NJ 30 720
|
||||
preplace netloc axi_bram_ctrl_0_BRAM_PORTA 1 2 2 760 -40 1070
|
||||
preplace netloc axi_bram_ctrl_0_BRAM_PORTB 1 2 2 750 -50 1060
|
||||
preplace netloc axi_gpio_0_GPIO 1 2 2 720J -60 NJ
|
||||
preplace netloc axi_smc_M00_AXI 1 2 1 710 -280n
|
||||
preplace netloc util_ds_buf_IBUF_OUT 1 0 2 -170 -210 180J
|
||||
preplace netloc util_vector_logic_0_Res 1 3 2 1060 150 N
|
||||
preplace netloc xdma_0_axi_aclk 1 1 2 190 -610 560
|
||||
preplace netloc xdma_0_axi_aresetn 1 1 2 220 -600 540
|
||||
preplace netloc xdma_0_user_lnk_up 1 1 2 NJ 30 540
|
||||
preplace netloc c_addsub_0_S 1 3 2 NJ -510 1260
|
||||
preplace netloc axi_bram_ctrl_0_BRAM_PORTA 1 2 2 550 -40 1070
|
||||
preplace netloc axi_bram_ctrl_0_BRAM_PORTB 1 2 2 560 -10 1060
|
||||
preplace netloc axi_smc_M00_AXI 1 2 1 530 -240n
|
||||
preplace netloc diff_clock_rtl_0_1 1 0 1 NJ -140
|
||||
preplace netloc xdma_0_M_AXI 1 1 1 360 -300n
|
||||
preplace netloc xdma_0_M_AXI_LITE 1 1 1 370 -520n
|
||||
preplace netloc xdma_0_axi_periph_M00_AXI 1 1 2 400 -40 700
|
||||
preplace netloc xdma_0_pcie_mgt 1 1 3 NJ 10 740J -30 NJ
|
||||
levelinfo -pg 1 -10 180 550 910 1120
|
||||
pagesize -pg 1 -db -bbox -sgen -170 -580 1290 260
|
||||
preplace netloc xdma_0_M_AXI 1 1 1 210 -260n
|
||||
preplace netloc xdma_0_M_AXI_LITE 1 1 1 200 -540n
|
||||
preplace netloc xdma_0_axi_periph_M00_AXI 1 2 1 530 -540n
|
||||
preplace netloc xdma_0_axi_periph_M01_AXI 1 2 1 550 -450n
|
||||
preplace netloc xdma_0_pcie_mgt 1 1 4 NJ 10 530J -20 NJ -20 1260
|
||||
levelinfo -pg 1 -190 10 380 910 1170 1280
|
||||
pagesize -pg 1 -db -bbox -sgen -350 -790 1450 830
|
||||
"
|
||||
}
|
||||
{
|
||||
"da_axi4_cnt":"2",
|
||||
"da_board_cnt":"4",
|
||||
"da_bram_cntlr_cnt":"2",
|
||||
"da_axi4_cnt":"7",
|
||||
"da_board_cnt":"6",
|
||||
"da_bram_cntlr_cnt":"3",
|
||||
"da_xdma_cnt":"1"
|
||||
}
|
||||
|
|
|
|||
Binary file not shown.
Loading…
Add table
Add a link
Reference in a new issue