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it's an adder now

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Nicholas Orlowsky 2025-06-28 08:41:37 -04:00
parent ba46ab8dc4
commit 8616605746
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376 changed files with 1693682 additions and 476560 deletions
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34
hello_world_dma.runs/synth_1/.Xil/top_wrapper_propImpl.xdc
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@ -21,38 +21,38 @@ set_property PACKAGE_PIN A4 [get_ports {pcie_mgt_txn[1]}]
set_property src_info {type:XDC file:1 line:15 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN B4 [get_ports {pcie_mgt_txp[1]}]
set_property src_info {type:XDC file:1 line:18 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC GTPE2_CHANNEL_X0Y5 [get_cells {top_i/xdma_0/inst/top_xdma_0_0_pcie2_to_pcie3_wrapper_i/pcie2_ip_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/gtp_channel.gtpe2_channel_i}]
set_property src_info {type:XDC file:1 line:19 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN C11 [get_ports {pcie_mgt_rxn[2]}]
set_property src_info {type:XDC file:1 line:20 export:INPUT save:INPUT read:READ} [current_design]
set_property src_info {type:XDC file:1 line:19 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN D11 [get_ports {pcie_mgt_rxp[2]}]
set_property src_info {type:XDC file:1 line:21 export:INPUT save:INPUT read:READ} [current_design]
set_property src_info {type:XDC file:1 line:20 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN C5 [get_ports {pcie_mgt_txn[2]}]
set_property src_info {type:XDC file:1 line:22 export:INPUT save:INPUT read:READ} [current_design]
set_property src_info {type:XDC file:1 line:21 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN D5 [get_ports {pcie_mgt_txp[2]}]
set_property src_info {type:XDC file:1 line:25 export:INPUT save:INPUT read:READ} [current_design]
set_property src_info {type:XDC file:1 line:24 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC GTPE2_CHANNEL_X0Y4 [get_cells {top_i/xdma_0/inst/top_xdma_0_0_pcie2_to_pcie3_wrapper_i/pcie2_ip_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/gtp_channel.gtpe2_channel_i}]
set_property src_info {type:XDC file:1 line:26 export:INPUT save:INPUT read:READ} [current_design]
set_property src_info {type:XDC file:1 line:25 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN C9 [get_ports {pcie_mgt_rxn[3]}]
set_property src_info {type:XDC file:1 line:27 export:INPUT save:INPUT read:READ} [current_design]
set_property src_info {type:XDC file:1 line:26 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN D9 [get_ports {pcie_mgt_rxp[3]}]
set_property src_info {type:XDC file:1 line:28 export:INPUT save:INPUT read:READ} [current_design]
set_property src_info {type:XDC file:1 line:27 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN C7 [get_ports {pcie_mgt_txn[3]}]
set_property src_info {type:XDC file:1 line:29 export:INPUT save:INPUT read:READ} [current_design]
set_property src_info {type:XDC file:1 line:28 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN D7 [get_ports {pcie_mgt_txp[3]}]
set_property src_info {type:XDC file:1 line:32 export:INPUT save:INPUT read:READ} [current_design]
set_property src_info {type:XDC file:1 line:31 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN F6 [get_ports {diff_clock_rtl_0_clk_p[0]}]
set_property src_info {type:XDC file:1 line:33 export:INPUT save:INPUT read:READ} [current_design]
set_property src_info {type:XDC file:1 line:32 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN E6 [get_ports {diff_clock_rtl_0_clk_n[0]}]
set_property src_info {type:XDC file:1 line:36 export:INPUT save:INPUT read:READ} [current_design]
set_property src_info {type:XDC file:1 line:35 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN G1 [get_ports {pcie_clkreq_l}]
set_property src_info {type:XDC file:1 line:37 export:INPUT save:INPUT read:READ} [current_design]
set_property src_info {type:XDC file:1 line:36 export:INPUT save:INPUT read:READ} [current_design]
set_property IOSTANDARD LVCMOS33 [get_ports {pcie_clkreq_l}]
set_property src_info {type:XDC file:1 line:38 export:INPUT save:INPUT read:READ} [current_design]
set_property src_info {type:XDC file:1 line:37 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN J1 [get_ports reset_rtl_0]
set_property src_info {type:XDC file:2 line:1 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN G4 [get_ports {leds_tri_o[1]}]
set_property PACKAGE_PIN G4 [get_ports {leds[1]}]
set_property src_info {type:XDC file:2 line:6 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN H4 [get_ports {leds_tri_o[0]}]
set_property PACKAGE_PIN H4 [get_ports {leds[0]}]
set_property src_info {type:XDC file:2 line:11 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN M1 [get_ports {LED_M2[0]}]
set_property src_info {type:XDC file:2 line:21 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe1 [get_nets [list {top_i/c_addsub_0_S[0]} {top_i/c_addsub_0_S[1]} {top_i/c_addsub_0_S[2]} {top_i/c_addsub_0_S[3]} {top_i/c_addsub_0_S[4]} {top_i/c_addsub_0_S[5]} {top_i/c_addsub_0_S[6]} {top_i/c_addsub_0_S[7]} {top_i/c_addsub_0_S[8]} {top_i/c_addsub_0_S[9]} {top_i/c_addsub_0_S[10]} {top_i/c_addsub_0_S[11]} {top_i/c_addsub_0_S[12]} {top_i/c_addsub_0_S[13]} {top_i/c_addsub_0_S[14]} {top_i/c_addsub_0_S[15]} {top_i/c_addsub_0_S[16]} {top_i/c_addsub_0_S[17]} {top_i/c_addsub_0_S[18]} {top_i/c_addsub_0_S[19]} {top_i/c_addsub_0_S[20]} {top_i/c_addsub_0_S[21]} {top_i/c_addsub_0_S[22]} {top_i/c_addsub_0_S[23]} {top_i/c_addsub_0_S[24]} {top_i/c_addsub_0_S[25]} {top_i/c_addsub_0_S[26]} {top_i/c_addsub_0_S[27]} {top_i/c_addsub_0_S[28]} {top_i/c_addsub_0_S[29]} {top_i/c_addsub_0_S[30]} {top_i/c_addsub_0_S[31]}]]