it's an adder now
This commit is contained in:
parent
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commit
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376 changed files with 1693682 additions and 476560 deletions
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@ -0,0 +1,2 @@
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NumberHits:1
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Timestamp: Sat Jun 28 02:34:41 UTC 2025
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@ -0,0 +1,358 @@
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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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// --------------------------------------------------------------------------------
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// Tool Version: Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
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// Date : Wed Jun 25 03:38:25 2025
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// Host : media-wawa running 64-bit NixOS 25.05 (Warbler)
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// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
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// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ top_c_addsub_0_1_sim_netlist.v
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// Design : top_c_addsub_0_1
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// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
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// or synthesized. This netlist cannot be used for SDF annotated simulation.
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// Device : xc7a100tlfgg484-2L
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// --------------------------------------------------------------------------------
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`timescale 1 ps / 1 ps
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(* CHECK_LICENSE_TYPE = "top_c_addsub_0_1,c_addsub_v12_0_14,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "c_addsub_v12_0_14,Vivado 2022.1" *)
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(* NotValidForBitStream *)
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module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
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(A,
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S);
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(* x_interface_info = "xilinx.com:signal:data:1.0 a_intf DATA" *) (* x_interface_parameter = "XIL_INTERFACENAME a_intf, LAYERED_METADATA undef" *) input [1:0]A;
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(* x_interface_info = "xilinx.com:signal:data:1.0 s_intf DATA" *) (* x_interface_parameter = "XIL_INTERFACENAME s_intf, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value data} bitwidth {attribs {resolve_type generated dependency bitwidth format long minimum {} maximum {}} value 2} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} integer {signed {attribs {resolve_type generated dependency signed format bool minimum {} maximum {}} value FALSE}}}} DATA_WIDTH 2}" *) output [1:0]S;
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wire [1:0]A;
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wire [1:0]S;
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wire NLW_U0_C_OUT_UNCONNECTED;
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(* C_BORROW_LOW = "1" *)
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(* C_CE_OVERRIDES_BYPASS = "1" *)
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(* C_CE_OVERRIDES_SCLR = "0" *)
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(* C_IMPLEMENTATION = "0" *)
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(* C_SCLR_OVERRIDES_SSET = "1" *)
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(* C_VERBOSITY = "0" *)
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(* C_XDEVICEFAMILY = "artix7l" *)
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(* KEEP_HIERARCHY = "soft" *)
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(* c_a_type = "1" *)
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(* c_a_width = "2" *)
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(* c_add_mode = "0" *)
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(* c_ainit_val = "0" *)
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(* c_b_constant = "1" *)
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(* c_b_type = "1" *)
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(* c_b_value = "01" *)
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(* c_b_width = "2" *)
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(* c_bypass_low = "0" *)
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(* c_has_bypass = "0" *)
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(* c_has_c_in = "0" *)
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(* c_has_c_out = "0" *)
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(* c_has_ce = "0" *)
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(* c_has_sclr = "0" *)
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(* c_has_sinit = "0" *)
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(* c_has_sset = "0" *)
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(* c_latency = "0" *)
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(* c_out_width = "2" *)
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(* c_sinit_val = "0" *)
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(* downgradeipidentifiedwarnings = "yes" *)
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(* is_du_within_envelope = "true" *)
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decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_c_addsub_v12_0_14 U0
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(.A(A),
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.ADD(1'b1),
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.B({1'b0,1'b0}),
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.BYPASS(1'b0),
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.CE(1'b1),
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.CLK(1'b0),
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.C_IN(1'b0),
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.C_OUT(NLW_U0_C_OUT_UNCONNECTED),
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.S(S),
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.SCLR(1'b0),
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.SINIT(1'b0),
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.SSET(1'b0));
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endmodule
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|
||||
xrmDfXFG2vPrnWBJC9LioJ9VYIzoVfHcwUUykQ==
|
||||
|
||||
`pragma protect key_keyowner="Synplicity", key_keyname="SYNP15_1", key_method="rsa"
|
||||
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
|
||||
`pragma protect key_block
|
||||
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||||
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|
||||
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|
||||
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|
||||
0OvIF/BCuhbhm4dsJNLznIwPFpuwDQBQ1xbHVQ==
|
||||
|
||||
`pragma protect data_method = "AES128-CBC"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5728)
|
||||
`pragma protect data_block
|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
wJWb6kt4sy876RB9UMBsi4NKJ7Dr9fBc2tffng==
|
||||
`pragma protect end_protected
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
parameter GRES_WIDTH = 10000;
|
||||
parameter GRES_START = 10000;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
wire GRESTORE;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
reg GRESTORE_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
assign (strong1, weak0) GRESTORE = GRESTORE_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GRESTORE_int = 1'b0;
|
||||
#(GRES_START);
|
||||
GRESTORE_int = 1'b1;
|
||||
#(GRES_WIDTH);
|
||||
GRESTORE_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
|
|
@ -0,0 +1,504 @@
|
|||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
|
||||
-- Date : Wed Jun 25 03:38:25 2025
|
||||
-- Host : media-wawa running 64-bit NixOS 25.05 (Warbler)
|
||||
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ top_c_addsub_0_1_sim_netlist.vhdl
|
||||
-- Design : top_c_addsub_0_1
|
||||
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
|
||||
-- synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
-- Device : xc7a100tlfgg484-2L
|
||||
-- --------------------------------------------------------------------------------
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1hv67mlvASZeO1ILfMn6z1sEzuwKNd28yoPW
|
||||
`protect end_protected
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
port (
|
||||
A : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S : out STD_LOGIC_VECTOR ( 1 downto 0 )
|
||||
);
|
||||
attribute NotValidForBitStream : boolean;
|
||||
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
|
||||
attribute CHECK_LICENSE_TYPE : string;
|
||||
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "top_c_addsub_0_1,c_addsub_v12_0_14,{}";
|
||||
attribute downgradeipidentifiedwarnings : string;
|
||||
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "c_addsub_v12_0_14,Vivado 2022.1";
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
signal NLW_U0_C_OUT_UNCONNECTED : STD_LOGIC;
|
||||
attribute C_BORROW_LOW : integer;
|
||||
attribute C_BORROW_LOW of U0 : label is 1;
|
||||
attribute C_CE_OVERRIDES_BYPASS : integer;
|
||||
attribute C_CE_OVERRIDES_BYPASS of U0 : label is 1;
|
||||
attribute C_CE_OVERRIDES_SCLR : integer;
|
||||
attribute C_CE_OVERRIDES_SCLR of U0 : label is 0;
|
||||
attribute C_IMPLEMENTATION : integer;
|
||||
attribute C_IMPLEMENTATION of U0 : label is 0;
|
||||
attribute C_SCLR_OVERRIDES_SSET : integer;
|
||||
attribute C_SCLR_OVERRIDES_SSET of U0 : label is 1;
|
||||
attribute C_VERBOSITY : integer;
|
||||
attribute C_VERBOSITY of U0 : label is 0;
|
||||
attribute C_XDEVICEFAMILY : string;
|
||||
attribute C_XDEVICEFAMILY of U0 : label is "artix7l";
|
||||
attribute KEEP_HIERARCHY : string;
|
||||
attribute KEEP_HIERARCHY of U0 : label is "soft";
|
||||
attribute c_a_type : integer;
|
||||
attribute c_a_type of U0 : label is 1;
|
||||
attribute c_a_width : integer;
|
||||
attribute c_a_width of U0 : label is 2;
|
||||
attribute c_add_mode : integer;
|
||||
attribute c_add_mode of U0 : label is 0;
|
||||
attribute c_ainit_val : string;
|
||||
attribute c_ainit_val of U0 : label is "0";
|
||||
attribute c_b_constant : integer;
|
||||
attribute c_b_constant of U0 : label is 1;
|
||||
attribute c_b_type : integer;
|
||||
attribute c_b_type of U0 : label is 1;
|
||||
attribute c_b_value : string;
|
||||
attribute c_b_value of U0 : label is "01";
|
||||
attribute c_b_width : integer;
|
||||
attribute c_b_width of U0 : label is 2;
|
||||
attribute c_bypass_low : integer;
|
||||
attribute c_bypass_low of U0 : label is 0;
|
||||
attribute c_has_bypass : integer;
|
||||
attribute c_has_bypass of U0 : label is 0;
|
||||
attribute c_has_c_in : integer;
|
||||
attribute c_has_c_in of U0 : label is 0;
|
||||
attribute c_has_c_out : integer;
|
||||
attribute c_has_c_out of U0 : label is 0;
|
||||
attribute c_has_ce : integer;
|
||||
attribute c_has_ce of U0 : label is 0;
|
||||
attribute c_has_sclr : integer;
|
||||
attribute c_has_sclr of U0 : label is 0;
|
||||
attribute c_has_sinit : integer;
|
||||
attribute c_has_sinit of U0 : label is 0;
|
||||
attribute c_has_sset : integer;
|
||||
attribute c_has_sset of U0 : label is 0;
|
||||
attribute c_latency : integer;
|
||||
attribute c_latency of U0 : label is 0;
|
||||
attribute c_out_width : integer;
|
||||
attribute c_out_width of U0 : label is 2;
|
||||
attribute c_sinit_val : string;
|
||||
attribute c_sinit_val of U0 : label is "0";
|
||||
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
|
||||
attribute is_du_within_envelope : string;
|
||||
attribute is_du_within_envelope of U0 : label is "true";
|
||||
attribute x_interface_info : string;
|
||||
attribute x_interface_info of A : signal is "xilinx.com:signal:data:1.0 a_intf DATA";
|
||||
attribute x_interface_parameter : string;
|
||||
attribute x_interface_parameter of A : signal is "XIL_INTERFACENAME a_intf, LAYERED_METADATA undef";
|
||||
attribute x_interface_info of S : signal is "xilinx.com:signal:data:1.0 s_intf DATA";
|
||||
attribute x_interface_parameter of S : signal is "XIL_INTERFACENAME s_intf, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value data} bitwidth {attribs {resolve_type generated dependency bitwidth format long minimum {} maximum {}} value 2} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} integer {signed {attribs {resolve_type generated dependency signed format bool minimum {} maximum {}} value FALSE}}}} DATA_WIDTH 2}";
|
||||
begin
|
||||
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_c_addsub_v12_0_14
|
||||
port map (
|
||||
A(1 downto 0) => A(1 downto 0),
|
||||
ADD => '1',
|
||||
B(1 downto 0) => B"00",
|
||||
BYPASS => '0',
|
||||
CE => '1',
|
||||
CLK => '0',
|
||||
C_IN => '0',
|
||||
C_OUT => NLW_U0_C_OUT_UNCONNECTED,
|
||||
S(1 downto 0) => S(1 downto 0),
|
||||
SCLR => '0',
|
||||
SINIT => '0',
|
||||
SSET => '0'
|
||||
);
|
||||
end STRUCTURE;
|
||||
21
hello_world_dma.cache/ip/2022.1/5/4/545344bc7fb3e6c2/top_c_addsub_0_1_stub.v
Executable file
21
hello_world_dma.cache/ip/2022.1/5/4/545344bc7fb3e6c2/top_c_addsub_0_1_stub.v
Executable file
|
|
@ -0,0 +1,21 @@
|
|||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
|
||||
// Date : Wed Jun 25 03:38:24 2025
|
||||
// Host : media-wawa running 64-bit NixOS 25.05 (Warbler)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ top_c_addsub_0_1_stub.v
|
||||
// Design : top_c_addsub_0_1
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7a100tlfgg484-2L
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "c_addsub_v12_0_14,Vivado 2022.1" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(A, S)
|
||||
/* synthesis syn_black_box black_box_pad_pin="A[1:0],S[1:0]" */;
|
||||
input [1:0]A;
|
||||
output [1:0]S;
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
|
||||
-- Date : Wed Jun 25 03:38:25 2025
|
||||
-- Host : media-wawa running 64-bit NixOS 25.05 (Warbler)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ top_c_addsub_0_1_stub.vhdl
|
||||
-- Design : top_c_addsub_0_1
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7a100tlfgg484-2L
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
A : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
S : out STD_LOGIC_VECTOR ( 1 downto 0 )
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "A[1:0],S[1:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "c_addsub_v12_0_14,Vivado 2022.1";
|
||||
begin
|
||||
end;
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,2 @@
|
|||
NumberHits:1
|
||||
Timestamp: Thu Jun 26 02:22:16 UTC 2025
|
||||
Binary file not shown.
3688
hello_world_dma.cache/ip/2022.1/5/7/57382e13b83a039f/top_xbar_0_sim_netlist.v
Executable file
3688
hello_world_dma.cache/ip/2022.1/5/7/57382e13b83a039f/top_xbar_0_sim_netlist.v
Executable file
File diff suppressed because it is too large
Load diff
4133
hello_world_dma.cache/ip/2022.1/5/7/57382e13b83a039f/top_xbar_0_sim_netlist.vhdl
Executable file
4133
hello_world_dma.cache/ip/2022.1/5/7/57382e13b83a039f/top_xbar_0_sim_netlist.vhdl
Executable file
File diff suppressed because it is too large
Load diff
65
hello_world_dma.cache/ip/2022.1/5/7/57382e13b83a039f/top_xbar_0_stub.v
Executable file
65
hello_world_dma.cache/ip/2022.1/5/7/57382e13b83a039f/top_xbar_0_stub.v
Executable file
|
|
@ -0,0 +1,65 @@
|
|||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
|
||||
// Date : Tue Jun 24 20:48:29 2025
|
||||
// Host : media-wawa running 64-bit NixOS 25.05 (Warbler)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ top_xbar_0_stub.v
|
||||
// Design : top_xbar_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7a100tlfgg484-2L
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "axi_crossbar_v2_1_27_axi_crossbar,Vivado 2022.1" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, aresetn, s_axi_awaddr, s_axi_awprot,
|
||||
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
|
||||
s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arprot, s_axi_arvalid,
|
||||
s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, m_axi_awaddr,
|
||||
m_axi_awprot, m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid,
|
||||
m_axi_wready, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot,
|
||||
m_axi_arvalid, m_axi_arready, m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
|
||||
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awaddr[31:0],s_axi_awprot[2:0],s_axi_awvalid[0:0],s_axi_awready[0:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid[0:0],s_axi_wready[0:0],s_axi_bresp[1:0],s_axi_bvalid[0:0],s_axi_bready[0:0],s_axi_araddr[31:0],s_axi_arprot[2:0],s_axi_arvalid[0:0],s_axi_arready[0:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid[0:0],s_axi_rready[0:0],m_axi_awaddr[63:0],m_axi_awprot[5:0],m_axi_awvalid[1:0],m_axi_awready[1:0],m_axi_wdata[63:0],m_axi_wstrb[7:0],m_axi_wvalid[1:0],m_axi_wready[1:0],m_axi_bresp[3:0],m_axi_bvalid[1:0],m_axi_bready[1:0],m_axi_araddr[63:0],m_axi_arprot[5:0],m_axi_arvalid[1:0],m_axi_arready[1:0],m_axi_rdata[63:0],m_axi_rresp[3:0],m_axi_rvalid[1:0],m_axi_rready[1:0]" */;
|
||||
input aclk;
|
||||
input aresetn;
|
||||
input [31:0]s_axi_awaddr;
|
||||
input [2:0]s_axi_awprot;
|
||||
input [0:0]s_axi_awvalid;
|
||||
output [0:0]s_axi_awready;
|
||||
input [31:0]s_axi_wdata;
|
||||
input [3:0]s_axi_wstrb;
|
||||
input [0:0]s_axi_wvalid;
|
||||
output [0:0]s_axi_wready;
|
||||
output [1:0]s_axi_bresp;
|
||||
output [0:0]s_axi_bvalid;
|
||||
input [0:0]s_axi_bready;
|
||||
input [31:0]s_axi_araddr;
|
||||
input [2:0]s_axi_arprot;
|
||||
input [0:0]s_axi_arvalid;
|
||||
output [0:0]s_axi_arready;
|
||||
output [31:0]s_axi_rdata;
|
||||
output [1:0]s_axi_rresp;
|
||||
output [0:0]s_axi_rvalid;
|
||||
input [0:0]s_axi_rready;
|
||||
output [63:0]m_axi_awaddr;
|
||||
output [5:0]m_axi_awprot;
|
||||
output [1:0]m_axi_awvalid;
|
||||
input [1:0]m_axi_awready;
|
||||
output [63:0]m_axi_wdata;
|
||||
output [7:0]m_axi_wstrb;
|
||||
output [1:0]m_axi_wvalid;
|
||||
input [1:0]m_axi_wready;
|
||||
input [3:0]m_axi_bresp;
|
||||
input [1:0]m_axi_bvalid;
|
||||
output [1:0]m_axi_bready;
|
||||
output [63:0]m_axi_araddr;
|
||||
output [5:0]m_axi_arprot;
|
||||
output [1:0]m_axi_arvalid;
|
||||
input [1:0]m_axi_arready;
|
||||
input [63:0]m_axi_rdata;
|
||||
input [3:0]m_axi_rresp;
|
||||
input [1:0]m_axi_rvalid;
|
||||
output [1:0]m_axi_rready;
|
||||
endmodule
|
||||
69
hello_world_dma.cache/ip/2022.1/5/7/57382e13b83a039f/top_xbar_0_stub.vhdl
Executable file
69
hello_world_dma.cache/ip/2022.1/5/7/57382e13b83a039f/top_xbar_0_stub.vhdl
Executable file
|
|
@ -0,0 +1,69 @@
|
|||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
|
||||
-- Date : Tue Jun 24 20:48:29 2025
|
||||
-- Host : media-wawa running 64-bit NixOS 25.05 (Warbler)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ top_xbar_0_stub.vhdl
|
||||
-- Design : top_xbar_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7a100tlfgg484-2L
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
m_axi_awaddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
|
||||
m_axi_awprot : out STD_LOGIC_VECTOR ( 5 downto 0 );
|
||||
m_axi_awvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
m_axi_awready : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
|
||||
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
m_axi_wvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
m_axi_wready : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
m_axi_bresp : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
m_axi_bvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
m_axi_bready : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
m_axi_araddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
|
||||
m_axi_arprot : out STD_LOGIC_VECTOR ( 5 downto 0 );
|
||||
m_axi_arvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
m_axi_arready : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
|
||||
m_axi_rresp : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
m_axi_rvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
m_axi_rready : out STD_LOGIC_VECTOR ( 1 downto 0 )
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "aclk,aresetn,s_axi_awaddr[31:0],s_axi_awprot[2:0],s_axi_awvalid[0:0],s_axi_awready[0:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid[0:0],s_axi_wready[0:0],s_axi_bresp[1:0],s_axi_bvalid[0:0],s_axi_bready[0:0],s_axi_araddr[31:0],s_axi_arprot[2:0],s_axi_arvalid[0:0],s_axi_arready[0:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid[0:0],s_axi_rready[0:0],m_axi_awaddr[63:0],m_axi_awprot[5:0],m_axi_awvalid[1:0],m_axi_awready[1:0],m_axi_wdata[63:0],m_axi_wstrb[7:0],m_axi_wvalid[1:0],m_axi_wready[1:0],m_axi_bresp[3:0],m_axi_bvalid[1:0],m_axi_bready[1:0],m_axi_araddr[63:0],m_axi_arprot[5:0],m_axi_arvalid[1:0],m_axi_arready[1:0],m_axi_rdata[63:0],m_axi_rresp[3:0],m_axi_rvalid[1:0],m_axi_rready[1:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "axi_crossbar_v2_1_27_axi_crossbar,Vivado 2022.1";
|
||||
begin
|
||||
end;
|
||||
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|
|
@ -0,0 +1,2 @@
|
|||
NumberHits:1
|
||||
Timestamp: Wed Jun 25 01:24:53 UTC 2025
|
||||
BIN
hello_world_dma.cache/ip/2022.1/5/b/5b0eac07e8a7e46d/u_ila_0.dcp
Normal file
BIN
hello_world_dma.cache/ip/2022.1/5/b/5b0eac07e8a7e46d/u_ila_0.dcp
Normal file
Binary file not shown.
30405
hello_world_dma.cache/ip/2022.1/5/b/5b0eac07e8a7e46d/u_ila_0_sim_netlist.v
Executable file
30405
hello_world_dma.cache/ip/2022.1/5/b/5b0eac07e8a7e46d/u_ila_0_sim_netlist.v
Executable file
File diff suppressed because one or more lines are too long
65812
hello_world_dma.cache/ip/2022.1/5/b/5b0eac07e8a7e46d/u_ila_0_sim_netlist.vhdl
Executable file
65812
hello_world_dma.cache/ip/2022.1/5/b/5b0eac07e8a7e46d/u_ila_0_sim_netlist.vhdl
Executable file
File diff suppressed because one or more lines are too long
22
hello_world_dma.cache/ip/2022.1/5/b/5b0eac07e8a7e46d/u_ila_0_stub.v
Executable file
22
hello_world_dma.cache/ip/2022.1/5/b/5b0eac07e8a7e46d/u_ila_0_stub.v
Executable file
|
|
@ -0,0 +1,22 @@
|
|||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
|
||||
// Date : Tue Jun 24 22:34:57 2025
|
||||
// Host : media-wawa running 64-bit NixOS 25.05 (Warbler)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ u_ila_0_stub.v
|
||||
// Design : u_ila_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7a100tlfgg484-2L
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "ila,Vivado 2022.1" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[31:0],probe1[31:0]" */;
|
||||
input clk;
|
||||
input [31:0]probe0;
|
||||
input [31:0]probe1;
|
||||
endmodule
|
||||
32
hello_world_dma.cache/ip/2022.1/5/b/5b0eac07e8a7e46d/u_ila_0_stub.vhdl
Executable file
32
hello_world_dma.cache/ip/2022.1/5/b/5b0eac07e8a7e46d/u_ila_0_stub.vhdl
Executable file
|
|
@ -0,0 +1,32 @@
|
|||
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
|
||||
-- Date : Tue Jun 24 22:34:57 2025
|
||||
-- Host : media-wawa running 64-bit NixOS 25.05 (Warbler)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ u_ila_0_stub.vhdl
|
||||
-- Design : u_ila_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7a100tlfgg484-2L
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
probe0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe1 : in STD_LOGIC_VECTOR ( 31 downto 0 )
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe0[31:0],probe1[31:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2022.1";
|
||||
begin
|
||||
end;
|
||||
Loading…
Add table
Add a link
Reference in a new issue